Superjunction semiconductor device

Abstract

To provide a super-junction semiconductor device which makes a depletion layer of an edge termination region easy to be spread without changing pitches of an active region and the edge termination region.SOLUTION: A super-junction semiconductor device comprises: a buffer layer 2 of a first conductivity type, which is provided on a front face of a semiconductor wafer 1 of the first conductivity type, with a lower impurity concentration than that of the semiconductor wafer 1; a drift layer 15 of the first conductivity type, which is provided on a top face of the buffer layer 2, with a lower impurity concentration than that of the buffer layer 2; and a first parallel pn structure 20 in which a first column region 3 of the first conductivity type and a second column region 4 of a second conductivity type provided in the drift layer 15 and reaching the buffer layer 2 are alternately disposed in a repeated manner in a direction in parallel with the front face. A termination structure part 40 includes a second parallel pn structure 20B in which a first column region 3 and a second column region 4 become shallower step by step toward a termination part. In the termination structure part 40, a bottom of the second column region 4 is provided in the second column region 4 inside of the drift layer 15.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This invention relates to a superjunction semiconductor device. [Background technology]

[0002] In a typical n-channel vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor), the n-type conduction layer (drift layer) is the highest-resistance semiconductor layer among the multiple semiconductor layers formed in the semiconductor substrate. The electrical resistance of this n-type drift layer significantly affects the overall on-resistance of the vertical MOSFET. By reducing the thickness of the n-type drift layer and shortening the current path, it is possible to reduce the overall on-resistance of the vertical MOSFET.

[0003] However, vertical MOSFETs also have the function of maintaining their breakdown voltage by extending the depletion layer to the high-resistance n-type drift layer in the off state. Therefore, if the n-type drift layer is thinned to reduce on-resistance, the extension of the depletion layer in the off state becomes shorter, making it easier to reach the breakdown field strength at low applied voltages and reducing the breakdown voltage. On the other hand, to increase the breakdown voltage of a vertical MOSFET, it is necessary to increase the thickness of the n-type drift layer, which increases the on-resistance. This relationship between on-resistance and breakdown voltage is called a trade-off relationship, and it is generally difficult to improve both of them simultaneously. This trade-off relationship between on-resistance and breakdown voltage is also known to hold true for semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors), bipolar transistors, and diodes.

[0004] A superjunction (SJ) structure is known as a semiconductor device structure that solves the problems described above. For example, a MOSFET having a superjunction structure (hereinafter referred to as SJ-MOSFET) is known. Figure 21 is a schematic plan view showing the structure of a conventional SJ-MOSFET structure 1. Figure 22 is a schematic cross-sectional view of Figure 21 along line A-A' showing the structure of a conventional SJ-MOSFET structure 1. Figure 21 shows the arrangement of the n-type column region 103 and the p-type column region 104 of conventional structure 1 in a plan view. Figure 22 shows the cross-sectional structure of the n-type column region 103 and the p-type column region 104 of conventional structure 1.

[0005] As shown in Figure 22, the conventional SJ-MOSFET of structure 1 is, for example, made of silicon (Si) with a high impurity concentration n ++ An n-type buffer layer 102 is epitaxially grown on a n-type semiconductor substrate 101, and an n-type drift layer 106 is epitaxially grown on the n-type buffer layer 102. From the surface 200 of the n-type drift layer 106 ++ A p-type column region 104 is provided toward the type semiconductor substrate 101. ++ An n-type buffer layer 102 is provided between the p-type semiconductor substrate 101 and the bottom of the p-type column region 104. In Figure 22, the p-type column region 104 and the n-type ++ An n-type buffer layer 102 is provided between the n-type semiconductor substrates 101, but the p-type column region 104 and the n-type column region 103 are n ++ It may be in contact with the semiconductor substrate 101.

[0006] In the n-type drift layer 106, a parallel structure (hereinafter referred to as a parallel pn region 120) in which p-type regions (p-type column regions 104) and n-type regions (n-type column regions 103) that extend in a direction perpendicular to the main surface of the substrate and have a narrow width in a plane parallel to the main surface of the substrate are alternately and repeatedly arranged in a plane parallel to the main surface of the substrate is provided. The n-type column regions 103 that make up the parallel pn region 120 are regions with a higher impurity concentration than the n-type buffer layer 102. In the parallel pn region 120, by making the impurity concentrations contained in the p-type column regions 104 and the n-type column regions 103 substantially equal, a pseudo non-doped layer can be created in the off state to achieve high breakdown voltage.

[0007] Also, as shown in FIGS. 21 and 22, the parallel pn region 120 is provided not only in the active region 130 which is a region where current flows when the element structure is formed and in the on state, but also in the edge termination region 140 surrounding the active region 130. The edge termination region 140 is a region that relaxes the electric field on the surface 200 side of the n-type drift layer 106 and maintains the breakdown voltage. In the edge termination region 140, in order to relax the electric field, an edge termination R portion 142 with rounded corners is provided.

[0008] Also, the SJ-MOSFET of the conventional structure 1 has a MOS gate (insulated gate composed of metal-oxide-semiconductor) structure on the surface 200 side of the n-type drift layer 106. Although not shown, on the parallel pn region 120 of the active region 130 where current flows when the element is formed and in the on state, a MOS gate structure including a p-type base region, an n + type source region, a p ++ type contact region, a gate insulating film, and a gate electrode is provided.

[0009] As a front surface electrode, a source electrode in contact with the p ++ type contact region and the n + type source region is provided, and on the back surface of the n ++ type semiconductor substrate 101 (the surface opposite to the surface where the n-type buffer layer 102 is provided), a drain electrode (not shown) is provided as a back surface electrode.

[0010] In such an SJ-MOSFET, when a voltage is applied between the drain electrode and the source electrode, the p-type base region and the n-type drift layer are formed. 106 A depletion layer spreads between these regions, maintaining the breakdown voltage. Since the depletion layer spreads vertically from the source electrode side to the drain electrode side, as well as horizontally, it is necessary to devise a termination structure that controls the spread of the depletion layer in the edge termination region 140. As the characteristics of the element are mainly determined by the characteristics of the active region 130, the breakdown voltage of the edge termination region 140 is kept higher than that of the active region 130 in order to maximize the performance of the element.

[0011] The voltage withstand capability is determined by the width of the depletion layer, which depends on the impurity concentration. The lower the impurity concentration and the wider the depletion layer, the higher the voltage withstand capability. When the laterally expanding depletion layer reaches the edge of the element, punch-through occurs and the voltage withstand capability cannot be maintained. Therefore, it is necessary to stop the expansion of the depletion layer in the edge termination region 140. However, if the expansion of the depletion layer is stopped abruptly, an avalanche current will be generated due to electric field concentration, leading to element destruction. If it is stopped gradually, the width of the edge termination region 140 will widen, making the element larger. Therefore, it is necessary to suppress the expansion of the depletion layer in a balanced way.

[0012] In SJ-MOSFETs, the parallel pn region 120 is also located in the edge termination region 140, making it crucial to control the depletion layer of the pn junction in the edge termination region 140.

[0013] Furthermore, a semiconductor device is known that exhibits less reduction in breakdown voltage due to process variations due to a superjunction structure in which the depth of the first semiconductor pillar region and the second semiconductor pillar region adjacent to the high-resistance semiconductor layer are provided in a boundary region in which the depth gradually decreases towards the terminal end (see, for example, Patent Document 1 below).

[0014] Furthermore, a semiconductor device is known in which, after ion implantation is performed on the first semiconductor layer deposited on the first parallel pn layer to form the p-type region of the second parallel pn layer, a local insulating film is formed. As a result, there are no steps on the semiconductor surface due to the local insulating film, and even when the parallel pn layer is miniaturized, an ion implantation mask can be formed accurately without causing pattern defects, thereby improving the breakdown voltage of the termination structure (see, for example, Patent Document 2 below). [Prior art documents] [Patent Documents]

[0015] [Patent Document 1] Japanese Patent Publication No. 2007-335844 [Patent Document 2] Japanese Patent Publication No. 2016-021547 [Overview of the project] [Problems that the invention aims to solve]

[0016] Thus, in SJ-MOSFETs, if the impurity concentration in the parallel pn region 120 is increased too much to reduce on-resistance, the depletion layer does not expand easily and the breakdown voltage decreases. To maximize the characteristics of the active region 130, the breakdown voltage of the edge-termination region 140 is set higher than that of the active region 130. In the edge-termination region 140, as in the active region 130, electrons and holes in adjacent n-type column regions 103 and p-type column regions 104 combine along the electric field distribution, causing the depletion layer to expand. However, since no voltage is applied to the surface side of the edge-termination region 140, the electric field is distributed in a fan shape centered on the source electrode termination of the active region 130. As a result, the supply of electrons and holes tends to become unbalanced, making it difficult for the edge-termination region 140 to expand outward and thus difficult to increase its breakdown voltage.

[0017] In the conventional SJ-MOSFET structure 1, as shown in Figures 21 and 22, the parallel pn region 120 has the same pitch as the active region 130 and the parallel pn region 120 of the edge termination region 140, meaning that the width of the n-type column region 103 and the p-type column region 104 are the same. In this case, the edge termination region 140 is less prone to depletion, and there is a problem that the breakdown voltage of the edge termination region 140 tends to decrease.

[0018] Figure 23 is a schematic plan view showing the structure of the conventional SJ-MOSFET structure 2. Figure 24 is a schematic cross-sectional view of the A-A' section of Figure 23 showing the structure of the conventional SJ-MOSFET structure 2. Figure 23 shows the arrangement of the n-type column region 103 and p-type column region 104 of the conventional structure 2 in a plan view. Figure 24 shows the cross-sectional structure of the n-type column region 103 and p-type column region 104 of the conventional structure 2. In the conventional SJ-MOSFET structure 2, one method to make the breakdown voltage of the edge-termination region 140 higher than that of the active region 130 is to make the pitch of the parallel pn region 120 of the edge-termination region 140 narrower than that of the active region 130, thereby making it easier to widen the depletion layer. Another method to make the breakdown voltage of the edge-termination region 140 higher than that of the active region 130 is to lower the impurity concentration of the parallel pn region 120 of the edge-termination region 140.

[0019] However, when the pitch of the parallel pn region 120 differs between the active region 130 and the edge termination region 140, controlling the pitch switching section becomes difficult, and variations in the manufacturing process can easily lead to a decrease in withstand voltage due to electric field imbalance.

[0020] This invention aims to provide a superjunction semiconductor device that facilitates widening of the depletion layer in the edge termination region without changing the pitch between the active region and the edge termination region, in order to solve the problems of the prior art described above. [Means for solving the problem]

[0021] To solve the above-mentioned problems and achieve the objectives of the present invention, the superjunction semiconductor device according to this invention has the following features: It is a superjunction semiconductor device having an active region and a termination structure disposed outside the active region and surrounding the periphery of the active region. A buffer layer of a first conductivity type having a lower impurity concentration than the semiconductor substrate is provided on the front surface of a semiconductor substrate of a first conductivity type. A drift layer of a first conductivity type having a lower impurity concentration than the buffer layer is provided on the upper surface of the buffer layer. A first parallel pn structure is provided within the drift layer in which a first column region of a first conductivity type and a second column region of a second conductivity type reaching the buffer layer are repeatedly and alternately arranged in a direction parallel to the front surface. A base region of a second conductivity type is provided on the surface layer of the first parallel pn structure of the active region. A source region of a first conductivity type is selectively provided on the surface layer of the base region of the active region. A gate electrode is provided on the surface of the portion of the base region sandwiched between the source region and the first column region via a gate insulating film. The terminal structure has a second parallel pn structure in which the depths of the first column region and the second column region gradually become shallower towards the terminal. In the terminal structure, the bottom of the second column region is located within the drift layer. At least one of the second column regions of the second parallel pn structure protrudes toward the semiconductor substrate side beyond two of the first column regions of the second parallel pn structure that are adjacent to that at least one second column region.

[0022] Furthermore, the superjunction semiconductor device according to this invention is characterized in that, in the above-described invention, the first column region of the active region and the first column region of the termination structure are of the same width, and the second column region of the active region and the second column region of the termination structure are of the same width.

[0023] Furthermore, the superjunction semiconductor device according to this invention is characterized in that, in the invention described above, the width of the portion of the second column region that is in contact with the drift layer is wider than the width of the portion that is in contact with the first column region.

[0024] Furthermore, the superjunction semiconductor device according to this invention is characterized in that, in the invention described above, the bottom of the second column region of the termination structure is located within the drift layer, except for the second column region closest to the active region and closest to the termination portion.

[0025] Furthermore, the superjunction semiconductor device according to this invention is characterized in that, in the termination structure portion, in the second column region which is shallower in depth than the adjacent second column region, only one side of the bottom is in contact with the drift layer.

[0026] Furthermore, the superjunction semiconductor device according to this invention is characterized in that, in the invention described above, the first parallel pn structure and the second parallel pn structure are striped in a plan view.

[0027] Furthermore, the superjunction semiconductor device according to this invention is characterized in that, in the invention described above, the impurity concentration of the buffer layer is higher than the impurity concentration of the first column region.

[0028] According to the invention described above, the parallel pn region has a depth that gradually decreases as the n-type column region and the p-type column region move towards the end of the chip, and further , deep The depth is greater than the depth of the n-type column region, and the bottom ga n - A p-type column region is provided within the drift layer. This causes an electron shortage on the back side, and electrons are procured from the p-type column region, making it easier to extend the depletion layer toward the terminal side, and the n-type on the back side of the device + The depletion layer extends toward the buffer layer, making it easier to deplete the entire edge-terminal region and maintain the voltage resistance. In this way, the depletion layer can be easily extended without changing the pitch of the parallel pn regions in the active region and the edge-terminal region. [Effects of the Invention]

[0029] The superjunction semiconductor device according to the present invention has the effect of making it easier to widen the depletion layer in the edge termination region without changing the pitch between the active region and the edge termination region. [Brief explanation of the drawing]

[0030] [Figure 1] This is a cross-sectional view showing the structure of an SJ-MOSFET according to an embodiment. [Figure 2] This is a cross-sectional view showing another structure of the SJ-MOSFET according to the embodiment. [Figure 3] This is a schematic plan view showing the structure of an SJ-MOSFET according to an embodiment. [Figure 4] This is a schematic cross-sectional view of the A-A' section of Figure 3, showing the structure of the SJ-MOSFET according to the embodiment. [Figure 5] This is a schematic cross-sectional view of the B-B' section of Figure 3, showing the structure of the SJ-MOSFET according to the embodiment. [Figure 6] This is a schematic cross-sectional view of the C-C' section of Figure 3, showing the structure of the SJ-MOSFET according to the embodiment. [Figure 7] This is a schematic cross-sectional view of the D-D' section of Figure 3, showing the structure of the SJ-MOSFET according to the embodiment. [Figure 8] This is a schematic cross-sectional view of the E-E' section of Figure 3, showing the structure of the SJ-MOSFET according to the embodiment. [Figure 9] This graph shows the simulation results of the electric field distribution of a conventional SJ-MOSFET structure 1. [Figure 10] This graph shows the simulation results of the electric field distribution of the SJ-MOSFET according to the embodiment. [Figure 11] This graph shows the charge withstand capability of the edge termination region of a conventional SJ-MOSFET (structure 1) and an SJ-MOSFET according to the embodiment. [Figure 12] This is a schematic cross-sectional view of the A-A' section in Figure 21, showing the structure of the conventional SJ-MOSFET structure 3. [Figure 13] This graph shows the simulation results of the electric field distribution of a conventional SJ-MOSFET with structure 3. [Figure 14] This is a cross-sectional view (part 1) showing the state during the formation of the parallel pn region in the edge termination region of an SJ-MOSFET according to an embodiment. [Figure 15] This is a cross-sectional view (part 2) showing the state during the formation of the parallel pn region in the edge termination region of the SJ-MOSFET according to the embodiment. [Figure 16] This is a cross-sectional view (part 3) showing the state during the formation of the parallel pn region in the edge termination region of the SJ-MOSFET according to the embodiment. [Figure 17] This is a cross-sectional view (part 4) showing the state during the formation of the parallel pn region in the edge termination region of the SJ-MOSFET according to the embodiment. [Figure 18] This is a cross-sectional view (part 5) showing the state during the formation of the parallel pn region in the edge termination region of the SJ-MOSFET according to the embodiment. [Figure 19] This is a cross-sectional view (part 6) showing the state during the formation of the parallel pn region in the edge termination region of the SJ-MOSFET according to the embodiment. [Figure 20] Figures 14 to 19 show cross-sectional views illustrating the configuration of the parallel pn regions formed during the process described. [Figure 21] This is a schematic plan view showing the structure of a conventional SJ-MOSFET (structure 1). [Figure 22] This is a schematic cross-sectional view of the A-A' section in Figure 21, showing the structure of a conventional SJ-MOSFET. [Figure 23] This is a schematic plan view showing the structure of the conventional SJ-MOSFET (structure 2). [Figure 24] This is a schematic cross-sectional view of the A-A' section in Figure 23, showing the structure of the conventional SJ-MOSFET structure 2. [Modes for carrying out the invention]

[0031] Preferred embodiments of the superjunction semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers or regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. Furthermore, the + and - signs attached to n and p indicate higher and lower impurity concentrations, respectively, compared to layers or regions without these signs. When the notation for n and p, including + and -, is the same, it indicates similar concentrations, but does not necessarily mean that the concentrations are the same. In the following description of embodiments and in the accompanying drawings, similar components are denoted by the same reference numerals, and redundant explanations are omitted.

[0032] (Embodiment) The semiconductor device according to the present invention will be described using an SJ-MOSFET as an example. Figure 1 is a cross-sectional view showing the structure of an SJ-MOSFET according to an embodiment. The SJ-MOSFET 50 shown in Figure 1 is an SJ-MOSFET equipped with a MOS (Metal Oxide Semiconductor) gate on the front side (the side facing the p-type base region 5) of a semiconductor substrate 300 (semiconductor chip) made of silicon (Si). In Figure 1, only one unit cell (functional unit of the element) is shown, and other unit cells adjacent to it are omitted from the illustration.

[0033] n ++ The semiconductor substrate (first conductivity type semiconductor substrate) 1 is, for example, a silicon single crystal substrate doped with arsenic (As) or phosphorus (P). ++ On the semiconductor substrate 1, n + A buffer layer 2 is provided. + The type buffer layer 2 is n ++ It has a lower impurity concentration than semiconductor substrate type 1, and for example, it is doped with phosphorus. high concentration It is an n-type layer. + n - A drift layer 15 is provided. - The drift layer 15 is n + This is a low-concentration n-type layer having a lower impurity concentration than buffer layer 2, for example, being doped with phosphorus. ++ Semiconductor substrate type 1, n+ Type buffer layer 2, and n - The mold drift layer 15 is also included to form a semiconductor substrate 300. The upper surface of the semiconductor substrate 300 is the surface 200. A MOS gate structure (device structure) is formed on the front surface (surface 200) side of the semiconductor substrate 300. In addition, a back surface electrode 11, which serves as a drain electrode, is provided on the back surface of the semiconductor substrate 300.

[0034] The active region 30 of the SJ-MOSFET50 is provided with a parallel pn region 20 in which n-type column region 3 and p-type column region 4 are alternately arranged in a repeating pattern. The edge termination region 40 is provided with a parallel pn region 20B, which will be described later, in which n-type column region 3 and p-type column region 4 are alternately arranged in a repeating pattern.

[0035] In Figure 1, the direction in which the n-type column regions 3 and p-type column regions 4 of the parallel pn region 20 are alternately arranged is the x-direction. A p-type base region 5 is selectively provided on top of the p-type column region 4 of the active region 30. The bottom surface of the p-type base region 5 of the active region 30 is in contact with the top surface of the p-type column region 4. The p-type base region 5 of the active region 30 is provided on the surface 200 side of the semiconductor substrate 300. The p-type column region 4 extends from the surface 200 of the semiconductor substrate 300 to the n- + It is provided so as to reach the p-type buffer layer 2. The width of the upper surface of the p-type base region 5 is wider than the width of the p-type column region 4. The n-type column region 3 is similar to the p-type column region 4, extending from the surface 200 of the semiconductor substrate 300 to the n-type column region 4. + It is provided so as to reach the type buffer layer 2. As will be described later, the planar shapes of the n-type column region 3 and the p-type column region 4 in the active region 30 and the edge termination region 40 are, for example, stripe shapes. If the planar shape of the p-type column region 4 is stripe shape, then the planar shape of the p-type base region 5 is also stripe shape.

[0036] The impurity concentration in n-type column region 3 is n ++The impurity concentration is lower than that of the type semiconductor substrate 1. The impurity concentration in the p-type column region 4 and the impurity concentration in the p-type base region 5 may be equal. Also, the impurity concentration in the n-type column region 3 and the impurity concentration in the p-type column region 4 may be equal.

[0037] On the surface side of the p-type base region 5 of the active region 30, n + A type source region (first semiconductor region of the first conductivity type) 6 is selectively provided. On the surface side of the p-type base region 5 of the active region 30, n + p adjacent to type source region 6 ++ A type contact region 14 may be selectively provided.

[0038] An MOS gate structure is formed in the active region 30. Specifically, the n of the p-type base region 5 + A gate electrode 8 is provided on the surface of the portion sandwiched between the n-type source region 6 and the n-type column region 3, via a gate insulating film 7. The gate electrode 8 may also be provided on the surface of the n-type column region 3 via the gate insulating film 7.

[0039] The interlayer insulating film 9 is provided on the surface 200 side of the semiconductor substrate 300 so as to cover the gate electrode 8. The source electrode 10 is connected through a contact hole 24 opened in the interlayer insulating film 9. + The source region 6 of type p and the base region 5 are adjacent, n + It is electrically connected to the p-type source region 6 and the p-type base region 5. ++ When a type contact region 14 is provided, the source electrode 10 is n + Type source region 6 and p ++ Contacting type contact region 14, n + Type source region 6 and p ++ It is electrically connected to the type contact area 14.

[0040] The source electrode 10 is electrically insulated from the gate electrode 8 by the gate insulating film 7 and the interlayer insulating film 9. A protective film 64, such as a passivation film selectively made of polyimide, is provided on the source electrode 10.

[0041] Furthermore, in the edge termination region 40 that maintains the voltage resistance, a gate wiring 27 is provided on the side closest to the active region 30, away from the source electrode 10, and electrically connected to the gate electrode 8. The gate wiring 27 is provided in a substantially annular shape along the boundary between the active region 30 and the edge termination region 40.

[0042] In the region of the edge termination region 40 that faces the source electrode 10 and gate wiring 27 in the downward direction (y direction), a p-type base region 5B exposed on the front surface of the semiconductor substrate is provided so as to be in contact with the upper part of the n-type column region 3 and the p-type column region 4. Within the p-type base region 5B, the p-type base region exposed on the front surface of the semiconductor substrate ++ A type contact region 14B may be provided. In this case, the potential of the p-type column region 4 in contact with the p-type base region 5B becomes the source potential.

[0043] Multiple field plate electrodes 29 are arranged outside the gate wiring 27 (on the edge termination region 40 side) and at a distance from the gate wiring 27. The field plate electrodes 29 are electrically connected to the guard ring 28 by contact holes 25 opened in the interlayer insulating film 9. The field plate electrodes 29 and the guard ring 28 are provided in a ring shape on the outside of the gate wiring 27. The guard ring 28 is a region that mitigates the electric field in the edge termination region 40 and maintains withstand voltage.

[0044] A channel stopper electrode 62 is positioned outside the field plate electrode 29 and at a distance from it. The channel stopper electrode 62 is electrically connected to a p-type region 63 that functions as a channel stopper by a contact hole 26 opened in the interlayer insulating film 9. The p-type region 63 may have the same impurity concentration as the guard ring 28. The channel stopper electrode 62 and the p-type region 63 are arranged in a substantially annular shape outside the field plate electrode 29.

[0045] A parallel pn region 20B is provided in the edge termination region 40 of the SJ-MOSFET 50. As shown in Figure 1, the bottom and n of the parallel pn region 20B + Type buffer layer 2 Between these two regions, the impurity concentration is lower than that of n-type column region 3. - A type drift layer 15 is selectively provided. The p-type column region 4 is n as described later. - It is formed by ion implanting p-type impurities into the type drift layer 15. Also, the n-type column region 3 is n - It is formed by ion implanting n-type impurities into the type drift layer 15. The depth from the surface 200 of the n-type column region 3 and p-type column region 4 of the parallel pn region 20 is progressively shallower in the XY plane shown in Figure 1, as it moves outward from the SJ-MOSFET 50 (in the positive direction of the X axis, towards the p-type region 63). - Because the type drift layer 15 has a lower impurity concentration than the n-type column region 3, n - Type drift layer 15 The injected p-type impurities diffuse more freely than the n-type column region 3. Therefore, n - The bottom of the p-type column region 4 in contact with the n-type drift layer 15 is wider and bulges outwards at the point where the depth of the p-type column region 4 is greater than the depth of the n-type column region 3, compared to the portion of the p-type column region 4 in contact with the n-type column region 3. Due to this shape, the distance between adjacent p-type column regions 4 on either side of the n-type column region 3 is reduced, and the bottom of the p-type column region 4 has a region with a high concentration of p-type impurities that bulges outwards from the SJ-MOSFET 50. As a result, the bottom of the p-type column region 4 and the n-type + This has the effect of balanced depletion between the buffer layer 2 and the other layer, making electric field concentration less likely.

[0046] Furthermore, in this embodiment, n + The impurity concentration in the n-type buffer layer 2 is higher than that in the n-type column region 3. This reduces the on-resistance of the active region 30. Also, when high-energy particles such as cosmic rays penetrate the SJ-MOSFET 50 with a certain probability, the electric field state inside the SJ-MOSFET 50 changes, and the depletion layer becomes n+ Type buffer layer 2 and n ++ In some cases, it may reach near the boundary with the semiconductor substrate 1. In this case, n + Type buffer layer 2 and n ++ This method can mitigate the occurrence of avalanche due to electric field concentration caused by extreme concentration differences between the semiconductor substrate 1 and the semiconductor substrate.

[0047] The edge termination region 40 has an n-type drift layer 15 provided outside the parallel pn region 20. - The type drift layer 15 is provided at the bottom of the parallel pn region 20. - It is connected to the drift layer 15. - Outside the type drift layer 15, there is an n-type region. 65 Furthermore, the n-type region 65 may have the same impurity concentration as the n-type column region 3. - A channel stopper electrode 62 is provided on the upper surface of the type drift layer 15 and the n-type region 65 via an interlayer insulating film 9. The channel stopper electrode 62 is electrically connected to the p-type region 63 by a contact hole 26 opened in the interlayer insulating film 9.

[0048] Here, Figure 2 is a cross-sectional view showing another structure of the SJ-MOSFET according to the embodiment. In the shape of Figure 2, n - The bottom of the p-type column region 4 adjacent to the type drift layer 15 has the same width as the portion of the p-type column region 4 adjacent to the n-type column region 3. + Type buffer layers 2 and n - This shape is formed by epitaxially growing a type drift layer 15, then forming a trench, and filling the trench with an epitaxially grown p-type region. Note that the n-type column region 3 is n - When the drift layer 15 is epitaxially grown, ion implantation and the like are performed, -An n-type column region 3 with a higher impurity concentration than the type drift layer 15 may be formed. A trench is formed after the region that will become the n-type column region 3 is formed. In this case, since ion implantation to form the p-type column region 4 is not performed, the p-type impurities do not diffuse, resulting in the shape shown in Figure 2. Even in this shape, the effects of the SJ-MOSFET according to the embodiment are still present.

[0049] Furthermore, as shown in Figures 1 and 2, the parallel pn region 20B , the p-type column region 4 closest to the most active region 30 and the p-type column region 4 other than the p-type column region 4 closest to the terminal end teeth ,bottom The part, n + It is possible to reach the type buffer layer 2. Also, as shown in Figure 1, in the edge termination region 40, the depth is shallower than the adjacent p-type column region 4. In the p-type column region 4 indicated by arrow A, both sides of the bottom are n - The p-type drift layer 15 may be in contact with the p-type column region 4, or, as shown in Figure 2, the edge termination region 40 is shallower than the adjacent p-type column region 4, and in the p-type column region 4 indicated by arrow B, only one side of the bottom is n - It may be in contact with the drift layer 15.

[0050] Here, Figure 3 is a schematic plan view showing the structure of the SJ-MOSFET according to the embodiment. Figure 3 shows the parallel pn in plan view. region 20 and parallel pn region The arrangement of the n-type column region 3 and the p-type column region 4 in 20B is shown. As shown in Figure 3, a parallel pn region 20 is provided in the active region 30, which is the region where current flows when the device structure is formed and the device is in the ON state, and a parallel pn region 20B is provided in the edge termination region 40 surrounding the active region 30. The edge termination region 40 is a region that relaxes the electric field on the surface 200 side of the semiconductor substrate 300 and maintains the breakdown voltage. In the edge termination region 40, a rounded edge termination R portion 42 is provided at the corner to relax the electric field.

[0051] As shown in Figure 3, the pitch of parallel pn region 20 and parallel pn region 20B is the same. In parallel pn region 20 and parallel pn region 20B, the width of the n-type column region 3 is the same, and the width of the p-type column region 4 is also the same. Furthermore, the impurity concentration of the n-type column region 3 may be the same in parallel pn region 20 and parallel pn region 20B, and the impurity concentration of the p-type column region 4 may be the same in parallel pn region 20 and parallel pn region 20B.

[0052] Furthermore, Figure 4 is a schematic cross-sectional view of the A-A' section in Figure 3, showing the structure of the SJ-MOSFET according to the embodiment. In Figure 4, the number of n-type column regions 3 and p-type column regions 4 is shown in more detail than in Figure 3 in order to explain the configuration of the parallel pn region 20B in detail. The same applies to Figure 7, which will be described later. Figure 4 shows the active region. 30 The parallel pn region 20B of the edge termination region 40 on the x-direction side is shown, and is described in a simplified manner compared to Figure 1 (structures such as MOS gates provided on the surface 200 side of the semiconductor substrate 300, back electrode 11 provided on the back surface of the semiconductor substrate 300 are omitted, and the parallel pn region 20 and parallel pn region 20B are simplified).

[0053] Figure 5 is a schematic cross-sectional view of the B-B' section of Figure 3 showing the structure of the SJ-MOSFET according to the embodiment. Figure 6 is a schematic cross-sectional view of the C-C' section of Figure 3 showing the structure of the SJ-MOSFET according to the embodiment. Figures 5 and 6 show the active region. 30 This shows the structure of the parallel pn region 20B of the edge termination region 40 on the z-direction side.

[0054] As shown in Figures 4 to 6, the parallel pn region 20B has n-type column region 3 and p-type column region 4 that become progressively shallower as they approach the end of the SJ-MOSFET 50 (the region where the p-type region 63 is provided in the positive x-axis and positive z-axis directions). , deep The depth is greater than the depth of the n-type column region 3, ,bottom Department ga n - A p-type column region 4 is provided within the type drift layer 15. In this case, both or one of the bottom sides of the p-type column region 4 are n -It is in contact with the drift layer 15.

[0055] Thus, in this embodiment, the pn ratio is made extremely unbalanced and p-rich at the bottom of the parallel pn region 20B of the edge termination region 40. The pn ratio is the ratio of the product of the size (width × depth) of the p-type column region 4 and the impurity concentration of the p-type column region 4 to the product of the size (width × depth) of the n-type column region 3 and the impurity concentration of the n-type column region 3. P-rich means that the product of the size of the p-type column region 4 and the impurity concentration of the p-type column region 4 is greater than the product of the size of the n-type column region 3 and the impurity concentration of the n-type column region 3. As a result, electrons on the back side become deficient, and electrons are procured from the p-type column region 4, making it easier to widen the depletion layer toward the termination side (the region where the p-type region 63 is provided), and the n on the back side of the element + The depletion layer extends toward the buffer layer 2, making it easier to deplete the entire edge termination region 40 and maintain the breakdown voltage. Furthermore, in this structure, the electric field is concentrated on the back side, which reduces the effects of electric field concentration due to charges on the front side. Thus, in this embodiment, the depletion layer can be easily expanded without changing the pitch of the parallel pn regions 20 and 20B in the active region 30 and the edge termination region 40.

[0056] Here, Figure 7 is a schematic cross-sectional view of the D-D' section of Figure 3 showing the structure of the SJ-MOSFET according to the embodiment. Figure 8 is a schematic cross-sectional view of the E-E' section of Figure 3 showing the structure of the SJ-MOSFET according to the embodiment. Figures 7 and 8 show the active region. 30 The structure of the parallel pn region 20B from the edge termination R portion 42 is shown.

[0057] As shown in Figures 7 and 8, the parallel pn region 20B in this area has a constant depth for the n-type column region 3 and the p-type column region 4. This region is located between the source potential region and the drain potential region, and is easily depleted by applying a voltage between the drain and source. Since there is no need to create a structure that easily widens the depletion layer, it has the same structure as conventional designs.

[0058] Furthermore, in one specific example of the structure of the embodiment, with a voltage withstand capability of 650V, n + Type buffer layer 2 has a film thickness of 40 μm and an impurity concentration of 2 × 10⁻¹⁶. 16 / cm 3 In the active region 30, the n-type column region 3 and the p-type column region 4 have a depth of 20 μm and an impurity concentration peak of 6 × 10⁻⁶. 15 / cm 3 The widths of the n-type column region 3 and the p-type column region 4 are approximately 4 μm. ++ The semiconductor substrate 1 has a thickness of 60 μm and an impurity concentration of 4 × 10⁻¹⁶. 19 / cm 3 , n - The drift layer 15 has an impurity concentration of 3 × 10 14 / cm 3 It is to that extent.

[0059] Figure 9 is a graph showing the simulation results of the electric field distribution of an SJ-MOSFET with conventional structure 1 (Figure 22). Figure 10 is a graph showing the simulation results of the electric field distribution of an SJ-MOSFET according to embodiment (Figure 1). The simulation results are for a state in which p-type base regions 5 and 5B and guard ring 28 are formed. In the SJ-MOSFET with conventional structure 1, the depletion layer does not spread easily towards the termination side, resulting in a decrease in breakdown voltage. On the other hand, in the embodiment, the depletion layer spreads easily toward the termination side, so the depletion layer spreads toward the termination side, making it easier to deplete the entire edge termination region 40, and preventing a decrease in breakdown voltage.

[0060] Figure 11 is a graph showing the charge withstand capability of the edge termination region of a conventional SJ-MOSFET and an SJ-MOSFET according to the embodiment. In Figure 11, the vertical axis represents the breakdown voltage (BV) in units of V. The horizontal axis represents the charge line density on the surface of the edge termination region 40 in units of 1 × 10⁻¹⁰ 12The voltage is / cm. As shown in Figure 11, the breakdown voltage of the edge termination region 40 of the SJ-MOSFET according to the embodiment is higher than that of the edge termination region 140 of the conventional structure 1. Furthermore, in the conventional structure 1 SJ-MOSFET, the breakdown voltage decreases when there is a lot of positive charge on the surface of the edge termination region 140, but in the SJ-MOSFET according to the embodiment, the breakdown voltage does not decrease even when there is a lot of positive charge on the surface of the edge termination region 40. In this way, the SJ-MOSFET according to the embodiment can reduce the effects of electric field concentration due to surface charges.

[0061] Figure 12 is a schematic cross-sectional view of the A-A' section of Figure 21, showing the structure of the conventional structure 3 SJ-MOSFET. Figure 13 is a graph showing the simulation results of the electric field distribution of the conventional structure 3 SJ-MOSFET. The conventional structure 3 SJ-MOSFET is the SJ-MOSFET described in Patent Document 1. The planar schematic of the conventional structure 3 SJ-MOSFET is the same as the planar schematic of the conventional structure 1 SJ-MOSFET, so it is omitted (see Figure 21). As shown in Figure 12, in the conventional structure 3 SJ-MOSFET, the p-type column region 104 and the n-type column region 103 become progressively shallower towards the end, forming a parallel pn region 120 and an n-type Buffer layer n between 102 - Although a type drift layer 115 is provided, both sides or one side of the p-type column region 104 are surrounded by n-type column regions 103. Therefore, the p-type column region 104 receives electrons from the adjacent n-type column region 103 and becomes depleted, so the depletion layer does not easily spread in the depth direction as shown in Figure 13. In contrast, in the structure of the embodiment (see Figure 4), the p-type column region 4 protruding from the n-type column region 3 is n - Because electrons are supplied from the drift layer 15 and depletion occurs, the depletion layer tends to spread in the depth direction, as shown in Figure 10, and can maintain a higher voltage resistance than the conventional structure 3.

[0062] An example of a method for forming a part of the parallel pn region 20B in the edge termination region 40 of the semiconductor device according to the embodiment is shown. FIGS. 14 to 19 are cross-sectional views showing the states during the formation of the parallel pn region in the edge termination region of the SJ-MOSFET according to the embodiment. FIG. 20 is a cross-sectional view showing the configuration of the parallel pn region formed in the process of FIGS. 14 to 19.

[0063] First, an n ++ -type buffer layer 2 is formed on the n + -type semiconductor substrate 1. Note that an n ++ -type semiconductor wafer on which the n + -type buffer layer 2 is formed may be used. Next, an n " + -type epitaxial layer 17 is epitaxially grown on the surface of the n - -type buffer layer 2. Next, an ion implantation mask 16A having a predetermined opening is formed, for example, of a resist film on the surface of the n - -type epitaxial layer 17 by photolithography. The opening is provided in the region where the p-type column region 4A (see FIG. 20) having a deep depth is formed. Next, p-type impurities are implanted. As a result, a p-type implantation region 45 into which p-type impurities that will be part of the deep p-type column region 4A are implanted is formed. The state up to this point is described in FIG. 14.

[0064] Next, the ion implantation mask 16A is removed, and an ion implantation mask 16B having a predetermined opening is formed, for example, of a resist film on the surface of the n - -type epitaxial layer 17 by photolithography. The opening is provided in the region where the n-type column region 3A (see FIG. 20) having a deep depth is formed. Next, n-type impurities are implanted. As a result, an n-type implantation region 35 into which n-type impurities that will be part of the deep n-type column region 3A are implanted is formed. The state up to this point is described in FIG. 15.

[0065] Next, the ion implantation mask 16B is removed, and an n - -type epitaxial layer 18 is epitaxially grown on the surface of the n - -type epitaxial layer 17. Next, n- On the surface of the p-type epitaxial layer 18, an ion implantation mask 16C having a predetermined opening is formed, for example, with a resist film, by photolithography. The opening is provided within a region where a p-type column region 4A having a greater depth and a p-type column region 4B having a shallower depth (see FIG. 20) are to be formed. Next, p-type impurities are implanted. As a result, a p-type implantation region 45 into which p-type impurities that will form a part of the p-type column region 4A having a greater depth and the p-type column region 4B having a shallower depth are implanted is formed. The state up to this point is illustrated in FIG. 16.

[0066] Next, the ion implantation mask 16C is removed, and an - On the surface of the n-type epitaxial layer 18, an ion implantation mask 16D having a predetermined opening is formed, for example, with a resist film, by photolithography. The opening is provided within a region where an n-type column region 3A having a greater depth and an n-type column region 3B having the next greater depth (see FIG. 20) are to be formed. Next, n-type impurities are implanted. As a result, an n-type implantation region 35 into which n-type impurities that will form a part of the n-type column region 3A having a greater depth and the n-type column region 3B having the next greater depth are implanted is formed. The state up to this point is illustrated in FIG. 17.

[0067] Next, the ion implantation mask 16D is removed, and an - n-type epitaxial layer 19 is grown epitaxially on the surface of the n - -type epitaxial layer 18. Next, on the surface of the n - -type epitaxial layer 19, an ion implantation mask 16E having a predetermined opening is formed, for example, with a resist film, by photolithography. The opening is provided within a region where a p-type column region 4A having a greater depth and a p-type column region 4B having a shallower depth are to be formed. Next, p-type impurities are implanted. As a result, a p-type implantation region 45 into which p-type impurities that will form a part of the p-type column region 4A having a greater depth and the p-type column region 4B having a shallower depth are implanted is formed. The state up to this point is illustrated in FIG. 18.

[0068] Next, the ion implantation mask 16E is removed, and an -An ion implantation mask 16F having predetermined openings is formed on the surface of the n-type epitaxial layer 19 by photolithography, for example, using a resist film. The openings are provided within regions where a deep n-type column region 3A, a next deep n-type column region 3B, and a shallow n-type column region 3C (see Figure 20) are formed. Next, n-type impurities are implanted. This forms an n-type implantation region 35 in which n-type impurities are implanted, which becomes part of the n-type column regions 3A to 3C. - Type epitaxial layers 17 and 18 are n - This becomes the drift layer 15. The state up to this point is shown in Figure 19.

[0069] Subsequently, the epitaxial growth, p-type impurity injection, and n-type impurity injection shown in Figures 18 and 19 are repeated a predetermined number of times to form the n-type injection region 35 and the p-type injection region, and then heat treatment is performed. p-type column region 4 and n-type column region 3 As shown in Figure 20, it becomes progressively shallower towards the terminal direction, and further , deep difference ga n Deeper than the depth of type column region 3, ,bottom Department ga n - A parallel pn region 20B is formed, in which a p-type column region 4 is provided within the drift layer 15. In Figures 14 to 19, the width of the opening of the ion implantation mask 16 is the same as the width of the opening when forming the parallel pn region 20 in the active region 30. Therefore, it can be formed without changing the pitch of the pn column, and a decrease in withstand voltage due to electric field imbalance caused by variations in the manufacturing process can be prevented.

[0070] Furthermore, the p-type column region 4 of the parallel pn region 20B of the edge termination region 40 of the SJ-MOSFET according to the embodiment can also be formed as follows. First, n + Type buffer layer 2, n - The drift layer 15 is epitaxially grown. - When the n-type drift layer 15 is epitaxially grown, n-type impurities are ion-implanted to form the n-type column region 3. Next, the surface of the n-type column region 3 (epitaxially grown n -An oxide film is formed on the uppermost surface of the type drift layer 15. Next, a resist mask having openings at the positions where the p-type column region 4 is to be formed is formed on the surface of the oxide film using photolithography technology.

[0071] Next, using the resist mask as a mask, an opening is formed in the oxide film by dry etching, exposing the n-type column region 3. Then the resist mask is removed, and using the oxide film with the opening as a mask, for example, anisotropic dry etching is performed to form a trench for the p-type column in the n-type column region 3. Next, the oxide film is removed. Then, a p-type epitaxial layer is epitaxially grown to cover the surface of the n-type column region 3 and fill the inside of the trench for the p-type column, forming the p-type column region 4.

[0072] Even in this case, the width of the opening in the resist mask when forming the trench is the same as the width of the opening when forming the parallel pn region 20 in the active region 30. Therefore, it can be formed without changing the pitch of the pn column, and a decrease in breakdown voltage due to electric field imbalance caused by manufacturing process variations can be prevented.

[0073] As described above, according to the embodiment, the depth of the parallel pn region of the n-type column region and the p-type column region gradually decreases as they approach the end of the chip, and further , deep The depth is greater than the depth of the n-type column region, and the bottom ga n - A p-type column region is provided within the drift layer. This causes an electron shortage on the back side, and electrons are procured from the p-type column region, making it easier to extend the depletion layer toward the terminal side, and the n-type on the back side of the device + The depletion layer extends toward the buffer layer, making it easier to deplete the entire edge-terminal region and maintain the voltage resistance. In this way, the depletion layer can be easily extended without changing the pitch of the parallel pn regions in the active region and the edge-terminal region.

[0074] In the above description, the present invention has been explained using the example of a MOS gate structure constructed on the first main surface of a silicon substrate. However, the present invention is not limited to this, and various types of semiconductors (e.g., silicon carbide (SiC), etc.) and the surface orientation of the main surface of the substrate can be changed. Furthermore, although the embodiments of the present invention have been described using a planar MOSFET as an example, the present invention is not limited to this, and can be applied to various semiconductor devices such as trench MOSFETs and other superjunction semiconductor devices. In addition, in each embodiment of the present invention, the first conductivity type is n-type and the second conductivity type is p-type, but the present invention also holds true if the first conductivity type is p-type and the second conductivity type is n-type.

[0075] As described above, the superjunction semiconductor device according to the present invention is useful as a high-voltage semiconductor device used in power supply devices for power conversion devices and various industrial machines. [Explanation of Symbols]

[0076] 1, 101 n ++ Semiconductor substrate 2 n + Type buffer layer 3, 103 n-type column region 4, 4A, 4B, 104 p-type column regions 5, 5B p-type base region 6 n + Type source area 7 Gate insulating film 8 gates 9 Interlayer insulating film 10 Source electrodes 11 Backside electrode 14, 14B p ++ Type Contact Area 15, 115 n - Type drift layer 16A, 16B, 16C, 16D, 16E, 16F Ion implantation masks 17, 18, 19 n - Type epitaxial layer 20, 20B, 120 parallel pn regions 24, 25, 26 Contact holes 27 Gate wiring 28 Guard Rings 29 Field plate electrodes 30, 130 active area 35 n-type implant region 40, 140 edge termination region 42, 142 Edge termination R section 45 p-type implant region 50 SJ-MOSFET 62 channel stopper electrodes 63 p-type region 64 Protective film 65 n-type region 102 n-type buffer layer 10⁶ n-type drift layer 200 surface 300 Semiconductor substrates

Claims

1. A superjunction semiconductor device having an active region and a terminal structure disposed outside the active region and surrounding the periphery of the active region, A buffer layer of the first conductivity type, having a lower impurity concentration than the semiconductor substrate, is provided on the front surface of the first conductivity type semiconductor substrate. A first-conductivity type drift layer having a lower impurity concentration than the buffer layer is provided on the upper surface of the buffer layer, A first parallel pn structure is provided within the drift layer and has a first column region of a first conductivity type and a second column region of a second conductivity type arranged repeatedly and alternately in a direction parallel to the front surface, reaching the buffer layer. A base region of a second conductivity type is provided on the surface layer of the first parallel pn structure of the active region, A first conductivity type source region is selectively provided on the surface layer of the base region of the active region, A gate electrode is provided on the surface of the portion of the base region sandwiched between the source region and the first column region via a gate insulating film, Equipped with, The terminal structure has a second parallel pn structure in which the depth of the first column region and the second column region gradually becomes shallower as they approach the terminal portion. In the terminal structure, the bottom of the second column region is located within the drift layer, A superjunction semiconductor device characterized in that at least one of the second column regions of the second parallel pn structure protrudes toward the semiconductor substrate side beyond two of the first column regions of the second parallel pn structure that are adjacent to the at least one second column region.

2. The first column region of the active region and the first column region of the terminal structure are of the same width. The superjunction semiconductor device according to claim 1, characterized in that the second column region of the active region and the second column region of the terminal structure are of the same width.

3. The super-junction semiconductor device according to claim 1 or 2, characterized in that the width of the portion of the second column region in contact with the drift layer is wider than the width of the portion in contact with the first column region.

4. The super-junction semiconductor device according to any one of claims 1 to 3, characterized in that the bottom of the second column region of the terminal structure is located within the drift layer, except for the second column region closest to the active region and closest to the terminal portion.

5. The super-junction semiconductor device according to any one of claims 1 to 4, characterized in that in the terminal structure, in the second column region which is shallower in depth than the adjacent second column region, only one side of the bottom is in contact with the drift layer.

6. The superjunction semiconductor device according to any one of claims 1 to 5, characterized in that the first parallel pn structure and the second parallel pn structure are striped in a plan view.

7. The super-junction semiconductor device according to any one of claims 1 to 6, characterized in that the impurity concentration of the buffer layer is higher than the impurity concentration of the first column region.

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