Semiconductor device and method for manufacturing a semiconductor device

Abstract

To provide a semiconductor device capable of suppressing unevenness on a surface of a gate insulator film, and a manufacturing method of a semiconductor device.SOLUTION: A semiconductor device comprises: a substrate; a first electrode provided on a first face of the substrate; a second electrode provided on a second face of the substrate at an opposite side of the first face; an embedded electrode provided inside of a trench formed on the first face of the substrate; an upper electrode provided inside of the trench and provided closer to the first face than the embedded electrode; and a gate insulator film electrically separating a sidewall of the trench from the embedded electrode and the upper electrode. The gate insulator film includes a separation portion which separates the embedded electrode and the upper electrode, the embedded electrode includes a lower layer and a modified layer, which is provided at a position closer to the separation portion than the lower layer, and a crystal grain size in the modified layer is smaller than that in the lower layer.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device.

Background Art

[0002] Patent Document 1 discloses a semiconductor device including a semiconductor substrate of a first conductivity type and a first conductivity type accumulation layer formed on the front surface side of the semiconductor substrate and having a higher concentration than the impurity concentration of the semiconductor substrate. This semiconductor device further includes a trench portion formed on the front surface of the semiconductor substrate, and a transistor portion and a diode portion provided on the front surface of the semiconductor substrate. The trench portion includes a first conductive portion, a second conductive portion formed below the first conductive portion and below the central position in the depth direction of the accumulation layer, and an insulating film covering the side surface of the first conductive portion and the periphery of the second conductive portion. The trench portion has a split structure in which the insulating film insulates between the first conductive portion and the second conductive portion.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Generally, in a semiconductor device as shown in Patent Document 1, the parasitic capacitance between gate collectors affects the switching loss. This parasitic capacitance is called the feedback capacitance. In Patent Document 1, two different electrodes are formed in the trench. In such a structure, by connecting the upper top electrode to the gate and the lower buried electrode to the emitter, the semiconductor region near the buried electrode does not contribute to the feedback capacitance. Therefore, the feedback capacitance can be reduced, and the switching loss can be reduced.

[0005] In semiconductor devices such as those described in Patent Document 1, the insulating film that electrically separates the embedded electrode and the upper electrode is, for example, a silicon oxide film formed by oxidizing polysilicon formed as the embedded electrode. However, such silicon oxide films generally have large surface irregularities. This can be a factor in reducing the dielectric strength between the embedded electrode and the upper electrode. This can lead to an increase in emitter-gate leakage current and a decrease in the reliability of the gate insulating film.

[0006] This disclosure was made to solve the above-mentioned problems and aims to provide a semiconductor device and a method for manufacturing a semiconductor device that can suppress surface irregularities of the gate insulating film. [Means for solving the problem]

[0007] The semiconductor device according to the first disclosure comprises a substrate, a first electrode provided on a first surface of the substrate, a second electrode provided on a second surface of the substrate opposite to the first surface, an embedded electrode provided inside a trench formed on the first surface of the substrate, an upper electrode provided inside the trench and located on the first surface side of the embedded electrode, and a gate insulating film that electrically separates the side wall of the trench, the embedded electrode and the upper electrode, wherein the gate insulating film has a separation portion that separates the embedded electrode and the upper electrode, and the embedded electrode has a lower layer and a modified layer provided at a position closer to the separation portion than the lower layer, wherein the modified layer has a smaller crystal grain size than the lower layer.

[0008] The semiconductor device according to the second disclosure includes a substrate, a first electrode provided on a first surface of the substrate, a second electrode provided on a second surface of the substrate opposite to the first surface, an embedded electrode provided inside a trench formed on the first surface of the substrate, and provided inside the trench. The wholeThe device comprises an upper electrode provided on the first surface side of the embedded electrode, and a gate insulating film that electrically separates the trench side wall, the embedded electrode, and the upper electrode, wherein the gate insulating film has a separation portion that separates the embedded electrode and the upper electrode, and the embedded electrode has a lower layer and a modified layer provided closer to the separation portion than the lower layer, wherein the modified layer has a lower impurity concentration than the lower layer.

[0009] The semiconductor device according to the third disclosure comprises a substrate, a first electrode provided on a first surface of the substrate, a second electrode provided on a second surface of the substrate opposite to the first surface, an embedded electrode provided inside a trench formed on the first surface of the substrate, an upper electrode provided inside the trench and located on the first surface side of the embedded electrode, and a gate insulating film that electrically separates the side wall of the trench, the embedded electrode and the upper electrode, wherein the gate insulating film has a separation portion that separates the embedded electrode and the upper electrode, and the embedded electrode has a lower layer and an amorphous silicon layer provided at a position closer to the separation portion than the lower layer.

[0010] A method for manufacturing a semiconductor device according to the fourth disclosure comprises: forming a trench on the first surface of a substrate having a first surface and a second surface opposite to the first surface; forming an embedded electrode inside the trench; performing a surface modification treatment on the embedded electrode; forming a modified layer on the first surface side of the embedded electrode; oxidizing the modified layer or depositing it on the modified layer to form the gate insulating film; forming an upper electrode on the gate insulating film inside the trench; and the modified layer having a smaller grain size than the portion of the embedded electrode other than the modified layer. The surface modification treatment includes at least one of plasma treatment and laser irradiation. .

[0011] A method for manufacturing a semiconductor device according to the fifth disclosure involves forming a trench on the first surface of a substrate having a first surface and a second surface opposite to the first surface, forming an embedded electrode inside the trench, and forming an amorphous silicon layer on the embedded electrode inside the trench. DepositThe amorphous silicon layer is oxidized or deposited on the amorphous silicon to form a gate insulating film, and the upper electrode is formed on the gate insulating film inside the trench. [Effects of the Invention]

[0012] In the semiconductor device described in the first, second, and third disclosures and the method for manufacturing the semiconductor device described in the fourth and fifth disclosures, the surface irregularities of the gate insulating film between the embedded electrode and the upper electrode can be suppressed by the modified layer or amorphous silicon layer. [Brief explanation of the drawing]

[0013] [Figure 1] This is a cross-sectional view of the semiconductor device according to Embodiment 1. [Figure 2] This is a diagram illustrating the manufacturing method of a semiconductor device according to Embodiment 1. [Figure 3] This is a diagram illustrating the manufacturing method of a semiconductor device according to Embodiment 1. [Figure 4] This is a diagram illustrating the manufacturing method of a semiconductor device according to Embodiment 1. [Figure 5] This is a diagram illustrating the manufacturing method of a semiconductor device according to Embodiment 1. [Figure 6] This is a diagram illustrating the manufacturing method of a semiconductor device according to Embodiment 1. [Figure 7] This figure illustrates the manufacturing method of a semiconductor device according to Embodiment 2. [Figure 8] This figure illustrates the manufacturing method of a semiconductor device according to Embodiment 2. [Figure 9] This figure illustrates the manufacturing method of a semiconductor device according to Embodiment 2. [Figure 10] This figure illustrates a method for manufacturing a semiconductor device according to a modified example of Embodiment 2. [Modes for carrying out the invention]

[0014] The semiconductor device and the method for manufacturing the semiconductor device according to each embodiment will be described with reference to the drawings. The same or corresponding components may be denoted by the same reference numerals, and the repeated description may be omitted.

[0015] Embodiment 1. FIG.1 is a cross-sectional view of a semiconductor device 100 according to Embodiment 1. The semiconductor device 100 is a trench gate type transistor. The semiconductor device 100 is, for example, an n-channel insulated gate bipolar transistor (IGBT). The semiconductor device 100 includes a substrate having a drift layer 11 of the first conductivity type. The substrate is, for example, a silicon substrate. The first conductivity type is n-type, and the second conductivity type is p-type. However, the first conductivity type may be p-type and the second conductivity type may be n-type. An emitter electrode 41, which is a first electrode, is provided on the first surface of the substrate. A collector electrode 42, which is a second electrode, is provided on the second surface of the substrate opposite to the first surface.

[0016] A base layer 12 of the second conductivity type is provided on the first surface side of the drift layer 11. A collector layer 13 of the second conductivity type is provided on the second surface side of the drift layer 11. An emitter layer 14 of the first conductivity type is provided on the first surface side of the base layer 12. The emitter layer 14 is formed in a plurality of portions on the surface layer of the base layer 12. A trench 15 is formed on the first surface of the substrate. The trench 15 penetrates the emitter layer 14 and the base layer 12 from the first surface of the substrate and reaches the drift layer 11.

[0017] An embedded electrode 20 and an upper electrode 24 are provided inside the trench 15. The upper electrode 24 is provided on the first surface side of the embedded electrode 20. The gate insulating film 30 electrically separates the side wall of the trench 15, the embedded electrode 20, and the upper electrode 24. That is, the gate insulating film 30 has a first portion 31 formed between the embedded electrode 20 and the side wall of the trench 15, a second portion 32 formed between the upper electrode 24 and the side wall of the trench 15, and a separation portion 33 formed between the embedded electrode 20 and the upper electrode 24. The separation portion 33 separates the embedded electrode 20 and the upper electrode 24. The gate insulating film 30 is, for example, a silicon oxide film.

[0018] An interlayer insulating film 17 for separating the gate electrode and the emitter electrode 41 is provided on the upper electrode 24. The emitter electrode 41 is in contact with the base layer 12 and the emitter layer 14. Although not shown, the embedded electrode 20 is connected to the emitter electrode 41 on the outer periphery of the semiconductor device 100 or the like. Also, although not shown, the upper electrode 24 is connected to the gate electrode on the outer periphery of the semiconductor device 100 or the like.

[0019] The embedded electrode 20 has a lower layer 21 and a modified layer 22 provided at a position closer to the separation portion 33 than the lower layer 21. The lower layer 21 and the modified layer 22 are mainly made of polysilicon. The modified layer 22 has a smaller crystal grain size than the lower layer 21.

[0020] Next, a method for manufacturing the semiconductor device 100 will be described. FIGS. 2 to 6 are diagrams for explaining a method for manufacturing the semiconductor device 100 according to Embodiment 1. First, as shown in FIG. 2, a trench 15 is formed on the first surface of a substrate having a drift layer 11. The trench 15 can be formed using known lithography and etching techniques. The depth and width of the trench 15 are designed so that a desired breakdown voltage and characteristics can be ensured.

[0021] Next, as shown in Figure 3, a gate insulating film 30a is formed on the side walls of the trench 15 and on the first surface of the substrate. The gate insulating film 30a can be formed, for example, by thermal oxidation, deposition, or a combination thereof. Next, an embedded electrode 20a is formed inside the trench 15. The embedded electrode 20a can be formed, for example, by depositing polysilicon by chemical vapor deposition. Furthermore, the upper surface of the deposited polysilicon is set to a desired depth by etch-back.

[0022] Next, as shown in Figure 4, the embedded electrode 20a is subjected to a surface modification treatment. This forms a modified layer 22 on the first surface side of the embedded electrode 20a. In other words, an embedded electrode 20 having a lower layer 21 and a modified layer 22 is formed. As described above, the grain size of the modified layer 22 is smaller than that of the parts of the embedded electrode 20 other than the modified layer 22.

[0023] The modified layer 22 is formed, for example, by ion implanting Si into polysilicon, which is the material of the embedded electrode 20a. With this formation method, the impurity concentration of the modified layer 22 is lower than that of the lower layer 21. In this case, the modified layer 22 can be said to be a layer with a lower impurity concentration than the lower layer 21.

[0024] The modified layer 22 may be formed, for example, by ion implanting As, P, Ge, etc., into polysilicon, which is the material of the embedded electrode 20a. With such a formation method, the impurity concentration of the modified layer 22 will be higher than that of the lower layer 21. In this case, the modified layer 22 can be said to be a layer with a higher impurity concentration than the lower layer 21.

[0025] The modified layer 22 may be formed by discharge plasma or laser irradiation. Alternatively, the modified layer 22 may be formed by any combination of ion implantation, discharge plasma, or laser irradiation. Thus, the surface modification treatment includes at least one of ion implantation, plasma treatment, and laser irradiation.

[0026] Next, as shown in Figure 5, the portion of the gate insulating film 30a above the embedded electrode 20 is removed. Such selective etching of the gate insulating film 30a can be achieved, for example, by wet etching techniques. This forms the first portion 31 of the gate insulating film 30.

[0027] Next, as shown in Figure 6, the second portion 32 and the separation portion 33 of the gate insulating film 30 are simultaneously formed on the embedded electrode 20. The second portion 32 and the separation portion 33 can be formed, for example, by thermal oxidation, deposition, or a combination thereof. In other words, the separation portion 33 of the gate insulating film 30 is formed by oxidizing the modified layer 22 or by depositing the material of the gate insulating film 30 on the modified layer 22.

[0028] Note that the step of selectively removing the gate insulating film 30a shown in Figure 5 may be omitted. In this case, further oxidation or deposition will occur on the gate insulating film 30a shown in Figure 4. As a result, the gate insulating film 30a will be included in the second portion 32 and the separated portion 33.

[0029] Next, the upper electrode 24 is formed on the separated portion 33 of the gate insulating film 30 inside the trench 15. For the subsequent steps, the semiconductor device 100 shown in Figure 1 can be manufactured using known film deposition techniques, etching techniques, and processing techniques.

[0030] Next, the effects of this embodiment will be described. To save energy in power electronics equipment such as inverters, it is preferable to reduce the losses of semiconductor switching devices. Generally, losses are determined by the conduction loss or switching loss of the semiconductor switching device. The semiconductor device 100 of this embodiment has two electrodes, an embedded electrode 20 and an upper electrode 24, in the same trench. The upper electrode 24 is connected to the gate electrode, and the embedded electrode 20 is connected to the emitter electrode. As a result, the embedded electrode 20 is at the emitter potential, so the feedback capacitance can be suppressed. Therefore, switching losses can be reduced.

[0031] Furthermore, according to this embodiment, the surface modification treatment disrupts the atomic arrangement of crystals on the surface of the embedded electrode 20. This results in the formation of a modified layer 22 with a smaller crystal grain size. By oxidizing the modified layer 22, which has a smaller crystal grain size than the lower layer 21, the separation portion 33 of the gate insulating film 30 can be formed, thereby suppressing surface irregularities of the separation portion 33.

[0032] Furthermore, when the separation portion 33 is formed by deposition, the surface shape of the separation portion 33 inherits the surface irregularities of the embedded electrode 20. Therefore, by depositing the gate insulating film material 30 on the modified layer 22, which has a small grain size and small surface irregularities, the surface irregularities of the separation portion 33 can be suppressed.

[0033] As described above, according to this embodiment, the flatness of the separation portion 33 can be improved, and the decrease in the dielectric breakdown voltage of the separation portion 33 can be suppressed. This improves the insulation between the emitter and gate, and thus improves reliability.

[0034] The structure and manufacturing method of the semiconductor device 100 in this embodiment are examples and may be modified to the extent that they do not impede any problems. As a variation of this embodiment, the surface modification treatment may be performed on the entire wafer, or it may be selectively performed only on the embedded electrodes 20a using known photolithography techniques, etc. In particular, when the surface modification treatment is performed on the entire wafer, the damaged portion of the gate insulating film 30a other than the first portion 31 can be removed by the step of selectively removing the gate insulating film 30a shown in Figure 5.

[0035] Furthermore, when the atomic arrangement becomes random, polysilicon becomes amorphous silicon. In surface modification treatment, the surface modification treatment may be carried out until the polysilicon is converted to amorphous silicon. In other words, the modified layer 22 may be an amorphous silicon layer. Not limited to this, in surface modification treatment, the modified layer 22 may be kept in a microcrystalline state, which is intermediate between polysilicon and amorphous silicon. It is thought that the effect of suppressing the unevenness of the separated portion 33 is higher when the modified layer 22 is amorphous silicon than when it is microcrystalline.

[0036] Furthermore, when the modified layer 22 is oxidized to form the separation portion 33 of the gate insulating film 30, the modified layer 22 may or may not remain as a result of the oxidation. If the modified layer 22 does not remain, the modified layer 22 will not be present in the completed semiconductor device 100, and the separation portion 33 will be provided in contact with the lower layer 21.

[0037] After forming the modified layer 22 by the surface modification treatment shown in Figure 4, the surface of the modified layer 22 may be further planarized before forming the separation portion 33 of the gate insulating film 30. The planarization treatment is carried out, for example, by removing the surface layer of the modified layer 22 by etching. By adding the planarization treatment after surface modification, the separation portion 33 of the gate insulating film 30 that is formed later can be made even flatter.

[0038] In this embodiment, an IGBT was used as an example. However, the semiconductor device 100 is not limited to this and may be an RC (Reverse-Conducting) IGBT or a Metal Oxide Semiconductor Field Effect Transistor (MOSFET).

[0039] Furthermore, the substrate may be formed from a wide-bandgap semiconductor. The wide-bandgap semiconductor is a silicon carbide, gallium nitride-based material, or diamond. According to this embodiment, even when the semiconductor device 100 is formed from a wide-bandgap semiconductor and a high current flows through it, the reliability of the gate insulating film 30 can be improved.

[0040] The modifications described above can be appropriately applied to the semiconductor device and method for manufacturing the semiconductor device according to the following embodiments. Since the semiconductor device and method for manufacturing the semiconductor device according to the following embodiments have many similarities with Embodiment 1, the differences from Embodiment 1 will be the focus of this explanation.

[0041] Embodiment 2. This embodiment differs from Embodiment 1 in that, instead of surface modification treatment being applied to the embedded electrode, an amorphous silicon layer is formed on the embedded electrode. The other configurations are the same as in Embodiment 1. Figures 7 to 9 illustrate the manufacturing method of the semiconductor device 100 according to Embodiment 2. The steps up to forming a trench 15 on the first surface of the substrate and forming the embedded electrode 20a inside the trench 15 are the same as in Embodiment 1. Next, as shown in Figure 7, the portion of the gate insulating film 30a above the embedded electrode 20a is removed to form the first portion 31. Selective etching of the gate insulating film 30a can be achieved, for example, by wet etching technology.

[0042] Next, as shown in Figure 8, an amorphous silicon layer 234 is formed inside the trench 15, above the embedded electrode 20a and in the region where the gate insulating film 30a has been selectively removed. In other words, an amorphous silicon layer 234 is formed on the upper surface of the embedded electrode 20a, the side wall of the trench 15 above the embedded electrode 20a, and the first surface of the substrate. Amorphous silicon layer 2 34 is formed, for example, by chemical vapor deposition or plasma CVD (Chemical Vapor Deposition).

[0043] Next, as shown in Figure 9, the amorphous silicon layer 234 is oxidized to form the second portion 232 and the separation portion 233 of the gate insulating film.

[0044] In this embodiment as well, by oxidizing the amorphous silicon layer 234, which has a smaller grain size than polysilicon, to form the separation portion 233 of the gate insulating film, surface irregularities of the separation portion 233 can be suppressed.

[0045] Alternatively, a gate insulating film material may be deposited on the amorphous silicon layer 234 to form the second portion 232 and the separation portion 233 of the gate insulating film. In this case as well, surface irregularities of the separation portion 233 can be suppressed, similar to Embodiment 1.

[0046] When the amorphous silicon layer 234 is oxidized to form the separation portion 233 of the gate insulating film, the amorphous silicon layer 234 on the embedded electrode 20a may or may not remain as a result of the oxidation. If the amorphous silicon layer 234 does not remain, a structure like that shown in Figure 9 is obtained. If the amorphous silicon layer 234 remains, the amorphous silicon layer 234 will be provided between the embedded electrode 20a and the separation portion 233 in Figure 9.

[0047] Figure 10 illustrates a method for manufacturing a semiconductor device 100 according to a modified example of Embodiment 2. Figure 10 shows the state in which an amorphous silicon layer 234 has been formed. In this modified example, the amorphous silicon layer 234 is formed on top of the gate insulating film 30a. In other words, the step of selectively removing the gate insulating film 30a shown in Figure 7 is omitted. In this case, the second portion of the gate insulating film and the portion on the first surface of the substrate have a two-layer structure consisting of a silicon oxide film formed from the amorphous silicon layer 234 and the gate insulating film 30a.

[0048] The technical features described in this embodiment may be used in combination as appropriate.

[0049] The various aspects of this disclosure are summarized below as an appendix. (Note 1) circuit board and A first electrode provided on the first surface of the substrate, A second electrode is provided on the second surface of the substrate opposite to the first surface, An embedded electrode provided inside a trench formed on the first surface of the substrate, An upper electrode provided inside the trench and located on the first surface side of the embedded electrode, A gate insulating film electrically separates the side wall of the trench, the embedded electrode, and the upper electrode. Equipped with, The gate insulating film has a separation portion that separates the embedded electrode and the upper electrode. The embedded electrode has a lower layer and a modified layer located closer to the separation portion than the lower layer. The semiconductor device is characterized in that the modified layer has a smaller crystal grain size than the lower layer. (Note 2) The semiconductor device according to Appendix 1, characterized in that the modified layer has a lower impurity concentration than the lower layer. (Note 3) The semiconductor device according to Appendix 1, characterized in that the modified layer has a higher impurity concentration than the lower layer. (Note 4) The semiconductor device according to any one of the appendices 1 to 3, characterized in that the modified layer is amorphous silicon. (Note 5) The aforementioned substrate is A first conductive drift layer, A second conductive base layer provided on the first surface side of the drift layer, The second conductive collector layer provided on the second surface side of the drift layer, The first conductive emitter layer provided on the first surface side of the base layer, Equipped with, The semiconductor device according to any one of the appendices 1 to 4, characterized in that the trench penetrates the base layer and the emitter layer from the first surface of the substrate and reaches the drift layer. (Note 6) The semiconductor device according to any one of the appendices 1 to 5, characterized in that the substrate is formed of a wide-bandgap semiconductor. (Note 7) The semiconductor device according to Appendix 6, characterized in that the wide-bandgap semiconductor is silicon carbide, gallium nitride-based material, or diamond. (Note 8) circuit board and A first electrode provided on the first surface of the substrate, A second electrode is provided on the second surface of the substrate opposite to the first surface, An embedded electrode provided inside a trench formed on the first surface of the substrate, An upper electrode provided inside the trench and located on the first surface side of the embedded electrode, A gate insulating film electrically separates the side wall of the trench, the embedded electrode, and the upper electrode. Equipped with, The gate insulating film has a separation portion that separates the embedded electrode and the upper electrode. The embedded electrode has a lower layer and a modified layer located closer to the separation portion than the lower layer. The semiconductor device is characterized in that the modified layer has a lower impurity concentration than the lower layer. (Note 9) circuit board and A first electrode provided on the first surface of the substrate, A second electrode is provided on the second surface of the substrate opposite to the first surface, An embedded electrode provided inside a trench formed on the first surface of the substrate, An upper electrode provided inside the trench and located on the first surface side of the embedded electrode, A gate insulating film electrically separates the side wall of the trench, the embedded electrode, and the upper electrode. Equipped with, The gate insulating film has a separation portion that separates the embedded electrode and the upper electrode. The semiconductor device is characterized in that the embedded electrode has a lower layer and an amorphous silicon layer provided at a position closer to the separation portion than the lower layer. (Note 10) The aforementioned substrate is A first conductive drift layer, A second conductive base layer provided on the first surface side of the drift layer, The second conductive collector layer provided on the second surface side of the drift layer, The first conductive emitter layer provided on the first surface side of the base layer, Equipped with, The semiconductor device according to appendix 8 or 9, characterized in that the trench penetrates the base layer and the emitter layer from the first surface of the substrate and reaches the drift layer. (Note 11) The semiconductor device according to any one of appendices 8 to 10, characterized in that the substrate is formed of a wide-bandgap semiconductor. (Note 12) The semiconductor device according to Appendix 11, characterized in that the wide-bandgap semiconductor is silicon carbide, gallium nitride-based material, or diamond. (Note 13) A trench is formed on the first surface of a substrate having a first surface and a second surface opposite to the first surface. An embedded electrode is formed inside the trench. The embedded electrode is subjected to a surface modification treatment to form a modified layer on the first surface side of the embedded electrode. The modified layer is oxidized or deposited on the modified layer to form a gate insulating film. An upper electrode is formed on the gate insulating film inside the trench. A method for manufacturing a semiconductor device, characterized in that the modified layer has a smaller crystal grain size than the portion of the embedded electrode other than the modified layer. (Note 14) The method for manufacturing a semiconductor device according to Appendix 13, characterized in that the surface modification treatment includes at least one of ion implantation, plasma treatment, and laser irradiation. (Note 15) The method for manufacturing a semiconductor device according to Appendix 13 or 14, characterized in that the modified layer is amorphous silicon. (Note 16) A method for manufacturing a semiconductor device according to any one of appendices 13 to 15, characterized in that after forming the modified layer, the surface of the modified layer is planarized before forming the gate insulating film. (Note 17) A trench is formed on the first surface of a substrate having a first surface and a second surface opposite to the first surface. An embedded electrode is formed inside the trench. An amorphous silicon layer is formed inside the trench on the embedded electrode. The amorphous silicon layer is oxidized, or deposited on the amorphous silicon layer, to form a gate insulating film. A method for manufacturing a semiconductor device, characterized by forming an upper electrode on the gate insulating film inside the trench. [Explanation of Symbols]

[0050] 11 Drift layer, 12 Base layer, 13 Collector layer, 14 Emitter layer, 15 Trench, 17 Interlayer insulating film, 20 Embedded electrode, 20a Embedded electrode, 21 Lower layer, 22 Modified layer, 24 Upper electrode, 30 Gate insulating film, 30a Gate insulating film, 31 First part, 32 Second part, 33 Separation part, 34 Amorphous silicon layer, 41 Emitter electrode, 42 Collector electrode, 100 Semiconductor device, 232 Second part, 233 Separation part, 234 Amorphous silicon layer

Claims

1. circuit board and A first electrode provided on the first surface of the substrate, A second electrode is provided on the second surface of the substrate opposite to the first surface, An embedded electrode provided inside a trench formed on the first surface of the substrate, An upper electrode provided inside the trench and positioned on the first surface side of the embedded electrode, A gate insulating film electrically separates the side wall of the trench, the embedded electrode, and the upper electrode. Equipped with, The gate insulating film has a separation portion that separates the embedded electrode and the upper electrode. The embedded electrode has a lower layer and a modified layer located closer to the separation portion than the lower layer. The semiconductor device is characterized in that the modified layer has a smaller crystal grain size than the lower layer.

2. The semiconductor device according to claim 1, characterized in that the modified layer has a lower impurity concentration than the lower layer.

3. The semiconductor device according to claim 1, characterized in that the modified layer has a higher impurity concentration than the lower layer.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that the modified layer is amorphous silicon.

5. The aforementioned substrate is A first conductive drift layer, A second conductive base layer provided on the first surface side of the drift layer, The second conductive collector layer provided on the second surface side of the drift layer, The emitter layer of the first conductivity type provided on the first surface side of the base layer, Equipped with, The semiconductor device according to any one of claims 1 to 3, characterized in that the trench penetrates the base layer and the emitter layer from the first surface of the substrate and reaches the drift layer.

6. The semiconductor device according to any one of claims 1 to 3, characterized in that the substrate is formed of a wide-bandgap semiconductor.

7. The semiconductor device according to claim 6, characterized in that the wide bandgap semiconductor is silicon carbide, gallium nitride-based material, or diamond.

8. circuit board and A first electrode provided on the first surface of the substrate, A second electrode is provided on the second surface of the substrate opposite to the first surface, An embedded electrode provided inside a trench formed on the first surface of the substrate, An upper electrode provided inside the trench, the entire upper electrode being positioned on the first surface side of the embedded electrode, A gate insulating film electrically separates the side wall of the trench, the embedded electrode, and the upper electrode. Equipped with, The gate insulating film has a separation portion that separates the embedded electrode and the upper electrode. The embedded electrode has a lower layer and a modified layer located closer to the separation portion than the lower layer. The semiconductor device is characterized in that the modified layer has a lower impurity concentration than the lower layer.

9. circuit board and A first electrode provided on the first surface of the substrate, A second electrode is provided on the second surface of the substrate opposite to the first surface, An embedded electrode provided inside a trench formed on the first surface of the substrate, An upper electrode provided inside the trench and positioned on the first surface side of the embedded electrode, A gate insulating film electrically separates the side wall of the trench, the embedded electrode, and the upper electrode. Equipped with, The gate insulating film has a separation portion that separates the embedded electrode and the upper electrode. The semiconductor device is characterized in that the embedded electrode has a lower layer and an amorphous silicon layer provided at a position closer to the separation portion than the lower layer.

10. The aforementioned substrate is A first conductive drift layer, A second conductive base layer provided on the first surface side of the drift layer, The second conductive collector layer provided on the second surface side of the drift layer, The emitter layer of the first conductivity type provided on the first surface side of the base layer, Equipped with, The semiconductor device according to claim 8 or 9, characterized in that the trench penetrates the base layer and the emitter layer from the first surface of the substrate and reaches the drift layer.

11. The semiconductor device according to any one of claims 8 or 9, characterized in that the substrate is formed of a wide-bandgap semiconductor.

12. The semiconductor device according to claim 11, characterized in that the wide bandgap semiconductor is silicon carbide, gallium nitride-based material, or diamond.

13. A trench is formed on the first surface of a substrate having a first surface and a second surface opposite to the first surface. An embedded electrode is formed inside the trench. The embedded electrode is subjected to a surface modification treatment to form a modified layer on the first surface side of the embedded electrode. The modified layer is oxidized or deposited on the modified layer to form a gate insulating film. An upper electrode is formed on the gate insulating film inside the trench. The modified layer has a smaller crystal grain size than the portion of the embedded electrode other than the modified layer. A method for manufacturing a semiconductor device, characterized in that the surface modification treatment includes at least one of plasma treatment and laser irradiation.

14. The method for manufacturing a semiconductor device according to claim 13, characterized in that the modified layer is amorphous silicon.

15. A method for manufacturing a semiconductor device according to claim 13 or 14, characterized in that the surface of the modified layer is planarized after forming the modified layer but before forming the gate insulating film.

16. A trench is formed on the first surface of a substrate having a first surface and a second surface opposite to the first surface. An embedded electrode is formed inside the trench. An amorphous silicon layer is deposited on the embedded electrode inside the trench. The amorphous silicon layer is oxidized, or deposited on the amorphous silicon layer, to form a gate insulating film. A method for manufacturing a semiconductor device, characterized by forming an upper electrode on the gate insulating film inside the trench.

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