Semiconductor device and method for manufacturing a semiconductor device

Abstract

To provide a semiconductor device, in which degradation of heat dissipation can be suppressed even when material cost is reduced, and a manufacturing method of the semiconductor device.SOLUTION: A semiconductor device comprises: a substrate that has a first principal surface and a second principal surface which is opposite to the first principal surface; and a first conductor layer that covers the second principal surface and contains dendrite. A via hole that penetrates through the substrate and has an inner wall surface is formed in the substrate, and the first conductor layer covers the inner wall surface.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device.

Background Art

[0002] A semiconductor device is known in which a conductor layer connected to a source electrode of a field effect transistor is formed on the upper surface of an epitaxial substrate, a via hole reaching the conductor layer is formed in the epitaxial substrate, and a gold plating layer connected to the conductor layer through the via hole is formed on the lower surface of the epitaxial substrate. In such a semiconductor device, a silver paste is used to connect the gold plating layer to the conductor layer of the mounting substrate, and heat generated in the field effect transistor is released to the mounting substrate through the gold plating layer. Further, when the conductor layer of the mounting substrate is grounded, the source electrode is also grounded through the silver paste, the gold plating layer, and the conductor layer.

Prior Art Documents

Patent Documents

[0003]

Patent Document Ⅰ

Patent Document Ⅱ

Patent Document Ⅲ

Summary of the Invention

Problems to be Solved by the Invention

[0004] In order to reduce material costs, it is conceivable to use a material cheaper than gold for the plating layer. However, when a material cheaper than gold is used, there is a risk that the heat dissipation performance will deteriorate.

[0005] The purpose of the present disclosure is to provide a semiconductor device and a method for manufacturing a semiconductor device that can suppress a decrease in heat dissipation performance even when the material cost is reduced.

Means for Solving the Problems

[0006] The semiconductor device of this disclosure comprises a substrate having a first main surface and a second main surface opposite to the first main surface, and a first conductive layer covering the second main surface and containing dendrites, wherein via holes having inner wall surfaces are formed in the substrate penetrating the substrate, the first conductive layer has a second conductive layer covering the inner wall surface, provided on the first main surface and having a first surface exposed to the via holes, the first conductive layer has a first portion directly covering the first surface and a second portion directly covering the second main surface, and the average thickness of the first portion is 0.2 μm or more. The first conductive layer and bonding material are then mounted on the substrate. . [Effects of the Invention]

[0007] According to this disclosure, it is possible to suppress a decrease in heat dissipation even when reducing material costs. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a cross-sectional view showing a semiconductor device according to an embodiment. [Figure 2] Figure 2 shows an overview of the second main surface of the substrate. [Figure 3] Figure 3 is a cross-sectional view showing an example of the use of a semiconductor device according to the embodiment. [Figure 4] Figure 4 is a cross-sectional view (part 1) showing a first example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 5] Figure 5 is a cross-sectional view (part 2) showing a first example of a semiconductor device manufacturing method according to the embodiment. [Figure 6] Figure 6 is a cross-sectional view (part 3) showing a first example of a semiconductor device manufacturing method according to the embodiment. [Figure 7] Figure 7 is a cross-sectional view (part 4) showing a first example of a semiconductor device manufacturing method according to the embodiment. [Figure 8] Figure 8 is a cross-sectional view (part 5) showing a first example of a semiconductor device manufacturing method according to the embodiment. [Figure 9]FIG. 9 is a cross-sectional view (part 6) showing a first example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 10] FIG. 10 is a cross-sectional view (part 7) showing a first example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 11] FIG. 11 is a cross-sectional view (part 1) showing a second example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 12] FIG. 12 is a cross-sectional view (part 2) showing a second example of a method for manufacturing a semiconductor device according to an embodiment.

Mode for Carrying Out the Invention

[0009] [Description of Embodiments of the Present Disclosure] First, embodiments of the present disclosure will be listed and described.

[0010] 〔1〕 A semiconductor device according to one aspect of the present disclosure includes a substrate having a first main surface and a second main surface opposite to the first main surface, and a first conductor layer covering the second main surface and including dendrites. A via hole penetrating the substrate and having an inner wall surface is formed in the substrate, and the first conductor layer covers the inner wall surface.

[0011] Since the first conductor layer covers the second main surface and includes dendrites, a large contact area can be obtained between the first conductor layer and the bonding material when the semiconductor device is mounted on the mounting substrate using the bonding material. Therefore, heat is easily transferred from the first conductor layer to the bonding material. Therefore, even if a material less expensive than gold is used for the first conductor layer to reduce the material cost, a decrease in heat dissipation can be suppressed. Also, due to the large contact area obtained, excellent bonding strength can be obtained between the first conductor layer and the mounting substrate.

[0012] 〔2〕 In 〔1〕, it has a second conductor layer provided on the first main surface and having a first surface exposed in the via hole, and the first conductor layer may directly cover the first surface. In this case, a potential can be applied to the second conductor layer through the first conductor layer.

[0013] 〔3〕In [2], the average thickness of the first portion covering the first surface of the first conductor layer may be 0.2 μm or more. In this case, a potential can be more stably applied to the second conductor layer through the first conductor layer.

[0014] 〔4〕In [3], the second major surface has a central region and an annular peripheral region provided around the central region and having a certain width, the width of the annular peripheral region is within 40 μm, and the average thickness of the second portion covering the second major surface in the central region of the first conductor layer may be greater than the average thickness of the first portion. In order to stably apply a potential to the second conductor layer through the first conductor layer, it is preferable that the portion of the first conductor layer covering the second major surface is thicker than the first portion. However, even if the portion of the first conductor layer covering the second major surface is thicker than the first portion, if the first conductor layer is thin in the central region, it may be difficult to stably apply a potential. By the average thickness of the second portion being greater than the average thickness of the first portion, it is easier to achieve stable potential application.

[0015] 〔5〕In [4], the arithmetic mean surface roughness of the second portion may be 1.5 μm or more. In this case, it is easy to suppress a decrease in heat dissipation performance, and it is also easy to obtain excellent bonding strength between the first conductor layer and the mounting substrate.

[0016] 〔6〕In [4] or [5], the arithmetic mean surface roughness of the second portion may be 5 times or more the arithmetic mean surface roughness of the first portion. In this case, it is easy to suppress a decrease in heat dissipation performance, and it is also easy to obtain excellent bonding strength between the first conductor layer and the mounting substrate.

[0017] 〔7〕In any one of [2] to [6], it may have a transistor provided with a source electrode connected to the second conductor layer. In this case, a potential such as a ground potential can be applied to the source electrode through the first conductor layer and the second conductor layer.

[0018] 〔8〕In any one of [1] to [7], the first conductor layer may contain copper. In this case, it is easy to reduce the material cost.

[0019] [9] In any of [1] to [8], the substrate may have a silicon carbide substrate constituting the second main surface and a semiconductor layer provided on the silicon carbide substrate and constituting the first main surface. In this case, it is easier to obtain excellent breakdown voltage.

[0020]

[10] In any of [1] to [9], the mounting substrate having a third conductive layer and a bonding material for bonding the first conductive layer to the third conductive layer may be included. In this case, heat can be transferred from the first conductive layer to the third conductive layer.

[0021]

[11] A method for manufacturing a semiconductor device according to one aspect of the present disclosure includes the steps of forming via holes having inner walls that penetrate a substrate having a first main surface and a second main surface opposite to the first main surface, and forming a first conductive layer including dendrites that covers the second main surface and the inner wall surface.

[0022] Because the first conductive layer covers the second main surface and contains dendrites, a large contact area is obtained between the first conductive layer and the bonding material when the semiconductor device is mounted on a substrate using a bonding material. Therefore, heat is easily transferred from the first conductive layer to the bonding material. Consequently, even if a material cheaper than gold is used for the first conductive layer to reduce material costs, a decrease in heat dissipation can be suppressed. In addition, the large contact area results in excellent bonding strength between the first conductive layer and the substrate.

[0023]

[12] In

[11] , before the step of forming the via hole, there is a step of forming a second conductive layer having a first surface in contact with the first main surface, wherein the via hole is formed such that the first surface is exposed to the via hole, and the first conductive layer is formed so as to directly cover the first surface. In this case, a potential can be applied to the second conductive layer through the first conductive layer.

[0024]

[13] In

[12] , the step of forming the first conductive layer may include the steps of forming a first plating layer at a first current density by electroplating and forming a second plating layer containing dendrites on the first plating layer at a second current density higher than the first current density by electroplating. In this case, it is easier to form a thicker portion of the first conductive layer that covers the second conductive layer while incorporating dendrites into the first conductive layer. By forming a thicker portion of the first conductive layer that covers the second conductive layer, it becomes easier to stably apply a potential to the second conductive layer through the first conductive layer.

[0025]

[14] In

[12] , the step of forming the first conductive layer may include the steps of forming a second plating layer containing dendrites at a second current density by electroplating, and forming a first plating layer on the second plating layer at a first current density lower than the second current density by electroplating. In this case as well, it is easier to form a thicker portion of the first conductive layer that covers the second conductive layer while incorporating dendrites into the first conductive layer. By forming a thicker portion of the first conductive layer that covers the second conductive layer, it becomes easier to stably apply a potential to the second conductive layer through the first conductive layer.

[0026] [Details of the embodiments of this disclosure] The embodiments of this disclosure will be described in detail below, but this disclosure is not limited to these embodiments. In this specification and drawings, components having substantially the same functional configuration may be denoted by the same reference numerals to avoid redundant descriptions.

[0027] (Configuration of a semiconductor device) Figure 1 is a cross-sectional view showing a semiconductor device according to an embodiment. As shown in Figure 1, the semiconductor device 100 according to the embodiment mainly comprises a substrate 10, a source electrode 31, a drain electrode 32, and a gate electrode 33.

[0028] The substrate 10 is an epitaxial substrate and comprises a silicon carbide (SiC) substrate 11 and a semiconductor layer 12. The semiconductor layer 12 is provided on the silicon carbide substrate 11. The semiconductor layer 12 is, for example, a nitride semiconductor layer containing gallium (Ga). The nitride semiconductor layer constitutes part of a high electron mobility transistor (HEMT) 101, such as an electron transport layer (channel layer) and an electron supply layer (barrier layer). The substrate 10 has a first main surface 1 and a second main surface 2 opposite to the first main surface 1. The first main surface 1 is the upper surface of the substrate 10, and the second main surface 2 is the lower surface of the substrate 10. The silicon carbide substrate 11 constitutes the second main surface 2, and the semiconductor layer 12 constitutes the first main surface 1.

[0029] A source electrode 31, a drain electrode 32, and a gate electrode 33 are provided on a semiconductor layer 12. The source electrode 31 and the drain electrode 32 have, for example, a tantalum (Ta) layer and an aluminum (Al) layer stacked in sequence. The source electrode 31 and the drain electrode 32 make ohmic contact with the semiconductor layer 12. The gate electrode 33 has, for example, a nickel (Ni) layer, a palladium (Pd) layer, and a gold (Au) layer stacked in sequence. The gate electrode 33 makes Schottky contact with the semiconductor layer 12.

[0030] A source electrode 31, a drain electrode 32, a gate electrode 33, and an insulating film 41 covering the semiconductor layer 12 are provided. The insulating film 41 is, for example, a silicon nitride (SiN) film.

[0031] A via hole 60 is formed in the substrate 10, penetrating the substrate 10. The via hole 60 has an inner wall surface 61. The via hole 60 reaches the source electrode 31. The source electrode 31 has a first surface 34 exposed to the via hole 60. The first surface 34 can also be considered the bottom surface of the via hole 60. The source electrode 31 is an example of a second conductive layer.

[0032] The first conductive layer 50 has a plating underlayer 51 and a plating layer 52. The plating underlayer 51 directly covers the second main surface 2 of the substrate 10, the inner wall surface 61 of the via hole 60, and the first surface 34 of the via hole 60. The plating layer 52 covers the plating underlayer 51. The plating underlayer 51 has, for example, sequentially stacked nickel-chromium alloy (NiCr) layers and a gold (Au) layer. A copper layer may be used instead of the gold layer. The plating layer 52 covers the plating underlayer 51. The material of the plating layer 52 is, for example, a material that is cheaper than gold. The plating layer 52 is, for example, a copper layer. The plating layer 52 contains dendrites, and large irregularities exist on the surface of the plating layer 52.

[0033] Here, the first conductive layer 50 will be described in detail. Figure 2 is a diagram showing an outline of the second main surface 2 of the substrate 10. As shown in Figure 2, the outer shape of the second main surface 2 is, for example, rectangular. The second main surface 2 has a central region 2A and a peripheral region 2B. The central region 2A has a shape similar to the outer shape of the second main surface 2. The peripheral region 2B is provided around the central region 2A and has a certain width. The width of the peripheral region 2B is, for example, within 40 μm. The width of the peripheral region 2B may be 40 μm. As shown in Figure 1, the first conductive layer 50 has a first portion 50A and a second portion 50B. The first portion 50A covers the first surface 34. The second portion 50B covers the second main surface 2 in the central region 2A.

[0034] The average thickness of the first section 50A is, for example, 0.2 μm or more. The average thickness of the first section 50A is the average value of the thickness of the first conductive layer 50 with respect to the first surface 34.

[0035] The average thickness of the second section 50B is greater than the average thickness of the first section 50A, for example, 1.0 μm or more. The average thickness of the second section 50B is the average value of the thickness of the first conductive layer 50 with respect to the second main surface 2.

[0036] The arithmetic mean surface roughness Ra of the second part 50B is, for example, 1.5 μm or more. Furthermore, the arithmetic mean surface roughness Ra of the second part 50B is greater than that of the first part 50A, for example, 5 times or more.

[0037] (Examples of semiconductor device usage) Next, an example of the use of the semiconductor device 100 according to the embodiment will be described. Figure 3 is a cross-sectional view showing an example of the use of the semiconductor device 100 according to the embodiment.

[0038] For example, the semiconductor device 100 is used by being mounted on a mounting substrate 70, as shown in Figure 3. The mounting substrate 70 has a base portion 71 and a third conductive layer 72 provided on the base portion 71. The first conductive layer 50 is bonded to the third conductive layer 72 by a bonding material 73. The bonding material 73 includes, for example, silver. The bonding material 73 is also present in the via holes 60. The bonding material 73 is in contact with the surface of the first conductive layer 50 facing the third conductive layer 72 and with the surface of the third conductive layer 72 facing the first conductive layer 50.

[0039] A potential such as the ground potential is applied to the third conductive layer 72. This potential is applied to the source electrode 31 through the bonding material 73 and the first conductive layer 50. Therefore, the potential of the third conductive layer 72 is applied to the source electrode 31.

[0040] In this embodiment, the first conductive layer 50 covers the second main surface 2 and contains dendrites. Therefore, when mounted on the mounting substrate 70, a large contact area is obtained between the first conductive layer 50 and the bonding material 73. Consequently, heat is easily transferred from the first conductive layer 50 to the bonding material 73. Therefore, even if a less expensive material than gold, such as copper, is used for the plating layer 52 to reduce material costs, a decrease in heat dissipation can be suppressed.

[0041] Furthermore, a large contact area is obtained between the first conductive layer 50 and the bonding material 73, resulting in excellent bonding strength between the first conductive layer 50 and the mounting substrate 70. In other words, excellent bonding strength is obtained due to the so-called anchoring effect.

[0042] The first conductive layer 50 directly covers the first surface 34 of the source electrode 31, thereby allowing a potential to be applied to the source electrode 31 through the first conductive layer 50.

[0043] The average thickness of the first portion 50A is 0.2 μm or more, which allows for a more stable potential transfer to the source electrode 31 through the first conductive layer 50. The average thickness of the first portion 50A is preferably 0.5 μm or more, and more preferably 1.0 μm or more.

[0044] The fact that the average thickness 50B of the second portion is greater than the average thickness of the first portion 50A makes it easier to apply a stable potential to the source electrode 31. In order to apply a stable potential to the source electrode 31 through the first conductive layer 50, it is preferable that the portion of the first conductive layer 50 covering the second main surface 2 is thicker than the first portion 50A. However, even if the portion of the first conductive layer 50 covering the second main surface 2 is thicker than the first portion 50A, if the first conductive layer 50 is thick only in the peripheral region 2B and thin in the central region 2A, it may become difficult to apply a stable potential.

[0045] Having an arithmetic mean surface roughness Ra of 1.5 μm or more in the second portion 50B makes it easier to suppress a decrease in heat dissipation and to obtain excellent bonding strength between the first conductive layer 50 and the mounting substrate 70. The arithmetic mean surface roughness Ra of the second portion 50B is preferably 2.0 μm or more, and more preferably 3.0 μm or more.

[0046] The arithmetic mean surface roughness Ra of the second portion 50B is five times or more the arithmetic mean surface roughness Ra of the first portion 50A, which helps to suppress a decrease in heat dissipation and makes it easier to obtain excellent bonding strength between the first conductive layer 50 and the mounting substrate 70. The arithmetic mean surface roughness Ra of the second portion 50B is preferably seven times or more, and more preferably ten times or more, the arithmetic mean surface roughness Ra of the first portion 50A.

[0047] The HEMT101 is configured with a source electrode 31, which allows a potential such as ground potential to be applied to the source electrode 31 through the first conductive layer 50. In this embodiment, the source electrode 31 is an example of a second conductive layer, but the source electrode 31 may be provided separately from the second conductive layer, or the source electrode 31 may be electrically connected to the second conductive layer.

[0048] The inclusion of copper in the first conductive layer 50 makes it easier to reduce material costs.

[0049] Because the substrate 10 has a silicon carbide substrate 11 and a semiconductor layer 12, it is easy to obtain excellent voltage resistance. For example, the semiconductor device 100 can be used in applications that require high voltage resistance.

[0050] (First example of a method for manufacturing a semiconductor device) Next, a first example of a method for manufacturing the semiconductor device 100 according to the embodiment will be described. Figures 4 to 10 are cross-sectional views showing a first example of a method for manufacturing the semiconductor device 100 according to the embodiment.

[0051] In the first example, as shown in Figure 4, a semiconductor layer 12 is first formed on the silicon carbide substrate 11 by, for example, metal-organic chemical vapor deposition (MOCVD). As a result, an epitaxial substrate 10 is obtained.

[0052] Next, as shown in Figure 5, the source electrode 31, drain electrode 32, and gate electrode 33 are formed on the semiconductor layer 12.

[0053] Next, as shown in Figure 6, an insulating film 41 is formed to cover the source electrode 31, drain electrode 32, gate electrode 33, and semiconductor layer 12.

[0054] Next, as shown in Figure 7, via holes 60 are formed in the substrate 10, penetrating the substrate 10. The via holes 60 have an inner wall surface 61. The via holes 60 are formed so as to reach the source electrode 31. The first surface 34 of the source electrode 31 is exposed to the via hole 60. The first surface 34 can also be considered the bottom surface of the via hole 60.

[0055] Next, as shown in Figure 8, a plating underlayer 51 is formed to cover the second main surface 2 of the substrate 10, the inner wall surface 61 of the via hole 60, and the first surface 34 of the via hole 60. In forming the plating underlayer 51, for example, a nickel-chromium alloy layer and a gold layer are laminated in that order by a sputtering method. A copper layer may be formed instead of the gold layer.

[0056] Next, as shown in Figure 9, a first plating layer 53 is formed to cover the plating underlayer 51 by electroplating. The first plating layer 53 is formed under conditions that result in a relatively small arithmetic mean surface roughness Ra. The material of the first plating layer 53 is, for example, a material less expensive than gold. The first plating layer 53 is, for example, a copper layer.

[0057] Next, as shown in Figure 10, a plating layer 52 including the first plating layer 53 and the second plating layer 54 is formed by electroplating a second plating layer 54 on the first plating layer 53. The material of the second plating layer 54 is, for example, a material that is cheaper than gold. The second plating layer 54 is, for example, a copper layer. The second plating layer 54 is formed to include dendrites. The second plating layer 54 is formed under the condition that its arithmetic mean surface roughness Ra is greater than the arithmetic mean surface roughness Ra of the first plating layer 53. For example, the second current density when forming the second plating layer 54 is made higher than the first current density when forming the first plating layer 53. In electroplating, the higher the current density, the higher the plating rate in the area closer to the counter electrode and the lower the plating rate in the area farther from the counter electrode. Therefore, local deposition of the second plating layer 54 is promoted on the part of the substrate 10 that covers the second main surface 2, while deposition is less likely to occur inside the via holes 60. As a result, a second plating layer 54 containing dendrites can be formed.

[0058] In this way, the semiconductor device 100 according to the embodiment can be manufactured.

[0059] In the first example, it is easy to form a thicker first portion 50A of the first conductive layer 50 while incorporating dendrites into the first conductive layer 50. By forming a thicker first portion 50A, it becomes easier to stably apply a potential to the source electrode 31 through the first conductive layer 50.

[0060] (Second example of a semiconductor device manufacturing method) Next, a second example of a method for manufacturing the semiconductor device 100 according to the embodiment will be described. Figures 11 to 12 are cross-sectional views showing a second example of a method for manufacturing the semiconductor device 100 according to the embodiment.

[0061] In the second example, first, the same procedure as in the first example is followed to form the underplating layer 51 (see Figure 8). Next, as shown in Figure 11, a second plating layer 54 covering the underplating layer 51 is formed by electroplating. The material of the second plating layer 54 is, for example, a material less expensive than gold. The second plating layer 54 is, for example, a copper layer. The second plating layer 54 is formed to contain dendrites. The second plating layer 54 is formed under conditions that result in a relatively large arithmetic mean surface roughness Ra.

[0062] Next, as shown in Figure 12, a plating layer 52 including the first plating layer 53 and the second plating layer 54 is formed by electroplating, by forming the first plating layer 53 on the second plating layer 54. The material of the first plating layer 53 is, for example, a material that is cheaper than gold. The first plating layer 53 is, for example, a copper layer. The first plating layer 53 is formed under conditions that the variation in the thickness of the first plating layer 53 itself is smaller than the variation in the thickness of the second plating layer 54. For example, the first current density when forming the first plating layer 53 is lower than the second current density when forming the second plating layer 54.

[0063] In this way, the semiconductor device 100 according to the embodiment can be manufactured.

[0064] In the second example as well, it is easier to form a thicker first portion 50A of the first conductive layer 50 while incorporating dendrites into the first conductive layer 50. By forming a thicker first portion 50A, it becomes easier to stably apply a potential to the source electrode 31 through the first conductive layer 50.

[0065] The arithmetic mean surface roughness can be measured using an atomic force microscope (AFM).

[0066] Although embodiments have been described in detail above, the invention is not limited to any particular embodiment, and various modifications and changes are possible within the scope described in the claims. [Explanation of Symbols]

[0067] 1: First main surface 2: Second main surface 2A: Central area 2B: Peripheral area 10: Circuit board 11: Silicon carbide substrate 12: Semiconductor layer 31: Source electrode 32: Drain electrode 33: Gate 34: 1st page 41: Insulating film 50: First conductive layer 50A: 1st part 50B: 2nd part 51: Base layer 52: Plating layer 53: First plating layer 54: Second plating layer 60: Beer Hall 61: Interior wall surface 70: Implemented circuit board 71: Base 72: Third conductive layer 73: Bonding material 100: Semiconductor Devices 101: High electron mobility transistor

Claims

1. A substrate having a first main surface and a second main surface opposite to the first main surface, The second main surface is covered by a first conductive layer containing dendrites, It has, The substrate has via holes formed therein that penetrate the substrate and have an inner wall surface. The first conductive layer covers the inner wall surface, It has a second conductive layer provided on the first main surface and having a first surface exposed to the via hole, The first conductive layer has a first portion that directly covers the first surface and a second portion that directly covers the second main surface. The average thickness of the first portion is 0.2 μm or more. A semiconductor device mounted on a substrate via the first conductive layer and a bonding material.

2. The semiconductor device according to claim 1, wherein the thickness of the first portion of the first conductive layer is less than the thickness of the second portion.

3. A semiconductor device according to claim 1 or claim 2, having a transistor equipped with a source electrode connected to the second conductive layer.

4. The semiconductor device according to claim 1 or claim 2, wherein the first conductive layer contains copper.

5. The aforementioned substrate is The silicon carbide substrate constituting the second main surface, A semiconductor layer is provided on the silicon carbide substrate and constitutes the first main surface, A semiconductor device according to claim 1 or claim 2, having the following features.

6. The mounting substrate has a third conductive layer, The semiconductor device according to claim 1 or claim 2, wherein the bonding material bonds the first conductive layer to the third conductive layer.

7. A step of forming via holes having inner walls that penetrate the substrate, on a substrate having a first main surface and a second main surface opposite to the first main surface, A step of covering the second main surface and the inner wall surface and forming a first conductive layer containing dendrites, It has, Prior to the step of forming the via holes, there is a step of forming a second conductive layer having a first surface in contact with the first main surface, The via hole is formed such that the first surface is exposed to the via hole. The first conductive layer is formed to directly cover the first surface, The step of forming the first conductive layer is: A step of forming a second plating layer containing dendrites at a second current density by electroplating, A step of forming a first plating layer on the second plating layer by electroplating at a first current density lower than the second current density, A method for manufacturing a semiconductor device, A method for manufacturing a semiconductor device, wherein the semiconductor device is mounted on a mounting substrate via the first conductive layer and a bonding material.

8. A substrate having a first main surface and a second main surface opposite to the first main surface, A second conductive layer provided on the first main surface, The second main surface is covered by a first conductive layer containing dendrites, It has, The substrate has via holes formed that penetrate the substrate and have inner wall surfaces. The second conductive layer has a first surface that is exposed to the via hole, The first conductive layer is composed of a metal layer that directly covers the second main surface and a dendrite layer that includes the dendrites and is provided on the metal layer. Covering the aforementioned inner wall surface, It has a first portion that covers the first surface and a second portion that directly covers the second main surface, A semiconductor device mounted on a substrate via the first conductive layer and a bonding material.

9. The semiconductor device according to claim 8, wherein the average thickness of the first portion is 0.2 μm or more.

10. The semiconductor device according to claim 8 or claim 9, wherein the thickness of the first portion of the first conductive layer is less than the thickness of the second portion.

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