Semiconductor package stems, semiconductor packages

Abstract

To provide a stem for a semiconductor package capable of improving transmission characteristics when the semiconductor package is configured, and the semiconductor package.SOLUTION: A stem for a semiconductor package 1 includes: an eyelet 10 including a flat unit 11 having a first surface 11a and a second surface 11b opposite to the first surface 11a, a cavity unit 12 opened in the first surface 11a of the flat unit 11, and a metal block 13 protruding from the second surface 11b of the flat unit 11; and a lead penetrating from the first surface 11a to the second surface 11b. Volume of the metal block 13 is substantially the same as that of the cavity unit 12.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a stem for a semiconductor package and a semiconductor package.

Background Art

[0002] In a semiconductor package on which a light-emitting element is mounted, when the heat generated by the mounted light-emitting element is large, a cooling element for temperature adjustment may be mounted, and the light-emitting element may be mounted on an element mounting substrate disposed on the cooling element.

[0003] In such a structure, since the cooling element is relatively thick, the signal lead is lengthened accordingly. Therefore, the transmission line length from the signal lead to the light-emitting element becomes long, a predetermined characteristic impedance cannot be obtained, and the transmission characteristics of the semiconductor package may deteriorate.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] The present invention has been made in view of the above points, and an object thereof is to provide a stem for a semiconductor package capable of improving transmission characteristics when a semiconductor package is configured.

Means for Solving the Problems

[0006] The stem for a semiconductor package includes an eyelet having a flat plate portion having a first surface and a second surface opposite to the first surface, a cavity portion opening in the first surface of the flat plate portion, and a metal block protruding from the second surface of the flat plate portion, and penetrating from the first surface to the second surface One or more through holes, and a first lead and a second lead arranged adjacent to each other within the same through hole and sealed around the periphery of the sealing portion.The volume of the metal block is approximately the same as the volume of the cavity. [Effects of the Invention]

[0007] According to the disclosed technology, it is possible to provide a semiconductor package stem that can improve the transmission characteristics when a semiconductor package is constructed. [Brief explanation of the drawing]

[0008] [Figure 1] This figure illustrates a stem for a semiconductor package according to the first embodiment. [Figure 2] This figure illustrates a semiconductor package according to the first embodiment. [Figure 3] This is a cross-sectional view illustrating a semiconductor package related to a comparative example. [Figure 4] This figure illustrates a semiconductor package stem according to Modification 1 of the First Embodiment. [Figure 5] This figure illustrates a semiconductor package according to Modification 1 of the First Embodiment. [Figure 6] This is a diagram (part 1) explaining the results of the simulation. [Figure 7] This is a diagram (part 2) explaining the results of the simulation. [Figure 8] This is the third diagram explaining the simulation results. [Modes for carrying out the invention]

[0009] The embodiments for carrying out the invention will be described below with reference to the drawings. In each drawing, the same reference numerals are used for identical components, and redundant explanations may be omitted.

[0010] <First Embodiment> Figure 1 illustrates a stem for a semiconductor package according to the first embodiment, where Figure 1(a) is a plan view and Figure 1(b) is a cross-sectional view along line AA in Figure 1(a).

[0011] Referring to Figure 1, the semiconductor package stem 1 according to the first embodiment includes an eyelet 10, a first lead 21, a second lead 22, a third lead 23, a fourth lead 24, a fifth lead 25, a sixth lead 26, a seventh lead 27, an eighth lead 28, and a sealing portion 30. The semiconductor package stem 1 can be used, for example, as a stem for optical communication.

[0012] Furthermore, unless there is a need to distinguish between the first lead 21, the second lead 22, the third lead 23, the fourth lead 24, the fifth lead 25, the sixth lead 26, the seventh lead 27, and the eighth lead 28, they will simply be referred to as "leads."

[0013] The eyelet 10 comprises a flat plate portion 11, a cavity portion 12, and a metal block 13.

[0014] The flat plate portion 11 is a disc-shaped member and has a first surface 11a and a second surface 11b which is the opposite surface of the first surface 11a. The first surface 11a and the second surface 11b are substantially parallel. The diameters of the first surface 11a and the second surface 11b are not particularly limited and can be appropriately determined according to the purpose, for example, φ3.8 mm and φ5.6 mm. The distance D1 from the first surface 11a to the second surface 11b, that is, the thickness of the flat plate portion 11, is not particularly limited and can be appropriately determined according to the purpose. The distance D1 is, for example, about 1.0 mm to 2 mm. The flat plate portion 11 can be formed from a metal material such as iron, iron-nickel alloy, Kovar, or copper. The surface of the flat plate portion 11 may be plated with gold or the like.

[0015] In this application, "disc-shaped" refers to an object with a planar shape that is approximately circular and has a predetermined thickness. The ratio of thickness to diameter is irrelevant. It also includes objects with partially formed recesses, protrusions, through holes, etc. Furthermore, in this application, "planar view" refers to viewing the object from the direction normal to the first surface 11a of the flat plate portion 11, and "planar shape" refers to the shape of the object when viewed from the direction normal to the first surface 11a of the flat plate portion 11.

[0016] One or more notch portions having a shape that is recessed from the outer peripheral side toward the center side in a plan view may be formed at the outer edge portion of the flat plate portion 11. The notch portion is, for example, a depression having a substantially triangular or substantially rectangular planar shape. The notch portion can be used, for example, for positioning when mounting a semiconductor element on the stem 1 for a semiconductor package. Also, the notch portion can be used, for example, for positioning the rotational direction of the stem 1 for a semiconductor package.

[0017] The cavity portion 12 opens to the first surface 11a of the flat plate portion 11. In other words, the cavity portion 12 is a recess that is recessed from the first surface 11a of the flat plate portion 11 toward the second surface 11b side. The cavity portion 12 is formed by a bottom surface 12a and an inner surface 12b connected to the outer edge of the bottom surface 12a. The cavity portion 12 is a region for arranging a cooling element. The planar shape and volume of the cavity portion 12 can be appropriately determined according to the cooling element to be arranged. In the example of FIG. 1, the planar shape of the cavity portion 12 is substantially rectangular, and the space defined by the bottom surface 12a and the inner surface 12b of the cavity portion 12 is substantially a rectangular parallelepiped.

[0018] The inner surface 12b of the cavity portion 12 is preferably substantially perpendicular to the first surface 11a of the flat plate portion 11. Thereby, the area of the cavity portion 12 at the portion opening to the first surface 11a of the flat plate portion 11 can be reduced, so that the region for arranging the cooling element does not need to be made larger than necessary. As a result, the flat plate portion 11 can be miniaturized. Note that substantially perpendicular means a case where the angle formed between the objects is 90 ± 5 degrees. Also, the bottom surface 12a of the cavity portion 12 is preferably substantially parallel to the first surface 11a of the flat plate portion 11. Thereby, it becomes easy to arrange a cooling element inside the cavity portion 12. Note that substantially parallel means a case where the angle formed between the objects is 180 ± 5 degrees.

[0019] Also, the distance D2 from the first surface 11a of the flat plate portion 11 to the bottom surface 12a of the cavity portion 12 is preferably at least 1 / 2 of the distance D1 from the first surface 11a to the second surface 11b of the flat plate portion 11. Thereby, a cooling element with a relatively high height can be arranged in the cavity portion 12. The distance D2 is more preferably at least 2 / 3 of the distance D1, and even more preferably at least 3 / 4 of the distance D1. The larger the distance D2, the higher the cooling element that can be arranged in the cavity portion 12.

[0020] The metal block 13 protrudes downward from the second surface 11b of the flat plate portion 11. The protruding amount P of the metal block 13 with respect to the second surface 11b of the flat plate portion 11 is about the same as the distance D2 from the first surface 11a of the flat plate portion 11 to the bottom surface 12a of the cavity portion 12. The protruding amount P is, for example, within ±20% with respect to the distance D2. The volume of the metal block 13 is substantially the same as the volume of the cavity portion 12. Note that substantially the same means that the volume of the metal block 13 is within ±10% of the volume of the cavity portion 12. In a plan view, the metal block 13 is located at a position substantially overlapping the cavity portion 12. Note that substantially overlapping means that in a plan view, 80% or more of the area of the metal block 13 overlaps the cavity portion 12.

[0021] When the flat plate portion 11 is made of metal, the metal block 13 can be integrally formed with the flat plate portion 11. The metal block 13 can be formed simultaneously with the flat plate portion 11 and the cavity portion 12 by pressing a metal plate. By pressing the metal plate so as to provide the metal block 13 protruding on the lower surface side of the metal plate, the material that originally existed at the position of the cavity portion 12 can escape to the lower surface side of the metal plate. Therefore, it becomes easy to form the inner surface 12b of the cavity portion 12 substantially perpendicular to the first surface 11a of the flat plate portion 11.

[0022] The metal block 13 may be used in place of the lead for GND. That is, since the metal block 13 is electrically connected to the flat plate portion 11, the flat plate portion 11 can be brought to GND potential by connecting the metal block 13 to GND. This eliminates the need for a lead for GND.

[0023] Each lead penetrates from the first surface 11a to the second surface 11b of the flat plate portion 11. More specifically, each lead is inserted into a through-hole 11x that penetrates the flat plate portion 11 from the first surface 11a to the second surface 11b, with its longitudinal direction oriented in the thickness direction of the flat plate portion 11, and is sealed around the periphery by a sealing portion 30. The sealing portion 30 is made of an insulating material such as glass. As the glass, for example, hard glass with a relative permittivity of approximately 5.5 or soft glass with a relative permittivity of approximately 6.7 can be used. Note that one lead may be placed in one through-hole 11x, or multiple leads may be placed in one through-hole 11x. In the example in Figure 1, two or four leads are placed in one through-hole 11x.

[0024] The upper ends of the first lead 21 and the second lead 22 may be flush with the first surface 11a of the flat plate portion 11. Alternatively, the first lead 21 and the second lead 22 may protrude upward from the first surface 11a of the flat plate portion 11. In this case, the amount of protrusion of the first lead 21 and the second lead 22 from the first surface 11a is preferably about 0.1 mm to 0.3 mm. Leads other than the first lead 21 and the second lead 22 may also be flush with the first surface 11a of the flat plate portion 11. Alternatively, leads other than the first lead 21 and the second lead 22 may protrude upward from the first surface 11a of the flat plate portion 11.

[0025] Each lead protrudes downward from the second surface 11b of the flat plate portion 11. The amount of protrusion of each lead from the second surface 11b of the flat plate portion 11 is, for example, about 6 to 10 mm. Each lead is made of a metal such as an iron-nickel alloy or Kovar, and a gold plating or the like may be formed on the surface of each lead.

[0026] The first lead 21 and the second lead 22 are arranged adjacent to each other and serve as paths for differential signals that are electrically connected to the light-emitting element when the light-emitting element is mounted on the semiconductor package stem 1 and used as a semiconductor package. The leads other than the first lead 21 and the second lead 22 serve as paths for signals that are electrically connected to, for example, a cooling element mounted on the semiconductor package stem 1, or signals that are electrically connected to a temperature sensor mounted on the semiconductor package stem 1. The number of leads is not limited and may be increased or decreased as needed.

[0027] Figure 2 illustrates a semiconductor package according to the first embodiment, where Figure 2(a) is a plan view and Figure 2(b) is a partial cross-sectional view along line BB in Figure 2(a).

[0028] Referring to Figure 2, the semiconductor package 2 according to the first embodiment includes a semiconductor package stem 1 (see Figure 1), a cooling element 100, a substrate 110 for mounting elements, and a light-emitting element 120. In the semiconductor package 2, a cap integrated with a lens or window for extracting light emitted from the light-emitting element 120 is fixed to the semiconductor package stem 1 by resistance welding or the like, but this is a well-known structure and is therefore omitted from the illustration here. The cap is formed from a metal such as Kovar or stainless steel and hermetically seals the main components of the semiconductor package stem 1, such as the light-emitting element 120, inside.

[0029] At least a portion of the cooling element 100 is housed in the cavity portion 12. The cooling element 100 may be entirely housed in the cavity portion 12. Preferably, the amount of protrusion of the upper surface of the cooling element 100 from the first surface 11a of the flat plate portion 11 is 0.1 mm or more and 0.3 mm or less. This suppresses the amount of protrusion of the first lead 21 and the second lead 22 from the first surface 11a of the flat plate portion 11, which is advantageous for improving the transmission characteristics of the semiconductor package 2, as will be described later.

[0030] The cooling element 100 is fixed to the bottom surface 12a of the cavity 12, for example, by an adhesive with high thermal conductivity. The cooling element 100 is a cooling element that cools the light-emitting element 120 which generates heat when it emits light, and is, for example, a Peltier element. The cooling capacity of the cooling element 100 can be adjusted by changing the voltage applied from the outside. The height of the cooling element 100 is, for example, about 1 mm to 2 mm.

[0031] The element mounting substrate 110 is placed on the cooling element 100. The element mounting substrate 110 is fixed to the cooling element 100 by, for example, a highly thermally conductive adhesive. A light-emitting element 120 is mounted on the element mounting substrate 110. The light-emitting element 120 is, for example, a semiconductor laser chip with a wavelength of 1310 nm.

[0032] Wirings 111 and 112 are formed on the element mounting substrate 110, electrically connected to the terminals of the light-emitting element 120. Wirings 111 and 112 extend to the side of the element mounting substrate 110 that is close to the first lead 21 and the second lead 22. Wiring 111 is electrically connected to the first lead 21 via a linear member 130. Wiring 112 is electrically connected to the second lead 22 via a linear member 130. The linear member 130 can be, for example, a bonding wire, but is not particularly limited as long as it is a linear member.

[0033] Wirings 111 and 112 are differential wiring. For example, a positive-sequence signal is input to wiring 111 via the first lead 21 and the linear member 130. In addition, an inverted-sequence signal, which is the positive-sequence signal, is input to wiring 112 via the second lead 22 and the linear member 130.

[0034] Note that the wiring electrically connected to the terminals of the light-emitting element 120 is not limited to differential wiring. For example, it can also be wired from a coaxial structure with a single lead. In that case, it is preferable that the wiring consists of a signal line and GND wiring on both sides of the signal line using a coplanar structure. Here, the GND wiring can be made conductive to the back surface of the element mounting substrate 110 by vias or side metallization.

[0035] The semiconductor package stem 1 can improve the transmission characteristics when a semiconductor package is constructed. This will be explained below with reference to the comparative example in Figure 3.

[0036] Figure 3 is a cross-sectional view illustrating a semiconductor package related to the comparative example. Note that the plan view illustrating the semiconductor package related to the comparative example is the same as in Figure 1(a), and therefore is omitted. Figure 3 corresponds to the cross-section along line AA in Figure 1.

[0037] Referring to Figure 3, the semiconductor package 2X in the comparative example has eyelets 10 formed only from the flat plate portion 11 and does not have a cavity portion 12 and a metal block 13. The cooling element 100 is fixed to the first surface 11a of the flat plate portion 11. Therefore, the position of the element mounting substrate 110 placed on the cooling element 100 is far from the first surface 11a of the flat plate portion 11. Corresponding to the position of the element mounting substrate 110, the length of the portions of the first lead 21 and the second lead 22 that protrude from the first surface 11a is longer than that of the semiconductor package 2.

[0038] In the first lead 21 and second lead 22 that constitute the differential line, the portion sealed around the periphery by the sealing portion 30 within the through hole 11x has a structure that satisfies a predetermined differential impedance. In contrast, the portions of the first lead 21 and second lead 22 that protrude from the first surface 11a cause impedance mismatch, which interferes with high-frequency transmission. The semiconductor package 2X is prone to impedance mismatch because the portions of the first lead 21 and second lead 22 that protrude from the first surface 11a are long.

[0039] On the other hand, the semiconductor package 2, which allows the cooling element 100 to be placed in the cavity 12, can significantly shorten the length of the protruding portions of the first lead 21 and second lead 22 from the first surface 11a compared to the semiconductor package 2X. Therefore, the semiconductor package 2 is less prone to impedance mismatching, and it is easy to reduce reflection loss by matching the characteristic impedance. As a result, the transmission characteristics of the semiconductor package 2 can be improved. In other words, the semiconductor package 2 can transmit high-frequency signals well to the light-emitting element 120.

[0040] <Variation 1 of the First Embodiment> Modification 1 of the first embodiment shows an example in which a relay substrate is provided on the semiconductor package stem. In Modification 1 of the first embodiment, the description of components that are the same as those described in the previously described embodiment may be omitted.

[0041] Figure 4 illustrates a semiconductor package stem according to Modification 1 of the First Embodiment, where Figure 4(a) is a partial plan view and Figure 4(b) is a partial cross-sectional view along the CC line in Figure 4(a).

[0042] Referring to Figure 4, the semiconductor package stem 1A according to Modification 1 of the First Embodiment differs from the semiconductor package stem 1 (see Figure 1) in that it further includes a relay substrate 140 arranged on the first surface 11a side of the flat plate portion 11.

[0043] The relay substrate 140 is fixed to the first surface 11a of the flat plate portion 11 by solder such as AuSn or adhesive. Relay wirings 141 and 142 are formed on the upper surface of the relay substrate 140. Relay wiring 141 is electrically connected to the first lead 21 by conductive bonding material 150 (solder, etc.). Relay wiring 142 is electrically connected to the second lead 22 by conductive bonding material 150 (solder, etc.). For example, a glass substrate or a ceramic substrate can be used as the relay substrate 140. A resin substrate (such as a glass epoxy substrate) may also be used as the relay substrate 140.

[0044] Figure 5 illustrates a semiconductor package according to Modification 1 of the First Embodiment, where Figure 5(a) is a partial plan view and Figure 5(b) is a partial cross-sectional view along the DD line in Figure 5(a).

[0045] Referring to Figure 5, the semiconductor package 2A according to Modification 1 of the First Embodiment has a relay substrate 140, similar to Figure 4. The wiring 111 of the element mounting substrate 110 is electrically connected to the relay wiring 141 of the relay substrate 140 via the linear member 130. In addition, the wiring 112 of the element mounting substrate 110 is electrically connected to the relay wiring 142 of the relay substrate 140 via the linear member 130.

[0046] By providing the relay board 140, the desired impedance can be achieved, and the pitch of the differential line can be converted. This allows the first lead 21 and the second lead 22 to be connected to the wiring 111 and 112 of the element mounting board 110 with minimal loss.

[0047] Furthermore, in semiconductor package 2A, the linear member 130 can be made shorter compared to semiconductor package 2, thus reducing parasitic inductance. This is also advantageous for high-frequency signal transmission. It is preferable that the upper surface of the element mounting substrate 110 and the upper surface of the relay substrate 140 are on the same plane. That is, if the element mounting substrate 110 and the relay substrate 140 are the same thickness, it is preferable that the upper surface of the cooling element 100 is flush with the first surface 11a of the flat plate portion 11. This allows the linear member 130 to be made even shorter.

[0048] <simulation> Next, we will explain the simulation results for semiconductor packages 2A and 2X. The simulation was performed using the analysis software: ANSYS Electromagnetics Suite 2019 R3.

[0049] In semiconductor package 2A, the protrusion of the first lead 21 and the second lead 22 from the first surface 11a was set to 0.4 mm, and in semiconductor package 2X, the protrusion of the first lead 21 and the second lead 22 from the first surface 11a was set to 1.0 mm for the simulation. In semiconductor package 2A, the thickness of the relay substrate 140 was set to 0.2 mm, and the protrusion of the first lead 21 and the second lead 22 from the top surface of the relay substrate 140 was set to 0.2 mm.

[0050] The characteristic impedance (Ω) was determined for semiconductor packages 2A and 2X, and the results shown in Figure 6 were obtained. From Figure 6, it can be seen that the characteristic impedance of semiconductor package 2X is approximately 120Ω around 40ps. In contrast, the characteristic impedance of semiconductor package 2A is around 50Ω throughout, confirming that a characteristic impedance close to ideal can be obtained.

[0051] Furthermore, when the insertion loss (dB) was calculated for semiconductor packages 2A and 2X, the results shown in Figure 7 were obtained. From Figure 7, it can be seen that the insertion loss (dB) of semiconductor package 2A is significantly improved compared to semiconductor package 2X in the range of approximately 0 to 50 GHz.

[0052] Furthermore, when the reflection loss (dB) was calculated for semiconductor packages 2A and 2X, the results shown in Figure 8 were obtained. From Figure 8, it can be seen that the reflection loss (dB) in semiconductor package 2A is significantly improved compared to semiconductor package 2X in the range of approximately 10 to 50 GHz.

[0053] Furthermore, the results in Figures 7 and 8 indicate that while semiconductor package 2X can only transmit signals of a few GHz, semiconductor package 2A can transmit signals of 30-40 GHz well.

[0054] Although preferred embodiments have been described in detail above, the invention is not limited to the embodiments described above, and various modifications and substitutions can be made to the embodiments described above without departing from the scope of the claims. [Explanation of symbols]

[0055] 1.1A Semiconductor Package Stem 2.2A semiconductor package 10 eyelets 11 Flat plate part 11a 1st page 11b Side 2 11x through holes 12 Cavity section 12a Bottom 12b Inside surface 13 Metal Blocks 21 First Lead 22. Second lead 23 Third lead 24 4th lead 25. 5th lead 26. Sixth lead 27. 7th lead 28. 8th lead 30 Sealing part 100 Cooling elements 110-element mounting substrate 111,112 Wiring 120 light-emitting elements 130 Linear member 140 relay board 141,142 Relay wiring 150 Conductive bonding material

Claims

1. An eyelet comprising a flat plate portion having a first surface and a second surface opposite to the first surface, a cavity portion opening to the first surface of the flat plate portion, and a metal block protruding from the second surface of the flat plate portion, One or more through holes penetrating from the first surface to the second surface, The first lead and the second lead are arranged adjacent to each other within the same through hole and are sealed around the periphery of the sealing portion, A stem for semiconductor packaging, wherein the volume of the metal block is approximately the same as the volume of the cavity portion.

2. The semiconductor package stem according to claim 1, wherein, in a plan view, the metal block is located in a position that substantially overlaps with the cavity portion.

3. The aforementioned flat plate portion is made of metal. The semiconductor package stem according to claim 1, wherein the metal block is formed integrally with the flat plate portion.

4. The semiconductor package stem according to claim 1, wherein the inner surface of the cavity portion is substantially perpendicular to the first surface.

5. The semiconductor package stem according to claim 1, wherein the distance from the first surface to the bottom surface of the cavity is 1 / 2 or more of the distance from the first surface to the second surface.

6. The system further includes a relay board arranged on the first side, The relay board has relay wiring formed on it. The semiconductor package stem according to claim 1, wherein the relay wiring is electrically connected to the first lead and the second lead.

7. A semiconductor package stem according to claim 1, A cooling element, at least a portion of which is housed in the cavity, A substrate placed on the cooling element, The substrate has a light-emitting element mounted on it, Wiring electrically connected to the light-emitting element is formed on the substrate. The wiring is electrically connected to the first lead and the second lead via a linear member in a semiconductor package.

8. A semiconductor package stem according to claim 6, A cooling element is disposed on the bottom surface of the cavity portion, A substrate placed on the cooling element, The substrate has a light-emitting element mounted on it, Wiring electrically connected to the light-emitting element is formed on the substrate. A semiconductor package in which the aforementioned wiring is electrically connected to the relay wiring via a linear member.

9. The semiconductor package according to claim 8, wherein the upper surface of the substrate and the upper surface of the relay substrate are on the same plane.

10. The semiconductor package according to any one of claims 7 to 9, wherein the amount of the cooling element protruding from the first surface is 0.1 mm or more and 0.3 mm or less.

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