Semiconductor device and its driving method

Abstract

To provide a semiconductor device that can reduce the loss, and a driving method for the same.SOLUTION: A semiconductor device includes a first electrode, a first semiconductor layer provided on the first electrode in a diode region, a second semiconductor layer provided on the first electrode in an IGBT region, a third semiconductor layer provided in the diode region, a border region, and the IGBT region and existing on the first semiconductor layer and the second semiconductor layer, a fourth semiconductor layer provided on the third semiconductor layer in the border region and the IGBT region, a fifth semiconductor layer provided on the third semiconductor layer and the fourth semiconductor layer, a second electrode provided in the diode region, a third electrode provided in the IGBT region, and a fourth electrode extending from an upper surface of the fifth semiconductor layer to the third semiconductor layer and insulated electrically from the third electrode in the border region.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The embodiments relate to a semiconductor device and a method for driving the same. [Background technology]

[0002] Conventionally, RC-IGBTs (Reverse Conducting-IGBTs), which have a diode region and an IGBT (Insulated Gate Bipolar Transistor) region, have been known. In RC-IGBTs, the freewheeling current from the emitter side to the collector side of the IGBT region can be passed through the diode region.

[0003] When a freewheeling current flows through the diode region of an RC-IGBT, i.e., when the diode region is ON, the more carriers such as electrons and holes are injected into the base layer, the lower the ON voltage of the diode region becomes. The lower the ON voltage of the diode region, the smaller the steady-state loss of the diode region. On the other hand, the more carriers there are in the base layer, the greater the recovery loss when the diode region recovers. Thus, there is a trade-off relationship between the steady-state loss and the recovery loss of the diode region. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2015-141935 [Overview of the Initiative] [Problems that the invention aims to solve]

[0005] The embodiment aims to provide a semiconductor device and a method for driving the same that can reduce losses. [Means for solving the problem]

[0006] The semiconductor device according to this embodiment is a semiconductor device having a diode region, an IGBT region, and a boundary region located between the diode region and the IGBT region. The semiconductor device comprises: a first electrode provided across the diode region, the boundary region, and the IGBT region; a first semiconductor layer of a first conductivity type provided on the first electrode in the diode region; a second semiconductor layer of a second conductivity type provided on the first electrode in the IGBT region; a third semiconductor layer of a first conductivity type provided across the diode region, the boundary region, and the IGBT region, located on the first semiconductor layer in the diode region and on the second semiconductor layer in the IGBT region, with an impurity concentration lower than that of the first semiconductor layer; a fourth semiconductor layer of a first conductivity type provided on the third semiconductor layer in the boundary region and the IGBT region, with an impurity concentration higher than that of the upper layer of the third semiconductor layer; a fifth semiconductor layer of a second conductivity type provided on the third semiconductor layer in the diode region and on the fourth semiconductor layer in the boundary region and the IGBT region; and a sixth semiconductor layer of a first conductivity type provided on the upper part of the fifth semiconductor layer in the IGBT region. , in the diode region, extending from the upper surface of the fifth semiconductor layer toward the third semiconductor layer, a second electrode adjacent to the fifth semiconductor layer and the third semiconductor layer in a first direction toward the IGBT region, in the IGBT region, extending from the upper surface of the sixth semiconductor layer toward the third semiconductor layer, a third electrode adjacent to the sixth semiconductor layer, the fifth semiconductor layer, the fourth semiconductor layer, and the third semiconductor layer in a first direction, in the boundary region, extending from the upper surface of the fifth semiconductor layer toward the third semiconductor layer, a fourth electrode adjacent to the fifth semiconductor layer, the fourth semiconductor layer, and the third semiconductor layer in a first direction and electrically insulated from the third electrode, a fifth electrode provided on the fifth semiconductor layer, a first insulating film provided between the second electrode and the fifth semiconductor layer, and between the second electrode and the third semiconductor layer, between the third electrode and the fifth electrode, between the third electrode and the sixth semiconductor layer, between the third electrode and the fifth semiconductor layer,The device comprises a second insulating film provided between the third electrode and the fourth semiconductor layer, and between the third electrode and the third semiconductor layer, and a third insulating film provided between the fourth electrode and the fifth electrode, between the fourth electrode and the fifth semiconductor layer, between the fourth electrode and the fourth semiconductor layer, and between the fourth electrode and the third semiconductor layer.

[0007] The driving method according to the embodiment is a driving method for the semiconductor device described above. The first conductivity type is n-type, and the second conductivity type is p-type. In the conduction state of the diode region, a negative voltage is applied to the fourth electrode in the boundary region relative to the second electrode. Before the diode region recovers, a positive voltage is applied to the fourth electrode relative to the second electrode. While a reverse recovery current is flowing in the diode region, a negative voltage is applied to the fourth electrode relative to the second electrode.

[0008] The driving method according to the embodiment is a driving method for the semiconductor device described above. The first conductivity type is p-type, and the second conductivity type is n-type. In the conduction state of the diode region, a positive voltage is applied to the fourth electrode in the boundary region relative to the second electrode. Before the diode region recovers, a negative voltage is applied to the fourth electrode relative to the second electrode. While a reverse recovery current is flowing in the diode region, a positive voltage is applied to the fourth electrode relative to the second electrode. [Brief explanation of the drawing]

[0009] [Figure 1] This is a cross-sectional view showing a semiconductor device according to the first embodiment. [Figure 2] This is a circuit diagram showing a half-bridge circuit incorporating a semiconductor device according to the first embodiment. [Figure 3]Figure 3(a) is a graph showing the time change of the voltage between the gate electrode and emitter electrode in the IGBT region of the first semiconductor device shown in Figure 2, with time on the horizontal axis and voltage on the vertical axis; Figure 3(b) is a graph showing the time change of the voltage between the gate electrode and emitter electrode in the boundary region of the first semiconductor device, with time on the horizontal axis and voltage on the vertical axis; Figure 3(c) is a graph showing the time change of the voltage between the gate electrode and emitter electrode in the IGBT region of the second semiconductor device shown in Figure 2, with time on the horizontal axis and voltage on the vertical axis; and Figure 3(d) is... Figure 3(e) is a graph showing the time change of the voltage between the gate electrode and emitter electrode in the boundary region of the second semiconductor device, with time on the horizontal axis and voltage on the vertical axis. Figure 3(f) is a graph showing the time change of the voltage between the collector electrode and emitter electrode and the collector current of the first semiconductor device, with time on the horizontal axis and voltage and current on the vertical axis. [Figure 4] Figures 4(a) to 4(c) are schematic diagrams illustrating the operation of the boundary region. [Figure 5] Figure 5(a) is a graph with time on the horizontal axis and current and voltage on the vertical axis, showing the relationship between the time change of the current flowing through the diode region and boundary region and the time change of the voltage between the gate electrode and emitter electrode in the boundary region. Figure 5(b) is a graph with time on the horizontal axis and current on the vertical axis, showing an enlarged view of the area enclosed by the dashed line A in Figure 5(a), and showing the time change of the current flowing through the diode region and boundary region in the first embodiment and the time change of the current flowing through the diode region and boundary region in the reference example. [Figure 6] This is a cross-sectional view showing a first modified example of the semiconductor device according to the first embodiment. [Figure 7] This is a cross-sectional view showing a second modified example of the semiconductor device according to the first embodiment. [Figure 8] This is a cross-sectional view showing a semiconductor device according to a second embodiment. [Figure 9A] This is a cross-sectional view showing a first modified example of the semiconductor device according to the second embodiment. [Figure 9B] This is a top view showing a first modified example of the semiconductor device according to the second embodiment. [Figure 10] This is a cross-sectional view showing a second modified example of the semiconductor device according to the second embodiment. [Figure 11] This is a cross-sectional view showing a semiconductor device according to the third embodiment. [Figure 12] This is a cross-sectional view showing a semiconductor device according to the fourth embodiment. [Figure 13] This is a cross-sectional view showing a semiconductor device according to the fifth embodiment. [Modes for carrying out the invention]

[0010] The embodiments will be described below with reference to the drawings. Note that the drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the sizes of the parts, etc., are not necessarily the same as those of actual objects. Furthermore, even when representing the same part, the dimensions and ratios may be shown differently in different drawings. In addition, in this specification and in each drawing, elements similar to those described in previously shown drawings are denoted by the same reference numerals, and detailed explanations are omitted where appropriate.

[0011] Furthermore, in order to make the explanation easier to understand, the arrangement and configuration of each part will be described using the XYZ Cartesian coordinate system. The X, Y, and Z axes are mutually orthogonal. The direction in which the X axis extends will be referred to as the "X direction," the direction in which the Y axis extends as the "Y direction," and the direction in which the Z axis extends as the "Z direction." Also, for the sake of clarity, the direction of the arrow in the Z direction will be considered upward, and the opposite direction will be considered downward, but these directions are unrelated to the direction of gravity.

[0012] Furthermore, in the following, the + and - notations indicate the relative levels of impurity concentration in each conductivity type. Specifically, notations with a "+" indicate a relatively higher impurity concentration than those with a "-". Also, notations without a "+" or "-" indicate a relatively higher impurity concentration than those with a "+", and a relatively lower impurity concentration than those with a "-". Here, "impurity concentration" refers to the net impurity concentration after the cancellation of both donor and acceptor impurities in each region.

[0013] <First Embodiment> First, let me describe the first embodiment. Figure 1 is a cross-sectional view showing a semiconductor device according to this embodiment. The semiconductor device 100 according to this embodiment is an RC-IGBT. The semiconductor device 100 is configured with a diode region S1, an IGBT region S3, and a boundary region S2 located between the diode region S1 and the IGBT region S3.

[0014] In this embodiment, the semiconductor device 100 has a lower electrode 110 and n + A cathode layer 111 of the shape and p + A collector layer 112 of type n, an n-type layer 113, an n-type barrier layer 115, a p-type layer 116, and n + The semiconductor device comprises a shape emitter layer 117, an internal electrode 122, a gate electrode 131, another internal electrode 132, a gate electrode 141, an upper electrode 150, and a plurality of insulating films 161, 162, 163, and 164. The individual parts of the semiconductor device 100 will be described in detail below.

[0015] The lower electrode 110 is made of a conductive material such as a metal. The lower electrode 110 is provided over substantially the entire lower surface of the semiconductor device 100. That is, the lower electrode 110 is provided across the diode region S1, the boundary region S2, and the IGBT region S3. In the diode region S1, the lower electrode 110 functions as a cathode electrode, and in the IGBT region S3, it functions as a collector electrode.

[0016] n + In this embodiment, the n-shaped cathode layer 111 is disposed on the portions of the lower electrode 110 located in the diode region S1 and the boundary region S2.

[0017] p + In this embodiment, the p-shaped collector layer 112 is disposed on the portion of the lower electrode 110 located in the IGBT region S3, and is not provided in the diode region S1 and the boundary region S2. In other words, in this embodiment, from the boundary between the n + -shaped cathode layer 111 and the p + -shaped collector layer 112, a certain region towards the diode region S1 becomes the boundary region S2.

[0018] The length D1 of the boundary region S2 in the direction from the diode region S1 towards the IGBT region S3, that is, in the X direction, is not particularly limited, but is preferably shorter than the distance D2 between the upper electrode 150 and the lower electrode 110.

[0019] The n-type layer 113 is provided across the diode region S1, the boundary region S2, and the IGBT region S3. And in this embodiment, in the diode region S1 and the boundary region S2, the n-type layer 113 is disposed on the n + -shaped cathode layer 111, and in the IGBT region, it is disposed on the p + -shaped collector layer 112.

[0020] The n-type layer 113 has an n-type buffer region 114a and an n - -type base region 114b.

[0021] The n-type buffer region 114a is provided across the diode region S1, the boundary region S2, and the IGBT region S3. And in this embodiment, in the diode region S1 and the boundary region S2, the n-type buffer region 114a is disposed on the n + -shaped cathode layer 111, and in the IGBT region, it is disposed on the p + -shaped collector layer 112. The impurity concentration of the n-type buffer region 114a is, n+ The impurity concentration is lower than that of the cathode layer 111 of type n. However, the semiconductor device does not necessarily need to have an n-type buffer region.

[0022] n - The n-shaped base region 114b is located on the n-shaped buffer region 114a in the diode region S1, boundary region S2, and IGBT region S3. - The impurity concentration in the base region 114b of the n-type is lower than the impurity concentration in the buffer region 114a of the n-type.

[0023] The n-type barrier layer 115 is n in the boundary region S2 and the IGBT region S3. - It is located on the upper part of the base region 114b of the n type. In this embodiment, the n type barrier layer 115 is not provided in the diode region S1. The impurity concentration of the n type barrier layer 115 is n - The impurity concentration is higher than that of the base region 114b of the n-type layer. In other words, the impurity concentration of the n-type barrier layer 115 is higher than that of the upper layer of the n-type layer 113.

[0024] The p-type layer 116 is provided in the diode region S1, the boundary region S2, and the IGBT region S3. In the diode region S1, the p-type layer 116 is n - It is positioned on the base region 114b of the shape, n - It is in contact with the base region 114b of the shape. Furthermore, in the boundary region S2 and the IGBT region S3, the p-shaped layer 116 is placed on the n-shaped barrier layer 115 and is in contact with the n-shaped barrier layer 115.

[0025] The p-shaped layer 116 consists of a p-shaped region 116a and multiple p + It has a region 116b of the shape and a region 116a of the shape p, in the diode region S1, n - It is positioned on the base region 114b of the shape, n -It is in contact with the base region 114b of the p-type. Furthermore, in the boundary region S2 and the IGBT region S3, the p-type region 116a is located on the n-type barrier layer 115 and is in contact with the n-type barrier layer 115. The p-type region 116a functions as a p-type anode layer in the diode region S1 and as a p-type base layer in the IGBT region S3.

[0026] each p + The p-shaped region 116b is located in the upper part of the p-shaped region 116a. + The regions 116b of the shape are separated from each other in the X direction. + In the region 116b of the shape, in the diode region S1, p + It functions as the anode layer of the shape, and in the IGBT region S3, p + It functions as a contact layer.

[0027] In this embodiment, each p provided in the boundary region S2 + The length L1 in the X direction of region 116b of shape is determined by each p provided in the diode region S1. + The length L2 in the X direction of the region 116b is approximately equal to the length L2 of the region 116b. In addition, in this embodiment, each p provided in the boundary region S2 + The length of region 116b in the Y direction is determined by each p provided in the diode region S1. + The length of the region 116b in the Y direction is approximately equal to the length of the region 116b in shape. Therefore, when viewed from above, that is, in the direction from the upper electrode 150 to the lower electrode 110, each p provided in the boundary region S2 + The area of ​​region 116b is the area of ​​each p provided in the diode region S1. + The area of ​​region 116b is approximately equal to the area of ​​the region 116b. However, each p provided in the boundary region + The length of the region in the X direction and each p provided in the diode region + The relationship between the shape region and the length in the X direction, and each p provided in the boundary region + The length of the region in the Y direction and each p provided in the diode region + The relationship between the shape region and the length in the Y direction is not limited to the above.

[0028] n + The p-type emitter layer 117 is located in the upper part of the p-type layer 116 in the IGBT region S3, and is not provided in the diode region S1 or the boundary region S2.

[0029] p + A collector layer 112 of type n, buffer regions 114a and n of type n - The base region 114b is of type n, the barrier layer 115 is of type n, the layer 116 is of type p, and n + The emitter layer 117 contains a semiconductor material such as silicon.

[0030] Multiple trenches T1 are provided in the diode region S1. The multiple trenches T1 are arranged in the X direction. Each trench T1 is on the upper surface of the p-type layer 116, more specifically each p + From the upper surface of region 116b, n - It extends to the base region 114b of the shape. The lower end of each trench T1 is n - It is located above the lower surface of the base region 114b of the shape.

[0031] An internal electrode 122 is placed inside each trench T1. Each internal electrode 122 is made of a conductive material such as a metal material. Each internal electrode 122 is on the upper surface of the p-type layer 116, more specifically each p + From the upper surface of region 116b, n - It extends to the base region 114b of the shape. The lower end of each internal electrode 122 is n - It is located above the lower surface of the base region 114b of the shape. Each internal electrode 122 is located in the p-type layer 116 and n - It is adjacent to the base region 114b of the shape in the X direction.

[0032] Multiple trenches T2a are provided in the IGBT region S3. Note that Figure 1 shows one of the multiple trenches T2a. The multiple trenches T2a are arranged in the X direction. Each trench T2a is n + From the upper surface of the emitter layer 117 of the shape, n -It extends to the base region 114b of the shape. The lower end of each trench T2a is n - It is located above the lower surface of the base region 114b of the shape.

[0033] Each trench T2a contains a gate electrode 131. Each gate electrode 131 is made of a conductive material such as a metal. Each gate electrode 131 is n + From the upper surface of the emitter layer 117 of the shape, n - It extends to the base region 114b of the shape. The lower end of each gate electrode 131 is n - It is located above the lower surface of the base region 114b of the shape. Each gate electrode 131 is n + The emitter layer 117 is of type p, the p-type layer 116 is of type n, the barrier layer 115 is of type n, and n - It is adjacent to the base region 114b of the shape in the X direction.

[0034] Furthermore, a trench T2b is provided in the IGBT region S3. Trench T2b is located closer to the boundary region S2 than the multiple trenches T2. Trench T2b extends from the upper surface of the p-type layer 116 to n - It extends to the base region 114b of the shape. The lower end of trench T2b is n - It is located above the lower surface of the base region 114b of the shape.

[0035] An internal electrode 132 is positioned inside the trench T2b. The internal electrode 132 is made of a conductive material such as a metal material. The internal electrode 132 is positioned on the upper surface of the p-type layer 116, more specifically p + From the upper surface of region 116b, n - It extends to the base region 114b of the shape. The lower end of the internal electrode 132 is n - It is located above the lower surface of the base region 114b of the shape. The internal electrode 132 is located above the p-type layer 116, the n-type barrier layer 115, and n - It is adjacent to the base region 114b of the shape in the X direction.

[0036] Multiple trenches T3 are provided in the boundary region S2. The multiple trenches T3 are arranged in the X direction. Each trench T3 is on the upper surface of the p-shaped layer 116, more specifically each p + From the upper surface of region 116b, n - It extends into the base region 114b of the shape. The lower end of each trench T3 is n - It is located above the lower surface of the base region 114b of the shape.

[0037] Each trench T3 contains a gate electrode 141. Each gate electrode 141 is made of a conductive material such as a metal. Each gate electrode 141 extends from the upper surface of the p-type layer 116 to n - It extends to the base region 114b of the shape. The lower end of each gate electrode 141 is n - It is located above the lower surface of the base region 114b of the shape. Each gate electrode 141 is located above the p-shaped layer 116, the n-shaped barrier layer 115, and n - The n-shaped base region 114b is adjacent to the n-shaped barrier layer 115 in the X direction. Therefore, in this embodiment, the region of the semiconductor device 100 in which the n-shaped barrier layer 115 adjacent to the gate electrode 141 is provided corresponds to the boundary region S2.

[0038] Although Figure 1 shows an example where there are two gate electrodes 141 in the boundary region S2, the number of gate electrodes 141 in the boundary region S2 is not limited to two.

[0039] The upper electrode 150 is made of a conductive material such as a metallic material. The upper electrode 150 is placed on the p-type layer 116 in the diode region S1, the boundary region S2, and the IGBT region S3. In addition, the upper electrode 150 is placed on the internal electrode 122 in the diode region S1, on the gate electrode 141 in the boundary region S2, and on the gate electrode 131 and the internal electrode 132 in the IGBT region S3. In the diode region S1, the upper electrode 150 functions as the anode electrode, and in the IGBT region S3, it functions as the emitter electrode.

[0040] Each insulating film 161 is present in the diode region S1 between each internal electrode 122 and the upper electrode 150, between each internal electrode 122 and the p-type layer 116, and between each internal electrode 122 and the n - It is positioned between the base region 114b of the shape.

[0041] Each insulating film 162 is located between each gate electrode 131 and the upper electrode 150 in the IGBT region S3, and between each gate electrode 131 and n + Between the emitter layer 117 and the gate electrode 131 and the p-type layer 116, between the gate electrode 131 and the n-type barrier layer 115, and between the gate electrode 131 and the n-type layer - It is positioned between the base region 114b of the shape.

[0042] The insulating film 163 is present in the IGBT region S3 between the internal electrode 132 and the upper electrode 150, between the internal electrode 132 and the p-type layer 116, and between the internal electrode 132 and n - It is positioned between the base region 114b of the shape.

[0043] Each insulating film 164 in the boundary region S2 is between each gate electrode 141 and the upper electrode 150, between each gate electrode 141 and the p-type layer 116, between each gate electrode 141 and the n-type barrier layer 115, and between each gate electrode 141 and the n - It is positioned between the base region 114b of the shape. In this embodiment, each insulating film 164 is in contact with the n-shaped barrier layer 115.

[0044] Each insulating film 161, 162, 163, and 164 is made of an insulating material such as silicon oxide or silicon nitride.

[0045] In this embodiment, trenches T1, T2a, T2b, and T3 are arranged at approximately constant intervals in the X direction. Therefore, in the boundary region S2, the distance L3 in the X direction between two adjacent gate electrodes 141 is approximately equal to the distance L4 in the X direction between two adjacent internal electrodes 122 in the diode region S1. However, the relationship between distance L3 and distance L4 is not limited to the above.

[0046] The internal electrodes 122 and 132 are electrically connected to the upper electrode 150 within the semiconductor device 100. The gate electrode 131 is not electrically connected to the internal electrodes 122 and 132 and the upper electrode 150 within the semiconductor device 100. That is, the gate electrode 131 is electrically insulated from the internal electrodes 122 and 132 and the upper electrode 150. The gate electrode 141 is not electrically connected to the internal electrodes 122 and 132, the upper electrode 150, and the gate electrode 131 within the semiconductor device 100. That is, the gate electrode 141 is electrically insulated from the internal electrodes 122 and 132, the upper electrode 150, and the gate electrode 131. However, all internal electrodes 122 may be electrically insulated from the upper electrode 150 and the gate electrode 131 and electrically connected to the gate electrode 141. Also, some of the multiple internal electrodes 122 may be electrically insulated from the upper electrode 150 and the gate electrode 131 and electrically connected to the gate electrode 141.

[0047] Next, an example of the use of the semiconductor device 100 according to this embodiment will be described. Figure 2 is a circuit diagram showing a half-bridge circuit incorporating the semiconductor device according to this embodiment. The two semiconductor devices 100 can be incorporated into a half-bridge circuit C. centre One of the two semiconductor devices 100 incorporated into the bridge circuit C is called the "first semiconductor device 100A," and the other is called the "second semiconductor device 100B."

[0048] The lower electrode 110, i.e., the collector electrode, of the first semiconductor device 100A is electrically connected to the upper electrode 150, i.e., the emitter electrode, of the second semiconductor device 100B. One terminal of a load L, such as a motor, is electrically connected to the connection point CP between the lower electrode 110 of the first semiconductor device 100A and the upper electrode 150 of the second semiconductor device 100B.

[0049] Furthermore, the gate electrode 131 of the IGBT region S3 of the first semiconductor device 100A is electrically connected to the first signal source SG1 via a resistor R1, etc. The gate electrode 141 of the boundary region S2 of the first semiconductor device 100A is electrically connected to a second signal source SG2, which is separate from the first signal source SG1, via a resistor R2, etc. The gate electrode 131 of the IGBT region S3 of the second semiconductor device 100B is electrically connected to the third signal source SG3 via a resistor R3, etc. The gate electrode 141 of the boundary region S2 of the second semiconductor device 100B is electrically connected to a fourth signal source SG4, which is separate from the third signal source SG3, via a resistor R4, etc.

[0050] Figure 3(a) is a graph showing the time change of the voltage between the gate electrode and emitter electrode in the IGBT region of the first semiconductor device shown in Figure 2, with time on the horizontal axis and voltage on the vertical axis. Figure 3(b) is a graph showing the time change of the voltage between the gate electrode and the emitter electrode in the boundary region of the first semiconductor device, with time on the horizontal axis and voltage on the vertical axis. Figure 3(c) is a graph showing the time change of the voltage between the gate electrode and emitter electrode in the IGBT region of the second semiconductor device shown in Figure 2, with time on the horizontal axis and voltage on the vertical axis. Figure 3(d) is a graph showing the time change of the voltage between the gate electrode and emitter electrode in the boundary region of the second semiconductor device, with time on the horizontal axis and voltage on the vertical axis. Figure 3(e) is a graph showing the time evolution of the voltage between the collector electrode and emitter electrode of the first semiconductor device, and the time evolution of the collector current, with time on the horizontal axis and voltage and current on the vertical axis. Figure 3(f) is a graph showing the time evolution of the voltage between the collector electrode and emitter electrode of the second semiconductor device, and the time evolution of the collector current, with time on the horizontal axis and voltage and current on the vertical axis. Figures 4(a) to 4(c) are schematic diagrams illustrating the operation of the boundary region. In Figures 4(a) to 4(c), holes are represented by a circle with the letter "h" enclosed, and electrons are represented by a circle with the letter "e" enclosed. The direction of movement of holes and electrons is indicated by arrows. In the following, applying a voltage between the gate electrodes 131, 141 and the upper electrode 150 such that the potential of the gate electrodes 131, 141 is higher than the potential of the upper electrode 150, which functions as the emitter electrode or anode electrode, is also referred to as "applying a positive voltage to the gate electrodes 131, 141." Similarly, applying a voltage between the gate electrodes 131, 141 and the upper electrode 150 such that the potential of the gate electrodes 131, 141 is lower than the potential of the upper electrode 150 is also referred to as "applying a negative voltage to the gate electrodes 131, 141."

[0051] First, let's explain the state before time t1. As shown in Figure 3(a), the first signal source SG1 applies a voltage V11 to the gate electrode 131 of the IGBT region S3 of the first semiconductor device 100A before time t1. Here, the voltage V11 is a voltage lower than the threshold at which an n-type channel is formed in the p-type layer 116 of the IGBT region S3, and is, for example, a negative voltage. Therefore, before time t1, the IGBT region S3 of the first semiconductor device 100A is in the off state, as shown in Figure 3(e).

[0052] Furthermore, as shown in Figure 3(b), the second signal source SG2 applies a voltage V21 to the gate electrode 141 of the boundary region S2 of the first semiconductor device 100A before time t1. Here, the voltage V21 is a voltage lower than the threshold at which a p-type inversion layer is formed in the n-type barrier layer 115 of the boundary region S2, and is, for example, a negative voltage. Therefore, a p-type inversion layer is formed in the portion of the n-type barrier layer 115 located near the gate electrode 141.

[0053] Furthermore, as shown in Figure 3(c), the third signal source SG3 applies a voltage V12 to the gate electrode 131 of the IGBT region S3 of the second semiconductor device 100B before time t1. Here, the voltage V12 is a voltage higher than the threshold at which an n-type channel is formed in the p-type layer 116 of the IGBT region S3, and is, for example, a positive voltage. Therefore, before time t1, the IGBT region S3 of the second semiconductor device 100B is in the ON state, as shown in Figure 3(f).

[0054] Furthermore, as shown in Figure 3(d), the fourth signal source SG4 applies a voltage V21 to the gate electrode 141 of the boundary region S2 of the second semiconductor device 100B before time t1. Therefore, a p-type inversion layer is formed in the portion of the n-type barrier layer 115 located near the gate electrode 141.

[0055] Next, as shown in Figure 3(c), at time t1, the third signal source SG3 switches the voltage applied to the gate electrode 131 of the IGBT region S3 of the second semiconductor device 100B from voltage V12 to voltage V11. As a result, as shown in Figure 3(f), the IGBT region S3 of the second semiconductor device 100B switches from the ON state to the OFF state. Then, a freewheeling current begins to flow in the diode region S1 and boundary region S2 of the first semiconductor device 100A. That is, the diode region S1 and boundary region S2 of the first semiconductor device 100A are turned ON.

[0056] In this case, the second signal source SG2 continues to apply a voltage V21 to the gate electrode 141 of the boundary region S2 of the first semiconductor device 100A, as shown in Figure 3(b). Therefore, as shown in Figure 4(a), a p-type inversion layer continues to be formed in the portion of the n-type barrier layer 115 located near the gate electrode 141. Consequently, a p-type channel ch1 including this inversion layer is formed in the p-type layer 116, the n-type barrier layer 115, and the portion of the n-type layer 113 located around the gate electrode 141. Through the p-type channel ch1, from the p-type layer 116, and especially from the p+-type region 116b, n - Holes are easily injected into the base layer 114. Therefore, n- The amount of carriers in the base layer 114 increases. This reduces the on-resistance of the diode region S1 and boundary region S2 of the first semiconductor device 100A. As a result, the steady-state losses of the diode region S1 and boundary region S2 of the first semiconductor device 100A can be reduced.

[0057] Next, as shown in Figure 3(d), at time t2, before the recovery of the diode region S1 and boundary region S2 of the second semiconductor device 100B begins, the fourth signal source SG4 switches the voltage applied to the gate electrode 141 of the boundary region S2 of the second semiconductor device 100B from voltage V21 to voltage V22. Here, voltage V22 is a voltage higher than the threshold at which a p-type channel is formed in the n-type barrier layer 115, and is, for example, a positive voltage. Therefore, as shown in Figure 4(b), an n-type channel ch2 is formed in the n-type barrier layer 115 of the boundary region S2, and in the portion of the n-type layer 113 located around the gate electrode 141. In particular, the portion of the n-type barrier layer 115 located near the gate electrode 141 functions as an n-type storage layer. As a result, from the p-type layer 116, especially the p+-type region 116b, - It becomes more difficult to inject holes into the p-shaped base layer 114. Also, the voltage V22 may be a voltage higher than the threshold for forming n-shaped channels in the p-shaped layer 116. In this case, n-shaped channels are also formed in the p-shaped layer 116, and n - This makes it more difficult for holes to be injected into the shaped base layer 114. As a result, before recovery starts in the diode region S1 and boundary region S2 of the second semiconductor device 100B, n - This suppresses the increase in the amount of carriers within the base region 114b of the shape. As a result, the recovery loss of the second semiconductor device 100B can be reduced.

[0058] Next, as shown in Figure 3(a), at time t3, the first signal source SG1 switches the voltage applied to the gate electrode 131 of the IGBT region S3 of the first semiconductor device 100A from voltage V11 to voltage V12. As a result, as shown in Figure 3(e), the IGBT region S3 of the first semiconductor device 100A switches from the off state to the on state.

[0059] Figure 5(a) is a graph with time on the horizontal axis and current and voltage on the vertical axis, showing the relationship between the time change of the current flowing through the diode region and boundary region and the time change of the voltage between the gate electrode and emitter electrode in the boundary region. Figure 5(b) is a graph with time on the horizontal axis and current on the vertical axis, showing an enlarged view of the area enclosed by the dashed line A in Figure 5(a), and showing the time change of the current flowing through the diode region and boundary region in this embodiment and the time change of the current flowing through the diode region and boundary region in the reference example.

[0060] As shown in Figure 5(a), at time t3, the IGBT region S3 of the first semiconductor device 100A switches from the off state to the on state, initiating recovery in the diode region S1 and boundary region S2 of the second semiconductor device 100B. The current flowing through the diode region S1 and boundary region S2 of the second semiconductor device 100B gradually decreases from time t3 onwards, and from time t4 onwards, a reverse recovery current begins to flow from the lower electrode 110 to the upper electrode 150. Until time t4, when the reverse recovery current flows, the fourth signal source SG4 applies a voltage V22 to the gate electrode 141 of the boundary region S2 of the second semiconductor device 100B. Therefore, until time t4, an n-type channel ch2 is formed in the p-type layer 116, the n-type barrier layer 115, and the n-type layer 113 of the boundary region S2, in the portion located around the gate electrode 141. As a result, hole injection is suppressed until time t4. Consequently, the peak value Ir of the reverse recovery current can be reduced. As a result, the recovery loss in the diode region S1 and boundary region S2 of the first semiconductor device 100A can be reduced.

[0061] In the reference example shown in Figure 5(b), at time t2, the voltage applied to the gate electrode 141 in the boundary region S2 of the second semiconductor device 100B is not switched from voltage V21 to voltage V22. That is, the fourth signal source SG4 continues to apply voltage V21 to the gate electrode 141. In this case, the peak value of the reverse recovery current in this embodiment is higher than the peak value Ir of the reverse recovery current in the reference example.

[0062] Next, as shown in Figures 3(d) and 5(a), at time t4, the fourth signal source SG4 switches the voltage applied to the gate electrode 141 of the boundary region S2 of the second semiconductor device 100B from voltage V22 to voltage V21. As a result, as shown in Figure 4(c), a p-type channel ch1 is formed again in the p-type layer 116, the n-type barrier layer 115, and the n-type layer 113 of the boundary region S2. Through the p-type channel ch1, n - Hole discharge from the base layer 114 to the p-type layer 116 is promoted. As a result, recovery losses in the diode region S1 and boundary region S2 of the second semiconductor device 100B can be reduced.

[0063] Next, as shown in Figure 3(a), at time t5, the first signal source SG1 switches the voltage applied to the gate electrode 131 of the IGBT region S3 of the first semiconductor device 100A from voltage V12 to voltage V11. As a result, as shown in Figure 3(e), the IGBT region S3 of the first semiconductor device 100A switches from the ON state to the OFF state. Then, a freewheeling current begins to flow in the diode region S1 and boundary region S2 of the second semiconductor device 100B. That is, the diode region S1 and boundary region S2 of the second semiconductor device 100B are turned ON.

[0064] In this case, the fourth signal source SG4 continues to apply a voltage V21 to the gate electrode 141 of the boundary region S2 of the second semiconductor device 100B, as shown in Figure 3(d). Therefore, as shown in Figure 4(a), a p-type channel ch1 is formed in the portion of the p-type layer 116, the n-type barrier layer 115, and the n-type layer 113 located around the gate electrode 141 in the boundary region S2. Through the p-type channel ch1, the p-type layer 116 transmits signals, and in particular from the p+-type region 116b to the n-type layer. - Holes are easily injected into the base layer 114. Therefore, the on-resistance of the diode region S1 and boundary region S2 of the second semiconductor device 100B can be reduced. As a result, the steady-state loss of the diode region S1 and boundary region S2 of the second semiconductor device 100B can be reduced.

[0065] Next, as shown in Figure 3(b), the second signal source SG2 switches the voltage of the gate electrode 141 of the boundary region S2 of the first semiconductor device 100A from voltage V21 to voltage V22 at time t6, before the recovery of the diode region S1 and boundary region S2 of the first semiconductor device 100A begins. As a result, as shown in Figure 4(b), an n-type channel ch2 is formed in the n-type barrier layer 115 and the n-type layer 113 of the boundary region S2, in the portion located around the gate electrode 141. This causes the p-type layer 116, particularly the p+-type region 116b, to change direction. - It becomes more difficult to inject holes into the p-shaped base layer 114. Also, the voltage V22 may be a voltage higher than the threshold for forming n-shaped channels in the p-shaped layer 116. In this case, n-shaped channels are also formed in the p-shaped layer 116, and n - Further holes are less likely to be injected into the shaped base layer 114. As a result, the recovery loss in the diode region S1 and boundary region S2 of the first semiconductor device 100A can be reduced.

[0066] Next, as shown in Figure 3(c), at time t7, the third signal source SG3 switches the voltage applied to the gate electrode 131 of the IGBT region S3 of the second semiconductor device 100B from voltage V11 to voltage V12. As a result, as shown in Figure 3(f), the IGBT region S3 of the second semiconductor device 100B switches from the off state to the on state. This initiates the recovery of the diode region S1 and boundary region S2 of the first semiconductor device 100A.

[0067] Next, as shown in Figure 3(b), at time t8, when reverse recovery current begins to flow in the diode region S1 and boundary region S2 of the first semiconductor device 100A, the second signal source SG2 switches the voltage applied to the gate electrode 141 of the boundary region S2 of the first semiconductor device 100A from voltage V22 to voltage V21. As a result, as shown in Figure 4(c), a p-type channel ch1 is formed again in the p-type layer 116, the n-type barrier layer 115, and the n-type layer 113 of the boundary region S2, in the portion located around the gate electrode 141. Through the p-type channel ch1, n -Holes are easily discharged from the base layer 114 to the p-type layer 116. As a result, the recovery loss in the diode region S1 and boundary region S2 of the first semiconductor device 100A can be reduced.

[0068] The upper electrode 150 is electrically connected to the internal electrode 122. Therefore, when the diode region S1 is conducting, a negative voltage is applied to the gate electrode 141 in the boundary region S2 relative to the internal electrode 122. Before the diode region S1 recovers, a positive voltage is applied to the gate electrode 141 relative to the internal electrode 122. While the reverse recovery current is flowing through the diode region S1, a negative voltage is applied to the gate electrode 141 relative to the internal electrode 122.

[0069] Based on the above, the trade-off relationship between steady-state loss and recovery loss in the diode region S1 and boundary region S2 of the first semiconductor device 100A and the second semiconductor device 100B can be improved. Note that the above driving method for the semiconductor device 100 is just one example, and the driving method for the semiconductor device 100 is not particularly limited to the above method. For example, the time at which the fourth signal source SG4 switches the voltage applied to the gate electrode 141 of the boundary region S2 of the second semiconductor device 100B from voltage V22 to voltage V21 is not limited to the time t4 at which the reverse recovery current begins to flow. Similarly, the time at which the second signal source SG2 switches the voltage applied to the gate electrode 141 of the boundary region S2 of the first semiconductor device 100A from voltage V22 to voltage V21 is not limited to the time t8 at which the reverse recovery current begins to flow.

[0070] Next, the effects of this embodiment will be described. In this embodiment, the semiconductor device 100 is provided with an n-type barrier layer 115 and a gate electrode 141 adjacent to the n-type barrier layer 115 and electrically insulated from the gate electrode 131 of the IGBT region S3 in the boundary region S2. Therefore, by adjusting the voltage applied to the gate electrode 141 of the boundary region S2 separately from that applied to the gate electrode 131 of the IGBT region S3, the trade-off relationship between steady-state loss and recovery loss in the diode region S1 and boundary region S2 of the semiconductor device 100 can be improved. As a result, losses in the diode region S1 and boundary region S2 of the semiconductor device 100 can be reduced.

[0071] Furthermore, the boundary region S2 is more prone to current concentration during recovery than the diode region S1, and is therefore more susceptible to damage during recovery. In contrast, in this embodiment, an n-type barrier layer 115 and a gate electrode 141 are provided in the boundary region S2. Therefore, before recovery begins, the voltage applied to the gate electrode 141 can be adjusted to allow the n-type barrier layer 115 to function as an n-type storage layer. This allows the n-type barrier layer 115 of the boundary region S2 to function before recovery begins. - This suppresses an increase in the amount of carriers within the base region 114b of the shape. As a result, it is possible to suppress the destruction of the boundary region S2 of the semiconductor device 100 during recovery.

[0072] Furthermore, in this embodiment, the diode region S1 is not provided with an n-type barrier layer 115 and a gate electrode 141. Therefore, it is possible to suppress the decrease in the amount of carriers in the diode region S1 compared to the amount of carriers in the boundary region S2. This makes it possible to suppress an increase in the forward voltage of the diode region S1.

[0073] <First variation of the first embodiment> Next, a modified example of the first embodiment will be described. Figure 6 is a cross-sectional view showing a first modified example of the semiconductor device according to the first embodiment. In the following description, we will, in principle, only explain the differences from the first embodiment. Except for the matters described below, it is the same as the first embodiment. The same applies to the other modifications and embodiments described below.

[0074] In the first embodiment, in the boundary region S2, on the lower electrode 110, n + An example in which a cathode layer 111 of a certain shape is provided was described. However, as shown in Figure 6, in the boundary region S2, n + A cathode layer 111 of the shape does not necessarily have to be provided. And, p + A collector layer 112 of a certain shape is further provided in the boundary region S2, and in the boundary region S2, between the lower electrode 110 and the n-shaped layer 113, p+ An n-shaped collector layer 112 may be disposed. In this case, n + From the boundary between the shaped cathode layer 111 and the p + shaped collector layer of 112, a certain region toward the IGBT region S3 side becomes the boundary region S2.

[0075] Even in such a configuration, the trade-off relationship between the steady-state loss and the recovery loss of the diode region S1 and the boundary region S can be improved. Also, even in such a configuration, it is possible to suppress the boundary region S2 from being destroyed during recovery. Also, even in such a configuration, it is possible to suppress a decrease in the amount of carriers in the diode region S1.

[0076] <Second modification of the first embodiment> Next, a second modification of the first embodiment will be described. FIG. 7 is a cross-sectional view showing a second modification of the semiconductor device according to the first embodiment. n + Both the shaped cathode layer 111 and the p + shaped collector layer 112 are provided in the boundary region S2. In the boundary region S2, between the lower electrode 110 and the n-type layer 113, n + Both the shaped cathode layer 111 and the p + shaped collector layer 112 may be disposed.

[0077] Even in such a configuration, the trade-off relationship between the steady-state loss and the recovery loss of the diode region S1 and the boundary region S can be improved. Also, even in such a configuration, it is possible to suppress the boundary region S2 from being destroyed during recovery. Also, even in such a configuration, in the diode region S1, it is possible to suppress a decrease in the amount of carriers more than in the boundary region S2.

[0078] <Second embodiment> Next, a second embodiment will be described. FIG. 8 is a cross-sectional view showing the semiconductor device according to the present embodiment. In the semiconductor device 200 according to this embodiment, an n-type barrier layer 215 is also provided in the diode region S1. Furthermore, in this embodiment, each gate electrode 141 is electrically insulated from each internal electrode 122 of the diode region S1 and each gate electrode 131 and internal electrode 132 of the IGBT region S3.

[0079] In this configuration, the gate electrode 141 is electrically insulated from the internal electrode 122, and the n-type barrier layer 215 may also be provided in the diode region S1. Even in this configuration, the trade-off relationship between steady-state losses and recovery losses in the diode region S1 and the boundary region S2 can be improved. Furthermore, even in this configuration, the destruction of the boundary region S2 during recovery can be suppressed.

[0080] Furthermore, in this embodiment, the internal electrode 122 adjacent to the n-type barrier layer 215 in the diode region S1 is electrically insulated from the gate electrode 141. Therefore, it is possible to suppress the decrease in the amount of carriers in the diode region S1 compared to the amount of carriers in the boundary region S2.

[0081] <First modified example of the second embodiment> Next, a first modified example of the second embodiment will be described. Figure 9A is a cross-sectional view showing a first modified example of the semiconductor device according to the second embodiment. Figure 9B is a top view showing a first modified example of the semiconductor device according to the second embodiment. In the following description, we will, in principle, only explain the differences from the second embodiment. Except for the matters described below, it is the same as the second embodiment. The same applies to other modifications and embodiments described below. Also, in Figure 9B, the upper electrode 150 and the upper layers of the insulating films 161, 163, and 164 are omitted.

[0082] In the first and second embodiments, each p provided in the boundary region S2 + The length L1 in the X direction of region 116b of shape is such that each p provided in diode region S1 +is approximately equal to the length L2 in the X direction of the shaped region 116b. However, as shown in FIG. 9A, each p provided in the boundary region S2 + the length L21x in the X direction of the shaped region 216b is such that each p provided in the diode region S1 + the length L21x in the X direction of the shaped region 216b may be longer than the length L22x in the X direction of the shaped region 216b. Also, as shown in FIG. 9B, in the present embodiment, each p provided in the boundary region S2 + the length L21y in the Y direction of the shaped region 216b is such that each p provided in the diode region S1 + the length L21y in the Y direction of the shaped region 216b is approximately equal to the length L22y in the Y direction of the shaped region 216b. Therefore, when viewed from above, that is, in the direction from the upper electrode 150 toward the lower electrode 110, the area of each p + shaped region 216b provided in the boundary region S2 is larger than the area of each p + shaped region 216b provided in the diode region S1.

[0083] By configuring in this way, when the diode region S1 and the boundary region S2 are in the on state, holes are easily injected from the p + shaped region 216b in the boundary region S2 into the n - shaped base region 114b. Also, by configuring in this way, when the diode region S1 and the boundary region S2 are in the recovery state, holes are easily discharged from the n - shaped base region 114b in the boundary region S2 into the p + shaped region 216b. Thereby, it is possible to suppress the boundary region S2 from being destroyed during recovery.

[0084] However, the method of making the area of each p + shaped region provided in the boundary region larger than the area of each p + shaped region provided in the diode region is not limited to the above. For example, the length in the X direction of each p + shaped region provided in the boundary region is approximately equal to the length in the X direction of each p + shaped region provided in the diode region, and the length in the Y direction of each p + shaped region provided in the boundary region is such that each p +It may be longer than the length in the Y direction of the region of shape. Also, each p provided in the boundary region + The length of the region in the X direction is determined by each p provided in the diode region. + The length of the region in the X direction is longer than each p provided in the boundary region + The length of the region in the Y direction is determined by each p provided in the diode region. + It may be longer than the length of the region in the Y direction.

[0085] <Second modified example of the second embodiment> Next, a second modified example of the second embodiment will be described. Figure 10 is a cross-sectional view showing a second modified example of the semiconductor device according to the second embodiment. In the first and second embodiments, the distance L3 in the X direction between two adjacent gate electrodes 141 in the boundary region S2 is approximately equal to the distance L4 in the X direction between two adjacent internal electrodes 122 in the diode region S1. However, as shown in Figure 10, the distance L23 in the X direction between two adjacent gate electrodes 141 in the boundary region S2 may be shorter than the distance L24 in the X direction between two adjacent internal electrodes 122 in the diode region S1.

[0086] By configuring it in this way, the density of p-type channels ch1 in the boundary region S2 can be increased. Therefore, when the diode region S1 and the boundary region S2 are recovering, n - Holes are easily discharged from the base layer 114 to the p-type layer 116. This suppresses the destruction of the boundary region S2 during recovery.

[0087] <Third Embodiment> Next, a third embodiment will be described. Figure 11 is a cross-sectional view showing a semiconductor device according to this embodiment. In the semiconductor device 200 according to the second embodiment, an n-type barrier layer 215 is also provided in the diode region S1, and each gate electrode 141 in the boundary region S2 is electrically insulated from each internal electrode 122 in the diode region S1. In contrast, in the semiconductor device 300 according to this embodiment, although an n-type barrier layer 215 is also provided in the diode region S1, gate electrodes 321 are arranged in each trench T1 of the diode region S1, which are electrically connected to the gate electrodes 141 of the boundary region S2 and electrically insulated from the gate electrodes 131 and the upper electrode 150. Thus, gate electrodes 321 may be provided in the diode region S1.

[0088] Furthermore, the semiconductor device 300 according to this embodiment has n instead of n-type layer 113. - A base layer 314a of a certain shape is provided. In the boundary region S2, n + Cathode layer 111 and p + A collector layer 112 of the shape is not provided, n - A shaped base layer 314a is placed on the lower electrode 110 and is in contact with the lower electrode 110. That is, n + The cathode layer 111 and p + Between the collector layer 112 and the other layer, the impurity concentration is n + n is lower than the cathode layer 111 of the shape - An n-shaped base layer 314a is interposed. Therefore, in this embodiment, an n-shaped barrier layer 115 adjacent to the gate electrode 141 is provided in the semiconductor device 300, and n - The region where the shaped base layer 314a is in contact with the lower electrode 110 corresponds to the boundary region S2.

[0089] Thus, the diode region S1 may be provided with an n-type barrier layer 215 and gate electrodes 321 electrically connected to each gate electrode 141 of the boundary region S2. + The cathode layer 111 and p + Between the collector layer 112 and the other layer, the impurity concentration is n + n is lower than the impurity concentration of the cathode layer 111 of the shape -A base layer 314a of a certain shape may be interposed. In such a configuration, carrier concentration in the boundary region S2 can be suppressed. This prevents the boundary region S2 from being destroyed during recovery.

[0090] <Fourth Embodiment> Next, a fourth embodiment will be described. Figure 12 is a cross-sectional view showing a semiconductor device according to this embodiment. In the semiconductor device 200 according to the second embodiment, an n-type barrier layer 215 is also provided in the diode region S1, and each gate electrode 141 of the boundary region S2 is electrically insulated from each internal electrode 122 of the diode region S1. In contrast, in the semiconductor device 400 according to this embodiment, although an n-type barrier layer 215 is also provided in the diode region S1, gate electrodes 321 electrically connected to the gate electrodes 141 of the boundary region S2 are arranged in some of the trenches T1 of the diode region S1, and internal electrodes 122 electrically insulated from the gate electrodes 141 of the boundary region S2 are arranged in the remaining trenches T1 of the diode region S1.

[0091] Specifically, in this embodiment, in the diode region S1, the gate electrodes 321 and internal electrodes 122 are arranged alternately in the X direction. In contrast, in the boundary region S2, gate electrodes 141 are arranged in all trenches T3. Therefore, the average number of gate electrodes 141 provided per unit length ΔL in the X direction in the boundary region S2 is greater than the average number of gate electrodes 321 provided per unit length ΔL in the X direction in the diode region S1. The average number of gate electrodes provided per unit length ΔL in the X direction in a given region can be calculated, for example, by dividing the total number of gate electrodes in that region by the length of that region in the X direction. Thus, in this embodiment, among the regions where an n-type barrier layer 115 is provided adjacent to the gate electrode of the semiconductor device 400, the region with a smaller average number of gate electrodes per unit length ΔL corresponds to the boundary region S2.

[0092] Thus, the n-type barrier layer 215 and gate electrode 321 are also provided in the diode region S1, and the average number of gate electrode 141s provided per unit length ΔL in the X direction in the boundary region S2 may be greater than the average number of gate electrode 321s provided per unit length ΔL in the X direction in the diode region S1. In this configuration as well, the trade-off relationship between steady-state losses and recovery losses in the diode region S1 and the boundary region S2 can be improved. Furthermore, in this configuration as well, destruction of the boundary region S2 during recovery can be suppressed. Furthermore, in this configuration as well, the decrease in the amount of carriers in the diode region S1 compared to the amount of carriers in the boundary region S2 can be suppressed.

[0093] In this embodiment, no internal electrodes electrically connected to the upper electrode 150 are provided in the boundary region S2. However, if the average number of gate electrodes 141 provided per unit length ΔL in the X direction in the boundary region S2 is greater than the average number of gate electrodes 321 provided per unit length ΔL in the X direction in the diode region S1, then internal electrodes electrically connected to the upper electrode 150 may be provided in the boundary region S2.

[0094] <Fifth Embodiment> Next, a fifth embodiment will be described. Figure 13 is a cross-sectional view showing a semiconductor device according to this embodiment. In the first to fourth embodiments, the n-type barrier layer 115 is in contact with the insulating film 164. In contrast, in the semiconductor device 500 according to this embodiment, the n-type barrier layer 515 is not in contact with the insulating film 164.

[0095] The n-type barrier layer 515 is provided within the p-type layer 116, more specifically, within the p-type region 116a. The upper surface 515a, lower surface 515b, and both sides 515c of the n-type barrier layer 515 are covered by the p-type region 116a. In the p-type layer 116, the length ΔT in the X direction of the portion located between the n-type barrier layer 515 and the insulating film 164 is set to such a length that when a positive voltage V22 is applied to the gate electrode 141, the n-type inversion layer formed in the p-type layer 116 comes into contact with the n-type barrier layer 515.

[0096] Thus, the n-type barrier layer 515 is provided within the p-type layer 116, and the side surface 515c of the n-type barrier layer 515 may be covered by the p-type layer 116. Even in this configuration, the trade-off relationship between steady-state losses and recovery losses in the diode region S1 and boundary region S2 can be improved. Furthermore, even in this configuration, the destruction of the boundary region S2 during recovery can be suppressed. In addition, in this configuration, the voltage V21 can be 0V instead of a negative voltage. That is, signal sources SG2 and SG4 that apply a negative voltage to the gate electrode 141 are no longer necessary.

[0097] Although several embodiments and modifications have been described above, these can be combined with each other. For example, the semiconductor device 100 according to the first embodiment, the semiconductor device 300 according to the third embodiment, the semiconductor device 400 according to the fourth embodiment, and the semiconductor device 500 according to the fifth embodiment can be combined with the p in the first modification of the second embodiment. +A configuration relating to the area of ​​the shaped region 216b may be applied. Also, for example, a configuration relating to the distances L23 and L24 between adjacent electrodes in the second modification of the second embodiment may be applied to the semiconductor device 100 according to the first embodiment, the semiconductor device 300 according to the third embodiment, the semiconductor device 400 according to the fourth embodiment, and the semiconductor device 500 according to the fifth embodiment. Also, for example, a configuration of the first or second modification of the first embodiment may be applied to the semiconductor device 200 according to the second embodiment, the semiconductor device 400 according to the fourth embodiment, and the semiconductor device 500 according to the fifth embodiment. Also, for example, a configuration of the fifth embodiment may be applied to the semiconductor device 200 according to the second embodiment, the semiconductor device 300 according to the third embodiment, and the semiconductor device 400 according to the fourth embodiment.

[0098] Furthermore, although the above embodiments describe an example where the semiconductor device is an n-channel type RC-IGBT, the semiconductor device may also be a p-channel type RC-IGBT. In this case, the p-type of each layer in the above embodiments is replaced with an n-type, and the n-type of each layer in the above embodiments is replaced with a p-type. Also, in this case, the positive voltage in the above embodiments is replaced with a negative voltage, and the positive voltage is replaced with a negative voltage. That is, in the conduction state of the diode region, a positive voltage is applied to the gate electrode in the boundary region against the internal electrode, and before the diode region recovers, a negative voltage is applied to the gate electrode in the boundary region against the internal electrode, and while the reverse recovery current is flowing in the diode region, a positive voltage is applied to the gate electrode in the boundary region against the internal electrode.

[0099] The embodiments include the following aspects:

[0100] (Note 1) A semiconductor device comprising a diode region, an IGBT region, and a boundary region located between the diode region and the IGBT region, A first electrode provided across the diode region, the boundary region, and the IGBT region, In the diode region, a first semiconductor layer of a first conductivity type is provided on the first electrode, In the IGBT region, a second semiconductor layer of a second conductivity type is provided on the first electrode, A third semiconductor layer of first conductivity type is provided extending across the diode region, the boundary region, and the IGBT region, located on the first semiconductor layer in the diode region and on the second semiconductor layer in the IGBT region, and having an impurity concentration lower than that of the first semiconductor layer. In the boundary region and the IGBT region, a fourth semiconductor layer of a first conductivity type is provided on the third semiconductor layer, and the impurity concentration is higher than that of the upper layer of the third semiconductor layer. A fifth semiconductor layer of second conductivity type is provided on the third semiconductor layer in the diode region and on the fourth semiconductor layer in the boundary region and the IGBT region, In the IGBT region, a sixth semiconductor layer of first conductivity type is provided on the upper part of the fifth semiconductor layer, In the diode region, extending from the upper surface of the fifth semiconductor layer toward the third semiconductor layer, the fifth semiconductor layer and the third semiconductor layer, and a second electrode adjacent to the diode region toward the IGBT region in a first direction, In the IGBT region, extending from the upper surface of the sixth semiconductor layer toward the third semiconductor layer, the sixth semiconductor layer, the fifth semiconductor layer, the fourth semiconductor layer, and the third semiconductor layer, and the third electrode adjacent to the first direction, In the boundary region, extending from the upper surface of the fifth semiconductor layer toward the third semiconductor layer, the fifth semiconductor layer, the fourth semiconductor layer, and the third semiconductor layer are adjacent in the first direction to the fourth electrode, which is electrically insulated from the third electrode. A fifth electrode provided on the fifth semiconductor layer, A first insulating film is provided between the second electrode and the fifth semiconductor layer, and between the second electrode and the third semiconductor layer, A second insulating film is provided between the third electrode and the fifth electrode, between the third electrode and the sixth semiconductor layer, between the third electrode and the fifth semiconductor layer, between the third electrode and the fourth semiconductor layer, and between the third electrode and the third semiconductor layer. A third insulating film is provided between the fourth electrode and the fifth electrode, between the fourth electrode and the fifth semiconductor layer, between the fourth electrode and the fourth semiconductor layer, and between the fourth electrode and the third semiconductor layer. A semiconductor device equipped with a semiconductor device.

[0101] (Note 2) A semiconductor device comprising a diode region, an IGBT region, and a boundary region located between the diode region and the IGBT region, A first electrode provided across the diode region, the boundary region, and the IGBT region, In the diode region, a first semiconductor layer of a first conductivity type is provided on the first electrode, In the IGBT region, a second semiconductor layer of a second conductivity type is provided on the first electrode, A third semiconductor layer of first conductivity type is provided extending across the diode region, the boundary region, and the IGBT region, located on the first semiconductor layer in the diode region and on the second semiconductor layer in the IGBT region, and having an impurity concentration lower than that of the first semiconductor layer. In the diode region, the boundary region, and the IGBT region, a fourth semiconductor layer of a first conductivity type is provided on the third semiconductor layer, and the impurity concentration is higher than the impurity concentration in the upper layer of the third semiconductor layer. In the diode region, the boundary region, and the IGBT region, a fifth semiconductor layer of second conductivity type is provided on the fourth semiconductor layer, In the IGBT region, a sixth semiconductor layer of first conductivity type is provided on the upper part of the fifth semiconductor layer, In the diode region, extending from the upper surface of the fifth semiconductor layer toward the third semiconductor layer, the fifth semiconductor layer, the fourth semiconductor layer, and the third semiconductor layer, and a second electrode adjacent to the fifth semiconductor layer, the fourth semiconductor layer, and the third semiconductor layer in a first direction toward the IGBT region, In the IGBT region, extending from the upper surface of the sixth semiconductor layer toward the third semiconductor layer, the sixth semiconductor layer, the fifth semiconductor layer, the fourth semiconductor layer, and the third semiconductor layer, and the third electrode adjacent to the first direction, In the boundary region, the fourth electrode extends from the upper surface of the fifth semiconductor layer toward the third semiconductor layer, and is adjacent to the fifth semiconductor layer, the fourth semiconductor layer, and the third semiconductor layer in the first direction, and is electrically insulated from the second electrode and the third electrode. A fifth electrode provided on the fifth semiconductor layer, A first insulating film is provided between the second electrode and the fifth semiconductor layer, between the second electrode and the fourth semiconductor layer, and between the second electrode and the third semiconductor layer, A second insulating film is provided between the third electrode and the fifth electrode, between the third electrode and the sixth semiconductor layer, between the third electrode and the fifth semiconductor layer, between the third electrode and the fourth semiconductor layer, and between the third electrode and the third semiconductor layer. A third insulating film is provided between the fourth electrode and the fifth electrode, between the fourth electrode and the fifth semiconductor layer, between the fourth electrode and the fourth semiconductor layer, and between the fourth electrode and the third semiconductor layer. A semiconductor device equipped with a semiconductor device.

[0102] (Note 3) A semiconductor device comprising a diode region, an IGBT region, and a boundary region located between the diode region and the IGBT region, A first electrode provided across the diode region, the boundary region, and the IGBT region, In the diode region, a first semiconductor layer of a first conductivity type is provided on the first electrode, In the IGBT region, a second semiconductor layer of a second conductivity type is provided on the first electrode, A third semiconductor layer of first conductivity type is provided extending across the diode region, the boundary region, and the IGBT region, located on the first semiconductor layer in the diode region and on the second semiconductor layer in the IGBT region, and having an impurity concentration lower than that of the first semiconductor layer. In the IGBT region, a fourth semiconductor layer of a first conductivity type is provided on the third semiconductor layer, and the impurity concentration is higher than that of the upper layer of the third semiconductor layer. A fifth semiconductor layer of second conductivity type is provided on the third semiconductor layer in the diode region and the boundary region, and on the fourth semiconductor layer in the IGBT region, In the IGBT region, a sixth semiconductor layer of first conductivity type is provided on the upper part of the fifth semiconductor layer, In the diode region, a seventh semiconductor layer of first conductivity type is provided in the fifth semiconductor layer, and its sides are covered by the fifth semiconductor layer. In the diode region, extending from the upper surface of the fifth semiconductor layer toward the third semiconductor layer, the fifth semiconductor layer and the third semiconductor layer, and a second electrode adjacent to the diode region toward the IGBT region in a first direction, In the IGBT region, extending from the upper surface of the sixth semiconductor layer toward the third semiconductor layer, the sixth semiconductor layer, the fifth semiconductor layer, the fourth semiconductor layer, and the third semiconductor layer, and the third electrode adjacent to the first direction, In the boundary region, extending from the upper surface of the fifth semiconductor layer toward the third semiconductor layer, the fifth semiconductor layer and the third semiconductor layer are adjacent to the fourth electrode in the first direction and electrically insulated from the third electrode, A fifth electrode provided on the fifth semiconductor layer, A first insulating film is provided between the second electrode and the fifth semiconductor layer, and between the second electrode and the third semiconductor layer, A second insulating film is provided between the third electrode and the fifth electrode, between the third electrode and the sixth semiconductor layer, between the third electrode and the fifth semiconductor layer, between the third electrode and the fourth semiconductor layer, and between the third electrode and the third semiconductor layer. A third insulating film is provided between the fourth electrode and the fifth electrode, between the fourth electrode and the fifth semiconductor layer, and between the fourth electrode and the third semiconductor layer. A semiconductor device equipped with a semiconductor device.

[0103] (Note 4) In the diode region, an additional second electrode extends from the upper surface of the fifth semiconductor layer toward the third semiconductor layer and is adjacent to the second electrode in the first direction, with the fifth semiconductor layer in between. In the boundary region, an additional fourth electrode extends from the upper surface of the fifth semiconductor layer toward the third semiconductor layer and is adjacent to the fourth electrode in the first direction, with the fifth semiconductor layer in between. Furthermore, The semiconductor device according to any one of the appendices 1 to 3, wherein the distance in the first direction between the fourth electrode and the other fourth electrode is shorter than the distance in the first direction between the second electrode and the other second electrode.

[0104] (Note 5) A semiconductor device comprising a diode region, an IGBT region, and a boundary region located between the diode region and the IGBT region, A first electrode provided across the diode region, the boundary region, and the IGBT region, In the diode region, a first semiconductor layer of a first conductivity type is provided on the first electrode, In the IGBT region, a second semiconductor layer of a second conductivity type is provided on the first electrode, A third semiconductor layer of first conductivity type is provided extending across the diode region, the boundary region, and the IGBT region, located on the first semiconductor layer in the diode region and on the second semiconductor layer in the IGBT region, and having an impurity concentration lower than that of the first semiconductor layer. In the diode region, the boundary region, and the IGBT region, a fourth semiconductor layer of a first conductivity type is provided on the third semiconductor layer, and the impurity concentration is higher than the impurity concentration in the upper layer of the third semiconductor layer. In the diode region, the boundary region, and the IGBT region, a fifth semiconductor layer of second conductivity type is provided on the fourth semiconductor layer, In the IGBT region, a sixth semiconductor layer of first conductivity type is provided on the upper part of the fifth semiconductor layer, In the diode region, extending from the upper surface of the fifth semiconductor layer toward the third semiconductor layer, the fifth semiconductor layer, the fourth semiconductor layer, and the third semiconductor layer, and a second electrode adjacent to the fifth semiconductor layer, the fourth semiconductor layer, and the third semiconductor layer in a first direction toward the IGBT region, In the IGBT region, extending from the upper surface of the sixth semiconductor layer toward the third semiconductor layer, the sixth semiconductor layer, the fifth semiconductor layer, the fourth semiconductor layer, and the third semiconductor layer, and the third electrode adjacent to the first direction, In the diode region and the boundary region, a plurality of fourth electrodes extend from the upper surface of the fifth semiconductor layer toward the third semiconductor layer, are adjacent to the fifth semiconductor layer, the fourth semiconductor layer, and the third semiconductor layer in the first direction, are insulated from the second and third electrodes, and the average number of fourth electrodes provided per unit length in the first direction in the boundary region is greater than the average number provided per unit length in the first direction in the diode region. A fifth electrode provided on the fifth semiconductor layer, A first insulating film is provided between the second electrode and the fifth semiconductor layer, between the second electrode and the fourth semiconductor layer, and between the second electrode and the third semiconductor layer, A second insulating film is provided between the third electrode and the fifth electrode, between the third electrode and the sixth semiconductor layer, between the third electrode and the fifth semiconductor layer, between the third electrode and the fourth semiconductor layer, and between the third electrode and the third semiconductor layer. A plurality of third insulating films are provided between each of the fourth electrodes and the fifth electrode, between each of the fourth electrodes and the fifth semiconductor layer, between each of the fourth electrodes and the fourth semiconductor layer, and between each of the fourth electrodes and the third semiconductor layer. A semiconductor device equipped with a semiconductor device.

[0105] (Note 6) In the boundary region, a portion of the third semiconductor layer is on the first electrode and located between the first semiconductor layer and the second semiconductor layer in the first direction, as described in any one of appendices 1 to 5.

[0106] (Note 7) The semiconductor device according to any one of the appendices 1 to 5, wherein the first semiconductor layer and the second semiconductor layer are also provided in the boundary region and are located between the first electrode and the third semiconductor layer in the boundary region.

[0107] (Note 8) The semiconductor device according to any one of the appendices 1 to 5, wherein the second semiconductor layer is also provided in the boundary region and is located between the first electrode and the third semiconductor layer in the boundary region.

[0108] (Note 9) The semiconductor device according to any one of the appendices 1 to 5, wherein the first semiconductor layer is also provided in the boundary region and is located between the first electrode and the third semiconductor layer in the boundary region.

[0109] (Note 10) A semiconductor device comprising a diode region, an IGBT region, and a boundary region located between the diode region and the IGBT region, A first electrode provided across the diode region, the boundary region, and the IGBT region, In the diode region, a first semiconductor layer of a first conductivity type is provided on the first electrode, In the IGBT region, a second semiconductor layer of a second conductivity type is provided on the first electrode, A third semiconductor layer of first conductivity type is located on the first semiconductor layer in the diode region, on the first electrode in the boundary region, and on the second semiconductor layer in the IGBT region, and has an impurity concentration lower than that of the first semiconductor layer. In the diode region, the boundary region, and the IGBT region, a fourth semiconductor layer of a first conductivity type is provided on the third semiconductor layer, and the impurity concentration is higher than the impurity concentration in the upper layer of the third semiconductor layer. In the diode region, the boundary region, and the IGBT region, a fifth semiconductor layer of second conductivity type is provided on the fourth semiconductor layer, In the IGBT region, a sixth semiconductor layer of first conductivity type is provided on the upper part of the fifth semiconductor layer, In the diode region, extending from the upper surface of the fifth semiconductor layer toward the third semiconductor layer, the fifth semiconductor layer, the fourth semiconductor layer, and the third semiconductor layer, and a second electrode adjacent to the fifth semiconductor layer, the fourth semiconductor layer, and the third semiconductor layer in a first direction toward the IGBT region, In the IGBT region, extending from the upper surface of the sixth semiconductor layer toward the third semiconductor layer, the sixth semiconductor layer, the fifth semiconductor layer, the fourth semiconductor layer, and the third semiconductor layer, and the third electrode adjacent to the first direction, In the boundary region, extending from the upper surface of the fifth semiconductor layer toward the third semiconductor layer, the fifth semiconductor layer, the fourth semiconductor layer, and the third semiconductor layer are adjacent in the first direction to the fourth electrode, which is electrically insulated from the third electrode. A fifth electrode provided on the fifth semiconductor layer, A first insulating film is provided between the second electrode and the fifth semiconductor layer, between the second electrode and the fourth semiconductor layer, and between the second electrode and the third semiconductor layer, A second insulating film is provided between the third electrode and the fifth electrode, between the third electrode and the sixth semiconductor layer, between the third electrode and the fifth semiconductor layer, between the third electrode and the fourth semiconductor layer, and between the third electrode and the third semiconductor layer. A third insulating film is provided between the fourth electrode and the fifth electrode, between the fourth electrode and the fifth semiconductor layer, between the fourth electrode and the fourth semiconductor layer, and between the fourth electrode and the third semiconductor layer. A semiconductor device equipped with a semiconductor device.

[0110] (Note 11) The fifth semiconductor layer is A first semiconductor region provided across the diode region, the boundary region, and the IGBT region, The diode region, the boundary region, and the IGBT region include a plurality of second semiconductor regions provided in the upper layer of the first semiconductor region, having an impurity concentration higher than that of the first semiconductor region, and being separated from each other in a first direction. A semiconductor device according to any one of the appendices 1 to 10, wherein, when viewed from a second direction toward the first electrode from the fifth electrode, the area of ​​the second semiconductor region in the boundary region is larger than the area of ​​the second semiconductor region in the diode region.

[0111] (Note 12) The semiconductor device according to any one of the appendices 1 to 11, wherein the length of the boundary region in the first direction is shorter than the distance between the lower surface of the first semiconductor layer and the upper surface of the fifth semiconductor layer in the diode region.

[0112] (Note 13) The first conductivity type is n-type, and the second conductivity type is p-type. In the conduction state of the diode region, a negative voltage is applied to the fourth electrode in the boundary region relative to the second electrode. Before the recovery of the diode region, a positive voltage is applied to the fourth electrode relative to the second electrode. A method for driving a semiconductor device according to any one of appendices 1 to 9, 11, and 12, wherein a negative voltage is applied to the fourth electrode relative to the second electrode while a reverse recovery current is flowing through the diode region.

[0113] (Note 14) The first conductivity type is p-type, and the second conductivity type is n-type. In the conduction state of the diode region, a positive voltage is applied to the fourth electrode in the boundary region relative to the second electrode. Before the recovery of the diode region, a negative voltage is applied to the fourth electrode relative to the second electrode. A method for driving a semiconductor device according to any one of appendices 1 to 9, 11, and 12, wherein a positive voltage is applied to the fourth electrode relative to the second electrode while a reverse recovery current is flowing through the diode region.

[0114] Although embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]

[0115] 100, 100A, 100B, 200, 300, 400, 500: Semiconductor equipment 110: Lower electrode 111 :n + Shape of cathode layer 112 :p + Shape of collector layer 113 :n-type layer 114a: n-type buffer area 114b :n - Base area of ​​shape 314a :n - Shape base layer 115, 215, 515: n-type barrier layer 116 :p-type layer 116a: p-shaped region 116b, 216b:p + The domain of shape 117 :n + shape of emitter layer 122: Internal electrode 131: Grid gate 132: Internal electrode 141: Guard gate 150: Upper electrode 161, 162, 163, 164: Insulating film 321: Grid gate 515a:Top surface 515b: Bottom surface 515c: Side C: Half-bridge circuit D1: Length in the X direction of the boundary region D2 :Distance L: Load L1, L2, L21x, L21y, L22x, L22y: Length L3, L4, L23, L24: Distance R1, R2, R3, R4: Resistance S1: Diode region S2 : Boundary area S3 :IGBT area SG1, SG2, SG3, SG4: Signal source T1, T2, T2a, T2b, T3: Trench V11, V12, V21, V22: Voltage ch1: p-type channel ch2: n-shaped channel

Claims

1. A semiconductor device having a diode region, an IGBT region, and a boundary region located between the diode region and the IGBT region, A first electrode provided across the diode region, the boundary region, and the IGBT region, In the diode region, a first semiconductor layer of a first conductivity type is provided on the first electrode, In the IGBT region, a second semiconductor layer of a second conductivity type is provided on the first electrode, A third semiconductor layer of a first conductivity type is provided extending across the diode region, the boundary region, and the IGBT region, located on the first semiconductor layer in the diode region and on the second semiconductor layer in the IGBT region, and having an impurity concentration lower than that of the first semiconductor layer. In the boundary region and the IGBT region, a fourth semiconductor layer of a first conductivity type is provided on the third semiconductor layer, and the impurity concentration is higher than that of the upper layer of the third semiconductor layer. A fifth semiconductor layer of second conductivity type is provided on the third semiconductor layer in the diode region and on the fourth semiconductor layer in the boundary region and the IGBT region, In the IGBT region, a sixth semiconductor layer of first conductivity type is provided on the upper part of the fifth semiconductor layer, In the diode region, extending from the upper surface of the fifth semiconductor layer toward the third semiconductor layer, the fifth semiconductor layer and the third semiconductor layer, and a second electrode adjacent to the diode region toward the IGBT region in a first direction, In the IGBT region, extending from the upper surface of the sixth semiconductor layer toward the third semiconductor layer, the sixth semiconductor layer, the fifth semiconductor layer, the fourth semiconductor layer, and the third semiconductor layer, and the third electrode adjacent to the first direction, In the boundary region, the fourth electrode extends from the upper surface of the fifth semiconductor layer toward the third semiconductor layer, and is adjacent to the fifth semiconductor layer, the fourth semiconductor layer, and the third semiconductor layer in the first direction, and is electrically insulated from the second electrode and the third electrode. A fifth electrode provided on the fifth semiconductor layer, A first insulating film is provided between the second electrode and the fifth semiconductor layer, and between the second electrode and the third semiconductor layer, A second insulating film is provided between the third electrode and the fifth electrode, between the third electrode and the sixth semiconductor layer, between the third electrode and the fifth semiconductor layer, between the third electrode and the fourth semiconductor layer, and between the third electrode and the third semiconductor layer. A third insulating film is provided between the fourth electrode and the fifth electrode, between the fourth electrode and the fifth semiconductor layer, between the fourth electrode and the fourth semiconductor layer, and between the fourth electrode and the third semiconductor layer. A semiconductor device equipped with a semiconductor device.

2. A semiconductor device having a diode region, an IGBT region, and a boundary region located between the diode region and the IGBT region, A first electrode provided across the diode region, the boundary region, and the IGBT region, In the diode region, a first semiconductor layer of a first conductivity type is provided on the first electrode, In the IGBT region, a second semiconductor layer of a second conductivity type is provided on the first electrode, A third semiconductor layer of a first conductivity type is provided extending across the diode region, the boundary region, and the IGBT region, located on the first semiconductor layer in the diode region and on the second semiconductor layer in the IGBT region, and having an impurity concentration lower than that of the first semiconductor layer. In the diode region, the boundary region, and the IGBT region, a fourth semiconductor layer of a first conductivity type is provided on the third semiconductor layer, and the impurity concentration is higher than that of the upper layer of the third semiconductor layer. In the diode region, the boundary region, and the IGBT region, a fifth semiconductor layer of second conductivity type is provided on the fourth semiconductor layer, In the IGBT region, a sixth semiconductor layer of first conductivity type is provided on the upper part of the fifth semiconductor layer, In the diode region, extending from the upper surface of the fifth semiconductor layer toward the third semiconductor layer, the fifth semiconductor layer, the fourth semiconductor layer, and the third semiconductor layer, and a second electrode adjacent to the fifth semiconductor layer, the fourth semiconductor layer, and the third semiconductor layer in a first direction toward the IGBT region, In the IGBT region, extending from the upper surface of the sixth semiconductor layer toward the third semiconductor layer, the sixth semiconductor layer, the fifth semiconductor layer, the fourth semiconductor layer, and the third semiconductor layer, and the third electrode adjacent to the first direction, In the boundary region, the fourth electrode extends from the upper surface of the fifth semiconductor layer toward the third semiconductor layer, and is adjacent to the fifth semiconductor layer, the fourth semiconductor layer, and the third semiconductor layer in the first direction, and is electrically insulated from the second electrode and the third electrode. A fifth electrode provided on the fifth semiconductor layer, A first insulating film is provided between the second electrode and the fifth semiconductor layer, between the second electrode and the fourth semiconductor layer, and between the second electrode and the third semiconductor layer, A second insulating film is provided between the third electrode and the fifth electrode, between the third electrode and the sixth semiconductor layer, between the third electrode and the fifth semiconductor layer, between the third electrode and the fourth semiconductor layer, and between the third electrode and the third semiconductor layer. A third insulating film is provided between the fourth electrode and the fifth electrode, between the fourth electrode and the fifth semiconductor layer, between the fourth electrode and the fourth semiconductor layer, and between the fourth electrode and the third semiconductor layer. A semiconductor device equipped with a semiconductor device.

3. In the diode region, an additional second electrode extends from the upper surface of the fifth semiconductor layer toward the third semiconductor layer and is adjacent to the second electrode in the first direction, with the fifth semiconductor layer in between. In the boundary region, an additional fourth electrode extends from the upper surface of the fifth semiconductor layer toward the third semiconductor layer and is adjacent to the fourth electrode in the first direction, with the fifth semiconductor layer in between. Furthermore, The semiconductor device according to claim 1 or 2, wherein the distance between the fourth electrode and the other fourth electrode in the first direction is shorter than the distance between the second electrode and the other second electrode in the first direction.

4. A semiconductor device having a diode region, an IGBT region, and a boundary region located between the diode region and the IGBT region, A first electrode provided across the diode region, the boundary region, and the IGBT region, In the diode region, a first semiconductor layer of a first conductivity type is provided on the first electrode, In the IGBT region, a second semiconductor layer of a second conductivity type is provided on the first electrode, A third semiconductor layer of a first conductivity type is provided extending across the diode region, the boundary region, and the IGBT region, located on the first semiconductor layer in the diode region and on the second semiconductor layer in the IGBT region, and having an impurity concentration lower than that of the first semiconductor layer. In the diode region, the boundary region, and the IGBT region, a fourth semiconductor layer of a first conductivity type is provided on the third semiconductor layer, and the impurity concentration is higher than that of the upper layer of the third semiconductor layer. In the diode region, the boundary region, and the IGBT region, a fifth semiconductor layer of second conductivity type is provided on the fourth semiconductor layer, In the IGBT region, a sixth semiconductor layer of first conductivity type is provided on the upper part of the fifth semiconductor layer, In the diode region, extending from the upper surface of the fifth semiconductor layer toward the third semiconductor layer, the fifth semiconductor layer, the fourth semiconductor layer, and the third semiconductor layer, and a second electrode adjacent to the fifth semiconductor layer, the fourth semiconductor layer, and the third semiconductor layer in a first direction toward the IGBT region, In the IGBT region, extending from the upper surface of the sixth semiconductor layer toward the third semiconductor layer, the sixth semiconductor layer, the fifth semiconductor layer, the fourth semiconductor layer, and the third semiconductor layer, and the third electrode adjacent to the first direction, In the diode region and the boundary region, a plurality of fourth electrodes are provided, extending from the upper surface of the fifth semiconductor layer toward the third semiconductor layer, adjacent to the fifth semiconductor layer, the fourth semiconductor layer, and the third semiconductor layer in the first direction, insulated from the second electrode and the third electrode, and the average number of fourth electrodes provided per unit length in the first direction in the boundary region is greater than the average number provided per unit length in the first direction in the diode region. A fifth electrode provided on the fifth semiconductor layer, A first insulating film is provided between the second electrode and the fifth semiconductor layer, between the second electrode and the fourth semiconductor layer, and between the second electrode and the third semiconductor layer, A second insulating film is provided between the third electrode and the fifth electrode, between the third electrode and the sixth semiconductor layer, between the third electrode and the fifth semiconductor layer, between the third electrode and the fourth semiconductor layer, and between the third electrode and the third semiconductor layer. A plurality of third insulating films are provided between each of the fourth electrodes and the fifth electrode, between each of the fourth electrodes and the fifth semiconductor layer, between each of the fourth electrodes and the fourth semiconductor layer, and between each of the fourth electrodes and the third semiconductor layer. A semiconductor device equipped with a semiconductor device.

5. The semiconductor device according to any one of claims 1 to 4, wherein in the boundary region, a portion of the third semiconductor layer is on the first electrode and located between the first semiconductor layer and the second semiconductor layer in a first direction.

6. The semiconductor device according to any one of claims 1 to 4, wherein the first semiconductor layer and the second semiconductor layer are also provided in the boundary region and are located between the first electrode and the third semiconductor layer in the boundary region.

7. The semiconductor device according to any one of claims 1 to 4, wherein the second semiconductor layer is also provided in the boundary region and is located between the first electrode and the third semiconductor layer in the boundary region.

8. The semiconductor device according to any one of claims 1 to 4, wherein the first semiconductor layer is also provided in the boundary region and is located between the first electrode and the third semiconductor layer in the boundary region.

9. A semiconductor device having a diode region, an IGBT region, and a boundary region located between the diode region and the IGBT region, A first electrode provided across the diode region, the boundary region, and the IGBT region, In the diode region, a first semiconductor layer of a first conductivity type is provided on the first electrode, In the IGBT region, a second semiconductor layer of a second conductivity type is provided on the first electrode, A third semiconductor layer having a first conductivity type, located on the first semiconductor layer in the diode region, on the first electrode in the boundary region, and on the second semiconductor layer in the IGBT region, wherein the impurity concentration is lower than that of the first semiconductor layer. In the diode region, the boundary region, and the IGBT region, a fourth semiconductor layer of a first conductivity type is provided on the third semiconductor layer, and the impurity concentration is higher than that of the upper layer of the third semiconductor layer. In the diode region, the boundary region, and the IGBT region, a fifth semiconductor layer of second conductivity type is provided on the fourth semiconductor layer, In the IGBT region, a sixth semiconductor layer of first conductivity type is provided on the upper part of the fifth semiconductor layer, In the diode region, extending from the upper surface of the fifth semiconductor layer toward the third semiconductor layer, the fifth semiconductor layer, the fourth semiconductor layer, and the third semiconductor layer, and a second electrode adjacent to the fifth semiconductor layer, the fourth semiconductor layer, and the third semiconductor layer in a first direction toward the IGBT region, In the IGBT region, extending from the upper surface of the sixth semiconductor layer toward the third semiconductor layer, the sixth semiconductor layer, the fifth semiconductor layer, the fourth semiconductor layer, and the third semiconductor layer, and the third electrode adjacent to the first direction, In the boundary region, the fourth electrode extends from the upper surface of the fifth semiconductor layer toward the third semiconductor layer, and is adjacent to the fifth semiconductor layer, the fourth semiconductor layer, and the third semiconductor layer in the first direction, and is electrically insulated from the second electrode and the third electrode. A fifth electrode provided on the fifth semiconductor layer, A first insulating film is provided between the second electrode and the fifth semiconductor layer, between the second electrode and the fourth semiconductor layer, and between the second electrode and the third semiconductor layer, A second insulating film is provided between the third electrode and the fifth electrode, between the third electrode and the sixth semiconductor layer, between the third electrode and the fifth semiconductor layer, between the third electrode and the fourth semiconductor layer, and between the third electrode and the third semiconductor layer. A third insulating film is provided between the fourth electrode and the fifth electrode, between the fourth electrode and the fifth semiconductor layer, between the fourth electrode and the fourth semiconductor layer, and between the fourth electrode and the third semiconductor layer. Equipped with, A semiconductor device wherein the average number of second electrodes provided per unit length in the first direction in the diode region is less than the average number of fourth electrodes provided per unit length in the first direction in the boundary region.

10. The fifth semiconductor layer is A first semiconductor region is provided extending over the diode region, the boundary region, and the IGBT region, The diode region, the boundary region, and the IGBT region include a plurality of second semiconductor regions provided in the upper layer of the first semiconductor region, having an impurity concentration higher than that of the first semiconductor region, and being separated from each other in a first direction. The semiconductor device according to any one of claims 1 to 9, wherein, when viewed from a second direction toward the first electrode from the fifth electrode, the area of ​​the second semiconductor region in the boundary region is larger than the area of ​​the second semiconductor region in the diode region.

11. The semiconductor device according to any one of claims 1 to 10, wherein the length of the boundary region in the first direction is shorter than the distance between the lower surface of the first semiconductor layer and the upper surface of the fifth semiconductor layer in the diode region.

12. The first conductivity type is n-type, and the second conductivity type is p-type. In the conduction state of the diode region, a negative voltage is applied to the fourth electrode in the boundary region relative to the second electrode. Before the recovery of the diode region, a positive voltage is applied to the fourth electrode relative to the second electrode. A method for driving a semiconductor device according to any one of claims 1 to 8, 10, and 11, wherein a negative voltage is applied to the fourth electrode relative to the second electrode while a reverse recovery current is flowing through the diode region.

13. A semiconductor device having a diode region, an IGBT region, and a boundary region located between the diode region and the IGBT region, A first electrode provided across the diode region, the boundary region, and the IGBT region, In the diode region, a first semiconductor layer of a first conductivity type is provided on the first electrode, In the IGBT region, a second semiconductor layer of a second conductivity type is provided on the first electrode, A third semiconductor layer of a first conductivity type is provided extending across the diode region, the boundary region, and the IGBT region, located on the first semiconductor layer in the diode region and on the second semiconductor layer in the IGBT region, and having an impurity concentration lower than that of the first semiconductor layer. In the boundary region and the IGBT region, a fourth semiconductor layer of a first conductivity type is provided on the third semiconductor layer, and the impurity concentration is higher than that of the upper layer of the third semiconductor layer. A fifth semiconductor layer of second conductivity type is provided on the third semiconductor layer in the diode region and on the fourth semiconductor layer in the boundary region and the IGBT region, In the IGBT region, a sixth semiconductor layer of first conductivity type is provided on the upper part of the fifth semiconductor layer, In the diode region, extending from the upper surface of the fifth semiconductor layer toward the third semiconductor layer, the fifth semiconductor layer and the third semiconductor layer, and a second electrode adjacent to the diode region toward the IGBT region in a first direction, In the IGBT region, extending from the upper surface of the sixth semiconductor layer toward the third semiconductor layer, the sixth semiconductor layer, the fifth semiconductor layer, the fourth semiconductor layer, and the third semiconductor layer, and the third electrode adjacent to the first direction, In the boundary region, the fourth electrode extends from the upper surface of the fifth semiconductor layer toward the third semiconductor layer, and is adjacent to the fifth semiconductor layer, the fourth semiconductor layer, and the third semiconductor layer in the first direction, and is electrically insulated from the second electrode and the third electrode. A fifth electrode provided on the fifth semiconductor layer, A first insulating film is provided between the second electrode and the fifth semiconductor layer, and between the second electrode and the third semiconductor layer, A second insulating film is provided between the third electrode and the fifth electrode, between the third electrode and the sixth semiconductor layer, between the third electrode and the fifth semiconductor layer, between the third electrode and the fourth semiconductor layer, and between the third electrode and the third semiconductor layer. A third insulating film is provided between the fourth electrode and the fifth electrode, between the fourth electrode and the fifth semiconductor layer, between the fourth electrode and the fourth semiconductor layer, and between the fourth electrode and the third semiconductor layer. Equipped with, A semiconductor device wherein the average number of second electrodes provided per unit length in the first direction in the diode region is less than the average number of fourth electrodes provided per unit length in the first direction in the boundary region.

14. The first conductivity type is p-type, and the second conductivity type is n-type. In the conduction state of the diode region, a positive voltage is applied to the fourth electrode in the boundary region relative to the second electrode. Before the recovery of the diode region, a negative voltage is applied to the fourth electrode relative to the second electrode. A method for driving a semiconductor device according to any one of claims 1 to 8, 10, and 11, wherein a positive voltage is applied to the fourth electrode relative to the second electrode while a reverse recovery current is flowing through the diode region.

15. A semiconductor device having a diode region, an IGBT region, and a boundary region located between the diode region and the IGBT region, A first electrode provided across the diode region, the boundary region, and the IGBT region, In the diode region, a first semiconductor layer of a first conductivity type is provided on the first electrode, In the IGBT region, a second semiconductor layer of a second conductivity type is provided on the first electrode, A third semiconductor layer of a first conductivity type is provided extending across the diode region, the boundary region, and the IGBT region, located on the first semiconductor layer in the diode region and on the second semiconductor layer in the IGBT region, and having an impurity concentration lower than that of the first semiconductor layer. In the boundary region and the IGBT region, a fourth semiconductor layer of a first conductivity type is provided on the third semiconductor layer, and the impurity concentration is higher than that of the upper layer of the third semiconductor layer. A fifth semiconductor layer of second conductivity type is provided on the third semiconductor layer in the diode region and on the fourth semiconductor layer in the boundary region and the IGBT region, In the IGBT region, a sixth semiconductor layer of first conductivity type is provided on the upper part of the fifth semiconductor layer, In the diode region, extending from the upper surface of the fifth semiconductor layer toward the third semiconductor layer, the fifth semiconductor layer and the third semiconductor layer, and a second electrode adjacent to the diode region toward the IGBT region in a first direction, In the IGBT region, extending from the upper surface of the sixth semiconductor layer toward the third semiconductor layer, the sixth semiconductor layer, the fifth semiconductor layer, the fourth semiconductor layer, and the third semiconductor layer, and the third electrode adjacent to the first direction, In the boundary region, the fourth electrode extends from the upper surface of the fifth semiconductor layer toward the third semiconductor layer, and is adjacent to the fifth semiconductor layer, the fourth semiconductor layer, and the third semiconductor layer in the first direction and is electrically insulated from the third electrode. In the IGBT region, an internal electrode extends from the upper surface of the sixth semiconductor layer toward the third semiconductor layer, and is adjacent to the sixth semiconductor layer, the fifth semiconductor layer, the fourth semiconductor layer, and the third semiconductor layer in the first direction and electrically insulated from the third electrode and the fourth electrode, A fifth electrode provided on the fifth semiconductor layer, A first insulating film is provided between the second electrode and the fifth semiconductor layer, and between the second electrode and the third semiconductor layer, A second insulating film is provided between the third electrode and the fifth electrode, between the third electrode and the sixth semiconductor layer, between the third electrode and the fifth semiconductor layer, between the third electrode and the fourth semiconductor layer, and between the third electrode and the third semiconductor layer. A third insulating film is provided between the fourth electrode and the fifth electrode, between the fourth electrode and the fifth semiconductor layer, between the fourth electrode and the fourth semiconductor layer, and between the fourth electrode and the third semiconductor layer. A semiconductor device equipped with a semiconductor device.

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