Semiconductor device and its manufacturing method

Abstract

To provide a semiconductor device with a plurality of trench gates which require techniques for suppressing pattern collapse during a manufacturing process.SOLUTION: In a semiconductor device 1, 2, 3, 4, 5, when a semiconductor substrate is viewed from above, a portion of the semiconductor substrate 10 sandwiched between adjacent trench gates 30 in the first direction includes a trunk 16A extending along a second direction orthogonal to the first direction, and a branch 16B protruding from the trunk.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The technology disclosed in this specification relates to a semiconductor device having a plurality of trench gates and a method for manufacturing the same.

Background Art

[0002] Development of semiconductor devices such as MOSFETs and IGBTs having a plurality of trench gates has been underway. Such a semiconductor device is manufactured by forming a plurality of trenches on one main surface of a semiconductor substrate and then forming trench gates in each of the plurality of trenches. Patent Document 1 discloses an example of such a semiconductor device having a plurality of trench gates.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a semiconductor device having a plurality of trench gates, in order to reduce the on-resistance, it is desired to increase the channel area by shortening the distance between adjacent trench gates. In order to shorten the distance between adjacent trench gates, when forming a plurality of trenches, one main surface of the semiconductor substrate must be processed so that the distance between adjacent trenches becomes shorter. At this time, a part of the semiconductor substrate remaining between adjacent trenches is processed into a thin plate shape. Therefore, there is a concern about pattern collapse of a part of the thin plate-shaped semiconductor substrate. In particular, as disclosed in Patent Document 1, when the distance between adjacent trench gates is shortened so that the entire region between adjacent trench gates becomes a channel, the problem of pattern collapse becomes apparent. In a semiconductor device having a plurality of trench gates, a technique for suppressing such pattern collapse during the manufacturing process is required. [Means for solving the problem]

[0005] The semiconductor devices (1, 2, 3, 4, 5) disclosed herein include a semiconductor substrate (10) having a first main surface (10b) and a second main surface (10a), wherein a first semiconductor region (14) of a first conductivity type, a second semiconductor region (16) of a second conductivity type, and a third semiconductor region (18) of a first conductivity type are arranged in this order along the thickness direction of the semiconductor substrate, and the third semiconductor region is provided at a position where it is exposed to the first main surface; and a plurality of trench gates (30) provided on the semiconductor substrate so as to extend from the first main surface of the semiconductor substrate, beyond the third and second semiconductor regions, to the first semiconductor region. Each of the plurality of trench gates may be spaced apart from each other along a first direction when the semiconductor substrate is viewed in plan. A portion of the semiconductor substrate sandwiched between adjacent trench gates in the first direction may have, when viewed in plan, a trunk (16A) extending along a second direction perpendicular to the first direction, and a branch (16B) protruding from the trunk.

[0006] In the semiconductor device described above, a portion of the semiconductor substrate sandwiched between adjacent trench gates is composed of a main body and a branch. The branch is formed to protrude from the side surface of the thin plate-shaped main body. Therefore, the branch can function to support the main body. In this way, the semiconductor device has a structure that can suppress pattern collapse during the manufacturing process.

[0007] A method for manufacturing semiconductor devices (1, 2, 3, 4, 5) disclosed herein may include a trench forming step of forming a plurality of trenches (TR) on the first main surface of a semiconductor substrate (10) having a first main surface (10b) and a second main surface (10a), wherein a first semiconductor region (14) of a first conductivity type, a second semiconductor region (16) of a second conductivity type, and a third semiconductor region (18) of a first conductivity type are arranged in this order along the thickness direction of the semiconductor substrate, the third semiconductor region is provided at a position exposed to the first main surface, and each of the plurality of trenches is formed so as to reach the first semiconductor region beyond the third and second semiconductor regions from the first main surface of the semiconductor substrate; and a step of forming a trench gate (30) in each of the plurality of trenches. Each of the plurality of trench gates may be arranged at intervals from one another along a first direction when the semiconductor substrate is viewed in plan. A portion of the semiconductor substrate sandwiched between adjacent trench gates in the first direction may have, when viewed in plan, a trunk extending along a second direction perpendicular to the first direction, and branches protruding from the trunk.

[0008] In the semiconductor device manufactured by the above manufacturing method, a portion of the semiconductor substrate sandwiched between adjacent trench gates is composed of a main body and a branch. The branch is formed to protrude from the side surface of the thin plate-like main body. Therefore, the branch can function to support the main body. In this way, in the above semiconductor device manufacturing method, when multiple trenches are formed in the trench formation step, pattern collapse of a portion of the semiconductor substrate sandwiched between adjacent trenches is suppressed. [Brief explanation of the drawing]

[0009] [Figure 1] This is a schematic cross-sectional view of the main part of the semiconductor device of this embodiment, corresponding to the cross-sectional view shown by line II in Figure 3. [Figure 2] This is a cross-sectional view of the main part of the semiconductor device of this embodiment, schematically showing the cross-sectional view corresponding to line II-II in Figure 3. [Figure 3]This is a cross-sectional view of the main part of the semiconductor device of this embodiment, schematically showing the cross-sectional view corresponding to line III-III in Figures 1 and 2. [Figure 4] The flowchart for the manufacturing method of the semiconductor device according to this embodiment is shown. [Figure 5] A schematic perspective view of the main parts of the manufacturing process in the semiconductor device manufacturing method of this embodiment is shown. [Figure 6] This is a cross-sectional view of the main part of a modified semiconductor device of this embodiment, schematically showing the cross-sectional view corresponding to line III-III in Figures 1 and 2. [Figure 7] This is a cross-sectional view of the main part of a modified semiconductor device of this embodiment, schematically showing the cross-sectional view corresponding to line III-III in Figures 1 and 2. [Figure 8] This is a cross-sectional view of the main part of a modified semiconductor device of this embodiment, schematically showing the cross-sectional view corresponding to line III-III in Figures 1 and 2. [Figure 9] This is a cross-sectional view of the main part of a modified semiconductor device of this embodiment, schematically showing the cross-sectional view corresponding to line III-III in Figures 1 and 2. [Modes for carrying out the invention]

[0010] As shown in Figures 1 to 3, the semiconductor device 1 is a type of power device called a MOSFET (metal-oxide-semiconductor field effect transistor) and includes a semiconductor substrate 10. The semiconductor substrate 10 is not particularly limited, but may be silicon carbide (SiC), for example. Alternatively, the semiconductor substrate 10 may be a semiconductor material such as silicon (Si), gallium nitride (GaN), or gallium oxide (Ga2O3). Here, the thickness direction of the semiconductor substrate 10 is the z direction, one direction parallel to the upper surface 10b of the semiconductor substrate 10 (i.e., one direction perpendicular to the z direction) is the x direction, and the direction perpendicular to both the z direction and the x direction is the y direction.

[0011] The semiconductor device 1 further includes a drain electrode 22 covering the lower surface 10a of the semiconductor substrate 10, a source electrode 24 covering the upper surface 10b of the semiconductor substrate 10, and a plurality of trench gates 30 provided in the upper layer of the semiconductor substrate 10. Each of the plurality of trench gates 30 is provided in a trench TR formed in the upper surface 10b of the semiconductor substrate 10. Each of the plurality of trench gates 30 has a gate insulating film 32 covering the inner surface of the trench TR, and a gate electrode 34 insulated from the semiconductor substrate 10 by the gate insulating film 32. The gate electrode 34 is also insulated from the source electrode 24 by an interlayer insulating film. When each of the plurality of trench gates 30 is observed from a direction perpendicular to the upper surface 10b of the semiconductor substrate 10 (i.e., the z direction) (hereinafter referred to as "when the semiconductor substrate 10 is viewed from above"), in this example it extends along the y direction. Also, when the semiconductor substrate 10 is viewed from above, each of the plurality of trench gates 30 is spaced apart from each other along the x direction in this example.

[0012] The semiconductor substrate 10 is n + A drain region 12 of type n, a drift region 14 of type n, a body region 16 of type p, and n + It has a source region 18 of a certain type. The drain region 12, drift region 14, body region 16, and source region 18 are arranged in this order along the thickness direction of the semiconductor substrate 10. Other semiconductor regions may be interposed between these semiconductor regions 12, 14, 16, and 18.

[0013] The drain region 12 is located in the lower layer of the semiconductor substrate 10 and is positioned to be exposed on the lower surface 10a of the semiconductor substrate 10. The drain region 12 is in ohmic contact with the drain electrode 22 that covers the lower surface 10a of the semiconductor substrate 10.

[0014] The drift region 14 is provided between the drain region 12 and the body region 16, separating the drain region 12 from the body region 16. The concentration of n-type impurities in the drift region 14 is lower than that in the drain region 12. The drift region 14 is in contact with the bottom surface and the lower part of the side surface of the trench gate 30.

[0015] The body region 16 is provided between the drift region 14 and the source region 18, separating the drift region 14 from the source region 18. The body region 16 is in contact with the side surface of the trench gate 30. The body region 16 is electrically connected to the source electrode 24 through a body contact region (not shown) with a high concentration of p-type impurities formed at a position exposed on the upper surface of the semiconductor substrate 10.

[0016] The source region 18 is provided on the body region 16 and is provided at a position exposed on the upper surface 10b of the semiconductor substrate 10. The source region 18 makes an ohmic contact with the source electrode 24 covering the upper surface 10b of the semiconductor substrate 10.

[0017] As shown in FIG. 3, the body region 16 sandwiched between the trench gates 30 adjacent in the x direction has a trunk portion 16A extending along the y direction and a plurality of branch portions 16B protruding from the trunk portion 16A when the semiconductor substrate 10 is viewed in plan. In FIG. 3, the cross-sectional layout of the body region 16 is shown, but other semiconductor regions sandwiched between the trench gates 30 adjacent in the x direction, that is, the upper end portion of the drift region 14 and the source region 18 also have the same cross-sectional layout. Therefore, a part of the semiconductor substrate 10 sandwiched between the trench gates 30 adjacent in the x direction is composed of a trunk portion and branch portions. Hereinafter, the forms of the trunk portion and the branch portions will be described with reference to the body region 16.

[0018] In this example, the stem portion 16A of the body region 16 has a thin plate-like form extending along the yz plane. The width W1 of the stem portion 16A of the body region 16 is the width measured along the direction in which a pair of trench gates 30 adjacent to the stem portion 16A face each other, that is, the x direction. The width W1 of the stem portion 16A of the body region 16 is not particularly limited, but may be, for example, 200 nm or less.

[0019] Each of the plurality of branch portions 16B of the body region 16 protrudes from the side surface of the stem portion 16A and has a form extending in the thickness direction of the semiconductor substrate 10 from the upper end to the lower end of the stem portion 16A. Here, the side surface of the stem portion 16A is a side surface parallel to the yz plane. In this example, the branch portion 16B of the body region 16 has a rectangular form when viewed in plan on the semiconductor substrate 10. This form is an example, and the branch portion 16B of the body region 16 can protrude from the side surface of the stem portion 16A in various forms. The width W2 of the branch portion 16B of the body region 16 is the width measured along the longitudinal direction of the stem portion 16A, that is, the y direction. The width W2 of the branch portion 16B of the body region 16 is not particularly limited, but may be, for example, 200 nm or less.

[0020] In this example, a plurality of branch portions 16B are provided on one side surface of the stem portion 16A of the body region 16, and a plurality of branch portions 16B are also provided on the other side surface of the stem portion 16A of the body region 16. Each of the plurality of branch portions 16B provided on each side surface of the stem portion 16A of the body region 16 is arranged at intervals along the longitudinal direction of the stem portion 16A, that is, the y direction. In this example, the plurality of branch portions 16B are arranged periodically along the y direction. Thus, on the side surface of the body region 16, each of the plurality of branch portions 16B constitutes a convex portion, and a concave portion is formed between the branch portions 16B. The plurality of branch portions 16B of the body region 16 are configured to penetrate into the trench gates 30 adjacent in the x direction. Therefore, all the side surfaces constituting the branch portions 16B of the body region 16 are in contact with the trench gates 30. Thus, the side surface of the body region 16 and the side surface of the trench gate 30 are configured to mesh with each other.

[0021] Next, the operation of the semiconductor device 1 will be explained. The semiconductor device 1 is ON when a positive voltage is applied to the drain electrode 22, the source electrode 24 is grounded, and a voltage greater than or equal to a threshold voltage positive to the source electrode 24 is applied to the gate electrode 34 of the trench gate 30. At this time, an inversion layer is formed in the part of the body region 16 that separates the source region 18 and the drift region 14, on the side facing the trench gate 30. Electrons supplied from the source region 18 reach the drift region 14 via this inversion layer. Electrons that reach the drift region 14 flow vertically to the drain region 12. As a result, the drain electrode 22 and the source electrode 24 become conductive.

[0022] When a positive voltage is applied to the drain electrode 22, the source electrode 24 is grounded, and the gate electrode 34 of the trench gate 30 is grounded, no inversion layer is formed on the side of the trench gate 30, and the semiconductor device 1 is off. In this way, the semiconductor device 1 can operate as a switching element.

[0023] In semiconductor device 1, the width W1 of the main portion 16A of the body region 16 is small, and the distance between adjacent trench gates 30 is short. Therefore, in semiconductor device 1, a large channel area is secured, and the channel resistance is reduced. In particular, in semiconductor device 1, the width W1 of the main portion 16A of the body region 16 is 200 nm or less. In this case, when semiconductor device 1 is turned on, the inversion layers formed on each side surface of the trench gates 30 adjacent to the main portion 16A in the x direction connect, and the entire main portion 16A can become a channel. Therefore, semiconductor device 1 can have extremely low channel resistance. Note that the width W1 of the main portion 16A of the body region 16 may be 100 nm or less, and even 80 nm or less. The smaller the width W1 of the main portion 16A of the body region 16, the lower the channel resistance can be.

[0024] Furthermore, in semiconductor device 1, the width W2 of the branch portion 16B of the body region 16 is also 200 nm or less. Therefore, when semiconductor device 1 is turned on, the inversion layers formed on each of the sides of the trench gates 30 adjacent to the branch portion 16B in the y direction connect, and the entire branch portion 16B can become a channel. For this reason, semiconductor device 1 has extremely low channel resistance. Note that the width W2 of the branch portion 16B of the body region 16 may be 100 nm or less, and even 80 nm or less. The smaller the width W2 of the branch portion 16B of the body region 16, the lower the channel resistance can be.

[0025] Next, some of the manufacturing steps for the semiconductor device 1 will be described. Other steps that are omitted from the description are not particularly limited, and various technologies, including known manufacturing techniques, can be used.

[0026] First, as shown in Figure 4, a semiconductor substrate 10 is prepared in which a drain region 12, a drift region 14, a body region 16, and a source region 18 are arranged in this order along the depth direction of the semiconductor substrate 10 (step S1). This semiconductor substrate 10 is not particularly limited, but for example, it may be prepared by growing an n-type layer from the upper surface of the drain region 12 using epitaxial growth technology, and then implanting p-type and n-type impurity ions into a part of the n-type layer from the upper surface 10b of the semiconductor substrate 10 using ion implantation technology to form the body region 16 and the source region 18.

[0027] Next, as shown in Figure 4, a mask is patterned on the upper surface 10b of the semiconductor substrate 10 using photolithography technology, and then a trench TR is formed using anisotropic dry etching technology, penetrating the source region 18 and the body region 16 from the upper surface 10b of the semiconductor substrate 10 exposed at the opening of the mask to reach the drift region 14 (step S2). The trench TR is formed in a tapered shape, and the taper angle may be in the range of 87° to 90°.

[0028] Figure 5 shows a perspective view of the main part of the semiconductor substrate 10 after the trench TR has been formed. As shown in Figure 5, a portion of the semiconductor substrate 10 sandwiched between adjacent trench TRs is composed of a main portion 16A and a branch portion 16B. The branch portion 16B is formed to protrude from the side of the thin plate-like main portion 16A. Therefore, the branch portion 16B can function to support the main portion 16A. If the branch portion 16B is not formed, when multiple trench TRs are formed, a portion of the semiconductor substrate 10 sandwiched between adjacent trench TRs will be formed in a thin plate shape, raising concerns about the collapse of the pattern in a portion of the semiconductor substrate 10. On the other hand, in this manufacturing method, when multiple trench TRs are formed in the trench formation process, the branch portion 16B can function to support the main portion 16A, thus suppressing the collapse of the pattern in a portion of the semiconductor substrate 10. In particular, when the width W1 (see Figure 3) of the main portion 16A (see Figure 3) becomes 200 nm or less, so that the entire main portion 16A of the body region 16 becomes a channel, the problem of pattern collapse becomes apparent. In particular, when the width W1 of the main section 16A is 100 nm or less, and even less than 80 nm, the problem of pattern collapse becomes especially apparent. This manufacturing method is especially useful in such cases.

[0029] Next, as shown in Figure 4, a trench gate 30 is formed in the trench TR (step S3). Specifically, a gate insulating film 32 is deposited on the upper surface of the semiconductor substrate 10, including the inner surface of the trench TR, using CVD technology. Next, a polysilicon layer is deposited using CVD technology, and then the gate electrode 34 is formed by patterning the polysilicon layer. This forms the trench gate 30. Next, an interlayer insulating film is patterned to cover the gate electrode 34. Finally, the drain electrode 22 and source electrode 24 are formed to complete the semiconductor device 1 shown in Figures 1 to 3.

[0030] The following describes a modified semiconductor device.

[0031] In the semiconductor device 2 shown in Figure 6, a pair of body regions 16 facing each other in the x-direction with a trench gate 30 in between are configured such that a portion of the branch portion 16B of one body region 16 faces a portion of the branch portion 16B of the other body region 16. For example, in the semiconductor device 1 shown in Figure 3, the entire branch portion 16B of one body region 16 faced the entire branch portion 16B of the other body region 16. The trench gate 30 sandwiched between the branch portions 16B of the opposing pair of body regions 16 becomes a constricted portion, which increases the gate resistance. By configuring the semiconductor device 2 as shown in Figure 6, the constricted portion of the trench gate 30 is reduced, thus suppressing the increase in gate resistance.

[0032] In both the semiconductor device 3 shown in Figure 7 and the semiconductor device 4 shown in Figure 8, in a pair of body regions 16 facing each other in the x-direction with a trench gate 30 in between, the entire branch portion 16B of one body region 16 faces the trunk 16A between the branch portions 16B of the other body region 16. In the semiconductor device 3 shown in Figure 7, the layouts of each of the pair of adjacent body regions 16 in the x-direction are identical, while in the semiconductor device 4 shown in Figure 8, the layouts of each of the pair of adjacent body regions 16 in the x-direction are misaligned in the y-direction. In both the semiconductor device 3 shown in Figure 7 and the semiconductor device 4 shown in Figure 8, since there is virtually no constricted portion of the trench gate 30, the increase in gate resistance can be suppressed.

[0033] In the semiconductor device 5 shown in Figure 9, the branch portion 16B of the body region 16 has a triangular shape when the semiconductor substrate 10 is viewed from above. In this case as well, as in the other embodiments, pattern collapse during the manufacturing process can be suppressed.

[0034] The following summarizes the features of the technology disclosed herein. Note that the technical elements described below are independent elements that exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing.

[0035] (Feature 1) A semiconductor device, A semiconductor substrate having a first main surface and a second main surface, wherein a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, and a third semiconductor region of a first conductivity type are arranged in this order along the thickness direction of the semiconductor substrate, and the third semiconductor region is provided at a position exposed to the first main surface, The semiconductor substrate comprises a plurality of trench gates provided so as to extend from the first main surface of the semiconductor substrate, beyond the third and second semiconductor regions, to the first semiconductor region, Each of the plurality of trench gates is arranged with a gap between them along the first direction when the semiconductor substrate is viewed in plan view. A semiconductor device wherein a portion of the semiconductor substrate sandwiched between adjacent trench gates in the first direction has, when viewed in plan, a trunk extending along a second direction perpendicular to the first direction and a branch portion protruding from the trunk.

[0036] (Feature 2) The semiconductor device according to feature 1, wherein the width of the second semiconductor region of the trunk in the first direction is such that the entire second semiconductor region of the trunk becomes a channel when the semiconductor device is turned on.

[0037] (Feature 3) The semiconductor device according to feature 2, wherein the width of the second semiconductor region of the trunk in the first direction is 200 nm or less.

[0038] (Feature 4) The semiconductor device according to any one of features 1 to 3, wherein the width of the second semiconductor region among the branches in the second direction is such that the entire second semiconductor region among the branches becomes a channel when the semiconductor device is turned on.

[0039] (Feature 5) The semiconductor device according to feature 4, wherein the width of the second semiconductor region among the branches in the second direction is 200 nm or less.

[0040] (Feature 6) A semiconductor device according to any one of features 1 to 5, wherein, between a pair of the second semiconductor regions facing each other with the trench gate in between, one of the branches faces the trunk between the other branch and the branch in the first direction.

[0041] (Feature 7) A method for manufacturing a semiconductor device, A trench forming step for forming a plurality of trenches on the first main surface of a semiconductor substrate having a first main surface and a second main surface, wherein a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, and a third semiconductor region of a first conductivity type are arranged in this order along the thickness direction of the semiconductor substrate, the third semiconductor region is provided at a position exposed to the first main surface, and each of the plurality of trenches is formed so as to reach the first semiconductor region from the first main surface of the semiconductor substrate, beyond the third and second semiconductor regions, The process includes the step of forming a trench gate in each of the plurality of trenches, Each of the plurality of trench gates is arranged with a gap between them along the first direction when the semiconductor substrate is viewed in plan view. A method for manufacturing a semiconductor device, wherein a portion of the semiconductor substrate sandwiched between adjacent trench gates in the first direction has, when viewed in plan, a trunk extending along a second direction perpendicular to the first direction and a branch portion protruding from the trunk.

[0042] (Feature 8) The method for manufacturing a semiconductor device according to feature 7, wherein the width of the second semiconductor region of the trunk in the first direction is such that the entire second semiconductor region of the trunk becomes a channel when the semiconductor device is turned on.

[0043] (Feature 9) The method for manufacturing a semiconductor device according to feature 7 or 8, wherein the width of the second semiconductor region among the branches in the second direction is such that the entire second semiconductor region among the branches becomes a channel when the semiconductor device is turned on.

[0044] Although specific examples of the present invention have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various modifications and changes to the specific examples illustrated above. Furthermore, the technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technologies illustrated in this specification or drawings can achieve multiple objectives simultaneously, and achieving even one of these objectives itself constitutes technical usefulness. [Explanation of Symbols]

[0045] 1,2,3,4,5: Semiconductor device, 10: Semiconductor substrate, 12: Drain region, 14: Drift region, 16: Body region, 16A: Main body, 16B: Branch, 18: Source region, 22: Drain electrode, 24: Source electrode, 30: Trench gate

Claims

1. Semiconductor devices (1, 2, 3, 4, 5), A semiconductor substrate (10) having a first main surface (10b) and a second main surface (10a), wherein a first semiconductor region (14) of a first conductivity type, a second semiconductor region (16) of a second conductivity type, and a third semiconductor region (18) of a first conductivity type are arranged in this order along the thickness direction of the semiconductor substrate, and the third semiconductor region is provided at a position exposed to the first main surface, The semiconductor substrate comprises a plurality of trench gates (30) provided so as to extend from the first main surface of the semiconductor substrate, beyond the third and second semiconductor regions, to the first semiconductor region, Each of the plurality of trench gates is arranged with a gap between them along the first direction when the semiconductor substrate is viewed in plan view. A portion of the semiconductor substrate sandwiched between adjacent trench gates in the first direction has, when viewed in plan, a trunk (16A) extending along a second direction perpendicular to the first direction, and a branch portion (16B) protruding from the trunk. A semiconductor device in which the width of the second semiconductor region of the trunk in the first direction is such that the entire second semiconductor region of the trunk becomes a channel when the semiconductor device is turned on.

2. The semiconductor device according to claim 1, wherein the width of the second semiconductor region of the trunk in the first direction is 200 nm or less.

3. The semiconductor device according to claim 1, wherein the width of the second semiconductor region among the branches in the second direction is such that the entire second semiconductor region among the branches becomes a channel when the semiconductor device is turned on.

4. The semiconductor device according to claim 3, wherein the width of the second semiconductor region among the branches in the second direction is 200 nm or less.

5. The semiconductor device according to any one of claims 1 to 4, wherein, between a pair of second semiconductor regions facing each other with the trench gate in between, one branch faces the trunk between the other branch and the branch in the first direction.

6. A semiconductor device (1, 2, 3, 4, 5), A semiconductor substrate (10) having a first main surface (10b) and a second main surface (10a), wherein a first semiconductor region (14) of a first conductivity type, a second semiconductor region (16) of a second conductivity type, and a third semiconductor region (18) of a first conductivity type are arranged in this order along the thickness direction of the semiconductor substrate, and the third semiconductor region is provided at a position exposed to the first main surface, The semiconductor substrate comprises a plurality of trench gates (30) provided so as to extend from the first main surface of the semiconductor substrate, beyond the third and second semiconductor regions, to the first semiconductor region, Each of the plurality of trench gates is arranged with a gap between them along the first direction when the semiconductor substrate is viewed in plan view. A portion of the semiconductor substrate sandwiched between adjacent trench gates in the first direction has, when viewed in plan, a trunk (16A) extending along a second direction perpendicular to the first direction, and a branch portion (16B) protruding from the trunk. A semiconductor device in which the width of the second semiconductor region of the branch in the second direction is such that the entire second semiconductor region of the branch becomes a channel when the semiconductor device is turned on.

7. A method for manufacturing semiconductor devices (1, 2, 3, 4, 5), A trench forming step for forming a plurality of trenches (TR) on the first main surface of a semiconductor substrate (10) having a first main surface (10b) and a second main surface (10a), wherein a first semiconductor region (14) of a first conductivity type, a second semiconductor region (16) of a second conductivity type, and a third semiconductor region (18) of a first conductivity type are arranged in this order along the thickness direction of the semiconductor substrate, the third semiconductor region is provided at a position exposed to the first main surface, and each of the plurality of trenches is formed so as to reach the first semiconductor region from the first main surface of the semiconductor substrate, beyond the third and second semiconductor regions, The process includes the step of forming a trench gate (30) in each of the plurality of trenches, Each of the plurality of trench gates is arranged with a gap between them along the first direction when the semiconductor substrate is viewed in plan view. A portion of the semiconductor substrate sandwiched between adjacent trench gates in the first direction has, when viewed in plan, a trunk extending along a second direction perpendicular to the first direction, and branches protruding from the trunk. A method for manufacturing a semiconductor device, wherein the width of the second semiconductor region of the trunk in the first direction is such that the entire second semiconductor region of the trunk becomes a channel when the semiconductor device is turned on.

8. The method for manufacturing a semiconductor device according to claim 7, wherein the width of the second semiconductor region among the branches in the second direction is such that the entire second semiconductor region among the branches becomes a channel when the semiconductor device is turned on.

9. A method for manufacturing a semiconductor device (1, 2, 3, 4, 5), A trench forming step for forming a plurality of trenches (TR) on the first main surface of a semiconductor substrate (10) having a first main surface (10b) and a second main surface (10a), wherein a first semiconductor region (14) of a first conductivity type, a second semiconductor region (16) of a second conductivity type, and a third semiconductor region (18) of a first conductivity type are arranged in this order along the thickness direction of the semiconductor substrate, the third semiconductor region is provided at a position exposed to the first main surface, and each of the plurality of trenches is formed so as to reach the first semiconductor region from the first main surface of the semiconductor substrate, beyond the third and second semiconductor regions, The process includes the step of forming a trench gate (30) in each of the plurality of trenches, Each of the plurality of trench gates is arranged with a gap between them along the first direction when the semiconductor substrate is viewed in plan view. A portion of the semiconductor substrate sandwiched between adjacent trench gates in the first direction has, when viewed in plan, a trunk extending along a second direction perpendicular to the first direction, and branches protruding from the trunk. A method for manufacturing a semiconductor device, wherein the width of the second semiconductor region among the branches in the second direction is such that the entire second semiconductor region among the branches becomes a channel when the semiconductor device is turned on.

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