Chip package structure, method for manufacturing a chip package structure, and electronic device

Abstract

The present disclosure provides a chip package structure, a manufacturing method of the chip package structure, and an electronic device for the purpose of reducing the area of ​​the chip package structure and improving the speed of signal transmission, and relates to the field of semiconductor technology. The semiconductor structure includes a package substrate, a first chip, a conductive pillar, and a second chip, the package substrate having a first surface, the first chip is positioned on the first surface of the package substrate and electrically connected to the package substrate, the conductive pillar is positioned on the first surface of the package substrate and electrically connected to the package substrate, the second chip is positioned on a side of the first chip and the conductive pillar away from the package substrate and electrically connected to the conductive pillar, and the orthogonal projection of the conductive pillar on the package substrate is positioned within the range of the orthogonal projection of the first chip or the second chip on the package substrate. The chip package structure is configured for connection with a circuit board in an electronic device.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly, to chip package structures, methods for manufacturing chip package structures, and electronic devices.

Background Art

[0002] With the rapid development of wireless communication, automotive electronics, and other consumer electronics, there is a trend towards developing electronic devices with increased functionality. Therefore, when manufacturing these electronic devices, chips with different functions are usually packaged separately and then integrated, and the integrated components are arranged inside the electronic device.

[0003] Packaging is an important step in the manufacturing process of electronic devices. However, chips in the prior art tend to have problems such as large size after packaging and relatively slow signal transmission speed.

Summary of the Invention

Means for Solving the Problems

[0004] Examples of this disclosure provide a chip package structure, a method for manufacturing a chip package structure, and an electronic device for the purpose of reducing the area of the chip package structure and improving the speed of signal transmission.

[0005] To achieve the above objectives, examples of this disclosure have the following technical solutions.

[0006] In one embodiment, a chip package structure is provided. The chip package structure comprises a package substrate, a first chip, a conductive pillar, and a second chip, wherein the package substrate has a first surface, the first chip is positioned on the first surface of the package substrate and electrically connected to the package substrate, the conductive pillar is positioned on the first surface of the package substrate and electrically connected to the package substrate, the second chip is positioned to the side of the first chip and conductive pillar away from the package substrate and electrically connected to the conductive pillar, and the orthographic projection of the conductive pillar on the package substrate is positioned within the range of the orthographic projection of the first chip or the second chip on the package substrate.

[0007] In the chip package structure according to the above-described example of this disclosure, the second chip is positioned above the first chip such that the package substrate, the first chip, the conductive pillar, and the second chip form a stacked structure, which improves the compactness of the chip package structure and helps reduce the area of ​​the chip package structure. Furthermore, the conductive pillar is provided to realize an electrical connection between the second chip and the package substrate, and the conductive pillar is positioned below the first chip 2 or the second chip such that the orthographic projection of the conductive pillar on the package substrate is located within the range of the orthographic projection of the first chip 2 or the second chip on the package substrate. In this way, the space around the first chip 2 or the second chip can be kept free, which helps to further miniaturize the chip package structure and further reduce the area of ​​the chip package structure.

[0008] In some cases, the orthographic projection of the conductive pillars on the package substrate is also located within the range of the orthographic projection of the first chip on the package substrate.

[0009] In some examples, the chip package structure further comprises a package layer positioned between the package substrate and the second chip, covering the first chip and surrounding the sides of the conductive pillars.

[0010] In some examples, the orthographic projection of the second chip on the package substrate is located within the range of the orthographic projection of the package layer on the package substrate.

[0011] In some examples, the chip package structure further comprises a first fill portion, at least a portion of which is positioned between the package layer and the second chip, and the first fill portion surrounds each pin of the second chip.

[0012] In some examples, the chip package structure further includes an electromagnetic shielding layer, which covers not only the second chip but also at least the sides of the package layer.

[0013] In some examples, the package substrate further comprises at least one grounding wire, and the electromagnetic shielding layer also covers the sides of the package substrate and is electrically connected to the grounding wire.

[0014] In some examples, the second chip comprises multiple subchips that are stacked in a manner perpendicular to the package substrate.

[0015] In some cases, two adjacent subchips are electrically connected to each other.

[0016] In some examples, one of several subchips near the package substrate is electrically connected to a conductive pillar, while the other subchips are electrically connected to the package substrate by wires.

[0017] In some cases, the lateral surface of the second chip closer to the package substrate is higher than the lateral surface of the first chip further away from the package substrate, relative to the first surface of the package substrate.

[0018] In some examples, the distance between the lateral surface of the second chip closer to the package substrate and the first surface of the package substrate is h1, and the distance between the lateral surface of the first chip further away from the package substrate and the first surface of the package substrate is h2, where h1 and h2 satisfy the following conditions.

[0019]

number

[0020] In some examples, the number of conductive pillars is greater than one, and multiple conductive pillars are located on at least two opposing sides of the first chip.

[0021] In some examples, the chip package structure further comprises a second fill portion, at least a portion of which is positioned between the package substrate and the first chip, and the second fill portion surrounds each pin of the first chip.

[0022] In some examples, the package substrate has a second surface opposite to the first surface, and the chip package structure further comprises solder balls positioned on the second surface of the package substrate and electrically connected to the package substrate.

[0023] In other embodiments, other chip package structures are provided. The chip package structure comprises a package substrate having a first surface; a first chip disposed on the first surface of the package substrate and electrically connected to the package substrate; and a second chipset comprising a plurality of second chips positioned to the side of the first chip away from the package substrate, electrically connected to the package substrate, and continuously stacked in a direction perpendicular to the package substrate.

[0024] In some examples, two adjacent second chips are electrically connected to each other.

[0025] In some examples, each of the plurality of second chips is electrically connected to the package substrate by an electric wire.

[0026] In some examples, the chip package structure further includes a package layer, and the package layer is positioned between the package substrate and the second chip set and covers the first chip.

[0027] In some examples, the orthographic projection of the second chip set on the package substrate is positioned within the range of the orthographic projection of the package layer on the package substrate.

[0028] In some examples, the chip package structure further includes a first filling portion, at least a part of the first filling portion is positioned between the package layer and the second chip set, and the first filling portion surrounds the pins of each of the one second chip near the package substrate.

[0029] In some examples, the chip package structure further includes an electromagnetic shielding layer, and the electromagnetic shielding layer at least covers not only the second chip set but also the side of the package layer.

[0030] In some examples, the package substrate includes at least one ground wire, and the electromagnetic shielding layer covers the side of the package substrate and is electrically connected to the ground wire.

[0031] In some examples, the surface on the side of the second chip set closer to the package substrate is higher than the surface on the side of the first chip away from the package substrate with respect to the first surface of the package substrate.

[0032] In some examples, the distance between the surface on the side of the second chip set closer to the package substrate and the first surface of the package substrate is h1, the distance between the surface on the side of the first chip away from the package substrate and the first surface of the package substrate is h2, and h1 and h2 satisfy the following conditions.

[0033]

number

[0034] In some examples, the chip package structure further comprises a second fill portion, at least a portion of which is positioned between the package substrate and the first chip, and the second fill portion surrounds each pin of the first chip.

[0035] In some examples, the package substrate has a second surface opposite to the first surface, and the chip package structure further comprises solder balls positioned on the second surface of the package substrate and electrically connected to the package substrate.

[0036] In other embodiments, electronic devices are also provided. These electronic devices comprise a chip package structure as described in some of the examples above.

[0037] In another embodiment, a method for manufacturing a chip package structure is provided. The manufacturing method includes the steps of: providing a package substrate having a first surface on which first pads and second pads are arranged spaced apart; forming conductive pillars electrically connected to the second pads on the first surface of the package structure; arranging first chips electrically connected to the first pads on the first surface of the package substrate; and arranging second chips electrically connected to the conductive pillars to the side of the conductive pillars and first chips away from the package substrate, wherein the orthographic projection of the conductive pillars on the package substrate is located within the range of the orthographic projection of the second chips on the package substrate.

[0038] In some examples, prior to the step of positioning the conductive pillar away from the package substrate and the second chip to the side of the first chip, the manufacturing method further includes the steps of forming a package film covering the first chip and conductive pillar on the first chip and conductive pillar, and thinning the package film in order to expose the conductive pillar and to obtain a package layer covering the first chip.

[0039] In some examples, the step of forming conductive pillars on a first surface of a package substrate includes the steps of forming a package layer on a first chip that covers a first chip, forming vias in the package layer that expose a second pad, and filling the vias with a conductive material to form conductive pillars.

[0040] In some examples, the manufacturing method further includes the step of filling a first insulating material between the package layer and the second chip in order to form a first filling portion that surrounds each pin of the second chip.

[0041] In some examples, the manufacturing method further includes the step of forming an electromagnetic shielding layer that covers not only the second chip but also at least the sides of the package layer.

[0042] In some examples, the second chip comprises a plurality of subchips, and the step of arranging the second chip to the side of the first chip and the conductive pillar away from the package substrate includes the steps of stacking the plurality of subchips in a continuous manner in the thickness direction of the subchips to form the second chip, and soldering the second chip to the end of the conductive pillar away from the package substrate so that the second chip is electrically connected to the conductive pillar.

[0043] In some examples, after placing the first chip and before placing the second chip, the manufacturing method further includes the step of filling a second insulating material between the package substrate and the first chip to form a second filling portion, the second filling portion surrounding each pin of the first chip.

[0044] In some examples, a third pad is located on a second surface of the package substrate, the first and second surfaces are opposite to each other, and before or after forming the package layer, the manufacturing method further includes the step of forming a solder ball on the second surface of the package substrate that is electrically connected to the third pad.

[0045] It may be understood that, in relation to the beneficial effects of the electronic devices and manufacturing methods of the chip package structures provided by the aforementioned examples of this disclosure, the beneficial effects of the chip package structures described above, which are not repeated herein, can be referenced.

[0046] For a clearer explanation of the technical solutions in this disclosure, a brief introduction to the accompanying drawings, which may be used in some examples of this disclosure, may be provided hereafter. Clearly, the drawings in the following description are for illustrative purposes only, illustrating some examples of this disclosure, and other drawings may be available to those skilled in the art. Also, the drawings in the following description may be considered schematic diagrams, but are not limited to the actual size of the products related to the examples of this disclosure, the actual flow of the methods, etc. [Brief explanation of the drawing]

[0047] [Figure 1] This is a schematic diagram of a chip package structure based on several examples. [Figure 2] This is a top view of a chip package structure, showing several examples. [Figure 3] These are top views of other chip package structures, including some examples. [Figure 4] Figure 2 shows a cross-sectional view of the chip package structure, indicated in the B-B' direction. [Figure 5] Figure 2 shows a cross-sectional view of the chip package structure, indicated in the D-D' direction. [Figure 6] This is another cross-sectional view of the chip package structure shown in the B-B' direction in Figure 2. [Figure 7] This is a schematic diagram of several other chip package structures, based on various examples. [Figure 8] This is a schematic diagram of other chip package structures, based on several examples. [Figure 9] These are schematic diagrams of electronic devices, illustrating several examples. [Figure 10] This is a flowchart illustrating a method for manufacturing a chip package structure using several examples. [Figure 11A] This is a structural diagram corresponding to the steps in a method for manufacturing a chip package structure, using several examples. [Figure 11B] This is a structural diagram corresponding to the steps in a method for manufacturing a chip package structure, using several examples. [Figure 11C] This is a structural diagram corresponding to the steps in a method for manufacturing a chip package structure, using several examples. [Figure 11D] This is a structural diagram corresponding to the steps in a method for manufacturing a chip package structure, using several examples. [Figure 11E] This is a structural diagram corresponding to the steps in a method for manufacturing a chip package structure, using several examples. [Figure 12A] This is a structural diagram corresponding to the steps of a manufacturing method for conductive pillars, based on several examples. [Figure 12B] This is a structural diagram corresponding to the steps of a manufacturing method for conductive pillars, based on several examples. [Figure 12C] This is a structural diagram corresponding to the steps of a manufacturing method for conductive pillars, based on several examples. [Figure 13A] This is a structural diagram corresponding to steps in other manufacturing methods of conductive pillars, based on several examples. [Figure 13B]This is a structural diagram corresponding to steps in other manufacturing methods of conductive pillars, based on several examples. [Figure 13C] This is a structural diagram corresponding to steps in other manufacturing methods of conductive pillars, based on several examples. [Figure 14A] This is a structural diagram corresponding to the steps of the second chip manufacturing method, with several examples. [Figure 14B] This is a structural diagram corresponding to the steps of the second chip manufacturing method, with several examples. [Figure 14C] This is a structural diagram corresponding to the steps of the second chip manufacturing method, with several examples. [Modes for carrying out the invention]

[0048] Technical solutions in some examples of this disclosure are clearly and completely described with reference to the accompanying drawings. Clearly, the examples described are only a selection of examples, not all of them, of this disclosure. All other examples that can be obtained by those skilled in the art based on the examples provided by this disclosure are within the scope of protection of this disclosure.

[0049] In this disclosure, the directional or positional relationships indicated by terms such as “center,” “up,” “down,” “front,” “back,” “left,” “right,” “vertical,” “horizontal,” “up,” “down,” “inside,” and “outside” should be understood to be directional or positional relationships as shown in the drawings, solely for the purpose of ease of explanation and simplification of the explanation of this disclosure, and should not be understood as an limitation of this disclosure, as it does not indicate or imply that the indicated devices or elements must be positioned in a particular direction, or that they must be structured and operated in a particular direction.

[0050] Where the context does not require otherwise, the term “equipped with” throughout this specification and claims shall be interpreted as open-ended and including, that is, “equipped with, but not limited to.” Terms such as “examples,” “some examples,” and “more examples” are intended to indicate that a particular feature, structure, material, or property associated with that example is included in at least one example or example of this disclosure. The general descriptions of the above terms do not necessarily refer to the same example or example. Furthermore, any particular feature, structure, material, or property described may be included in any one or more examples or in any appropriate method.

[0051] Hereafter, the terms “first” and “second” are intended for illustrative purposes only and are not to be construed as indicating or signifying relative importance or the number of technical features being referred to. Therefore, features defined by “first” and “second” may indicate or signify that they include one or more features. In the examples of this disclosure, unless otherwise stated, “multiple” means two or more.

[0052] The term “connection” and its extensions may be used when describing some examples. For example, some examples may be described using the term “connection” to indicate that two or more components are in direct physical or electrical contact. For other examples, some examples may be described using the term “linking” to indicate that two or more components are in direct physical or electrical contact. However, the term “linking” may also mean that two or more components are not in direct contact but still cooperate or interact with each other. The examples disclosed herein are not necessarily limited to those contained herein.

[0053] "At least one of A, B, and C" and "at least one of A, B, or C" have the same meaning, including the following combinations of A, B, and C, namely A only, B only, C only, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0054] "A and / or B" includes the following three combinations: A only, B only, and the combination of A and B.

[0055] Furthermore, the use of "based on" implies openness and inclusiveness, as it means that a process, step, calculation, or other action "based on" one or more conditions or values ​​may be based on additional conditions or may exceed the actual value.

[0056] In this disclosure, the meanings of “on top of,” “above,” and “over the course of” should be interpreted in the broadest manner, such that “on top of” means not only “directly on top of” something, but also “on top of” something with an intermediate feature or layer in between, and “above” or “over the course of” means not only “above” or “over the course of” something, but also “above” or “over the course of” something without an intermediate feature or layer in between (i.e., directly on top of something).

[0057] This disclosure provides examples with reference to cross-sectional and / or plan views, which are considered ideal illustrative drawings. In the drawings, layer thicknesses and areas are enlarged for clarity. Therefore, variations in shape from the drawings are possible, for example, due to manufacturing techniques and / or tolerances. Thus, the examples should not be construed as being limited to the shapes of the areas shown herein, but rather as including deviations in shape, for example, due to manufacturing. For example, an etching area shown as a rectangle will generally have curved characteristics. Therefore, the areas shown in the drawings are essentially schematic, and their shapes are not intended to represent the actual shapes of areas in the device, nor are they intended to limit the scope of the examples.

[0058] In practice, as shown in Figure 1, the first chip 2' and the second chip 3' in the chip package structure 100' are typically arranged adjacent to each other on the package substrate 1' in a tiled manner.

[0059] Multiple gold fingers are positioned on the side of the package substrate 1' closer to the first chip 2' and the second chip 3'. The first chip 2' and the second chip 3' are connected to the gold fingers by gold wires 4' using a wire bonding (WB) process, so that the first chip 2' and the second chip 3' can be electrically connected by the connected gold wires 4' and the package substrate 1', thereby enabling communication between the first chip 2' and the second chip 3'.

[0060] However, the first chip 2' and the second chip 3' are placed next to each other, which increases the area of ​​the chip package structure 100'. Furthermore, due to the presence of the wire arc and gold fingers of the gold wire 4', it is necessary to reserve a specific area around the first chip 2' and the second chip 3', which further increases the area of ​​the chip package structure 100'. In general, the area of ​​the chip package structure 100' obtained after the first chip 2' and the second chip 3' are packaged is increased by at least 30% compared to the sum of the areas of the first chip 2' and the second chip 3'. Also, due to the long length and high resistance of the gold wire 4', the speed of signal transmission may be low in the process of transmitting signals between the first chip 2' and the second chip 3' through different gold wires 4'.

[0061] Accordingly, in some examples of this disclosure, a chip package structure 100 is provided. There may be various types of chip package structures 100, such as embedded multimedia cards (EMMC), universal flash storage (UFS), and multi-chip packages (MCP). As shown in Figures 2, 3, and 4, the chip package structure 100 comprises a first chip 2, a conductive pillar 6, and a second chip 4.

[0062] The first chip 2 and the second chip 4 may have different functions. For example, the first chip 2 may be a control device, and the second chip 4 may be a memory chip. The memory chip has a memory structure for providing storage functions. There can be various types of memory chips. For example, memory chips include, but are not limited to, NAND chips, resistive memory chips, and dynamic random access memory. Naturally, the first chip 2 may be a memory chip, and the second chip 4 may be a control device, and this is not limited to the examples of this disclosure.

[0063] In some examples, the chip package structure 100 further comprises a package substrate 1. The package substrate 1 is rigid and can therefore provide support for the first chip 2, conductive pillars 6, and second chip 4. For conductive pillars 6 not described herein, refer to the following description.

[0064] In some examples, as shown in Figure 4, the package substrate 1 comprises a plurality of dielectric layers 11 and a plurality of metal wiring layers 12 arranged alternately. One metal wiring layer 12 is positioned between two adjacent dielectric layers 11, and one dielectric layer 11 is positioned between two adjacent metal wiring layers 12. Each metal wiring layer 12 contains metal wires, and the metal wires in two adjacent metal wiring layers 12 can extend through the dielectric layer 11 between the two metal wiring layers 12 and be connected as required.

[0065] In some examples, the dielectric layer 11 in the package substrate 1 is formed by a spin coating method, and the metal wiring layer 12 in the package substrate 1 is formed by a physical vapor deposition (PVD) process combined with an electroplating process. Therefore, compared to a package substrate formed by an in-fill process, the package substrate 1 composed of the dielectric layer 11 and the metal wiring layer 12, provided by the examples of this disclosure, has a smaller thickness, smaller spacing between adjacent metal wiring layers 12, and consequently a higher density of metal wires in the metal wiring layer 12.

[0066] Optionally, the number of metal wiring layers 12 can be 4 or 5. Figure 4 shows four metal wiring layers 12.

[0067] The dielectric layer 11 can be made from an insulating resin material, including, but not limited to, polybenzoxazole (PBO) or polyimide (PI).

[0068] The metal wiring layer 12 may be made from a conductive material including, but is not limited to, gold, silver, copper, or aluminum.

[0069] In some examples, as shown in Figure 4, the package substrate 1 may further include a solder resist layer 13. For example, there may be two solder resist layers 13. Multiple dielectric layers 11 and multiple metal wiring layers 12 form an overlapping structure, with the two solder resist layers 13 positioned on the front and back sides of the overlapping structure, respectively.

[0070] The solder resist layer 13 not only serves as an insulator, but also protects the package substrate 1 and shields the metal wires in the package substrate 1 from oxidation.

[0071] Optionally, the solder resist layer 13 may be made from an organic material, such as solder resist ink, as long as it can perform its insulating function, and this is not limited to the examples of this disclosure.

[0072] In some examples, as shown in Figure 4, the package substrate 1 has a first surface A and a second surface B that are opposite to each other. The first surface is the top surface of the package substrate shown in Figure 4, and the second surface is the bottom surface of the package substrate shown in Figure 4.

[0073] As shown in Figure 4, the first surface A of the package substrate 1 is provided with first pads 14 and second pads 15 arranged at intervals. There may be multiple first pads 14 and multiple second pads 15. Figure 4 shows nine first pads 14 and two second pads 15.

[0074] In some examples, both the first pad 14 and the second pad 15 are located on the topmost metal wiring layer 12 of the package substrate 1. The solder resist layer 13 also has multiple vias, each of which exposes one of the first pads 14 or one of the second pads 15.

[0075] In some examples, as shown in Figure 4, the first chip 2 is positioned on the first surface A of the package substrate 1 and electrically connected to the package substrate 1.

[0076] Optionally, the first chip 2 is electrically connected to the first pad 14 of the package substrate 1.

[0077] In some examples, in the top views shown in Figures 2 and 3, the first chip 2 can be positioned in the center of the package substrate 1, and therefore each first pad 14 can be positioned in the center of the package substrate 1. The first chip 2 and the first pad 14 can be electrically connected by a soldering process. For example, the soldering process may be a thermal pressure soldering process, an ultrasonic pressure soldering process, or a thermoacoustic soldering process. Of course, the first chip 2 and the first pad 14 may be electrically connected by other means, and this is not limited to the examples of this disclosure.

[0078] In some examples, as shown in Figure 4, the chip package structure 100 further comprises conductive pillars 6. The conductive pillars 6 are positioned on the first surface A of the package substrate 1 and are electrically connected to the package substrate 1.

[0079] Optionally, the conductive pillar 6 is electrically connected to the second pad 15 of the package substrate 1.

[0080] In some examples, the conductive pillar 6 may be made from at least one of metallic copper, metallic aluminum, metallic silver, or tin.

[0081] In some examples, the conductive pillar 6 may be columnar, such as a cylinder or a prism. Naturally, the conductive pillar 6 may also be of other irregular shapes, and this is not limited to the examples of this disclosure.

[0082] In some examples, as shown in Figure 4, the second chip 4 is positioned to the side of the first chip 2 away from the package substrate 1 and to the side of the conductive pillar 6. The second chip 4 is electrically connected to the conductive pillar 6 and is not in direct electrical connection with the first chip 2.

[0083] The electrical connection between the second chip 4 and the conductive pillar 6 can be achieved in various ways. For example, in the example of this disclosure, the second chip 4 may be electrically connected to the conductive pillar 6 using flip-chip bonding.

[0084] Flip-chip bonding can be understood as referring to a process of forming a ridge on the connection pad of a chip and directly connecting the ridge to a PCB substrate or metal substrate. More specifically, in the examples of this disclosure, the second chip 4 and the conductive pillar 6 are electrically connected using flip-chip bonding, which means that a ridge is formed on the connection pad of the second chip 4 and directly connected to the conductive pillar 6.

[0085] In some examples, as shown in Figure 4, the second chip 4 comprises a body 40 and pins 41 located below the body 40. In this case, the chip package structure 100 further comprises a first pad 61 located between the pins 41 and the conductive pillar 6. The second chip 4 is electrically connected to the conductive pillar 6 by the first pad 61. For example, pins 41 refer to the connection pad, and the first pad 61 refers to the protrusion.

[0086] The pin 41 may be made from at least one of copper, titanium, nickel, tungsten, and silver, for example. The first pad 61 may be made from tin, for example. The second tip 4 may be electrically connected to the conductive pillar 6 by a soldering process. In some examples, the soldering process may be a thermal pressure soldering method, an ultrasonic pressure soldering method, or a thermoacoustic soldering process.

[0087] In some examples, the orthographic projection of the conductive pillar 6 on the package substrate 1 is located within the orthographic projection of the first chip 2 or the second chip 4 on the package substrate 1. For example, as can be seen from Figures 2 and 3, the second chip 4 can completely cover the conductive pillar 6, and the conductive pillar 6 is located within the boundary of the orthographic projection of the second chip 4 onto the package substrate 1.

[0088] When the orthographic projection of the conductive pillar 6 onto the package substrate 1 is positioned within the orthographic projection of the second chip 4 on the package substrate 1, the conductive pillar 6 can provide support to the second chip 4 to improve the stability of the second chip 4 and further improve the structural stability of the chip package structure 100.

[0089] Since the conductive pillar 6 is positioned below the second chip 4 and electrically connected to the lateral surface of the second chip 4 closer to the package substrate 1, the conductive pillar 6 can extend perpendicular to the first surface A of the package substrate 1 so as to be vertical. The length of the signal transmission path between the second chip 4 and the package substrate 1 is substantially equal to the height of the conductive pillar 6, or substantially equal to the distance between the first surface A and the lateral surface of the second chip 4 closer to the package substrate 1. In this method, the signal transmission path between the first chip 2 and the second chip 4 can be made considerably shorter, and the speed of signal transmission can be greatly improved.

[0090] Furthermore, the cross-sectional area of ​​the conductive pillar 6 is larger than that of the gold wire, and correspondingly, the resistance of the conductive pillar 6 is smaller than that of the gold wire, which helps to further improve the speed of signal transmission.

[0091] If the orthographic projection of the conductive pillar 6 on the package substrate 1 is located within the orthographic projection of the first chip 2 on the package substrate 1, then the orthographic projection of the conductive pillar 6 on the package substrate 1 may also be located within the orthographic projection of the second chip 4 on the package substrate 1. In this case, the region of the orthographic projection of the first chip 2 on the package substrate 1 can be larger than the region of the orthographic projection of the second chip 4 on the package substrate 1, and the conductive pillar 6 may be electrically connected to the second chip 4 after passing through the first chip 2.

[0092] Therefore, in some examples of the chip package structure 100 of this disclosure, the second chip 4 is positioned above the first chip 2 such that the package substrate 1, the first chip 2, the conductive pillar 6, and the second chip 4 form a stacked structure, which improves the compactness of the chip package structure 100 and helps reduce the area of ​​the chip package structure 100. Furthermore, by providing the conductive pillar 6 to realize an electrical connection between the second chip 4 and the package substrate 1, and by positioning the conductive pillar 6 below the first chip 2 or the second chip 4, the orthographic projection of the conductive pillar 6 on the package substrate 1 is positioned within the range of the orthographic projection of the first chip 2 or the second chip 4 on the package substrate 1. In this way, the space around the first chip 2 or the second chip 4 is not occupied, which helps to further miniaturize the chip package structure 100 and further reduce the area of ​​the chip package structure 100.

[0093] Furthermore, the effective length of the conductive pillar 6 is substantially equal to the distance between the first surface A and the side surface of the second chip 4 closer to the package substrate 1. Compared to the electrical connection between the second chip 4 and the package substrate 1 realized by gold wire, the signal transmission path between the first chip 2 and the second chip 4 in the example of this application is shortened, which helps to improve the speed of signal transmission. Moreover, compared to gold wire, the conductive pillar 6 is larger in size and has lower resistance, which helps to further improve the speed of signal transmission between the first chip 2 and the second chip 4. Thus, the chip package structure 100 can improve response speed, reduce power consumption, and save power.

[0094] For example, if the area of ​​the second chip is larger than the area of ​​the first chip, it should be noted that in the chip package structure, the size of the package plane is close to the size of the area of ​​the second chip.

[0095] In some examples, as shown in Figure 4, the lateral surface of the second chip 4 closer to the package substrate 1 is higher than the lateral surface of the first chip 2 further away from the package substrate 1, relative to the first surface A of the package substrate 1. In other words, there is a specific distance between the lateral surface of the second chip 4 closer to the package substrate 1 and the lateral surface of the first chip 2 further away from the package substrate 1. That is, the first chip 2 and the second chip 4 are spaced apart in a direction perpendicular to the first surface A.

[0096] In some examples, the distance between the lateral surface of the second chip 4 closer to the package substrate 1 and the lateral surface of the first chip 2 further away from the package substrate 1 is 20 μm or more. For example, the distance may be 20 μm, 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, etc. In this specification, "distance" refers to the distance in a direction perpendicular to the first surface.

[0097] With the above arrangement, signal interference between the second chip 4 and the first chip 2 can be avoided, which helps improve the reliability of the chip package structure 100.

[0098] Optionally, with respect to the first surface A of the package substrate 1, the end of the conductive pillar 6 away from the package substrate 1 is higher than the lateral surface of the first chip 2 away from the package substrate 1.

[0099] In some examples, as shown in Figure 4, the distance between the lateral surface of the second chip 4 closer to the package substrate 1 and the first surface A of the package substrate 1 is h1, and the distance between the lateral surface of the first chip 2 further away from the package substrate 1 and the first surface A of the package substrate 1 is h2, where h1 and h2 satisfy the following conditions.

[0100]

number

[0101] In some examples, the value of h2 / h1 could be, for example, 5 / 8, 5 / 7, 7 / 10, 3 / 4, 4 / 5, etc.

[0102] In some examples, the distance between the lateral surface of the first chip 2 that is further away from the package substrate 1 and the first surface A of the package substrate 1 is in the range of 50 μm to 80 μm. In this respect, the distance between the lateral surface of the second chip 4 that is closer to the package substrate 1 and the first surface A of the package substrate 1 may be between 70 μm and 110 μm. For example, when the distance between the lateral surface of the first chip 2 that is further away from the package substrate 1 and the first surface A of the package substrate 1 is 50 μm, the distance between the lateral surface of the second chip 4 that is closer to the package substrate 1 and the first surface A of the package substrate 1 may be 70 μm. In another example, when the distance between the lateral surface of the first chip 2 that is further away from the package substrate 1 and the first surface A of the package substrate 1 is 80 μm, the distance between the lateral surface of the second chip 4 that is closer to the package substrate 1 and the first surface A of the package substrate 1 may be 110 μm.

[0103] With the above arrangement, a specific distance is ensured between the first chip 2 and the second chip 4, thereby avoiding signal interference between the first chip 2 and the second chip 4. Based on this, it is also possible to prevent the distance between the first chip 2 and the second chip 4 from becoming too large, which ensures a thin and light structure for the chip package structure 100.

[0104] In some examples, as shown in Figures 2 and 3, the number of conductive pillars 6 is greater than one. Multiple conductive pillars 6 are located on at least two opposing sides of the first chip 2. For example, multiple conductive pillars 6 are located on two opposing sides of the first chip 2 (as shown in Figure 2), or multiple conductive pillars 6 are located on three or four sides of the first chip 2 (as shown in Figure 3).

[0105] In some examples, the number of conductive pillars 6 located on different sides of the first chip 2 may be the same or different. Multiple conductive pillars 6 located on the same side of the first chip 2 may be regularly arranged by at least one pillar, and of course, multiple conductive pillars 6 located on the same side of the first chip 2 may be arranged in a staggered pattern, and this is not limited to the examples of the present disclosure.

[0106] In this example, multiple conductive pillars 6 are positioned on at least two opposing sides of the first chip 2, which not only ensures electrical connection between the second chip 4 and the package substrate 1, but also provides a relatively balanced support force for the second chip 4, thereby ensuring the structural stability of the second chip 4.

[0107] In some examples, as shown in Figures 5 and 6, the chip package structure 100 further comprises a package layer 7. The package layer 7 is positioned between the package substrate 1 and the second chip 4, covering the first chip 2 and surrounding the sides of the conductive pillar 6.

[0108] In some examples, the package layer 7 has a layered structure as a whole, and the side surface of the package layer 7 away from the package substrate 1 is, for example, a flat surface, and this surface is flush with, for example, the side surface of the conductive pillar away from the package substrate 1, and the package layer 7 exposes the side surface of the conductive pillar 6 away from the package substrate 1.

[0109] In some examples, the orthographic projection area of ​​the package layer 7 onto the package substrate 1 essentially coincides with the area of ​​the first surface A of the package substrate 1, and the orthographic projection boundary of the package layer 7 onto the package substrate 1 essentially coincides with the boundary of the first surface A of the package substrate 1.

[0110] In some examples, the material of the package layer 7 may be a moldable composite material. In this respect, the package layer 7 may be formed by a molding process. The material of the package layer 7 may be other materials, and this is not limited to the examples of this disclosure.

[0111] With the above arrangement, not only can the first chip 2 be packaged by the package layer 7, but the package layer 7 also contacts the sides of the conductive pillar 6 to provide physical protection to the first chip 2 and the conductive pillar 6, and to fix the positions of the first chip 2 and the conductive pillar 6 on the package substrate, thereby ensuring the structural integrity and stability of the chip package structure 100.

[0112] In some examples, as shown in Figures 5 and 6, the orthographic projection of the second chip 4 on the package substrate 1 is located within the range of the orthographic projection of the package layer 7 on the package substrate 1.

[0113] For example, the orthographic region of the second chip 4 on the package substrate 1 is smaller than the orthographic region of the package layer 7 on the package substrate 1. The orthographic boundary of the package layer 7 on the package substrate 1 encloses the orthographic boundary of the second chip 4 on the package substrate 1, and there is a specific distance between the two boundaries.

[0114] With the above arrangement, the package layer 7 can provide specific support to the second chip 4.

[0115] In some examples, as shown in Figures 5 and 6, the chip package structure 100 further comprises a first fill portion 8. At least a portion of the first fill portion 8 is positioned between the package layer 7 and the second chip 4, and the first fill portion 8 surrounds each pin of the second chip 4.

[0116] For example, the first filling portion 8 is positioned between the package layer 7 and the second chip 4, and the second chip 4 covers the first filling portion 8. Alternatively, the first filling portion 8 is positioned not only between the package layer 7 and the second chip 4, but also on both sides of the second chip 4, and the orthographic projection of the second chip 4 onto the package substrate 1 is positioned within the range of the orthographic projection of the first filling portion 8 onto the package substrate 1.

[0117] The first fill portion 8 is filled between two adjacent pins to prevent a short circuit between any two adjacent pins of the second chip 4.

[0118] For example, the material of the first fill portion 8 may be an epoxy resin material. When the epoxy resin material is filled between the package layer 7 and the second chip 4 to form the first fill portion 8, a hole may be formed, and the area of ​​the hole may be, for example, 15% or less.

[0119] In this example, by placing the first fill portion 8 between the package layer 7 and the second chip 4, support can be provided for the second chip 4, and the bonding force between the second chip 4 and the package layer 7 is also increased, ensuring the structural stability of the second chip 4 and thereby improving the reliability of the chip package structure 100. Short circuits between any two adjacent pins of the second chip 4 can also be avoided, which ensures the yield of the chip package structure 100.

[0120] In some examples, as shown in Figures 5 and 6, the chip package structure 100 further comprises an electromagnetic shielding layer 9. The electromagnetic shielding layer 9 covers not only the second chip 4 but also at least the sides of the package layer 7.

[0121] For example, the electromagnetic shielding layer 9 covers not only the second chip 4 but also the sides of the package layer 7. Alternatively, the electromagnetic shielding layer 9 may cover not only the sides of the package layer 7 but also other components, such as the sides of the first fill portion 8, and this is not limited to the examples of this disclosure.

[0122] For example, the electromagnetic shielding layer 9 is made from a ferromagnetic material (such as steel) with very high magnetic permeability, and the electromagnetic shielding layer 9 can electromagnetically shield the area it covers.

[0123] By arranging the electromagnetic shielding layer 9, the first chip 2 and the second chip 4 can be effectively prevented from being subjected to electromagnetic interference, thereby improving the electromagnetic interference resistance of the chip package structure 100.

[0124] In some examples, as shown in Figures 5 and 6, the package substrate 1 further comprises at least one grounding wire 16. The grounding wire 16 is located in the metal wiring layer 12.

[0125] In some examples, as shown in Figures 5 and 6, the electromagnetic shielding layer 9 also covers the sides of the package substrate 1 and is electrically connected to the grounding wire 16.

[0126] In this example, the electromagnetic shielding layer 9 covers not only the second chip 4 but also the sides of the package layer 7 and the package substrate 1 in order to electromagnetically shield the chip package structure 100 and effectively prevent electromagnetic interference. Furthermore, the electromagnetic shielding layer 9 can be further electrically connected to the grounding wire 16 to guide electromagnetic radiation to the ground, which achieves double the anti-electromagnetic interference and further ensures the effective operation of the chip package structure 100. In this respect, the anti-electromagnetic interference capability of the chip package structure 100 is realized by the electromagnetic shielding layer 9, which has low process costs, is simple and convenient to implement, and is suitable for mass production.

[0127] In some examples, as shown in Figure 6, the second chip 4 comprises multiple subchips 42. For example, the multiple subchips 42 are stacked in a continuous manner in a direction perpendicular to the package substrate 1. For example, the multiple subchips are of the same type and, at their discretion, all of them are memory chips.

[0128] In some examples, the separation structure 43 is placed between two adjacent subchips 42. The material of the separation structure 43 may be an adhesive material. The two adjacent subchips 42 are connected by the adhesive material.

[0129] In some other examples, one subchip 42 near the package substrate 1 is electrically connected to a conductive pillar 6, thereby achieving an electrical connection with the package substrate 1 through the conductive pillar. Other subchips 42 are electrically connected to the package substrate 1 through wires by a wire bonding process.

[0130] For example, each subchip 42 is electrically connected to the package substrate 1 so as to communicate with the first chip 2. In this respect, each subchip 42 can store different information under the control of the first chip 2, which ensures the storage diversity of the chip package structure 100.

[0131] In some other examples, two adjacent subchips 42 are electrically connected, as shown in Figure 6. For example, two adjacent subchips 42 may be connected to each other by a gold wire. In other examples, the subchip 42 has subpins 401, and the chip package structure 100 further includes a second pad 402 located between the two adjacent subchips 42. As shown in Figure 6, the two adjacent subchips 42 are electrically connected through the pins and the second pad 402.

[0132] For example, the material of sub-pin 401 includes at least one of the metals copper, titanium, nickel, tungsten, and silver. The material of the second pad 402 may include tin. In this regard, the two adjacent sub-chips 42 are electrically connected by a soldering process.

[0133] For example, the soldering process could be a thermal pressure soldering method, an ultrasonic pressure soldering method, or a thermal ultrasonic soldering method.

[0134] In this example, by stacking multiple subchips 42 to form the second chip 4, the integration density of the chip package structure 100 can be improved, and the product performance of the chip package structure 100 can be improved based on securing a smaller package area.

[0135] It should be noted that the first chip 2 may also comprise multiple subchips. When the first chip 2 comprises multiple subchips, the subchips may be stacked continuously in a direction away from the package substrate 1.

[0136] In some examples, as shown in Figures 5 and 6, the chip package structure 100 further comprises a second filling portion 10. At least a portion of the second filling portion 10 is positioned between the package substrate 1 and the first chip 2, and the second filling portion 10 surrounds each pin of the first chip 2.

[0137] For example, the second filling portion 10 is positioned between the package substrate 1 and the first chip 2, and the first chip 2 covers the second filling portion 10. Alternatively, the second filling portion 10 is positioned not only between the package substrate 1 and the first chip 2, but also on both sides of the first chip 2, and the orthographic projection of the first chip 2 onto the package substrate 1 is positioned within the range of the orthographic projection of the second filling portion 10 onto the package substrate 1.

[0138] The second fill portion 10 is filled between any two adjacent pins of the first chip 2 to prevent a short circuit between the two adjacent pins.

[0139] For example, the material of the second filling portion 10 is an epoxy resin material.

[0140] When epoxy resin material or the like is filled between the package substrate 1 and the first chip 2 to form a second filling portion 10, holes may be formed, and the area of ​​the holes is, for example, 15% or less.

[0141] In this example, by placing the second filling portion 10 between the package substrate 1 and the first chip 2, support can be provided for the first chip 2, and the bonding force between the first chip 2 and the package substrate 1 can also be increased, ensuring the structural stability of the first chip 2 and thereby improving the reliability of the chip package structure 100. Short circuits between any two adjacent pins of the first chip 2 can also be avoided, which ensures the yield of the chip package structure 100.

[0142] In some examples, as shown in Figures 4, 5, and 6, a third pad 17 is provided on the second surface B of the package substrate 1. The third pad 17 is located on the metal wiring layer 12. For example, the number of third pads 17 is greater than 1.

[0143] For example, the solder resist layer 13 has multiple vias, and each via exposes one third pad 17.

[0144] In some examples, as shown in Figures 4, 5, and 6, the chip package structure 100 further comprises solder balls 20. The number of solder balls 20 is greater than one, and multiple solder balls 20 are positioned on the second surface B of the package substrate 1 and electrically connected to the package substrate 1.

[0145] Optionally, the solder balls 20 are electrically connected to the third pads 17 on the package substrate 1. Multiple solder balls 20 and multiple third pads 17 can be arranged in a one-to-one correspondence.

[0146] For example, the solder ball 20 can be soldered to the third pad 17 by a ball planting process.

[0147] The solder ball 20 is electrically connected to the metal wires in the package substrate 1 through the third pad 17. In this respect, the solder ball 20 can serve as a junction between the package substrate 1 and the outside, thereby realizing an electrical connection between the chip package structure 100 and the external module, and further, enabling communication between the chip package structure 100 and the external module.

[0148] For example, if the density of metal wires in the package substrate 1 is very high, the signal transmission path between the solder ball 20 and the metal wires in the package substrate 1 is shortened, which improves the signal transmission speed.

[0149] For example, the pins of the first chip 2 (i.e., input / output (I / O) terminals) are redistributed through the package substrate 1 and a plurality of solder balls 20 located on the second surface B of the package substrate 1. In this respect, the chip package structure 100 is a fan-out chip package structure, and the fan-out chip package structure is connected to an external module (such as a motherboard or printed circuit board) through the solder balls 20.

[0150] Examples of the present disclosure also provide other chip package structures 100. As shown in Figures 7 and 8, the chip package structure 100 comprises a first chip 2 and a second chipset 44. The second chipset 44 comprises a plurality of second chips 4. The plurality of second chips 4 are stacked continuously, for example, in a direction perpendicular to the package substrate 1.

[0151] The first chip 2 and the second chip 4 may have different functions. For example, the first chip 2 may be a control device, and the second chip 4 may be a memory chip. The memory chip has a memory structure for providing memory functionality. There are many types of memory chips. For example, memory chips include, but are not limited to, NAND chips, resistive memory chips, and dynamic random access memory. Naturally, the first chip 2 may be a memory chip, and the second chip 4 may be a control device, and this is not limited to the examples of this disclosure.

[0152] In some examples, the chip package structure 100 further comprises a package substrate 1. The package substrate 1 is rigid and can therefore provide support for the first chip 2 and the second chip 4.

[0153] For example, as shown in Figures 7 and 8, the package substrate 1 comprises a plurality of dielectric layers 11 and a plurality of metal wiring layers 12 arranged alternately. One metal wiring layer 12 is positioned between two adjacent dielectric layers 11, and one dielectric layer 11 is positioned between two adjacent metal wiring layers 12. Each metal wiring layer 12 contains metal wires, and the metal wires in two adjacent metal wiring layers 12 can extend through the dielectric layer 11 between the two adjacent metal wiring layers 12 and be connected as required.

[0154] In some examples, the dielectric layer 11 in the package substrate 1 is formed by a spin coating method, and the metal wiring layer 12 in the package substrate 1 is formed by a physical vapor deposition (PVD) process combined with an electroplating process. Therefore, compared to a package substrate formed by an in-fill process, the package substrate 1 composed of the dielectric layer 11 and the metal wiring layer 12, provided by the examples of this disclosure, has a smaller thickness, smaller spacing between adjacent metal wiring layers 12, and consequently a higher density of metal wires in the metal wiring layer 12.

[0155] Optionally, the number of metal wiring layers 12 can be four or five. Figure 7 shows four metal wiring layers 12.

[0156] The dielectric layer 11 may be made from an insulating resin material, for example, polybenzoxazole (PBO), polyimide (PI), etc., although this is not limited to the above.

[0157] The metal wiring layer 12 may be made from a conductive material including, but is not limited to, gold, silver, copper, or aluminum.

[0158] For example, as shown in Figure 7, the package substrate 1 may further include a solder resist layer 13. For example, there may be two solder resist layers 13. Multiple dielectric layers 11 and multiple metal wiring layers 12 form an overlapping structure, and the two solder resist layers 13 are positioned on the front and back sides of the overlapping structure, respectively.

[0159] The solder resist layer 13 not only serves as an insulator, but also protects the package substrate 1 and shields the metal wires in the package substrate 1 from oxidation.

[0160] Optionally, the solder resist layer 13 may be made from an organic material, such as solder resist ink, as long as it can perform its insulating function, and this is not limited to the examples of this disclosure.

[0161] In some examples, as shown in Figures 7 and 8, the package substrate 1 has a first surface A and a second surface B that are opposite to each other. The first surface is the top surface of the package substrate shown in Figures 7 and 8, and the second surface is the bottom surface of the package substrate shown in Figures 7 and 8.

[0162] As shown in Figures 7 and 8, the first surface A of the package substrate 1 is provided with first pads 14 and second pads 15 arranged at intervals. There may be multiple first pads 14 and multiple second pads 15. Figure 8 shows nine first pads 14 and two second pads 15.

[0163] For example, both the first pad 14 and the second pad 15 are positioned on the topmost metal wiring layer 12 of the package substrate 1. The solder resist layer 13 also has multiple vias, each of which exposes one of the first pads 14 or one of the second pads 15.

[0164] In some examples, as shown in Figures 7 and 8, the first chip 2 is positioned on the first surface A of the package substrate 1 and electrically connected to the package substrate 1.

[0165] Optionally, the first chip 2 is electrically connected to the first pad 14 of the package substrate 1.

[0166] For example, the first chip 2 and the first pad 14 may be electrically connected by a soldering process. For example, the soldering process may be a thermal pressure soldering process, an ultrasonic pressure soldering process, or a thermoacoustic soldering process. Of course, the first chip 2 and the first pad 14 may be electrically connected by other means, and this is not limited to the examples of this disclosure.

[0167] In some examples, as shown in Figures 7 and 8, the second chipset 44 is positioned to the side of the first chip 2 that is away from the package substrate 1. The second chipset 44 is electrically connected to the package substrate 1 and does not have a direct electrical connection to the first chip 2.

[0168] The second chipset 44 and the package substrate 1 can be electrically connected in various ways. For example, the second chipset 44 and the package substrate 1 can be electrically connected through the conductive structure 30.

[0169] The conductive structure 30 is electrically connected to the package substrate 1 and the second chipset 44.

[0170] For example, as shown in Figure 7, the conductive structure 30 may include a wire 31. One end of the wire 31 is electrically connected to the second chipset 44, and the other end of the wire 31 is electrically connected to the exposed metal wiring layer 12 in the package substrate 1, so that the second chipset 44 is electrically connected to the package substrate 1 by coupling a lead wire to the wire 31. In this regard, the material of the wire may include at least one of metallic gold, metallic aluminum, metallic silver, or metallic copper.

[0171] As a further example, as shown in Figure 8, the shape of the conductive structure 30 may be columnar, such as a cylinder or a prism. Naturally, the shape of the conductive structure 30 may also be other irregular shapes, and this is not limited to the examples of this disclosure. In this regard, the material of the conductive structure 30 may include at least one of metallic copper, metallic aluminum, metallic silver, or tin.

[0172] Therefore, in some examples of the chip package structure 100 of this disclosure, the second chipset 44 is placed above the first chip 2 such that the package substrate 1, the first chip 2, and the second chipset 44 form a stacked structure, which improves the compactness of the chip package structure 100 and helps reduce the area of ​​the chip package structure 100. Furthermore, by stacking multiple second chips 4 to form the second chipset 44, the integration density of the chip package structure 100 can be improved, and the product performance of the chip package structure 100 can be improved based on securing a smaller package area.

[0173] For example, a separation structure 43 is placed between two adjacent second chips 4. The material of the separation structure 43 may be an adhesive material. The two adjacent second chips 4 are connected by the adhesive material.

[0174] In some examples, two adjacent second chips 4 are electrically connected. Two adjacent second chips 4 can be electrically connected in various ways.

[0175] For example, two adjacent second chips 4 may be connected to each other by a wire. The wire material may include at least one of metallic gold, metallic aluminum, metallic silver, or metallic copper.

[0176] In another example, the second chip 4 has through-silicon vias (TSVs), which are filled with conductive material. The chip package structure 100 further includes a third pad 431 positioned between two adjacent second chips 4. As shown in Figure 8, the conductive metal in the TSV and the third pad 431 can be electrically connected by a soldering process, thereby achieving an electrical connection between the two connected second chips 4.

[0177] In another example, the second chip 4 may comprise a body and pins located below the body. In this regard, the chip package structure 100 further comprises pads located on the pins and another second chip 4. The second chip 4 is electrically connected to the other second chip 4 through the pads.

[0178] With the above arrangement, multiple second chips 4 can be directly connected to each other in order to secure a smaller package area. This shortens the signal transmission path between adjacent second chips 4 and improves the signal transmission speed.

[0179] In some other examples, as shown in Figure 7, in a plurality of second chips 4, each second chip 4 is electrically connected to the package substrate 1 via an electric wire 31.

[0180] For example, each second chip 4 is electrically connected to the package substrate 1 so as to communicate with the first chip 2. In this respect, each second chip 4 can store different information under the control of the first chip 2, which ensures the storage diversity of the chip package structure 100.

[0181] It should be noted that there may be multiple first chips 2. When there are multiple first chips 2, the multiple first chips 2 may be stacked continuously in a direction away from the package substrate 1.

[0182] In some examples, as shown in Figures 7 and 8, the lateral surface of the second chipset 44 closer to the package substrate 1 is higher than the lateral surface of the first chip 2 further away from the package substrate 1, relative to the first surface A of the package substrate 1. In other words, there is a certain distance between the lateral surface of the second chipset 44 closer to the package substrate 1 and the lateral surface of the first chip 2 further away from the package substrate 1. That is, the first chip 2 and the second chipset 44 are spaced apart in the direction perpendicular to the first surface A.

[0183] For example, the distance between the lateral surface of the second chipset 44 closer to the package substrate 1 and the lateral surface of the first chip 2 further away from the package substrate 1 is 20 μm or more. For example, the distance may be 20 μm, 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, etc. Here, "distance" refers to the distance in the direction perpendicular to the first surface.

[0184] With the above arrangement, signal interference between the second chipset 44 and the first chip 2 can be avoided, which is beneficial in improving the reliability and dependability of the chip package structure 100.

[0185] In some examples, as shown in Figure 8, the distance between the lateral surface of the second chipset 44 closer to the package substrate 1 and the first surface A of the package substrate 1 is h1, and the distance between the lateral surface of the first chip 2 further away from the package substrate 1 and the first surface A of the package substrate 1 is h2, where h1 and h2 satisfy the following conditions.

[0186]

number

[0187] For example, the value of h2 / h1 could be 5 / 8, 5 / 7, 7 / 10, 3 / 4, 4 / 5, etc.

[0188] In some examples, the distance between the lateral surface of the first chip 2 that is further away from the package substrate 1 and the first surface A of the package substrate 1 is in the range of 50 μm to 80 μm. In this regard, the distance between the lateral surface of the second chipset 44 that is closer to the package substrate 1 and the first surface A of the package substrate 1 may be between 70 μm and 110 μm. For example, when the distance between the lateral surface of the first chip 2 that is further away from the package substrate 1 and the first surface A of the package substrate 1 is 50 μm, the distance between the lateral surface of the second chipset 44 that is closer to the package substrate 1 and the first surface A of the package substrate 1 may be 70 μm. In other examples, when the distance between the lateral surface of the first chip 2 that is further away from the package substrate 1 and the first surface A of the package substrate 1 is 80 μm, the distance between the lateral surface of the second chipset 44 that is closer to the package substrate 1 and the first surface A of the package substrate 1 may be 110 μm.

[0189] With the above arrangement, a specific distance is ensured between the first chip 2 and the second chipset 44, thereby avoiding signal interference between the first chip 2 and the second chipset 44. Based on this, it is also possible to prevent the distance between the first chip 2 and the second chipset 44 from becoming too large, which ensures a thin and light structure for the chip package structure 100.

[0190] In some examples, as shown in Figures 7 and 8, the chip package structure 100 further comprises a package layer 7. The package layer 7 is positioned between the package substrate 1 and the second chipset 44, and the package layer 7 covers the first chip 2.

[0191] For example, the package layer 7 has a layered structure overall, and the lateral surface of the package layer 7 away from the package substrate 1 is, for example, a flat surface. If the conductive structure 30 is columnar in shape, the lateral surface of the package layer 7 away from the package substrate 1 is, for example, flush with the lateral surface of the conductive structure 30 away from the package substrate 1, and the package layer 7 exposes the lateral surface of the conductive structure 30 away from the package substrate 1.

[0192] For example, the orthographic projection area of ​​the package layer 7 onto the package substrate 1 essentially coincides with the area of ​​the first surface A of the package substrate 1, and the orthographic projection boundary of the package layer 7 onto the package substrate 1 essentially coincides with the boundary of the first surface A of the package substrate 1.

[0193] For example, the material of the package layer 7 may be a moldable composite material. In this respect, the package layer 7 may be formed by a molding process. The material of the package layer 7 may be other materials, and this is not limited to the examples of this disclosure.

[0194] With the above arrangement, the first chip 2 can not only be packaged by the package layer 7, but the first chip 2 can also be physically protected by the package layer 7, and the position of the first chip 2 on the package substrate can be fixed in order to ensure the structural integrity and stability of the chip package structure 100.

[0195] In some examples, as shown in Figures 7 and 8, the orthographic projection of the second chipset 44 on the package substrate 1 is located within the range of the orthographic projection of the package layer 7 on the package substrate 1.

[0196] For example, the orthographic region of the second chipset 44 on the package substrate 1 is smaller than the orthographic region of the package layer 7 on the package substrate 1. The orthographic boundary of the package layer 7 on the package substrate 1 encloses the orthographic boundary of the second chipset 44 on the package substrate 1, and there is a specific distance between the two boundaries.

[0197] With the above arrangement, the package layer 7 can provide specific support to the second chipset 44.

[0198] In some examples, as shown in Figures 7 and 8, the chip package structure 100 further comprises a first fill portion 8. At least a portion of the first fill portion 8 is positioned between the package layer 7 and the second chipset 44, and the first fill portion 8 surrounds each pin of one of the second chips 4 near the package substrate 1.

[0199] For example, the first fill portion 8 is positioned between the package layer 7 and the second chipset 44, with the second chipset 44 covering the first fill portion 8. Alternatively, the first fill portion 8 is positioned not only between the package layer 7 and the second chipset 44, but also on both sides of one second chip 4 near the package substrate 1, and the orthographic projection of one second chip 4 near the package substrate 1 onto the package substrate 1 is positioned within the range of the orthographic projection of the first fill portion 8 onto the package substrate 1.

[0200] The first filling portion 8 is filled between two adjacent pins to avoid a short circuit between any two adjacent pins of one of the second chips 4 near the package substrate 1.

[0201] For example, the material of the first fill portion 8 may be an epoxy resin material. When the epoxy resin material is filled between the package layer 7 and the second chipset 44 to form the first fill portion 8, a hole may be formed, and the area of ​​the hole may be, for example, 15% or less.

[0202] In this example, by placing the first fill portion 8 between the package layer 7 and the second chipset 44, support can be provided for the second chipset 44, and the bonding force between the second chipset 44 and the package layer 7 is also increased, ensuring the structural stability of the second chipset 44 and thereby improving the reliability of the chip package structure 100. Short circuits between any two adjacent pins of one second chip 4 near the package substrate 1 can also be avoided, thereby ensuring the yield of the chip package structure 100.

[0203] In some examples, as shown in Figure 8, the chip package structure 100 further comprises an electromagnetic shielding layer 9. The electromagnetic shielding layer 9 covers not only the second chipset 44 but also at least the sides of the package layer 7.

[0204] For example, the electromagnetic shielding layer 9 covers not only the second chipset 44 but also the sides of the package layer 7. Alternatively, the electromagnetic shielding layer 9 may cover not only the second chipset 44 but also the sides of the package layer 7, as well as other components, such as the sides of the first fill portion 8, and this is not limited to the examples of this disclosure.

[0205] For example, the electromagnetic shielding layer 9 is made from a ferromagnetic material (such as steel) with very high magnetic permeability, and the electromagnetic shielding layer 9 can electromagnetically shield the area it covers.

[0206] By placing the electromagnetic shielding layer 9, the first chip 2 and the second chipset 44 can be effectively prevented from being subjected to electromagnetic interference, thereby improving the electromagnetic interference resistance of the chip package structure 100.

[0207] In some examples, as shown in Figure 8, the package substrate 1 further comprises at least one grounding wire 16. The grounding wire 16 is located in the metal wiring layer 12.

[0208] In some examples, as shown in Figure 8, the electromagnetic shielding layer 9 also covers the sides of the package substrate 1 and is electrically connected to the grounding wire 16.

[0209] In this example, the electromagnetic shielding layer 9 covers not only the sides of the second chipset 44 and package layer 7 but also the sides of the package substrate 1 in order to electromagnetically shield the chip package structure 100 and effectively prevent electromagnetic interference. Furthermore, the electromagnetic shielding layer 9 can be electrically connected to the grounding wire 16 to guide electromagnetic radiation to the ground, which achieves double the anti-electromagnetic interference and ensures the effective operation of the chip package structure 100. In this respect, the anti-electromagnetic interference capability of the chip package structure 100 is realized by the electromagnetic shielding layer 9, which has low process costs, is simple and convenient to implement, and is suitable for mass production.

[0210] In some examples, as shown in Figures 7 and 8, the chip package structure 100 further comprises a second filling portion 10. At least a portion of the second filling portion 10 is positioned between the package substrate 1 and the first chip 2, and the second filling portion 10 surrounds each pin of the first chip 2.

[0211] For example, the second filling portion 10 is positioned between the package substrate 1 and the first chip 2, and the first chip 2 covers the second filling portion 10. Alternatively, the second filling portion 10 is positioned not only between the package substrate 1 and the first chip 2, but also on both sides of the first chip 2, and the orthographic projection of the first chip 2 onto the package substrate 1 is positioned within the range of the orthographic projection of the second filling portion 10 onto the package substrate 1.

[0212] The second fill portion 10 is filled between two adjacent pins to avoid a short circuit between any two adjacent pins of the first chip 2.

[0213] For example, the material of the second filling portion 10 is an epoxy resin material.

[0214] When epoxy resin material or the like is filled between the package substrate 1 and the first chip 2 to form a second filling portion 10, holes may be formed, and the area of ​​the holes is, for example, 15% or less.

[0215] In this example, by placing the second filling portion 10 between the package substrate 1 and the first chip 2, support can be provided for the first chip 2, and the bonding force between the first chip 2 and the package substrate 1 can also be increased, ensuring the structural stability of the first chip 2 and thereby improving the reliability of the chip package structure 100. Short circuits between any two adjacent pins of the first chip 2 can also be avoided, which ensures the yield of the chip package structure 100.

[0216] In some examples, as shown in Figures 7 and 8, the third pad 17 is located on the second surface B of the package substrate 1. The third pad 17 is located on the metal wiring layer 12. For example, the number of third pads 17 is greater than 1.

[0217] For example, the solder resist layer 13 has multiple vias, and each via exposes one third pad 17.

[0218] In some examples, as shown in Figures 7 and 8, the chip package structure 100 further comprises solder balls 20. The number of solder balls 20 is greater than one, and multiple solder balls 20 are positioned on the second surface B of the package substrate 1 and electrically connected to the package substrate 1.

[0219] Optionally, the solder balls 20 are electrically connected to the third pads 17 on the package substrate 1. Multiple solder balls 20 and multiple third pads 17 can be arranged in a one-to-one correspondence.

[0220] For example, the solder ball 20 can be soldered to the third pad 17 by a ball planting process.

[0221] The solder ball 20 is electrically connected to the metal wires in the package substrate 1 through the third pad 17. In this respect, the solder ball 20 can serve as a junction between the package substrate 1 and the outside, thereby realizing an electrical connection between the chip package structure 100 and the external module, and further, enabling communication between the chip package structure 100 and the external module.

[0222] For example, if the density of metal wires in the package substrate 1 is very high, the signal transmission path between the solder ball 20 and the metal wires in the package substrate 1 is shortened, and the signal transmission speed is improved.

[0223] For example, the pins of the first chip 2 (i.e., input / output (I / O) terminals) are redistributed through the package substrate 1 and a plurality of solder balls 20 located on the second surface B of the package substrate 1. In this respect, the chip package structure 100 is a fan-out chip package structure, and the fan-out chip package structure is connected to an external module (such as a motherboard or printed circuit board) through the solder balls 20.

[0224] Examples of this disclosure also provide an electronic device 1000. As shown in Figure 9, the electronic device 1000 comprises a chip package structure 100 according to some of the above examples.

[0225] For example, as shown in Figure 9, the electronic device may further include a cover plate 200, a display screen 300, an intermediate frame 400, and a rear enclosure 500.

[0226] The display screen 300 can be a liquid crystal display (LCD) screen, or it may be an organic light-emitting diode (OLED) display screen, a quantum dot light-emitting diode (QLED) display screen, a mini light-emitting diode (miniLED) display screen, or a micro light-emitting diode (microLED) display screen. The OLED display screen, QLED display screen, miniLED display screen, and microLED display screen are all self-emissive display screens.

[0227] The intermediate frame 400 may comprise a support plate 410 and a frame 420. The electronic device 1000 may further comprise a circuit board 600 disposed on the support plate 410. The chip package structure 100 is disposed on the circuit board 600 and electrically connected to the circuit board 600.

[0228] The beneficial effects that can be achieved by the electronic devices described herein can be referenced to the beneficial effects of semiconductor structures described above, which are not repeated here.

[0229] The above-mentioned electronic devices may be any one of the following: mobile phones, desktop computers, tablet computers, notebook computers, servers, in-car devices, wearable devices (such as smartwatches, smart bracelets, and smart glasses), mobile power supplies, game consoles, and digital multimedia players.

[0230] Examples of the present disclosure provide a method for manufacturing a chip package structure, which can be used, for example, to prepare a chip package structure 100 according to some of the above examples. Figure 10 is a flowchart of a method for manufacturing a chip package structure according to some examples of the present disclosure. Figures 11A to 11E, 12A to 12C, 13A to 13C, and 14A to 14C are structural cross-sectional views corresponding to steps in the method for manufacturing a chip package structure according to some examples, respectively. It should be understood that the steps shown in Figure 10 are not exclusive, and other steps may be performed before, after, or between any of the shown steps. Also, some of these steps may be performed simultaneously, or in an order different from the order shown in Figure 10.

[0231] As shown in Figure 10, the above manufacturing method includes the following steps S1 to S4.

[0232] S1: As shown in Figure 11A, a package substrate 1 is provided.

[0233] For example, the structure of package substrate 1 can be seen by referring to the illustrations in some of the above examples, which are not repeated here.

[0234] S2: As shown in Figures 11B and 12A, conductive pillars 6 are formed on the first surface A of the package substrate 1, and the conductive pillars 6 are electrically connected to the package substrate 1.

[0235] For example, the conductive pillar 6 can be formed by a sputtering process or an electroplating process. The material of the conductive pillar 6 may include at least one of copper, aluminum, silver, or tin.

[0236] S3: As shown in Figure 11C, the first chip 2 is placed on the first surface A of the package substrate 1. The first chip 2 is electrically connected to the package substrate 1.

[0237] For example, the method of connecting the first chip 2 and the package substrate 1 can be illustrated in some of the above examples, which are not repeated here.

[0238] S4: As shown in Figure 11D, the second chip 4 is positioned to the side of the conductive pillar 6 and the first chip 2, away from the package substrate 1. The second chip 4 is electrically connected to the conductive pillar 6.

[0239] For example, the orthographic projection of the conductive pillar 6 on the package substrate 1 is located within the orthographic projection of the first chip 2 or the second chip 4 on the package substrate 1.

[0240] The manufacturing methods disclosed in the preceding examples of this disclosure have the same structure and the same beneficial effects as the chip package structure 100 in some of the above examples, which are not repeated herein.

[0241] It should be noted that some of the steps of the above manufacturing method may be performed simultaneously or in a different order than that shown in Figure 10. For example, steps S2 and S3 may be reversed, that is, the first chip 2 may be placed first on the first surface A of the package substrate 1, and then the conductive pillar 6 may be formed on the first surface A of the package substrate 1.

[0242] In some examples, after step S2 above, the manufacturing method further includes S10 to S20.

[0243] S10: As shown in Figure 12B, the package film 07 is formed on the first chip 2 and the conductive pillar 6, and the package film 07 covers the first chip 2 and the conductive pillar 6.

[0244] Examples of the present disclosure may use chemical vapor deposition (CVD) or physical vapor deposition (PVD) to form the package film 07. The thickness of the package film is greater than the height of the conductive pillar and the thickness of the first chip, that is, with respect to the package substrate, the surface of the package film on the side away from the package substrate is higher than the surface of the conductive pillar on the side away from the package substrate and higher than the surface of the first chip on the side away from the package substrate.

[0245] S20: As shown in Figure 12C, the package film 07 is thinned to expose the conductive pillar 6, and the remaining package film 07 forms a package layer 7, which covers the first chip 2.

[0246] For example, the package film 07 can be thinned by mechanical polishing, chemical mechanical planarization, wet etching, and other thinning processes. In step S20 above, in the process of thinning the package film, the height of the conductive pillar 6 may be made lower to ensure that the conductive pillar 6 is exposed, thereby improving the creation of an electrical connection between the conductive pillar 6 and the second chip 4.

[0247] More specifically, the package film 07 covering the first chip 2 and the conductive pillar 6 can be formed by a molding material through a molding process.

[0248] In some examples, step S2 above includes steps S21 to S23.

[0249] S21: As shown in Figure 13A, the package layer 7 is formed on the first chip 2, and the package layer 7 covers the first chip 2.

[0250] More specifically, the covering package layer 7 may be formed by a molding material through a molding process.

[0251] S22: As shown in Figure 13B, vias 71 are formed in the package layer 7, and vias 71 expose the second pad 15.

[0252] In the examples of this disclosure, vias 71 may be formed through an etching process. The shape of vias 71 may be columnar, for example, a cylinder. The shape of vias 71 may also be other irregular shapes, and this is not limited to the examples of this disclosure.

[0253] S23: As shown in Figure 13C, a conductive material is filled in the vias to form conductive pillars 6.

[0254] In one example, the material of the conductive pillar 6 may be tin or the like. In this regard, the solder balls may be filled in vias, or they may be reflowed to form the solder pillar which is the conductive pillar 6 described above.

[0255] In some examples, as shown in Figure 11D, the above manufacturing method further includes the step of filling a first insulating material between the package layer 7 and the second chip 4 to form a first filling portion 8, the first filling portion 8 surrounding each pin of the second chip 4.

[0256] In one example, the first filling portion 8 is positioned between the package layer 7 and the second chip 4, and the second chip 4 covers the first filling portion 8. Alternatively, the first filling portion 8 is positioned not only between the package layer 7 and the second chip 4, but also on both sides of the second chip 4, and the orthographic projection of the second chip 4 onto the package substrate 1 is positioned within the range of the orthographic projection of the first filling portion 8 onto the package substrate 1.

[0257] The first fill portion 8 is filled between two adjacent pins to prevent a short circuit between any two adjacent pins of the second chip 4.

[0258] In one example, the first insulating material may be an epoxy resin material or the like.

[0259] In this example, by placing the first filling portion 8 between the package layer 7 and the second chip 4, support can be provided for the second chip 4, and the bonding force between the second chip 4 and the package layer 7 is also increased, which ensures the structural stability of the second chip 4 and also avoids short circuits between any two adjacent pins of the second chip 4, thereby further ensuring the yield of the chip package structure 100.

[0260] In some examples, the above manufacturing method further includes the step of forming an electromagnetic shielding layer 9, the electromagnetic shielding layer 9 covering at least the sides of the package layer 7 as well as the second chip 4, as shown in Figure 11E.

[0261] In one example, the electromagnetic shielding layer 9 is made from a ferromagnetic material (such as steel) with very high magnetic permeability, and the electromagnetic shielding layer 9 can electromagnetically shield the area it covers.

[0262] In the examples of this disclosure, the electromagnetic shielding layer 9 may be formed on the sides of the package layer 7 as well as the second chip 4 by methods such as spraying, electroplating, or vacuum sputtering. For example, a ferromagnetic material may be sprayed on the sides of the package layer 7 as well as the second chip 4 to form the electromagnetic shielding layer 9.

[0263] By arranging the electromagnetic shielding layer 9, the first chip 2 and the second chip 4 can be effectively prevented from being subjected to electromagnetic interference, thereby improving the electromagnetic interference resistance of the chip package structure 100.

[0264] In some examples, the second chip 4 comprises multiple subchips 42. In this respect, step S4 above includes steps S41 to S42.

[0265] S41: As shown in Figure 14A, multiple subchips 42 are stacked continuously along the thickness direction of the subchips 42 to form a second chip 4.

[0266] For example, multiple subchips 42 are stacked in a continuous manner along a direction perpendicular to the package substrate 1. For example, the multiple subchips are of the same type and, at their discretion, all of them are memory chips.

[0267] In some examples, the separation structure 43 is placed between two adjacent subchips 42. The material of the separation structure 43 may be an adhesive material. The two adjacent subchips 42 are superimposed by the adhesive material.

[0268] In some examples, there may be multiple connection relationships between multiple subchips 42; details can be found in the illustrations in some of the earlier examples and are not repeated here.

[0269] S42: As shown in Figure 14B, the second chip 4 is soldered to the end of the conductive pillar 6 that is away from the package substrate 1 so as to be electrically connected to the conductive pillar 6.

[0270] In some examples, as shown in Figure 14C, an electromagnetic shielding layer 9 may be formed after step S42, which covers at least the multiple subchips 42 and the sides of the package layer 7.

[0271] In this example, by stacking multiple subchips 42 to form a second chip 4, the integration density of the chip package structure 100 can be improved, and the product performance of the chip package structure 100 can be improved based on securing a small package volume.

[0272] In some examples, after placing the first chip 2 and before placing the second chip 4, the manufacturing method further includes the step of filling a second insulating material between the package substrate 1 and the first chip 2 to form a second filling portion 10, the second filling portion 10 surrounding each pin of the first chip 2, as shown in Figure 11C.

[0273] The second filling portion 10 is filled between two adjacent pins of any of the first chips 2 so as to avoid a short circuit between the two adjacent pins.

[0274] In some examples, the second insulating material can be an epoxy resin material or the like. In this regard, in this example, by disposing the second filling portion 10 between the package substrate 1 and the first chip 2, not only can support be provided for the first chip 2, but also the bonding force between the first chip 2 and the package substrate 1 can be improved, and the structural stability of the first chip 2 is ensured. A short circuit between any two adjacent pins of the first chip 2 can also be avoided, which ensures the yield of the chip package structure 100.

[0275] In some examples, the third pad 17 is disposed on the second surface B of the package substrate 1. The first surface A and the second surface B are opposite to each other. Before or after forming the package layer 7, the above manufacturing method further includes forming solder balls 20 on the second surface B of the package substrate 1, and the solder balls 20 are electrically connected to the third pad 17 as shown in FIG. 11D.

[0276] In some examples, the solder balls 20 can be soldered to the third pad 17 by a ball mounting process.

[0277] In some examples, the number of the solder balls 20 is greater than 1, and the plurality of solder balls 20 can form a ball grid array (BGA), and the ball grid array can be used as a joint portion between the chip package structure 100 and the outside.

[0278] The foregoing is merely a specific implementation of the present disclosure, and the protection scope of the present disclosure is not limited thereto. Modifications or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present disclosure should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Explanation of Reference Numerals

[0279] 1. 1' Package substrate 2, 2' First chip 3' Second chip 4. Second chip 6 Conductive Pillars 7 Packaging Layers 07 Package film 8. First filling portion 9 Electromagnetic shielding layer 10 Second filling portion 11 Dielectric layer 12 Metal wiring layer 13 Solder Resist Layer 14 First pad 15. Second pad 16 Ground wire 17. Third pad 20 Solder balls 30 Conductive Structure 31 Electric wire 40 Main Unit 41 pins 42 subchips 43 Separation structure 44. Second chipset 61 First pad 71 Beer 100, 100' Chip Package Structure 401 Sub-pin 402 Second pad 431 Third pad 200 cover plate 300 display screen 400 intermediate frames 410 Supporting board 420 frames 500 Back cabinet 600 circuit boards 1000 Electronic Devices A First surface B Second surface

Claims

1. A package substrate having a first surface, A first chip positioned on the first surface of the package substrate and electrically connected to the package substrate, A conductive pillar positioned on the first surface of the package substrate and electrically connected to the package substrate, A second chip is positioned to the side of the first chip and the conductive pillar, away from the package substrate, and is electrically connected to the conductive pillar, wherein the orthographic projection of the conductive pillar on the package substrate is located within the range of the orthographic projection of the first chip or the second chip on the package substrate. A chip package structure comprising, The aforementioned chip package structure further comprises a package layer, The package layer is positioned between the package substrate and the second chip, covers the first chip, and surrounds the sides of the conductive pillar. The chip package structure further comprises a first filling portion, At least a portion of the first filling portion is positioned between the package layer and the second chip, and the first filling portion surrounds each pin of the second chip. The chip package structure further includes a first pad positioned between the pin and the conductive pillar, which is in direct contact with the pin and the conductive pillar. The side surface of the second chip closer to the package substrate is higher than the side surface of the first chip further away from the package substrate, relative to the first surface of the package substrate. A chip package structure in which the distance between the lateral surface of the second chip closer to the package substrate and the first surface of the package substrate is h1, and the distance between the lateral surface of the first chip further away from the package substrate and the first surface of the package substrate is h2, and h1 and h2 satisfy the following conditions. [Math 1]

2. The chip package structure according to claim 1, wherein the orthographic projection of the second chip on the package substrate is located within the range of the orthographic projection of the package layer on the package substrate.

3. The aforementioned chip package structure further comprises an electromagnetic shielding layer, The chip package structure according to claim 1, wherein the electromagnetic shielding layer covers not only the second chip but also at least the sides of the package layer.

4. The package substrate is provided with at least one grounding wire. The chip package structure according to claim 3, wherein the electromagnetic shielding layer also covers the sides of the package substrate and is electrically connected to the grounding wire.

5. The chip package structure according to claim 1, wherein the second chip comprises a plurality of subchips that are continuously stacked in a direction perpendicular to the package substrate.

6. The chip package structure according to claim 5, wherein two adjacent subchips are electrically connected to each other.

7. The chip package structure according to claim 5, wherein one of the plurality of subchips near the package substrate is electrically connected to the conductive pillar, and the other of the plurality of subchips are electrically connected to the package substrate by wires.

8. The chip package structure according to claim 1, wherein the number of conductive pillars is greater than one, and the plurality of conductive pillars are positioned at least on two opposing sides of the first chip.

9. The chip package structure further comprises a second filling portion, The chip package structure according to claim 1, wherein at least a portion of the second filling portion is positioned between the package substrate and the first chip, and the second filling portion surrounds each pin of the first chip.

10. The package substrate has a second surface opposite to the first surface, The chip package structure according to claim 1, further comprising solder balls positioned on the second surface of the package substrate and electrically connected to the package substrate.

11. A package substrate having a first surface, A first chip is disposed on the first surface of the package substrate and electrically connected to the package substrate, A second chipset comprising a plurality of second chips positioned to the side of the first chip away from the package substrate, electrically connected to the package substrate, and continuously stacked in a direction perpendicular to the package substrate. A chip package structure comprising, The aforementioned chip package structure further comprises a package layer, The package layer is positioned between the package substrate and the second chipset, and covers the first chip. The chip package structure further comprises a first filling portion, At least a portion of the first filling portion is positioned between the package layer and the second chip, and the first filling portion surrounds each pin of the second chip. The chip package structure further includes a first pad positioned between the pin and the conductive pillar, which is in direct contact with the pin and the conductive pillar. The side surface of the second chipset closer to the package substrate is higher than the side surface of the first chip further away from the package substrate, relative to the first surface of the package substrate. A chip package structure in which the distance between the lateral surface of the second chip closer to the package substrate and the first surface of the package substrate is h1, and the distance between the lateral surface of the first chip further away from the package substrate and the first surface of the package substrate is h2, and h1 and h2 satisfy the following conditions. 【Number 1】

12. The chip package structure according to claim 11, wherein two adjacent second chips are electrically connected to each other.

13. The aforementioned chip package structure further comprises an electromagnetic shielding layer, The chip package structure according to claim 11, wherein the electromagnetic shielding layer covers not only the second chipset but also at least the sides of the package layer.

14. A method for manufacturing a chip package structure, The steps include providing a package substrate having a first surface, The steps include forming conductive pillars electrically connected to the package substrate on the first surface of the package substrate, The steps include: placing a first chip electrically connected to the package substrate on the first surface of the package substrate; The steps include placing a package layer on the first chip, The steps include placing a first filling portion on the package layer, A step of positioning a second chip electrically connected to the conductive pillar to the side of the conductive pillar and the first chip that is away from the package substrate, wherein the orthographic projection of the conductive pillar on the package substrate is located within the range of the orthographic projection of the first chip or the second chip on the package substrate. Includes, The package layer covers the first chip and surrounds the sides of the conductive pillar. A manufacturing method wherein at least a portion of the first filling portion is positioned between the package layer and the second chip, and the first filling portion surrounds each pin of the second chip.

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