Semiconductor structures and methods for wafer-scale chip packages

Abstract

To provide a semiconductor structure and a method for wafer scale chip package.SOLUTION: An embodiment semiconductor structure (100) includes a metal layer (304). The semiconductor structure (100) also includes a redistribution layer (RDL) structure including an RDL platform (352) and a plurality of RDL pillars (354) disposed between the RDL platform (352) and the metal layer (304). Additionally, the semiconductor structure (100) includes an under-bump metal (UBM) layer (392) disposed on the RDL platform (352) and a solder bump (102) disposed on the UBM layer (392), where the UBM layer (392), the RDL platform (352), and the RDL pillars (354) form an electrical connection between the solder bump (102) and the metal layer (304).SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] This application generally relates to semiconductor circuit packaging, and more particularly to semiconductor structures and methods for wafer scale chip packages.

Background Art

[0002] In wafer scale (level) chip scale packaging (WCSP), chips are directly mounted on a board. Individual chips are diced and directly mounted on the board without packaging using bump connections.

Summary of the Invention

[0003] The exemplary semiconductor structure includes a metal layer. The semiconductor structure also includes a redistribution layer (RDL) structure, which includes an RDL platform and a plurality of RDL pillars disposed between the RDL platform and the metal layer. Further, the semiconductor structure includes an under bump metal (UBM) layer disposed on the RDL platform and solder bumps disposed on the UBM layer, and the UBM layer, the RDL platform, and the RDL pillars form an electrical connection between the solder bumps and the metal layer.

[0004] The exemplary semiconductor structure includes a redistribution layer (RDL) structure, which includes an RDL platform and a plurality of RDL pillars supporting the RDL platform. Further, the semiconductor structure includes a first polyimide layer between the plurality of RDL pillars and on a first side of the RDL platform, and a second polyimide layer on a second side of the RDL platform, which is opposite to the first side of the RDL platform.

[0005] An exemplary method for forming a semiconductor structure includes depositing a metal layer on a wafer and forming a polyimide layer on the metal layer. The method also includes forming pillar openings in the polyimide layer and depositing a redistribution layer (RDL) within the pillar openings and on a portion of the polyimide layer, with the polyimide layer positioned between the metal layer and the RDL. [Brief explanation of the drawing]

[0006] [Figure 1] This is a cross-sectional view of an example semiconductor structure.

[0007] [Figure 2A] This is a top view of an example semiconductor structure. [Figure 2B] This is a top view of an example semiconductor structure. [Figure 2C] This is a top view of an example semiconductor structure. [Figure 2D] This is a top view of an example semiconductor structure.

[0008] [Figure 3A] This is a cross-sectional view illustrating an illustrative stage in the manufacturing of a semiconductor structure. [Figure 3B] This is a cross-sectional view illustrating an illustrative stage in the manufacturing of a semiconductor structure. [Figure 3C] This is a cross-sectional view illustrating an illustrative stage in the manufacturing of a semiconductor structure. [Figure 3D] This is a cross-sectional view illustrating an illustrative stage in the manufacturing of a semiconductor structure. [Figure 3E] This is a cross-sectional view illustrating an illustrative stage in the manufacturing of a semiconductor structure. [Figure 3F] This is a cross-sectional view illustrating an illustrative stage in the manufacturing of a semiconductor structure. [Figure 3G] This is a cross-sectional view illustrating an illustrative stage in the manufacturing of a semiconductor structure. [Figure 3H] This is a cross-sectional view illustrating an illustrative stage in the manufacturing of a semiconductor structure. [Figure 3I] This is a cross-sectional view illustrating an illustrative stage in the manufacturing of a semiconductor structure.

[0009] [Figure 4] This is an example of a transistor structure.

[0010] [Figure 5] This is a flowchart illustrating an example method for manufacturing a semiconductor structure.

[0011] [Figure 6] This is a flowchart illustrating an example method utilizing a semiconductor structure.

[0012] In the different figures, corresponding numbers and symbols generally refer to the corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate relevant aspects of the arrangement of the exemplary embodiments and are not necessarily drawn to a fixed scale. [Modes for carrying out the invention]

[0013] In wafer-scale chip-scale packaging (WCSP), the die is directly mounted on the printed circuit board (PCB) rather than being mounted on the PCB through a packaging process or as a packaged device. WCSP structures can be made smaller due to the absence of additional packaging. Furthermore, the use of direct connections in WCSP enables low-resistance, high-current operation.

[0014] In one example, a rigid bump laminated structure is used for WSPC. Solder bumps are placed on an underbump metal (UBM) layer, and the UBM layer is bonded to the underlying metal layer. This rigid structure may not be well-suited to handling mechanical stresses. Mechanical stresses can be particularly problematic during thermal cycling in subsequent processing steps. Mechanical stresses should be reduced because they can lead to failure.

[0015] Power transistors such as bipolar junction transistors (BJTs), thyristors, insulated gate bipolar transistors (IGBTs), or power metal-oxide-semiconductor field-effect transistors (MOSFETs) such as NexFET (trademark) devices manufactured by Texas Instruments may be well-suited for WCSPs. The power transistors can be large in size and may have high stresses in a WCSP environment in relation to the WCSP. Also, the power transistors may operate at high currents and low-resistance connections may be desirable.

[0016] In one example, the bump structure includes a redistribution layer (RDL). The RDL may include an RDL platform supported by RDL pillars. In one example, an array of bumps with an RDL structure is used for a power transistor. In one example, the RDL reduces mechanical stress on the bump structure. In one example, the RDL enables a low electrical resistance connection with high current-carrying capacity. For example, the bump structure of an embodiment has a resistance of less than 2.5 mΩ. One embodiment has two polyimide layers to absorb horizontal and vertical stresses and reduce breakage. One embodiment enables mounting of large power transistors, e.g., larger than 1 mm × 1 mm, using WCSP. One embodiment has good electromigration capabilities.

[0017] FIG. 1 illustrates a cross-sectional view of a semiconductor structure 100. Substrate 302 includes at least one transistor or integrated circuit, such as one or more power transistors like a BJT, thyristor, IGBT, or a power MOSFET such as a NexFET (trademark) device manufactured by Texas Instruments. In one example, substrate 302 includes analog circuit elements such as high-power analog circuit elements. Substrate 302 can be a semiconductor substrate such as silicon, comprising various metal, dielectric, and / or semiconductor layers. Metal layer 304 is disposed on substrate 302. In one example, metal layer 304 is a Metal 1 (MET1) layer, Metal 2 (MET2) layer, Metal 3 (MET3) layer, or another metal layer. Metal layer 304 can be copper, aluminum, or another metal such as a metal alloy. In one embodiment, the thicknesses of substrate 302 and metal layer 304 are 7 mm to 14 mm, such as 8 - 9 mm. On the side of substrate 302 opposite to metal layer 304, there is a backside metal layer 306. In some embodiments, backside metal layer 306 does not exist. In one example, backside metal layer 306 is composed of silver, nickel, or gold. Backside metal layer 306 can have a thickness of 1 μm to 5 μm, such as a thickness of about 3.4 μm. A passivation layer 332 is disposed on metal layer 304. Passivation layer 332 is an oxide layer such as silicon dioxide. A polyimide layer 334 is disposed on passivation layer 332. Polyimide layer 334 is composed of a polymer of imide monomers. In one example, polyimide layer 334 is 5 μm to 10 μm, such as 7.5 μm.

[0018] The pad openings 104 and 106 extend through the passivation layer 332 and the polyimide layer 334. The redistribution layer (RDL) structure 352 has an RDL platform 356 positioned on the polyimide layer 334 and RDL pillars 354 that extend between the RDL platform 356 and the metal layer 304 through the pad openings 104 and 106 to the metal layer 304. The RDL is made of a metal such as copper. In one example, the RDL platform 356 is 3 μm to 7 μm thick, for example, 5 μm thick. On the RDL platform 356 is a second polyimide layer, a polyimide layer 372. The polyimide layer 372 may cover most of the RDL platform 356 by covering the sides and part of the top of the RDL platform 356, with openings 374. In one embodiment, the polyimide layer 372 has a thickness of 5 μm to 10 μm, for example, 7.5 μm. In one example, the polyimide layer 372 has the same thickness as the polyimide layer 334. In another example, the polyimide layer 372 is thicker than the polyimide layer 334. In an additional example, the polyimide layer 372 is thinner than the polyimide layer 334. The underbump metal (UBM) layer 392 is in contact with the RDL platform 356 through an opening 374 in the polyimide layer 372. The UBM layer 392 is composed of a metal such as Ti, TiW, or another titanium alloy. The solder bump 102 is located on top of the UBM layer 392. The solder bump 102 provides physical and electrical connections to the PCB. The solder bump 102 may be composed of lead solder or lead-free solder.

[0019] The UBM layer 392, RDL platform 356, and RDL pillar 354 form an electrical connection between the solder bump 102 and the metal layer 304. This electrical connection provides a low-resistance electrical connection between the solder bump 102 and the metal layer 304. For example, such an electrical connection may have a resistance of less than 2.5 mΩ. Furthermore, the electrical connection between the solder bump 102 and the metal layer 304 can support a large current, for example, 10 A. The solder bump 102 is connected to the UBM layer 392, which is also connected to the RDL structure 352. The RDL pillar 354 extends through pad openings 104 and 106, providing a low-resistance electrical connection to the metal layer 304. The RDL pillar 354 is drawn outside the solder bump 102, rather than directly beneath it, but may be entirely or partially beneath the bump 102. In one embodiment, the pillar is located near the periphery of the RDL layer. The polyimide layer 334 below the RDL platform 356, between the RDL pillars 354, and surrounding the RDL pillars 354 provides lateral and vertical flexibility. The polyimide layer 372 above and around the RDL platform 356 provides additional physical support. The semiconductor structure 100 can withstand high levels of mechanical stress while handling high currents with low resistance.

[0020] In one example, the thickness of the substrate 302 and the metal layer 304 is approximately 8 millimeters. The back metal layer 306 has a thickness of approximately 3.4 μm, the RDL platform 356 has a thickness of approximately 5 μm, the polyimide layer 334 has a thickness of approximately 7.5 μm, and the polyimide layer 372 has a thickness of approximately 7.5 μm.

[0021] Figures 2A to 2D show top views of several exemplary semiconductor structures. Each pillar cross-section can be combined with the number and distribution of pillars and the geometry of each RDL platform. Figure 2A shows a top view of semiconductor structure 200, which may be a top view of semiconductor structure 100 shown in Figure 1. Bump 208 is located in the center of semiconductor structure 200. In some embodiments, bump 208 is offset from the center of semiconductor structure 200. The RDL platform 204 below bump 208 is disc-shaped. In other embodiments, the RDL may have other shapes, for example, oval or irregular. Also, pillars 206 are arranged in a ring around the center of bump 208. The RDL pillars 206 support the RDL platform 204. Although the RDL pillars 206 are shown as having a circular cross-section, they may have other cross-sections, such as oval or irregular cross-sectional shapes. Eight pillars are shown, but a different number of pillars may exist. For example, there may be 4 to 16 pillars. In some examples, there are even more pillars, for example, 16 to 32 pillars.

[0022] Figure 2B shows a top view of the semiconductor structure 210. The bump 218 is located within the semiconductor structure 210, and the RDL platform 214 is located beneath the bump 218. In the figure, the RDL platform 214 is square, but the RDL platform 214 may have other shapes, such as a rectangle or a square with rounded corners. The RDL pillars 216 support the RDL platform 214 and bond it to the metal layer below. There are four RDL pillars, but a different number of pillars, such as six or eight pillars, may be used.

[0023] Figure 2C shows the semiconductor structure 230. Bumps 238 are located within the semiconductor structure 230, and the RDL platform 234 is positioned beneath the bumps 238. The RDL platform 234 is formed as an octagon, but may be formed as another polygon such as a pentagon, hexagon, heptagon, nonagon, decagon, dodecagon, or dodecagon. Such polygons may have equal sides or sides of different lengths. RDL pillars 236 support the RDL platform 234 and electrically couple the RDL platform 234 to the conductive layer below. In one example, there are as many pillars as there are sides of the polygon. In other examples, there are more pillars than there are sides of the polygon, or fewer pillars than there are sides of the polygon.

[0024] Figure 2D shows a semiconductor structure 240. Bumps 248 are located within the semiconductor structure 240. RDL 244 is positioned below bumps 248. RDL pillars 246 support RDL 244 and electrically couple RDL 244 to the conductive layer below. RDL pillars may have other shapes, such as rectangles, other polygons, or irregular shapes.

[0025] Figures 3A to 3J illustrate the manufacturing of the semiconductor structure 100 shown in Figure 1. Figure 3A illustrates the semiconductor structure including a substrate 302. The substrate 302 is still in wafer form and may be a silicon substrate including transistors and / or integrated circuits, including various semiconductor, metal, and dielectric layers. The substrate 302 may include one or more power devices such as power transistors or power analog elements. A metal layer 304 is disposed on the substrate 302. The metal layer 304 may be a MET1 layer, a MET2 layer, a MET3 layer, or another metal layer. The substrate 302 may have a back metal layer 306 on the side opposite to the metal layer 304 of the substrate 302. The back metal layer 306 may be composed of silver, nickel, or gold.

[0026] In Figure 3B, the system deposits a passivation layer 312 on a metal layer 304. The passivation layer 312 may be an oxide layer such as silicon dioxide. The passivation layer 312 may be deposited, for example, by chemical vapor deposition (CVD). In Figure 3C, the system deposits a polyimide layer 322 on the passivation layer 312. The polyimide layer may be formed using stepwise polymerization or solid-phase synthesis. In Figure 3D, the system etches a pillar pattern including pad openings 104 and 106 in the passivation layer 332 and the polyimide layer 334. To achieve this, the system rotates a photoresist on the polyimide layer 322. The system then exposes the photoresist layer using a photolithography mask, which may be a positive or negative mask. This exposure transfers the pattern of the photolithography mask to the photoresist. Next, etching transfers the pattern from the photoresist layer to the polyimide layer 322 to create the polyimide layer 334, which is then transferred to the passivation layer 312 to create the passivation layer 332. After etching, the system can remove any remaining photoresist.

[0027] In Figure 3E, the system deposits RDL342 on a polyimide layer 334. The system can deposit RDL342 using vapor deposition, sputtering, or CVD. As RDL342 is deposited, it fills the pad openings 104 and 106, forming RDL pillars 354. In one embodiment, RDL342 is made of copper. In Figure 3F, the system patterns RDL342 to generate an RDL structure 352. The system applies photoresist to RDL342. The system then exposes the photoresist using a photolithography mask, which may be a positive or negative mask. This exposure transfers the pattern from the photolithography mask to the photoresist layer. The system then etches the RDL to transfer the pattern from the photoresist to the RDL. The system can remove any remaining photoresist.

[0028] In Figure 3G, the system applies a polyimide layer 362. In some examples, the polyimide layer 362 is made of the same material as the polyimide layer 334. In other examples, the polyimide layer 362 is made of a different polyimide material than the polyimide layer 334. In Figure 3H, the system patterns the polyimide layer 362 to produce a polyimide layer 372. The system performs photolithography by applying a photoresist to the polyimide layer 362. The system then etches the polyimide layer 362 to form an opening 374 within the polyimide layer 372. The system can also remove any remaining photoresist.

[0029] In Figure 3I, the system applies UBM382 to the polyimide layer 372 and to the RDL structure 352 through the opening 374. The system may apply UBM382 using vapor deposition, sputtering, or CVD. The UBM layer 382 may be a metal such as Ti, TiW, or another titanium alloy. As shown in Figure 1, solder bumps 102 are applied to the UBM layer 392. Solder bumps 102 consist of solder, which may be lead-free solder. Bumping may be performed using repassivation with a wet film or a dry film. With passivation and bumping with a wet film, the system applies a photoresist, exposes the photoresist, and grows the photoresist on the UBM layer 382. The system then performs plating using copper / solder or copper / nickel / solder plating. Next, the system strips off the photoresist. Next, the system etches the UBM material. Finally, the system reflows the UBM material by heating it. In bumping using dry film, the system performs dry film lamination, exposure, and development. The system then plates the dry film using Cu / Ni / solder plating. Next, the system strips the dry film and subsequently etches the UBM. Finally, the system performs reflow on the UBM layer 392.

[0030] Figure 4 illustrates a transistor structure 500 having an RDL polyimide structure for WCSP. Transistor structure 500 includes structures 502, 504, 506, 508, 510, 512, 514, and 516, which have a bump structure similar to the semiconductor structure 100 illustrated in Figure 1. Structures 502, 504, 506, 508, 510, 512, 514, and 516 are NexFET® devices manufactured by Texas Instruments, and current flows vertically. Structures 502, 504, 506, and 508 are sources, and structures 510, 512, 514, and 516 are drains. A back metal (not shown) connects the sources and drains.

[0031] Figure 5 illustrates a flowchart 600 for a method of one embodiment for manufacturing a semiconductor structure, such as the semiconductor structure 100 shown in Figure 1. In block 601, the system obtains a wafer. The wafer may include a substrate such as silicon, which contains at least one transistor or integrated circuit. The wafer may also contain various metal, semiconductor, and dielectric layers. The transistor or integrated circuit may include one or more power transistors, such as NexFET® devices manufactured by Texas Instruments, or analog power electronics.

[0032] In block 602, the system backgrinds the wafer. For example, the wafer is backgrinded from 6 mil to 14 mil, for example, from 8 mil to 9 mil. The system cleans the top surface of the wafer. The system also protects the wafer from mechanical damage and contamination by applying protective tape to the top surface of the wafer. The system loads the wafer onto a cassette, which is placed in the cassette holder of the backgrinding machine. The backgrinding machine picks up the back side of the wafer with a robotic arm, thereby positioning the wafer for backgrinding. The grinding wheel performs backgrinding on the wafer. The system may continuously clean the wafer with deionized water during backgrinding. After backgrinding, the wafer is returned to the cassette. The system removes the backgrinding tape from the wafer, for example, using a tape peeling tool.

[0033] In block 604, the system deposits a back metal on the back side of the wafer. Such metals can be applied using radio frequency (RF) or direct current (DC) sputtering and electron beam deposition. The back metallization layer may have a good ohmic contact layer, such as silver, nickel, or gold.

[0034] In block 606, the system deposits one or more metal layers on the front side of the wafer via metallization. Block 606 may be performed before block 602, between block 602 and block 604, or after block 604. The metal layers may be applied by sputtering, evaporation, or CVD. Sputtering may include, for example, ion beam sputtering, reactive sputtering, ion-assisted deposition (LAD), high-target utilization sputtering (HiTUS), high-power impulse magnetron sputtering (HiPIMS), or gas flow sputtering. In one embodiment, pulsed laser deposition is used. Examples of evaporation include thermal evaporation, electron beam evaporation, flash evaporation, or resistive evaporation. For example, a pattern may be applied to the metal layer by etching or lift-off. Etching deposits the metal layer, and a photoresist layer is applied to the metal layer. A pattern is transferred from a photolithography mask to a photoresist via exposure. The pattern from the photoresist is then transferred to the metal layer via etching. In lift-off, a photoresist layer is applied before the metal layer. Exposure transfers the pattern from the photolithography mask to the photoresist layer. The metal is then deposited on top of the photoresist and within the openings in the photoresist. Next, the photoresist is removed, removing the metal portion on the photoresist layer while leaving the deposited metal in the openings. The metal layer may be copper, aluminum, or another metal or alloy.

[0035] In block 608, the system deposits a passivation layer on the metal layer applied in block 606. The passivation layer may be an oxide such as silicon dioxide. The passivation layer may be deposited by CVD.

[0036] In block 610, the system forms a first polyimide layer on top of the passivation layer deposited in block 608. The first polyimide layer may be formed by stepwise polymerization or solid-phase synthesis.

[0037] In block 612, the system patterns the passivation layer deposited in block 608 and the first polyimide layer formed in block 610. A layer of photoresist is applied to the passivation layer. The photoresist layer is then patterned using a photolithography mask. The mask may be a positive or negative mask. Subsequently, the first polyimide layer and the passivation layer are etched. Thus, openings are formed in the first polyimide layer and the passivation layer. Next, the remaining photoresist may be removed.

[0038] In block 614, the system deposits RDL on the first polyimide layer and at the openings of the first polyimide layer and the passivation layer. The RDL may be copper or another metal. The system deposits the RDL using sputtering, vapor deposition, or CVD. The RDL is deposited in pillars based on a pattern in the first polyimide layer. The system also patterns the RDL. In one example, a photoresist is deposited on the polyimide layer and patterned before the RDL is deposited. Then, lift-off is performed to pattern the RDL. In another embodiment, photolithography and etching are performed on the RDL.

[0039] In block 618, the system forms and patterns a second polyimide layer. The system may form the second polyimide layer using stepwise polymerization or solid-phase synthesis. The second polyimide layer may be the same thickness as the first polyimide layer, thinner than the first polyimide layer, or thicker than the first polyimide layer. The system patterns the second polyimide layer using photolithography and etching. A photoresist is applied to the second polyimide layer. The photoresist is exposed by a photolithography mask. The second polyimide layer is then etched in the areas where the photoresist has been removed. The photoresist may be removed.

[0040] In block 622, the system deposits a UBM layer. The UBM may consist of titanium or a titanium alloy such as TiW. The UBM may be deposited by sputtering, vapor deposition, or electroless plating.

[0041] In block 626, the system forms solder bumps in the UBM layer deposited in block 622. The solder bumps may consist of Sn / Pb, Pb, Sn / Ag / Cu, Sn / Ag, or other alloys, which may be lead-based or lead-free solders. Bumping may be performed using repassivation with a wet film or a dry film. In passivation and bumping with a wet film, the system applies a photoresist onto the UBM, exposes it, and develops it. The system then performs copper / solder plating or copper / nickel / solder plating. The system removes the photoresist and etches the UBM. Finally, the system reflows the UBM to form solder balls. In bumping with a dry film, the system performs dry film lamination, exposure, and development. The system then applies dry film lamination Cu / Ni / solder plating. Next, the dry film is removed, followed by UBM etching. Finally, the system reflows to form solder bumps.

[0042] Figure 6 illustrates a flowchart 700 for one embodiment of a method utilizing a semiconductor structure in WCSP. In block 702, the system dices a chip to form a die. Multiple chips may each include a bump structure, such as the semiconductor structure 100 illustrated in Figure 1. Wafer dicing can be performed by scribing and breaking, for example by mechanical sawing using a dicing saw, or by laser cutting. The wafer may be mounted on a dicing tape during dicing.

[0043] In block 704, the dies are mounted individually on the PCB. The dies are inverted and positioned so that the solder balls face the appropriate circuit elements on the PCB. The solder balls are remelted, for example, using hot air reflow. The mounted chips may be underfilled with an electrically insulating adhesive to provide support and protection.

[0044] In block 706, the circuits on the die on the PCB are operational. For example, power transistors, such as NexFET® devices manufactured by Texas Instruments, can perform power switching. Power transistors can operate with low resistance and high current density. In one example, a power transistor can operate at up to 5A.

[0045] While examples of exemplary arrangements have been described in detail, various modifications, substitutions, and alterations can be made herein without departing from the spirit and scope of this application as defined by the attached claims.

[0046] Furthermore, the scope of this application is not limited to the examples described herein. Accordingly, the appended claims are intended to include, within their scope, other such processes, machines, manufactures, compositions, methods, procedures, or steps.

Claims

1. It is a semiconductor structure, A first metal layer on the first surface of the substrate, The first polyimide layer on the first metal layer, A redistribution layer (RDL) structure electrically connected to the first metal layer, RDL platform and A plurality of RDL pillars extending from the RDL platform through the first polyimide layer to the first metal layer, wherein the RDL platform and the plurality of RDL pillars are the same continuous metal layer, The RDL structure includes, A second polyimide layer disposed on the RDL platform and covering a portion of the side and top surface of the RDL platform, the second polyimide layer having a defined opening, An underbump metal (UBM) layer disposed on the RDL platform, the UBM layer includes a flat upper surface that extends throughout the opening so as to fill the opening and extend beyond the opening to the upper surface of the second polyimide layer, Solder bumps placed on the UBM layer, Includes, The UBM layer, the RDL platform, and the plurality of RDL pillars form a conductive electrical connection between the solder bump and the metal layer. A semiconductor structure in which the plurality of RDL pillars are arranged in a ring shape surrounding the solder bump such that none of the plurality of RDL pillars are directly below the solder bump.

2. The semiconductor structure according to claim 1, A semiconductor structure in which the first polyimide layer and the second polyimide layer are made of the same material.

3. The semiconductor structure according to claim 1, A semiconductor structure further comprising a passivation layer between the first metal layer and the first polyimide layer.

4. The semiconductor structure according to claim 1, A semiconductor structure in which the plurality of RDL pillars include a first RDL pillar and a second RDL pillar, and the distance between the first RDL pillar and the second RDL pillar is greater than the width of the solder bump.

5. The semiconductor structure according to claim 1, A semiconductor structure further comprising a second metal layer formed on a second surface of the substrate opposite to the first surface.

6. It is a semiconductor structure, Metal layer, A passivation layer disposed on the metal layer, A first polyimide layer is disposed on the passivation layer, Redistribution layer (RDL) structure, The RDL platform is disposed on the first polyimide layer, A plurality of RDL pillars extending between the RDL platform and the metal layer via the first polyimide layer and the passivation layer, wherein the plurality of RDL pillars are separated from each other laterally by the passivation layer and the first polyimide layer, The RDL structure includes, A second polyimide layer disposed on the RDL platform and covering the side and a portion of the uppermost layer of the RDL platform, the second polyimide layer having a defined opening, An underbump metal (UBM) disposed on the RDL platform, the UBM including a substantially flat upper layer extending into the opening such that the UBM completely fills the opening and extends beyond the opening to the uppermost layer of the second polyimide layer, Solder bumps placed on the UBM, Includes, The RDL platform and the plurality of RDL pillars are monolithic metal structures. The UBM, the RDL platform, and the plurality of RDL pillars form a conductive electrical connection between the solder bump and the metal layer. The plurality of RDL pillars are arranged in a ring shape surrounding the solder bump such that none of the plurality of RDL pillars are directly below the solder bump. A semiconductor structure in which the entire uppermost layer of the UBM is located on top of the uppermost layer of the second polyimide layer.

7. The semiconductor structure according to claim 6, A semiconductor structure in which the plurality of RDL pillars include first and second pillars positioned on both sides away from the region of the first polyimide layer directly below the UBM.

8. The semiconductor structure according to claim 7, A semiconductor structure in which the distance between the first pillar and the second pillar of the plurality of RDL pillars is greater than the width of the solder bump.

9. A method for forming a semiconductor structure, Depositing a metal layer on a semiconductor wafer, Forming a passivation layer on the aforementioned metal layer, Forming a first polyimide layer on the passivation layer, To form pillar openings extending through the first polyimide layer and the passivation layer, Depositing a redistribution layer (RDL) in the pillar opening and on a portion of the first polyimide layer in the same metal deposition process, wherein the RDL includes an RDL platform disposed on the first polyimide layer and a plurality of pillars extending from the RDL platform to the metal layer via the first polyimide layer and the passivation layer. A second polyimide layer is formed on the RDL platform, covering the top surface and sides of the RDL platform. Forming an opening in the second polyimide layer, The method involves completely filling the opening of the second polyimide layer with underbump metal (UBM), such that the UBM spreads throughout the opening and over a portion of the second polyimide layer, completely forming the uppermost layer on top of the second polyimide layer. Forming solder bumps on the UBM, Includes, A method in which the plurality of pillars are arranged in a ring shape surrounding the solder bump such that none of the plurality of pillars are directly below the solder bump.

10. The method according to claim 9, The process further includes backgrinding the back side of the semiconductor wafer, A method for depositing the metal layer, comprising depositing a front metal layer on the front side of the semiconductor wafer and depositing a back metal layer on the back side of the semiconductor wafer.

11. The method according to claim 9, A method in which the plurality of pillars are arranged around the region of the first polyimide layer directly beneath the UBM such that none of the plurality of pillars are directly beneath the UBM.

12. The method according to claim 9, A method wherein the first polyimide layer and the second polyimide layer are made of the same material.

13. The method according to claim 9, A method in which the plurality of pillars are arranged with a common radius with respect to the center of the RDL platform.

14. It is a semiconductor structure, A semiconductor substrate having a first surface and a second surface opposite to the first surface, A first metal layer on the first surface of the semiconductor substrate, The oxide layer on the first metal layer, The first polyimide layer on the oxide layer, A plurality of first openings that expose the first metal layer through the first polyimide layer and the oxide layer, A plurality of metal pillars for filling the plurality of first openings, the plurality of metal pillars connected to the first metal layer, A metal platform on the first polyimide layer and on the plurality of metal pillars, wherein the metal platform is electrically connected to the plurality of metal pillars, A second polyimide layer on the metal platform and the first polyimide layer, the second polyimide layer covering the side wall of the metal platform, A second opening that exposes the metal platform through the second polyimide layer, A second metal layer on the second polyimide layer, the second metal layer connected to the metal platform via the second opening, The bump on the second metal layer, Includes, A semiconductor structure in which the plurality of metal pillars are arranged in a ring shape surrounding the solder bump such that none of the plurality of metal pillars are directly beneath the solder bump.

15. The semiconductor structure according to claim 14, A semiconductor structure in which the second metal layer, the metal platform, and the plurality of metal pillars form an electrical connection between the bump and the first metal layer, and the electrical connection has a resistance of less than 2.5 mΩ.

16. The semiconductor structure according to claim 14, A semiconductor structure further comprising a third metal layer on the second surface of the semiconductor substrate.

17. The semiconductor structure according to claim 14, The semiconductor substrate is a semiconductor structure including a power transistor.

18. The semiconductor structure according to claim 14, A semiconductor structure comprising the metal platform and the plurality of metal pillars, each containing copper.

19. The semiconductor structure according to claim 14, The plurality of metal pillars have a circular cross-section, forming a semiconductor structure.

20. The semiconductor structure according to claim 14, The aforementioned metal platform is a semiconductor structure having a circular cross-section.

21. The semiconductor structure according to claim 14, A semiconductor structure in which the plurality of metal pillars include a first metal pillar and a second metal pillar, and the distance between the first metal pillar and the second metal pillar is greater than the width of the bump.

22. The semiconductor structure according to claim 14, A semiconductor structure in which the plurality of metal pillars are not located directly beneath the second metal layer.

Images