Semiconductor equipment

Abstract

To provide a semiconductor device that can facilitate adjustment of a saturation voltage and suppress variation in characteristics.SOLUTION: A semiconductor device 100 includes: an N-type semiconductor substrate 10 having a first main surface 10A and a second main surface 10B on the opposite side of the first main surface; a first trench 21 and a second trench 22 provided on the first main surface; a P-type first semiconductor layer 11 provided on the first main surface between the first trench and the second trench; an N-type second semiconductor layer 12 provided at a position sandwiching the first trench between itself and the first semiconductor layer on the first main surface, and contacting the first trench; a P-type third semiconductor layer 13 provided under the second semiconductor layer, and contacting the second semiconductor layer and the first trench; an N-type fourth semiconductor layer 14 provided under the third semiconductor layer, contacting the third semiconductor layer, and separated from the first trench; and a P-type fifth semiconductor layer 15 provided at a position sandwiching the second trench between itself and the first semiconductor layer on the first main surface.SELECTED DRAWING: Figure 2

Description

Technical Field

[0006] , , , ,

[0001] This disclosure relates to a semiconductor device.

Background Art

[0002] In an insulated gate bipolar transistor (IGBT), a semiconductor device in which a high-concentration N-type semiconductor layer is provided below a P-type channel region so as to contact the entire lower surface of the channel region is known (Patent Document 1). By providing the high-concentration N-type semiconductor layer, the saturation voltage can be reduced.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a conventional semiconductor device provided with a high-concentration N-type semiconductor layer, characteristics such as the threshold voltage of the MOS structure of the IGBT are likely to vary.

[0005] An object of this disclosure is to provide a semiconductor device that can easily adjust the saturation voltage and suppress variations in characteristics.

Means for Solving the Problems

[0006] A semiconductor device according to one embodiment of the present disclosure includes: a semiconductor substrate of a first conductivity type having a first main surface and a second main surface opposite to the first main surface; a first trench provided on the first main surface; a second trench provided on the first main surface; a first semiconductor layer of a second conductivity type provided on the first main surface between the first trench and the second trench; a second semiconductor layer of a first conductivity type provided on the first main surface at a position that sandwiches the first trench between the first semiconductor layer and the first semiconductor layer and is in contact with the first trench; a third semiconductor layer of a second conductivity type provided below the second semiconductor layer and in contact with the second semiconductor layer and the first trench; a fourth semiconductor layer of a first conductivity type provided below the third semiconductor layer, in contact with the third semiconductor layer and spaced apart from the first trench; and a fifth semiconductor layer of a second conductivity type provided on the first main surface at a position that sandwiches the second trench between the first semiconductor layer and the first semiconductor layer. A sixth semiconductor layer of first conductivity type is provided below the fifth semiconductor layer, is in contact with the fifth semiconductor layer, and is spaced apart from the second trench, The semiconductor layer comprises a first insulating film provided on the inner wall of the first trench, a gate trench electrode provided in the first trench via the first insulating film and facing the third semiconductor layer, a second insulating film provided on the inner wall of the second trench, an emitter trench electrode provided in the second trench via the second insulating film, a gate electrode connected to the gate trench electrode, an emitter electrode connected to the emitter trench electrode, and a collector electrode provided on the second main surface, wherein the fourth semiconductor layer contains impurities of the first conductivity type at a higher concentration than the semiconductor substrate and a lower concentration than the second semiconductor layer, and the lower end of the fifth semiconductor layer is located at the same level as or lower than the lower end of the third semiconductor layer. [Effects of the Invention]

[0007] According to this disclosure, the saturation voltage can be easily adjusted and variations in characteristics can be suppressed. [Brief explanation of the drawing]

[0008] [Figure 1] This figure shows the layout of the semiconductor layer and trench electrode in the semiconductor device according to the first embodiment. [Figure 2] This is a cross-sectional view showing a semiconductor device according to the first embodiment. [Figure 3] This is a cross-sectional view (part 1) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 4] This is a cross-sectional view (part 2) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 5] This is a cross-sectional view (part 3) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 6] This is a cross-sectional view (part 4) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 7] This is a cross-sectional view (part 5) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 8] This is a cross-sectional view (part 6) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 9] This is a cross-sectional view (part 7) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 10] This is a cross-sectional view (part 8) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 11] This is a cross-sectional view (9) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 12] This is a cross-sectional view (10) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 13] This is a cross-sectional view showing a semiconductor device according to a modified example of the first embodiment. [Figure 14] This figure shows the Vce-Ic characteristics. [Figure 15] This figure shows the results of a simulation regarding carrier concentration. [Figure 16] This is a cross-sectional view showing a semiconductor device according to a second embodiment. [Figure 17] This is a cross-sectional view showing a semiconductor device according to the third embodiment. [Modes for carrying out the invention]

[0009] Hereinafter, embodiments of the present disclosure will be specifically described with reference to the accompanying drawings. In this specification and drawings, components having substantially the same functional configuration may be denoted by the same reference numerals, and redundant descriptions may be omitted. In the following description, two directions parallel to the surface of the substrate and perpendicular to each other are defined as the X direction and the Y direction, and the direction perpendicular to the surface of the substrate is defined as the Z direction.

[0010] (First Embodiment) First, the first embodiment will be described. The first embodiment relates to a semiconductor device including an insulated gate bipolar transistor (IGBT). FIG. 1 is a diagram showing the layout of a semiconductor layer and trench electrodes in the semiconductor device according to the first embodiment. FIG. 2 is a cross-sectional view showing the semiconductor device according to the first embodiment. FIG. 2 corresponds to a cross-sectional view taken along line II-II in FIG. 1.

[0011] The semiconductor device 100 according to the first embodiment has an N-type semiconductor substrate 10 having a first main surface 10A and a second main surface 10B opposite to the first main surface 10A, as shown in Figure 1. The semiconductor substrate 10 is, for example, a silicon substrate. A plurality of gate trenches 21 and a plurality of emitter trenches 22 are formed on the first main surface 10A. The trenches 21 and 22 extend, for example, in the Y direction. For example, two trenches 21 form a pair, and two trenches 22 form a pair, and pairs of trenches 21 and pairs of trenches 22 are arranged alternately in the X direction. The distance between two adjacent trenches 21 in the X direction, the distance between two adjacent trenches 22 in the X direction, and the distance between adjacent trenches 21 and trenches 22 in the X direction are equal. In other words, if trenches 21 and 22 are not distinguished, multiple trenches are formed in a striped pattern at equal intervals in the X direction on the first main surface 10A. A first region R1 is defined between two adjacent trenches 21 in the X direction, a second region R2 is defined between adjacent trenches 21 and trench 22 in the X direction, and a third region R3 is defined between two adjacent trenches 22 in the X direction. In the first embodiment, in the X direction, the first region R1 and the third region R3 are arranged alternately, such as ..., third region R3, second region R2, first region R1, second region R2, third region R3, second region R2, first region R1, ..., with one second region R2 positioned between the first region R1 and the third region R3.

[0012] In the first region R1, an N-type semiconductor layer 12 is provided on the first main surface 10A. The N-type semiconductor layer 12 contains N-type impurities at a higher concentration than the semiconductor substrate 10. The N-type semiconductor layer 12 is exposed on the first main surface 10A and is in contact with the trench 21. A P-type semiconductor layer 13 is provided under the N-type semiconductor layer 12. The P-type semiconductor layer 13 is in contact with the N-type semiconductor layer 12 and the trench 21. In the Z direction, the lower end of the P-type semiconductor layer 13 is above the lower end of the trench 21. A P-type semiconductor layer 17 is formed in the vicinity of the interface between the P-type semiconductor layer 13 and the N-type semiconductor layer 12. The P-type semiconductor layer 17 may be formed across the N-type semiconductor layer 12 and the P-type semiconductor layer 13, or may be formed so as to include the interface between the N-type semiconductor layer 12 and the P-type semiconductor layer 13. The P-type semiconductor layer 17 is spaced apart from the trench 21. The P-type semiconductor layer 17 contains P-type impurities at a higher concentration than the P-type semiconductor layer 13. In the Z direction, the lower end of the P-type semiconductor layer 17 is above the lower end of the P-type semiconductor layer 13. An N-type semiconductor layer 14 is provided under the P-type semiconductor layer 13. The N-type semiconductor layer 14 contains N-type impurities at a higher concentration than the semiconductor substrate 10 and at a lower concentration than the N-type semiconductor layer 12. The N-type semiconductor layer 14 is in contact with the P-type semiconductor layer 13 and is spaced apart from the trench 21.

[0013] In the second region R2, a P-type semiconductor layer 11 is provided on the first main surface 10A. The P-type semiconductor layer 11 is in contact with the trench 21 and the trench 22. For example, in the Z direction, the lower end of the P-type semiconductor layer 11 is above the lower end of the trench 21. For example, the depth of the P-type semiconductor layer 11 is not less than the depth of the trench 21. The P-type semiconductor layer 11 contains P-type impurities at a lower concentration than the P-type semiconductor layer 13.

[0014] In the third region R3, a P-type semiconductor layer 15 is provided on the first main surface 10A. For example, the P-type semiconductor layer 15 contains P-type impurities at a concentration similar to that of the P-type semiconductor layer 13. The P-type semiconductor layer 15 is exposed to the first main surface 10A and is in contact with the trench 22. For example, in the Z direction, the lower end of the P-type semiconductor layer 15 may be at the same position as the lower end of the P-type semiconductor layer 13, or it may be lower than the lower end of the P-type semiconductor layer 13. For example, in the Z direction, the lower end of the P-type semiconductor layer 15 may be at the same position as the lower end of the P-type semiconductor layer 11, or it may be higher than the lower end of the P-type semiconductor layer 11. The depth of the P-type semiconductor layer 15 may be equal to the depth of the P-type semiconductor layer 13, greater than the depth of the P-type semiconductor layer 13, and less than or equal to the depth of the P-type semiconductor layer 11. A P-type semiconductor layer 18 is formed inside the P-type semiconductor layer 15. The P-type semiconductor layer 18 contains P-type impurities at a higher concentration than the P-type semiconductor layer 15. For example, the P-type semiconductor layer 18 contains P-type impurities at a concentration similar to that of the P-type semiconductor layer 17. An N-type semiconductor layer 16 is provided below the P-type semiconductor layer 15. The N-type semiconductor layer 16 contains N-type impurities at a higher concentration than the semiconductor substrate 10. For example, the N-type semiconductor layer 16 contains N-type impurities at a concentration similar to that of the N-type semiconductor layer 14. At least a portion of the N-type semiconductor layer 16 overlaps with the P-type semiconductor layer 15, is in contact with the P-type semiconductor layer 15, and is spaced apart from the trench 22.

[0015] An insulating film 30 is provided on the inner walls of trenches 21 and 22. An insulating film 31 is provided on the first main surface 10A. That is, the insulating film 31 covers the P-type semiconductor layer 11 and the N-type semiconductor layer 12. The insulating films 30 and 31 are, for example, thermal oxide films. A gate trench electrode 41 is provided in trench 21 via the insulating film 30. The gate trench electrode 41 faces the P-type semiconductor layer 13 via the insulating film 30. An emitter trench electrode 42 is provided in trench 22 via the insulating film 30. The gate trench electrode 41 and the emitter trench electrode 42 are formed using, for example, polycrystalline silicon. The insulating film 31 is also formed on the gate trench electrode 41 and the emitter trench electrode 42.

[0016] The portion of the insulating film 30 within the trench 21 functions as a gate insulating film. Within the first region R1, the N-type semiconductor layer 12, the P-type semiconductor layer 13, and the N-type semiconductor substrate 10 are aligned along the insulating film 30 within the trench 21, with the P-type semiconductor layer 13 functioning as a channel region. In other words, the MOS structure is formed by the first region R1, the insulating film 30, and the gate trench electrode 41.

[0017] An interlayer insulating film 50 is provided on top of the insulating film 31. The interlayer insulating film 50 is, for example, a BPSG (borophosphosilicate glass) film. An opening 51 reaching the P-type semiconductor layer 17 is formed in the interlayer insulating film 50, the insulating film 31, and the N-type semiconductor layer 12. The opening 51 divides the N-type semiconductor layer 12 into two parts. An opening 52 reaching the P-type semiconductor layer 18 is formed in the interlayer insulating film 50, the insulating film 31, and the P-type semiconductor layer 15. An emitter electrode (emitter pad) 61 is provided on top of the interlayer insulating film 50. The emitter electrode 61 contacts the N-type semiconductor layer 12 and the P-type semiconductor layer 13 through the opening 51, and contacts the P-type semiconductor layers 15 and 18 through the opening 52. The emitter electrode 61 is formed using, for example, aluminum.

[0018] A P-type semiconductor layer 63 is provided on the second main surface 10B, and an N-type semiconductor layer 62 is provided above the P-type semiconductor layer 63. The N-type semiconductor layer 62 is in contact with the P-type semiconductor layer 63. The N-type semiconductor layer 62 contains N-type impurities at a higher concentration than the semiconductor substrate 10. A collector electrode 64 is provided on the second main surface 10B, that is, below the P-type semiconductor layer 63. The collector electrode 64 is in contact with the P-type semiconductor layer 63. The collector electrode 64 is formed using, for example, a multilayer film of Al, Ti, Ni, and Au stacked sequentially downwards from the P-type semiconductor layer 63. The collector electrode 64 may be made of other materials, such as a multilayer film of Al, Ti, Ni, and Ag stacked sequentially downwards from the P-type semiconductor layer 63.

[0019] Each gate trench electrode 41 is drawn out, for example, near the outer periphery of the semiconductor device 100 and is commonly connected to a gate electrode (gate pad) (not shown). A shunt (resistor) may be provided between the gate trench electrode 41 and the gate electrode as appropriate, so that the power supply delay time is uniform throughout the semiconductor device 100. The gate electrode is formed, for example, from aluminum. Each emitter trench electrode 42 is drawn out, for example, near the outer periphery of the semiconductor device 100 and is connected to an emitter electrode (emitter pad) 61.

[0020] The P-type semiconductor layer 11 is electrically floating because it is not directly connected to the emitter electrode 61, the collector electrode 64, and the gate electrode.

[0021] Although not shown in the diagram, a so-called guard ring structure is provided on the outer periphery of the semiconductor device 100 to maintain its pressure resistance.

[0022] Next, a method for manufacturing the semiconductor device 100 according to the first embodiment will be described. Figures 3 to 12 are cross-sectional views showing the method for manufacturing the semiconductor device 100 according to the first embodiment.

[0023] First, as shown in Figure 3, a semiconductor substrate 10 having a first main surface 10A and a second main surface 10B is prepared, and a P-type semiconductor layer 11 is formed on the first main surface 10A in the region that becomes the second region R2 by ion implantation of P-type impurities and subsequent heat treatment.

[0024] Next, as shown in Figure 4, a plurality of gate trenches 21 and a plurality of emitter trenches 22 are formed on the first main surface 10A. In forming the trenches 21 and trenches 22, for example, a photoresist mask is formed on the first main surface 10A, and the semiconductor substrate 10 is etched using this mask. A first region R1 is defined between two adjacent trenches 21 in the X direction, a second region R2 is defined between two adjacent trenches 21 and trenches 22 in the X direction, and a third region R3 is defined between two adjacent trenches 22 in the X direction.

[0025] Next, as shown in Figure 5, insulating film 30 is formed on the inner walls of trenches 21 and 22. The insulating film 30 is also formed on the first main surface 10A. The insulating film 30 can be formed, for example, by thermal oxidation.

[0026] Next, as shown in Figure 6, a gate trench electrode 41 is formed in the trench 21 via an insulating film 30, and an emitter trench electrode 42 is formed in the trench 22 via an insulating film 30.

[0027] The P-type semiconductor layer 11 can be formed to a predetermined depth by heating during the formation of the insulating film 30, etc.

[0028] Next, as shown in Figure 7, the portion of the insulating film 30 on the semiconductor substrate 10 and the portion on the P-type semiconductor layer 11 are removed. That is, the insulating film 30 is removed from the region where the P-type semiconductor layer 13 and N-type semiconductor layer 12 are formed in the first region R1, the region where the P-type semiconductor layer 15 is formed in the third region R3, and the region where the P-type semiconductor layer 11 is formed in the second region R2. Then, an insulating film 31 for ion implantation is formed in the regions from which the insulating film 30 was removed. The insulating film 31 for ion implantation is thinner than the insulating film 30. The insulating film 31 can be formed, for example, by thermal oxidation. The insulating film 31 is also formed on the gate trench electrode 41 and the emitter trench electrode 42. Subsequently, the P-type semiconductor layer 13 is formed in the first region R1 and the P-type semiconductor layer 15 is formed in the third region R3 by ion implantation of P-type impurities. The P-type semiconductor layer 13 and the P-type semiconductor layer 15 can be formed simultaneously. The P-type semiconductor layer 13 and the P-type semiconductor layer 15 may be formed in different processes. Next, an N-type semiconductor layer 12 is formed in the first region R1 by ion implantation of N-type impurities. The insulating film 31 protects the surfaces of the semiconductor substrate 10 and the P-type semiconductor layer 11 during these ion implantations.

[0029] Next, as shown in Figure 8, an interlayer insulating film 50 is formed on top of the insulating film 31.

[0030] Next, as shown in Figure 9, an opening 51 reaching the P-type semiconductor layer 13 is formed in the interlayer insulating film 50, the insulating film 31, and the N-type semiconductor layer 12, and an opening 52 reaching the P-type semiconductor layer 15 is formed in the interlayer insulating film 50 and the insulating film 31. The openings 51 and 52 can be formed simultaneously. In forming the openings 51 and 52, for example, a photoresist mask is formed on the interlayer insulating film 50, and this mask is used to etch the interlayer insulating film 50, the insulating film 31, the N-type semiconductor layer 12, and the P-type semiconductor layer 15. The opening 52 enters the P-type semiconductor layer 15. The opening 51 may enter the P-type semiconductor layer 13.

[0031] Next, as shown in Figure 10, an N-type semiconductor layer 14 and a P-type semiconductor layer 17 are formed in the first region R1, and an N-type semiconductor layer 16 and a P-type semiconductor layer 18 are formed in the third region R3. In forming these semiconductor layers, ion implantation of N-type impurities for forming the N-type semiconductor layer 14 and N-type semiconductor layer 16 is performed in the first region R1 and the third region R3, respectively. Then, ion implantation of P-type impurities for forming the P-type semiconductor layer 17 and P-type semiconductor layer 18 is performed in the first region R1 and the third region R3, respectively. After these ion implantations, heat treatment is performed. In this way, the N-type semiconductor layer 14, N-type semiconductor layer 16, P-type semiconductor layer 17, and P-type semiconductor layer 18 can be formed. At least a portion of the N-type semiconductor layer 14 overlaps with the P-type semiconductor layer 13, and at least a portion of the N-type semiconductor layer 16 overlaps with the P-type semiconductor layer 15.

[0032] Next, as shown in Figure 11, an emitter electrode 61 is formed on the interlayer insulating film 50. The emitter electrode 61 contacts the N-type semiconductor layer 12 and the P-type semiconductor layer 13 through the opening 51, and contacts the P-type semiconductor layers 15 and 18 through the opening 52.

[0033] Next, as shown in Figure 12, an N-type semiconductor layer 62 is formed on the second main surface 10B by ion implantation of N-type impurities. Furthermore, a P-type semiconductor layer 63 is formed on the second main surface 10B by ion implantation of P-type impurities. Subsequently, a collector electrode 64 is formed on the second main surface 10B.

[0034] Although not shown in the diagram, gate electrodes are also formed that are connected to each gate trench electrode 41.

[0035] For example, after the formation of the P-type semiconductor layer 17, the P-type semiconductor layer 18, the N-type semiconductor layer 14, and the N-type semiconductor layer 16, and before the formation of the emitter electrode 61, an opening (not shown) reaching the emitter trench electrode 42 may be formed in the interlayer insulating film 50 near the outer periphery of the semiconductor device 100. The emitter electrode 61 can be connected to the emitter trench electrode 42 through this opening.

[0036] Here, the effects of the semiconductor device 100 according to the first embodiment will be described.

[0037] In the semiconductor device 100 according to the first embodiment, the N-type semiconductor layer 14 functions as a hole barrier layer. Furthermore, the N-type semiconductor layer 14 is spaced apart from the trench 21. Therefore, the characteristics of the MOS structure in the first region R1, such as the threshold voltage, are less affected by the N-type semiconductor layer 14. In other words, according to the first embodiment, variations in the characteristics of the MOS structure can be suppressed.

[0038] A second region R2 is provided adjacent to the first region R1, and a floating P-type semiconductor layer 11 is provided in the second region R2. Therefore, good static characteristics of the IGBT can be obtained due to the injection enhancement (IE) effect. Furthermore, the P-type semiconductor layer 11 and the P-type semiconductor layer 13 can be formed in separate processes; for example, the P-type semiconductor layer 11 can be formed deeper than the P-type semiconductor layer 13. Therefore, excellent breakdown voltage can be obtained while obtaining good MOS characteristics in the first region R1.

[0039] A third region R3 is provided so as to sandwich the second region R2 between the first region R1 and the third region R3, and a trench 22 is provided between the second region R2 and the third region R3. If a gate trench electrode 41 is provided in the trench 22, the short circuit safe operation area (SCSOA) and switching characteristics may deteriorate due to an increase in gate capacitance. In the first embodiment, since an emitter trench electrode 42 connected to the emitter electrode 61 is provided in the trench 22, the deterioration of characteristics due to an increase in gate capacitance can be avoided.

[0040] If trenches 21 and 22 are not distinguished, multiple trenches are arranged in a striped pattern at equal intervals in the X direction on the first main surface 10A. As a result, the density of the trenches is highly uniform, and variations in etching during trench formation can be suppressed. By suppressing variations in etching, the yield of the semiconductor device 100 can be improved, and variations in electrical characteristics can be reduced.

[0041] In the third region R3, a P-type semiconductor layer 15 connected to the emitter electrode 61 is provided in contact with the N-type semiconductor substrate 10. This allows for rapid discharge of carriers during the switching operation of the IGBT, thereby improving the switching characteristics.

[0042] Furthermore, the saturation voltage Vce(sat) can be adjusted according to the depth of the P-type semiconductor layer 15. In the cross-sectional view shown in Figure 2, the depth of the P-type semiconductor layer 15 is equal to the depth of the P-type semiconductor layer 13, but the depth of the P-type semiconductor layer 15 may be greater than the depth of the P-type semiconductor layer 13. Figure 13 is a cross-sectional view showing a semiconductor device according to a modified example of the first embodiment.

[0043] In the semiconductor device 101 according to a modification of the first embodiment, the depth of the P-type semiconductor layer 15 is greater than the depth of the P-type semiconductor layer 13 and less than or equal to the depth of the P-type semiconductor layer 11. The N-type semiconductor layer 16 is formed so that its entirety overlaps the P-type semiconductor layer 15. The other configurations are the same as in the first embodiment.

[0044] Comparing semiconductor device 100 and semiconductor device 101, their MOS characteristics are equivalent, and the saturation voltage Vce(sat) of semiconductor device 100 is lower than that of semiconductor device 101. The inventors of this application fabricated semiconductor devices following the first embodiment and its modified form, and the relationship between the collector-emitter voltage Vce and the collector current Ic (Vce-Ic characteristics) was actually measured for each, as shown in Figure 14. As shown in Figure 14, the threshold voltage was equivalent between the first embodiment and its modified form. On the other hand, the collector-emitter voltage Vce (saturation voltage Vce(sat)) when the rated collector current Ic was flowing was smaller in the first embodiment than in the modified form.

[0045] Furthermore, Figure 15 shows the results of simulations on carrier concentration performed by the inventors of the present invention for the first embodiment and its modified form. In this simulation, the hole concentration distribution in the Z direction was calculated for the portion of the first region R1 that includes the N-type semiconductor layer 14 in a plan view and for the portion of the third region R3 that includes the N-type semiconductor layer 16 in a plan view. In Figure 15, the solid line shows the simulation result for the first region R1 of the first embodiment, the dashed line shows the simulation result for the third region R3 of the first embodiment, the dashed line shows the simulation result for the first region R1 of the modified form, and the dashed line shows the simulation result for the third region R3 of the modified form.

[0046] As shown in Figure 15, in the first embodiment, simulation results showed that the hole concentration was higher in both the first region R1 and the third region R3 compared to the modified example. This is thought to be because, in the first embodiment, the P-type semiconductor layer 15 is formed shallower than in the modified example, resulting in a kind of carrier accumulation effect.

[0047] In this way, the saturation voltage Vce(sat) can be adjusted according to the depth of the P-type semiconductor layer 15, independently of the MOS characteristics. Furthermore, if the depth of the P-type semiconductor layer 15 is equal to the depth of the P-type semiconductor layer 13, the P-type semiconductor layer 15 and the P-type semiconductor layer 13 can be formed simultaneously. On the other hand, by forming the P-type semiconductor layer 15 and the P-type semiconductor layer 13 in separate processes, the saturation voltage Vce(sat) can be adjusted while obtaining the desired MOS characteristics.

[0048] It is preferable that the N-type semiconductor layer 16 is spaced apart from the trench 22. This is because it is possible to elicit a better IE effect and further lower the saturation voltage Vce(sat) to improve the efficiency of the semiconductor device 100.

[0049] The depth of the P-type semiconductor layer 11 is preferably greater than or equal to the depth of the trench 21. This is because it makes it easier to alleviate electric field concentration at the lower end of the trench 21.

[0050] (Second embodiment) Next, a second embodiment will be described. The second embodiment differs from the first embodiment mainly in the arrangement of the first region R1, the second region R2, and the third region R3. Figure 16 is a cross-sectional view showing a semiconductor device according to the second embodiment.

[0051] In the semiconductor device 200 according to the second embodiment, in addition to a plurality of gate trenches 21 and a plurality of emitter trenches 22, a plurality of emitter trenches 25 are formed on the first main surface 10A. The trenches 25 extend, for example, in the Y direction. Similar to the first embodiment, pairs of trenches 21 and pairs of trenches 22 are arranged alternately in the X direction. Also, two trenches 25 are arranged between adjacent pairs of trenches 21 and pairs of trenches 22. The distance between two adjacent trenches 21 in the X direction is equal to the distance between two adjacent trenches 22 in the X direction, the distance between two adjacent trenches 25 in the X direction, the distance between adjacent trenches 21 and trenches 25 in the X direction, and the distance between adjacent trenches 22 and trenches 25 in the X direction. In other words, if trenches 21, 22, and 25 are not distinguished, multiple trenches are formed in a striped pattern at equal intervals in the X direction on the first main surface 10A. Similar to the first embodiment, a first region R1 is defined between two adjacent trenches 21 in the X direction, and a third region R3 is defined between two adjacent trenches 22 in the X direction. A second region R2 is defined between adjacent trenches 21 and 25 in the X direction, between two adjacent trenches 25 in the X direction, and between adjacent trenches 25 and 22 in the X direction. In the second embodiment, in the X direction, the first region R1 and the third region R3 are arranged alternately, such as ..., third region R3, three second region R2, first region R1, three second region R2, third region R3, three second region R2, first region R1, ..., with three second region R2s placed between the first region R1 and the third region R3.

[0052] In the second region R2, a P-type semiconductor layer 11 is provided on the first main surface 10A. The P-type semiconductor layer 11 is in contact with two trenches (trench 21, trench 22, or trench 25) that define the second region R2 in the X direction.

[0053] An insulating film 30 is also provided on the inner wall of the trench 25. An emitter trench electrode 45 is provided inside the trench 25 via the insulating film 30. The emitter trench electrode 45 is formed using, for example, polycrystalline silicon. The emitter trench electrode 45, like the emitter trench electrode 42, is led out to, for example, the vicinity of the outer periphery of the semiconductor device 100 and connected to the emitter electrode (emitter pad) 61.

[0054] The other configurations are the same as in the first embodiment.

[0055] The second embodiment also yields the same effects as the first embodiment. Furthermore, the IE effect is further improved, and the saturation voltage Vce(sat) can be further reduced.

[0056] Furthermore, the number of trenches 25 placed between adjacent pairs of trenches 21 and pairs of trenches 22 is not limited; there may be one trench 25 or three or more.

[0057] (Third embodiment) Next, a third embodiment will be described. The third embodiment differs from the second embodiment mainly in the arrangement of the first region R1, the second region R2, and the third region R3. Figure 17 is a cross-sectional view showing a semiconductor device according to the third embodiment.

[0058] In the semiconductor device 300 according to the third embodiment, a plurality of gate trenches 21, a plurality of emitter trenches 22, a plurality of emitter trenches 25, and a plurality of gate trenches 26 are formed on the first main surface 10A. The trenches 26 extend, for example, in the Y direction. Similar to the second embodiment, pairs of trenches 21 and pairs of trenches 22 are arranged alternately in the X direction. In addition, two trenches 25 are arranged between adjacent pairs of trenches 21 and pairs of trenches 22. Furthermore, one trench 26 is arranged between two adjacent trenches 25. The distance between two adjacent trenches 21 in the X direction is equal to the distance between two adjacent trenches 22 in the X direction, the distance between adjacent trenches 21 and trenches 25 in the X direction, the distance between adjacent trenches 25 and trenches 26 in the X direction, and the distance between adjacent trenches 22 and trenches 25 in the X direction. In other words, if trenches 21, 22, 25, and 26 are not distinguished, multiple trenches are formed on the first main surface 10A in a striped pattern at equal intervals in the X direction. Similar to the second embodiment, a first region R1 is defined between two adjacent trenches 21 in the X direction, and a third region R3 is defined between two adjacent trenches 22 in the X direction. A second region R2 is defined between adjacent trenches 21 and 25 in the X direction, between adjacent trenches 25 and 26 in the X direction, and between adjacent trenches 26 and 22 in the X direction. In the third embodiment, in the X direction, the first region R1 and the third region R3 are arranged alternately, such as ..., third region R3, four second region R2, first region R1, four second region R2, third region R3, four second region R2, first region R1, ..., with four second region R2s placed between the first region R1 and the third region R3.

[0059] In the second region R2, a P-type semiconductor layer 11 is provided on the first main surface 10A. The P-type semiconductor layer 11 is in contact with two trenches (trench 21, trench 22, trench 25, or trench 26) that define the second region R2 in the X direction.

[0060] An insulating film 30 is also provided on the inner wall of the trench 26. A gate trench electrode 46 is provided inside the trench 26 via the insulating film 30. The gate trench electrode 46 is formed using, for example, polycrystalline silicon. The gate trench electrode 46, like the gate trench electrode 41, is led out to, for example, the vicinity of the outer periphery of the semiconductor device 100 and connected to a gate electrode (gate pad) (not shown).

[0061] The other configurations are the same as in the second embodiment.

[0062] The third embodiment also provides the same effects as the second embodiment. Furthermore, it is possible to increase the input capacitance while avoiding an increase in the gate capacitance in the MOS structure, which affects the characteristics of the IGBT. This reduces gate noise.

[0063] Although preferred embodiments have been described in detail above, the invention is not limited to the embodiments described above, and various modifications and substitutions can be made to the embodiments described above without departing from the scope of the claims. [Explanation of Symbols]

[0064] 10: Semiconductor substrates 10A, 10B: Main surface 11, 13, 15, 17, 18, 63: P-type semiconductor layer 12, 14, 16, 62: N-type semiconductor layer 21, 22, 25, 26: Trench 30, 31: Insulating film 41, 46: Gate trench electrodes 42, 45: Emitter trench electrodes 50: Interlayer insulating film 61: Emitter electrode 64: Collector electrode 100, 101, 200, 300: Semiconductor devices R1, R2, R3: area

Claims

1. A semiconductor substrate of a first conductivity type having a first main surface and a second main surface opposite to the first main surface, The first trench provided on the first main surface, A second trench provided on the first main surface, A first semiconductor layer of second conductivity type is provided on the first main surface between the first trench and the second trench, A second semiconductor layer of a first conductivity type is provided at a position that sandwiches the first trench between the first main surface and the first semiconductor layer, and is in contact with the first trench. A third semiconductor layer of second conductivity type is provided below the second semiconductor layer and is in contact with the second semiconductor layer and the first trench, A fourth semiconductor layer of first conductivity type is provided below the third semiconductor layer, is in contact with the third semiconductor layer, and is spaced apart from the first trench, A fifth semiconductor layer of second conductivity type is provided at a position that sandwiches the second trench between the first main surface and the first semiconductor layer, A sixth semiconductor layer of first conductivity type is provided below the fifth semiconductor layer, is in contact with the fifth semiconductor layer, and is spaced apart from the second trench, A first insulating film provided on the inner wall of the first trench, A gate trench electrode is provided in the first trench via the first insulating film and facing the third semiconductor layer, A second insulating film provided on the inner wall of the second trench, An emitter trench electrode provided in the second trench via the second insulating film, A gate electrode connected to the gate trench electrode, The emitter electrode connected to the emitter trench electrode, The collector electrode provided on the second main surface, It has, The fourth semiconductor layer contains impurities of the first conductivity type at a higher concentration than the semiconductor substrate and at a lower concentration than the second semiconductor layer. A semiconductor device wherein the lower end of the fifth semiconductor layer is located at the same level as or lower than the lower end of the third semiconductor layer.

2. A semiconductor substrate of a first conductivity type having a first main surface and a second main surface opposite to the first main surface, The first trench provided on the first main surface, A second trench provided on the first main surface, A third trench provided on the first main surface, A fourth trench provided on the first main surface, A first semiconductor layer of second conductivity type is provided on the first main surface between the first trench and the second trench, A second semiconductor layer of a first conductivity type is provided at a position that sandwiches the first trench between the first main surface and the first semiconductor layer, and is in contact with the first trench. A third semiconductor layer of second conductivity type is provided below the second semiconductor layer and is in contact with the second semiconductor layer and the first trench, A fourth semiconductor layer of first conductivity type is provided below the third semiconductor layer, is in contact with the third semiconductor layer, and is spaced apart from the first trench, A fifth semiconductor layer of second conductivity type is provided at a position that sandwiches the second trench between the first main surface and the first semiconductor layer, A first insulating film provided on the inner wall of the first trench, A first gate trench electrode is provided in the first trench via the first insulating film and facing the third semiconductor layer, A second insulating film provided on the inner wall of the second trench, A third insulating film provided on the inner wall of the third trench, A fourth insulating film provided on the inner wall of the fourth trench, A first emitter trench electrode provided in the second trench via the second insulating film, A gate electrode connected to the first gate trench electrode, The emitter electrode connected to the first emitter trench electrode, The collector electrode provided on the second main surface, A second gate trench electrode is provided in the third trench via the third insulating film, facing the third semiconductor layer and connected to the gate electrode, A second emitter trench electrode is provided in the fourth trench via the fourth insulating film and connected to the emitter electrode, It has, The first trench is located between the second trench and the third trench. The second trench is located between the first trench and the fourth trench. The third semiconductor layer is also in contact with the third trench. The fourth semiconductor layer is also spaced apart from the third trench. The fifth semiconductor layer is also in contact with the fourth trench. The third trench, the first trench, the second trench, and the fourth trench are arranged in a striped pattern at equal intervals. A semiconductor device wherein the lower end of the fifth semiconductor layer is located at the same level as or lower than the lower end of the third semiconductor layer.

3. The semiconductor device according to claim 2, wherein the fourth semiconductor layer contains an impurity of the first conductivity type at a higher concentration than that of the semiconductor substrate and at a lower concentration than that of the second semiconductor layer.

4. The semiconductor device according to any one of claims 1 to 3, wherein the lower end of the fifth semiconductor layer is located at a position equal to or higher than the lower end of the first semiconductor layer.

5. The semiconductor device according to any one of claims 1 to 4, wherein the depth of the first semiconductor layer from the first main surface is greater than or equal to the depth of the first trench from the first main surface.

6. The semiconductor device according to any one of claims 1 to 4, wherein the position of the lower end of the fifth semiconductor layer coincides with the position of the lower end of the third semiconductor layer.

7. The semiconductor device according to claim 6, wherein the lower end of the fifth semiconductor layer is located at a position equal to or higher than the lower end of the first semiconductor layer.

8. The semiconductor device according to any one of claims 1 to 7, wherein the emitter electrode is in contact with the second semiconductor layer, the third semiconductor layer, and the fifth semiconductor layer.

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