Manufacturing method for semiconductor devices

Abstract

To provide a semiconductor device capable of avoiding reduction in breakdown voltage while suppressing the area of a termination region.SOLUTION: A semiconductor device has: a semiconductor substrate; a cell region provided on a first plane side of the semiconductor substrate; and a termination region provided on the first plane side of the semiconductor substrate and outside the cell region. The termination region surrounds the cell region, including a plurality of first diffusion layers containing a first conductivity type impurity. In the cross-section of the termination region in a first direction perpendicular to the first plane, at least one of the plurality of first diffusion layers has a first region extending in the first direction from the first plane to a second plane of the semiconductor substrate, and a second region extending from the first region in a second direction orthogonal to the first direction. The concentration of the first conductivity type impurity contained in the second region is lower than that contained in the first region.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] Embodiments of the present invention relate to semiconductor devices and methods for manufacturing the same. [Background technology]

[0002] Power semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors) typically have a structure in their termination region that consists of multiple P-type semiconductor layers called guard rings to maintain breakdown voltage. In guard ring termination structures, the electric field becomes stronger around the P-type semiconductor layers. Therefore, forming deep, semi-circular P-type semiconductor layers is important to ensure breakdown voltage. However, guard ring layers with such a cross-sectional shape have a wide termination region. As a result, the area occupied by the termination region within the power semiconductor device increases, hindering the miniaturization of the device.

[0003] Therefore, one method to reduce the area of ​​the terminal region is to form a guard ring layer with a rectangular cross-sectional shape formed by low-temperature heat treatment. However, with a rectangular guard ring layer, the curvature of the corners becomes small. As a result, the electric field may concentrate near the corners, potentially reducing the breakdown voltage. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2022-3711 [Overview of the Initiative] [Problems that the invention aims to solve]

[0005] Embodiments of the present invention provide a semiconductor device and a method for manufacturing the same that can suppress the area of ​​the termination region while avoiding a decrease in breakdown voltage. [Means for solving the problem]

[0006] A semiconductor device according to one embodiment includes a semiconductor substrate, a cell region provided on the first surface side of the semiconductor substrate, and a termination region provided on the first surface side of the semiconductor substrate outside the cell region. The termination region continuously surrounds the cell region and includes a plurality of first diffusion layers containing a first conductivity type impurity. In a cross-section of the termination region in a first direction perpendicular to the first surface, at least one of the plurality of first diffusion layers has a first region extending in a first direction from the first surface of the semiconductor substrate toward the second surface, and a second region extending in a second direction perpendicular to the first direction from the first region. The concentration of the first conductivity type impurity contained in the second region is lower than the concentration of the first conductivity type impurity contained in the first region. [Brief explanation of the drawing]

[0007] [Figure 1] This is a cross-sectional view showing the schematic structure of a semiconductor device according to the first embodiment. [Figure 2A] This is a cross-sectional view showing the formation process of the first P-type impurity layer. [Figure 2B] This is a cross-sectional view showing the formation process of the second P-type impurity layer. [Figure 2C] This is a cross-sectional view showing the formation process of the third P-type impurity layer. [Figure 2D] This is a cross-sectional view showing the formation process of the fourth P-type impurity layer. [Figure 2E] This is a cross-sectional view showing the formation process of the fifth P-type impurity layer. [Figure 2F] This is a cross-sectional view showing the heat treatment process for each P-type impurity layer. [Figure 2G] This is a cross-sectional view showing the process of forming the interlayer insulating film. [Figure 2H] This is a cross-sectional view showing the process of forming an N-type buffer layer and a P-type collector layer. [Figure 3] This is a cross-sectional view showing the structure of the semiconductor device according to the first comparative example. [Figure 4] This is a cross-sectional view showing the structure of a semiconductor device according to the second comparative example. [Figure 5] This graph shows an example of the results of a simulation of the electric field distribution in the terminal region. [Figure 6]A graph showing an example of the result of simulating the electric field distribution in the end region when the width of the second region is changed. [Figure 7] A cross-sectional view showing a schematic structure of a semiconductor device according to the second embodiment. [Figure 8] A diagram showing an example of the result of simulating the breakdown voltage. [Figure 9] A cross-sectional view showing a schematic structure of a semiconductor device according to the third embodiment. [Figure 10A] A cross-sectional view showing a process of forming a first opening in a first interlayer insulating film. [Figure 10B] A cross-sectional view showing a process of forming a first conductive film. [Figure 10C] A cross-sectional view showing a process of removing a part of the first conductive film. [Figure 10D] A cross-sectional view showing a process of forming a second opening in a second interlayer insulating film. [Figure 10E] A cross-sectional view showing a process of forming a second conductive film. [Figure 10F] A cross-sectional view showing a process of removing a part of the second conductive film. [Figure 10G] A cross-sectional view showing a process of forming a passivation film. [Figure 11A] A cross-sectional view of a guard ring layer in which the second region extends on both sides of the first region. [Figure 11B] A cross-sectional view of a guard ring layer in which the bottom of the second region extending on both sides of the first region is disposed at a position shallower than the bottom of the first region. [Figure 11C] A cross-sectional view of a guard ring layer in which the bottom of the second region extending outside the first region is disposed at a position shallower than the bottom of the first region. [Figure 11D] A cross-sectional view of a guard ring layer in which the bottom of the second region extending inside the first region is disposed at a position shallower than the bottom of the first region. [Figure 11E] A cross-sectional view of a guard ring layer in which the bottom of the second region extending on both sides of the first region is disposed at a position deeper than the bottom of the first region. [Figure 11F]This is a cross-sectional view of a guard ring layer, where the bottom of the second region, which extends outside the first region, is located at a deeper position than the bottom of the first region. [Figure 11G] This is a cross-sectional view of a guard ring layer, where the bottom of the second region, which extends inside the first region, is located at a deeper position than the bottom of the first region. [Figure 11H] This is a cross-sectional view of a guard ring layer in which the second region extends on both sides of the first region, and the bottom of the first region is in contact with the second region. [Modes for carrying out the invention]

[0008] Embodiments of the present invention will be described below with reference to the drawings. These embodiments are not intended to limit the present invention.

[0009] (First Embodiment) Figure 1 is a cross-sectional view showing a schematic structure of a semiconductor device according to the first embodiment. The semiconductor device 1 shown in Figure 1 is an IGBT having a trench gate structure. This semiconductor device 1 includes a cell region 20 and a termination region 30 on the surface side of a semiconductor substrate 10. The cell region 20 and the termination region 30 are covered with an interlayer insulating film 40. The interlayer insulating film 40 is composed of, for example, a silicon oxide (SiO2) film. Note that the semiconductor device 1 is not limited to a trench gate IGBT, and may be, for example, a planar gate IGBT.

[0010] The semiconductor substrate 10 has a P-type collector layer 11, an N-type buffer layer 12, and an N-type base layer 13. Each layer will be described below.

[0011] The P-type collector layer 11 is located at the bottom of the semiconductor substrate 10. The P-type collector layer 11 functions as a collector for the IGBT. The thickness of the P-type collector layer 11 is, for example, 0.2 μm.

[0012] The N-type buffer layer 12 is stacked on the P-type collector layer 11. The concentration of N-type impurities in the N-type buffer layer 12 is higher than the concentration of N-type impurities in the N-type base layer 13. The thickness of the N-type buffer layer 12 is, for example, 1 μm.

[0013] The N-type base layer 13 is stacked on the N-type buffer layer 12. The N-type base layer 13 corresponds to the first semiconductor layer, and a cell region 20 and a termination region 30 are provided on its surface side (first surface side).

[0014] First, let's describe the cell region 20. The cell region 20 has a P-type base layer 21, a gate electrode 22, a gate insulating film 23, and an N-type emitter layer 24.

[0015] The P-type base layer 21 corresponds to the second diffusion layer and is provided on the surface of the semiconductor substrate 10 (N-type base layer 13). The concentration of P-type impurities in the P-type base layer 21 is lower than the concentration of P-type impurities in the first region 311 of the guard ring layer 310 provided in the termination region 30, which will be described later.

[0016] The gate electrode 22 penetrates the P-type base layer 21 from the surface of the semiconductor substrate 10 and terminates in the N-type base layer 13. The gate electrode 22 contains, for example, polysilicon.

[0017] The gate insulating film 23 electrically insulates the gate electrode 22 from the N-type base layer 13, the P-type base layer 21, and the N-type emitter layer 24. The gate insulating film 23 is, for example, a silicon oxide film.

[0018] The N-type emitter layer 24 corresponds to a third diffusion layer containing N-type impurities and faces the gate electrode 22 via the gate insulating film 23 within the P-type base layer 21. The N-type emitter layer 24 functions as the emitter of the IGBT.

[0019] Next, the terminal region 30 located outside the cell region 20 will be described. The terminal region 30 includes an N-type EQPR (EQuivalent-Potential Ring) layer 300 and multiple guard ring layers 310.

[0020] The EQPR layer 300 is located on the outermost side of the termination region 30. The concentration of N-type impurities in the EQPR layer 300 is higher than the concentration of N-type impurities in the N-type base layer 13. The EQPR layer 300 is at the same potential as the P-type collector layer 11.

[0021] Each of the multiple guard ring layers 310 is composed of a ring-shaped P-type diffusion layer that continuously surrounds the cell region 20. In this embodiment, seven guard ring layers are provided in the terminal region 30, but the number of guard ring layers can be any number.

[0022] As shown in Figure 1, the guard ring layer 310 according to this embodiment has a first region 311 and a second region 312 in the cross-section of the termination region 30 in a first direction perpendicular to the surface of the semiconductor substrate 10. Each diffusion region will be described below.

[0023] The first region 311 extends in the first direction from the front surface to the back surface (second surface) of the semiconductor substrate 10. The concentration of P-type impurities contained in the first region 311 is higher than the concentration of P-type impurities contained in the P-type base layer 21 of the cell region 20.

[0024] The second region 312 extends from near the bottom of the first region 311 in a second direction perpendicular to the first direction (a direction parallel to the surface of the semiconductor substrate 10). In this embodiment, the second region 312 protrudes from the bottom of the first region 311 toward the EQPR layer 300. Furthermore, the width of the bottom of each guard ring layer 310 (W1 + W2) is greater than the width of the top of each guard ring layer 310 located on the surface side of the semiconductor substrate 10 (W1). In addition, as shown in Figure 1, an N-type base layer 13, which is an N-type semiconductor layer, is provided on the upper part of the second region 312.

[0025] In this embodiment, all guard ring layers 310 have a first region 311 and a second region 312. However, some guard ring layers 310, for example, the guard ring layer 310 located closest to the cell region 20, may consist only of the first region 311 and not have the second region 312.

[0026] The manufacturing method of the semiconductor device according to the first embodiment described above will be explained below with reference to Figures 2A to 2H. Here, the manufacturing process of the termination region 30 will be mainly described.

[0027] First, as shown in Figure 2A, a resist 50 is formed on the surface of a semiconductor substrate 10a composed of an N-type base layer 13. The resist 50 is patterned so that the formation area of ​​the first region 311 of the guard ring layer 310 is open.

[0028] Next, boron (B) ions are irradiated from above the resist 50. At this time, for example, the dose of boron ions is 1 × 10⁻⁶. 13 cm -2 The settings are configured such that the acceleration voltage is set to 3.5 MeV. As a result, as shown in Figure 2A, the first P-type impurity layer 311a is formed inside the N-type base layer 13.

[0029] Next, as shown in Figure 2B, boron (B) ions are irradiated under different irradiation conditions. At this time, the dose of boron ions is, for example, 3 × 10⁻⁶. 13 cm -2 The acceleration voltage is set to, for example, 2 MeV, which is lower than when the first P-type impurity layer 311a is formed. As a result, as shown in Figure 2B, the second P-type impurity layer 311b is formed on the first P-type impurity layer 311a.

[0030] Next, as shown in Figure 2C, the irradiation conditions are further changed and boron (B) ions are irradiated. At this time, the dose of boron ions is, for example, 1 × 10⁻⁶. 14 cm -2It is set to, and increases compared to when the second P-type impurity layer 311b is formed. Also, the acceleration voltage is set to, for example, 1 MeV, and is reduced compared to when the second P-type impurity layer 311b is formed. As a result, as shown in FIG. 2C, the third P-type impurity layer 311c is formed on the second P-type impurity layer 311b.

[0031] Next, as shown in FIG. 2D, boron (B) ions are irradiated while further changing the irradiation conditions. At this time, the dose amount of boron ions is set to, for example, 3×10 14 cm -2 and increases compared to when the third P-type impurity layer 311c is formed. Also, the acceleration voltage is set to, for example, 100 KeV, and is reduced compared to when the third P-type impurity layer 311c is formed. As a result, as shown in FIG. 2D, the fourth P-type impurity layer 311d is formed on the third P-type impurity layer 311c. Thereafter, the resist 50 is removed.

[0032] The first P-type impurity layer 311a to the fourth P-type impurity layer 311d formed in the steps shown in FIGS. 2A to 2D above correspond to the state before diffusion of the first region 311. In the present embodiment, as described above, by injecting boron ions a plurality of times while changing the dose amount and acceleration voltage of boron ions, an impurity layer that becomes the source of the first region 311 is formed.

[0033] Next, as shown in FIG. 2E, a resist 60 is formed on the surface of the semiconductor substrate 10a. The resist 60 is patterned so that the formation location of the second region 312 is open. Subsequently, boron (B) ions are irradiated from above the resist 60. At this time, the dose amount and acceleration voltage of boron ions are set to 1×10 13 cm -2 and 3.5 MeV, respectively, in the same manner as the formation conditions of the first P-type impurity layer 311a. As a result, as shown in FIG. 2E, the fifth P-type impurity layer 312a is formed adjacent to the first P-type impurity layer 311a. The fifth P-type impurity layer 312a corresponds to the state before diffusion of the second region 312. Thereafter, the resist 60 is removed.

[0034] In this embodiment, the process of forming the first P-type impurity layer 311a to the fourth P-type impurity layer 311d and the process of forming the fifth P-type impurity layer 312a are continuous, but these processes do not have to be continuous. Also, in this embodiment, the fifth P-type impurity layer 312a is formed after the first P-type impurity layer 311a to the fourth P-type impurity layer 311d, but it may be formed earlier.

[0035] The first P-type impurity layers 311a to the fifth P-type impurity layers 312a formed as described above are heat-treated. As a result, as shown in Figure 2F, the boron in each P-type impurity layer is activated, and the first region 311 and the second region 312 are formed. At this time, low-temperature heat treatment below 1000°C is performed to suppress the diffusion of boron. This makes it possible to make the cross-sectional shape of the first region 311 and the second region 312 perpendicular to the semiconductor substrate 10 a rectangular shape with rounded corners.

[0036] Next, a cell region 20 is formed. Here, for example, a P-type base layer 21 and an N-type emitter layer 24 are formed by ion implantation. Additionally, a trench is formed by RIE (Reactive Ion Etching) that penetrates the P-type base layer 21 and terminates at the N-type emitter layer 24. Within this trench, a gate insulating film 23 and a gate electrode 22 are sequentially formed by CVD (Chemical Vapor Deposition).

[0037] Next, as shown in Figure 2G, an interlayer insulating film 40 is formed on the surface of the semiconductor substrate 10a on which the guard ring layer 310 is formed.

[0038] Finally, as shown in Figure 2H, an N-type buffer layer 12 and a P-type collector layer 11 are sequentially formed on the entire back surface of the semiconductor substrate 10a. The N-type buffer layer 12 can be formed, for example, by injecting phosphorus (P) ions into the back surface of the semiconductor substrate 10a and performing an annealing treatment. On the other hand, the P-type collector layer 11 can be formed by injecting boron ions into the back surface of the semiconductor substrate 10a and performing an annealing treatment. Note that the P-type collector layer 11 does not need to be formed in the termination region 30.

[0039] Here, a comparative example of a semiconductor device compared to the semiconductor device 1 according to the first embodiment described above will be explained.

[0040] Figure 3 is a cross-sectional view showing the structure of a semiconductor device according to the first comparative example. In this comparative example, the same reference numerals are used for components similar to those in the semiconductor device 1 according to the first embodiment, and detailed descriptions are omitted.

[0041] The semiconductor device 100 in this comparative example has a different cross-sectional shape of the guard ring layer in the termination region 30 compared to the first embodiment. In this modified example, the curvature of the guard ring layer 310a is rounded.

[0042] The guard ring layer 310a is formed by subjecting the boron injected onto the surface of the semiconductor substrate 10 to high-temperature and long-duration heat treatment, resulting in a deep and wide P-type diffusion layer extending from the surface of the semiconductor substrate 10. In other words, the cross-section of the guard ring layer 310a is close to a semicircular shape. However, a diffusion layer with a wide width W3, such as the guard ring layer 310a, is a factor that lengthens the termination region 30. Therefore, it becomes difficult to narrow the width of the termination region 30.

[0043] Figure 4 is a cross-sectional view showing the structure of a semiconductor device according to the second comparative example. In this comparative example as well, the same reference numerals are used for components similar to those in the semiconductor device 1 according to the first embodiment, and detailed descriptions are omitted.

[0044] In the semiconductor device 101 of this comparative example, the guard ring layer 310b of the termination region 30 has a cross-sectional shape close to a rectangle. The diffusion temperature of the guard ring layer 310b is set to a low temperature of 1000°C or less in order to suppress lateral spreading. As a result, the width W4 of the guard ring layer 310b is narrower than the width W3 of the guard ring layer 310a of the first comparative example described above. This makes it possible to suppress the size of the termination region 30.

[0045] However, in guard ring layer 310b, the curvature of the corner at the bottom is smaller than that of guard ring layer 310a in the first comparative example. As a result, the electric field concentrates near this corner, which reduces the breakdown voltage.

[0046] In contrast, the guard ring layer 310 according to this embodiment is formed by low-temperature heat treatment, similar to the second comparative example. Therefore, the electric field may concentrate at the corner of the first region 311.

[0047] However, the guard ring layer 310 has a second region 312 extending from the corner of the first region 311, where the concentration of P-type impurities is lower than that of the first region 311. This second region 312 can alleviate the electric field concentration at the corner of the first region 311.

[0048] Figure 5 is a graph showing an example of the simulation results of the electric field distribution in the termination region 30 for this embodiment and the second comparative example. In Figure 5, the horizontal axis shows the lateral position of the termination region 30 relative to the boundary between the cell region 20 and the termination region 30. The vertical axis shows the electric field on the surface of the semiconductor substrate 10 in the termination region 30.

[0049] According to the simulation results shown in Figure 5, this embodiment can suppress the electric field in the termination region 30 compared to the second comparative example. As a result, the breakdown voltage is improved, and therefore the expansion of the width of the termination region 30 can be suppressed.

[0050] Figure 6 is a graph showing an example of the simulation results of the electric field distribution in the terminal region 30 when the width W2 of the second region 312 is changed. In Figure 6, the horizontal axis shows the lateral position of the terminal region 30 relative to the boundary between the cell region 20 and the terminal region 30. The vertical axis shows the electric field on the surface of the semiconductor substrate 10 in the terminal region 30.

[0051] Figure 6 shows the simulation results of the electric field distribution for cases where the width W2 of the second region 312 is 2 μm, 4 μm, and 6 μm. Note that only the peak values ​​of the electric field are plotted in Figure 6.

[0052] According to the simulation results shown in Figure 6, the electric field on the surface of the semiconductor substrate 10 decreases as the width W2 of the second region 312 increases. However, if the width W2 is large, the termination region 30 becomes larger. Therefore, it is desirable that the sum of the width W1 of the first region 311 and the width W2 of the second region 312 be the same as or smaller than the width W4 of the guard ring layer 310b in the second comparative example.

[0053] According to the embodiment described above, the first region 311 and the second region 312, which have a rectangular cross-sectional shape, make it possible to suppress the area of ​​the terminal region while avoiding a decrease in withstand voltage.

[0054] In this embodiment, the concentration of P-type impurities in the second region 312 is uniform. However, a concentration gradient may exist within the second region 312. The concentration gradient of the P-type impurities layer can be formed by changing, for example, the dose of boron ions when forming the second region 312. For example, in the second region 312, the concentration of P-type impurities may decrease from the inner end, which is the part in contact with the first region 311, to the outer end, which is the part furthest from the first region 311. By having a concentration gradient of P-type impurities layer in the second region 312 in this way, it becomes possible to further relax the electric field of the terminal region 30.

[0055] (Second Embodiment) Figure 7 is a cross-sectional view showing the schematic structure of the semiconductor device according to the second embodiment. In Figure 7, the same reference numerals are used for components similar to those in the semiconductor device 1 according to the first embodiment described above, and detailed descriptions are omitted.

[0056] In the semiconductor device 1 according to the first embodiment described above, the second region 312 is located outside the first region 311, that is, on the EQPR layer 300 side. On the other hand, in the semiconductor device 2 according to this embodiment, as shown in Figure 7, the second region 312 is located inside the first region 311, that is, on the cell region 20 side.

[0057] The semiconductor device 2 according to this embodiment can also be manufactured by the same manufacturing process as the semiconductor device 1 according to the first embodiment described in the first embodiment. The second region 312 can be formed by changing the opening pattern of the resist 60 for boron ion implantation (see Figure 2E) to the inside of the first region 311.

[0058] Figure 8 shows an example of the results of a pressure resistance simulation for the second comparative example, the first embodiment, and the second embodiment. In Figure 8, type A, type B, and type C correspond to the second comparative example, the first embodiment, and the second embodiment, respectively.

[0059] Figure 8 shows -5 × 10 11 cm -2 The collector-emitter breakdown voltage under simulation conditions where an external charge is accumulated on the surface of the semiconductor substrate 10 in the termination region 30 is shown. If a negative charge is present on the surface of the semiconductor substrate 10, the electric field extends, and the guard ring layer 310 may not be able to withstand the lateral potential. In this case, the breakdown voltage decreases.

[0060] In this embodiment, by making the cross-sectional shape of the guard ring layer 310 rectangular, the electric field on the surface of the semiconductor substrate 10 in the termination region 30 can be mitigated. This improves charge robustness. Furthermore, in this embodiment, the second region 312 is formed to extend from the first region 311 toward the cell region 20. This secures space for the electric field to extend across the surface of the semiconductor substrate 10, thereby further improving charge robustness.

[0061] (Third embodiment) Figure 9 is a cross-sectional view showing the schematic structure of a semiconductor device according to the third embodiment. In Figure 9, components similar to those in the semiconductor device 1 according to the first embodiment described above are denoted by the same reference numerals, and detailed descriptions are omitted.

[0062] In addition to the components of the semiconductor device 1 according to the first embodiment described above, the semiconductor device 3 according to this embodiment includes a first field plate 321 and a second field plate 322 provided within the interlayer insulating film 40. The first field plate 321 faces each guard ring layer 310 via an interlayer insulating film 40. The first field plate 321 is made of a metal such as tungsten (W). The first field plate 321 is connected to the first region 311.

[0063] The second field plate 322 is laminated on the first field plate 321 via an interlayer insulating film 40. The second field plate 322 is made of a metal such as aluminum (Al).

[0064] The second field plate 322 is also connected to the first region 311 of each guard ring layer 310. The second field plate 322 is longer than the first field plate 321. The second field plate 322 is also thicker than the first field plate 321.

[0065] In this embodiment, a first field plate 321 and a second field plate 322 are provided in each guard ring layer 310, but the number of stacked field plates may differ for each guard ring layer 310. Furthermore, the first field plate 321 may be in contact with the first region 311 of each guard ring layer 310, and the second field plate 322 may also be in contact with the first field plate 321.

[0066] The first field plate 321 and the second field plate 322 are formed following the process of forming the guard ring layer 310 and the process of forming the cell region 20. Now, with reference to Figures 10A to 10G, the manufacturing methods for the first field plate 321 and the second field plate 322 will be described.

[0067] First, as shown in Figure 10A, a first interlayer insulating film 41 is formed on the surface of the semiconductor substrate 10a on which the guard ring layer 310 is formed. The first interlayer insulating film 41 is the lower layer portion of the interlayer insulating film 40. The thickness of the first interlayer insulating film 41 is, for example, 1.1 μm. Next, a first opening 411 is formed that penetrates the first interlayer insulating film 41 so as to expose a part of each first region 311. The first opening 411 is formed at the location where the first field plate 321 is formed.

[0068] Next, as shown in Figure 10B, a first conductive film 70 is formed on the first interlayer insulating film 41. The first conductive film 70 is a tungsten film formed, for example, by CVD. The thickness of the first conductive film 70 is, for example, 300 nm. In this step, the first opening 411 is filled with the first conductive film 70. By making the opening width of the first opening 411 as narrow as possible, the surface of the first conductive film 70 can be made almost flat.

[0069] Next, as shown in Figure 10C, unnecessary portions of the first conductive film 70 are removed using RIE. This completes the first field plate 321. The first conductive film 70 filled in the first opening 411 functions as a first contact plug that electrically connects the first field plate 321 to the first region 311.

[0070] Next, as shown in Figure 10D, a second interlayer insulating film 42 is formed on the first interlayer insulating film 41 so as to cover the first field plate 321. The second interlayer insulating film 42 is the intermediate layer portion of the interlayer insulating film 40. The thickness of the second interlayer insulating film 42 does not need to be greater than the thickness of the first interlayer insulating film 41, for example, 3 μm. Subsequently, a second opening 421 is formed between the first interlayer insulating film 41 and the second interlayer insulating film 42 so as to expose a part of the first region 311. The second opening 421 is formed at the location where the second field plate 322 is formed.

[0071] Next, as shown in Figure 10E, a second conductive film 71 is formed on the second interlayer insulating film 42. The second conductive film 71 is, for example, an aluminum film formed by PVD (Physical Vapor Deposition). The thickness of the second conductive film 71 is, for example, 4 μm. In this step, the second opening 421 is filled with the second conductive film 71.

[0072] Next, as shown in Figure 10F, unnecessary portions of the second conductive film 71 are removed using RIE. This completes the second field plate 322. The second conductive film 71 filled in the second opening 421 functions as a second contact plug that electrically connects the second field plate 322 to the first region 311.

[0073] Finally, as shown in Figure 10G, a passivation film 43 is formed on the second interlayer insulating film 42 so as to cover the second field plate 322. The passivation film 43 is the upper layer of the interlayer insulating film 40. The passivation film 43 consists of a laminated film formed by laminating, for example, a resin film such as polyimide and a semi-insulating film or an insulating film. Subsequently, in the same manner as in the first embodiment, an N-type buffer layer 12 and a P-type collector layer 11 are sequentially formed on the entire back surface of the semiconductor substrate 10a.

[0074] As described above, according to this embodiment, the first field plate 321 and the second field plate 322 are provided in the termination region 30. Therefore, the electric field on the surface of the semiconductor substrate 10 in the termination region 30 can be mitigated.

[0075] (Variation 1) A modified example of the first embodiment will be described below with reference to Figures 11A to 11H. In this modified example, the shape of the guard ring layer 310 differs from that of the first embodiment.

[0076] In the guard ring layer 310 shown in Figure 11A, the second region 312 extends on both sides of the first region 311. In this case, the width of the second region 312 does not need to be the same on both sides of the first region 311. It can be designed to have an optimal width on the inside and outside of the first region 311, depending on the electric field distribution on the surface of the semiconductor substrate 10.

[0077] In the guard ring layer 310 shown in Figure 11B, the bottom of the second region 312, which extends on both sides of the first region 311, is located at a shallower position than the bottom of the first region 311. In the guard ring layer 310 shown in Figure 11C, the bottom of the second region 312, which extends to the outside of the first region 311, is located at a shallower position than the bottom of the first region 311. In the guard ring layer 310 shown in Figure 11D, the bottom of the second region 312, which extends to the inside of the first region 311, is located at a shallower position than the bottom of the first region 311.

[0078] The relative positions of the bottoms of each region, as shown in Figures 11B to 11D, can be achieved by adjusting the acceleration voltage of the boron ions. Specifically, the acceleration voltage during the formation of the first P-type impurity layer 311a (see Figure 2A), which corresponds to the bottom of the first region 311, is greater than the acceleration voltage during the formation of the fifth P-type impurity layer 312a (see Figure 2E), which corresponds to the second region 312.

[0079] In the guard ring layer 310 shown in Figure 11E, the bottoms of the second region 312, which extend on both sides of the first region 311, are located deeper than the bottom of the first region 311. In the guard ring layer 310 shown in Figure 11F, the bottoms of the second region 312, which extend to the outside of the first region 311, are located deeper than the bottom of the first region 311. In the guard ring layer 310 shown in Figure 11G, the bottoms of the second region 312, which extend to the inside of the first region 311, are located deeper than the bottom of the first region 311. In the guard ring layer 310 shown in Figure 11H, the second region 312 extends on both sides of the first region 311, and the bottom of the first region 311 is in contact with the second region 312.

[0080] The relative positions of the bottoms of each region, as shown in Figures 11E to 11H, can also be achieved by adjusting the acceleration voltage of the boron ions. Specifically, the acceleration voltage during the formation of the first P-type impurity layer 311a is smaller than the acceleration voltage during the formation of the fifth P-type impurity layer 312a.

[0081] In this modified example described above, since each guard ring layer 310 has a second region 312, it is possible to suppress the area of ​​the terminal region while avoiding a decrease in withstand voltage.

[0082] Although multiple guard ring layers 310 are formed in the terminal region 30, it is not necessary for all guard ring layers 310 to have the same shape. In the terminal region 30, the shapes of the first region 311 and the second region 312, as shown in Figures 11A to 11H above, may be mixed.

[0083] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0084] 1-3: Semiconductor equipment 10: Semiconductor substrates 13: N-type base layer (first semiconductor layer) 20: Cell area 21: P-type base layer (second diffusion layer) 22: Grid gate 23: Gate Insulator 24: N-type emitter layer (third diffusion layer) 30: Termination area 310: Guard ring layer (first diffusion layer) 311:First area 312:Second area 321: First field plate (conductive layer) 322: Second field plate 322 (conductive layer)

Claims

1. A method for manufacturing a semiconductor device comprising a semiconductor substrate, a cell region provided on a first surface side of the semiconductor substrate, and a termination region provided on the first surface side of the semiconductor substrate outside the cell region, The method involves forming a plurality of first diffusion layers containing a first conductivity type impurity within the terminal region so as to surround the cell region, wherein in a cross-section of the terminal region in a first direction perpendicular to the first surface, at least one of the plurality of first diffusion layers has a first region extending in the first direction from the first surface to the second surface of the semiconductor substrate, and a second region extending in a second direction perpendicular to the first direction from the first region, and the concentration of the first conductivity type impurity contained in the second region is lower than the concentration of the first conductivity type impurity contained in the first region. A concentration gradient of the first conductivity type impurity is formed within the second region, such that the concentration of the first conductivity type impurity decreases as you move from the inner end adjacent to the first region to the outer end furthest from the first region. This includes forming the cross-sectional shape perpendicular to the semiconductor substrate in the first and second regions into a rectangular shape with rounded corners, A method for manufacturing a semiconductor device, wherein the concentration gradient of the first conductivity type impurity is formed by changing the dose amount of the first conductivity type impurity when forming the second region.

2. The first region and the second region are formed by heat treatment at 1000°C or lower. A method for manufacturing a semiconductor device according to claim 1.

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