A semiconductor structure having a barrier layer containing aluminum indium nitride, and a method for growing the semiconductor structure.

Abstract

The semiconductor structure (1) comprises a substrate (100) and an epitaxial III-N semiconductor layer stack (200) overlying the substrate (100). The epitaxial III-N semiconductor layer stack (200) comprises a first active III-N layer (201), a spacer layer (202) overlying the first active III-N layer (201), a diffusion barrier layer (203) overlying the spacer layer (202), and a second active III-N layer (204) overlying the diffusion barrier layer (203) and comprising indium aluminum nitride. A two-dimensional electron gas (20) is located between the first active III-N layer (201) and the second active III-N layer (204). The diffusion barrier layer (203) comprises gallium nitride, and the thickness of the diffusion barrier layer (203) is less than 1 nm.

Description

Detailed Description of the Invention

[0001] [Technical Field] The present invention generally relates to semiconductor structures including an InAlN barrier layer and methods for growing such semiconductor structures. More specifically, the present invention relates to semiconductor structures including an InAlN barrier layer exhibiting improved mobility and sheet resistance, and methods for growing such semiconductor structures.

[0002] [Background] GaN-based heterostructures have attracted interest for high-power and high-frequency applications because they exhibit high electron velocity and high critical electric field. For example, conventionally, an AlGaN / GaN heterostructure has been used in the manufacture of a field effect transistor, also referred to as a FET. In this structure, a two-dimensional electron gas, also referred to as 2DEG, is generated by the spontaneous piezoelectric polarization between AlGaN and GaN.

[0003] Increasing the density of the two-dimensional electron gas is effective for improving device performance. In order to increase the density of the two-dimensional electron gas, the aluminum content of the AlGaN barrier should be increased. However, AlGaN having a high aluminum content is highly strained with respect to GaN. The large strain affects the reliability of devices manufactured from these GaN-based heterostructures.

[0004] The ternary InAlN layer has the potential to replace conventional AlGaN as a barrier layer. Ternary InAlN can be lattice-matched to GaN in a composition of 17% indium and 83% aluminum. The lattice-matched InAlN / GaN heterostructure generates a high-density two-dimensional electron gas without any doping, due to differences in spontaneous polarization at the interface between the InAlN barrier layer and GaN. For example, applications in photonics range from the fabrication of blue and green light-emitting diodes to laser diodes across a wide wavelength range. For example, applications in electronics relate to high-electron-mobility transistors suitable for high-power, high-frequency, and / or high-temperature devices. Using InAlN as a lattice-matched barrier layer to GaN minimizes the effects of misfit-induced defects in nitride heterostructure devices, while generating a very high sheet carrier density while creating a heteroepitaxial interface with low strain and low defect density. To further increase electron mobility, an AlN ultrathin layer may be used as a conventional spacer layer between the InAlN barrier layer and the GaN channel layer. In this case, an InAlN / AlN / GaN heterostructure is formed. Electron mobility depends not only on the steepness of the interface between GaN and the AlN spacer, but also on the quality of the spacer layer itself in terms of compositional uniformity and crystal quality.

[0005] While the manufactured devices have the potential to be of high quality, controlling the growth of the above structure is not easy. In fact, the growth of InAlN is complicated by the thermal inhibition of indium incorporation into the solid phase at high temperatures. In other words, the growth of InAlN films is difficult because the optimal growth temperatures for the binary systems of InN and AlN in the InAlN film are different. Specifically, at temperatures above 450°C, InN separates. On the other hand, to obtain a good quality crystalline film, it is necessary to grow AlN at temperatures above 1000°C.

[0006] Figures 1A and 1B show the change in sheet resistance 91 of a wafer undergoing epitaxial growth of an InAlN / AlN / GaN heterostructure as a function of the rounded radius 92 from the center 93 of the wafer. Therefore, in both Figures 1A and 1B, point 93 corresponds to the center of the wafer, and point 94 corresponds to the edge of the wafer. Figure 1A shows the sheet resistance 95 of the wafer before thermal annealing. On the other hand, Figure 1B shows the sheet resistance 96 of the wafer after thermal annealing, for example, when the wafer is annealed at 750°C for 30 minutes. The sheet resistance 95 reaches 225 Ω / sq along the radius of the wafer before thermal annealing. On the other hand, the sheet resistance 96 increases from 250 Ω / sq to 425 Ω / sq along the radius of the wafer after thermal annealing. It is clear that the sheet resistance 96 of the wafer after thermal annealing is much higher than the sheet resistance 95 of the wafer before thermal annealing. For example, exposing the InAlN / AlN / GaN heterostructure to high temperatures during thermal annealing leads to a decrease in its sheet resistance. Furthermore, it can be seen from Figure 1B that the decrease in the sheet resistance 96 of the InAlN / AlN / GaN heterostructure after thermal annealing is more pronounced near the edges 94 of the wafer than near the center 93 of the wafer.

[0007] Hall measurements performed on the wafers examined in Figures 1A and 1B indicate that the decrease in the amount of electrons at 2DEG during thermal annealing of the wafer is not due to the amount of electrons. The Hall measurements show a clear decrease in electron mobility that is inversely proportional to the increase in sheet resistance. This decrease in mobility can be explained by a decrease in the steepness and compositional uniformity of the spacer layer.

[0008] [overview] Therefore, the embodiments of the present invention aim to present a semiconductor structure and manufacturing method that do not exhibit the inherent drawbacks of the prior art. More specifically, the object of the embodiments of the present invention is to present a semiconductor structure with improved thermal stability and improved electron mobility, and a method for manufacturing said semiconductor structure.

[0009] The scope of protection required according to various embodiments of the present invention is indicated solely by the independent claims.

[0010] If any embodiments and configurations described herein are not included in the scope of the independent claims, they should be construed as useful examples for understanding various embodiments of the invention.

[0011] There is a need for semiconductor structures for high-power and high-frequency applications. Such semiconductor structures include a lattice-matched barrier layer to GaN and exhibit improved thermal stability and improved electron mobility.

[0012] This objective is achieved by the following semiconductor structure, according to a first exemplary aspect of this disclosure. That is, the semiconductor structure is - circuit board and, - comprising an epitaxial III-N semiconductor layer stack (a stack of semiconductor layers) located on the substrate, The epitaxial III-N semiconductor layer stack is • The first active III-N layer, • A spacer layer located on the first activated III-N layer and containing aluminum nitride, • A diffusion barrier layer located on top of the spacer layer, The device comprises a second active III-N layer located on the diffusion barrier layer, in direct contact with the diffusion barrier layer, and containing indium aluminum nitride. A two-dimensional electron gas is located between the first active III-N layer and the second active III-N layer. The diffusion barrier layer contains gallium nitride, and the thickness of the diffusion barrier layer is less than 1 nm.

[0013] The conventional semiconductor structure includes an epitaxial III-N semiconductor layer stack comprising (i) a first active III-N layer, (ii) a spacer layer located above the first active III-N layer, and (iii) a second active III-N layer located above the spacer layer and containing aluminum indium nitride. In this semiconductor structure, the second active III-N layer containing aluminum indium nitride is located above the first active III-N layer and is in direct contact with the spacer layer, which is under very high tensile strain. Since the indium atoms are larger than the gas atoms or Al atoms contained in the first or second active III-N layer, these indium atoms cause very high local compressive strain in the lattice of the second active III-N layer. During thermal annealing, the indium atoms migrate from the second active III-N layer containing aluminum indium nitride to at least the interior of the spacer layer. In other words, the indium atoms in the second active III-N layer diffuse or migrate toward the first active III-N layer during thermal annealing. This disrupts the compositional uniformity of the spacer layer and smooths, blurs, or softens the interface between the spacer layer and the first active III-N layer.

[0014] The semiconductor structure according to the first aspect of the present invention is suitable for high-frequency applications. For example, a lattice-matched InAlN / GaN heterostructure generates a high-density two-dimensional electron gas without any doping due to the difference in spontaneous polarization at the interface between the InAlN barrier layer and GaN. By using InAlN as a lattice-matched barrier layer to the first active III-N layer, the effects of misfit-induced defects in nitride heterostructure devices are minimized, resulting in a very high sheet carrier density while providing a heteroepitaxial interface with low strain and low defect density. A spacer layer epitaxially grown between the first active III-N layer and the diffusion barrier layer further increases the electron mobility of the semiconductor structure.

[0015] For example, when a semiconductor structure is exposed to high temperatures, such as during thermal annealing, a diffusion barrier layer that epitaxially grows on the spacer layer and on which a second active III-N layer epitaxially grows prevents the diffusion or movement of indium atoms from the second active III-N layer to at least the interior of the spacer layer. Preferably, when a semiconductor structure is exposed to high temperatures, such as during thermal annealing, the diffusion barrier layer prevents the diffusion or movement of indium atoms from the second active III-N layer to the spacer layer and the first active III-N layer. Preferably, when a semiconductor structure is exposed to high temperatures, such as during thermal annealing, the diffusion barrier layer prevents the diffusion or movement of indium atoms from the second active III-N layer to the spacer layer, the first active III-N layer, and the substrate.

[0016] Therefore, compared to a semiconductor structure containing an epitaxial III-N semiconductor layer stack without a diffusion barrier layer grown between the spacer layer and the second active III-N layer, the diffusion barrier layer ensures improved thermal stability, improved electron mobility, and improved sheet resistance within the semiconductor structure. In other words, the diffusion barrier layer according to the first exemplary embodiment of this disclosure allows strain-mediated diffusion of indium atoms into the spacer layer of the semiconductor structure.

[0017] In the context of this disclosure, when the thickness of the diffusion barrier layer is less than 1 nm, the bottom of the conduction band of the diffusion barrier layer does not drop below the Fermi level at the interface with the second active III-N layer. This is because the discontinuity of the conduction band is not large, and the charge induced by the spontaneous polarization of the second active III-N layer is not large. For example, the thickness of the diffusion barrier layer is 1 nm or 0.5 nm. For example, the thickness of the diffusion barrier layer is 0.85 nm. For example, the diffusion barrier layer contains multiple monolayers of gallium nitride. For example, the diffusion barrier layer contains four or fewer monolayers of gallium nitride. By reducing the thickness of the diffusion barrier layer to less than 1 nm, the number of charges inside the diffusion barrier layer is minimized, thus minimizing leakage. When the thickness of the diffusion barrier is reduced to less than 1 nm, alloy scattering may increase as 2DEG is brought closer to the second active III-N layer. Therefore, the technical problem that can be solved by the semiconductor structure described herein may be minimizing leakage in a semiconductor structure having a second active III-N layer containing aluminum indium nitride.

[0018] According to the semiconductor structure of this disclosure, there is no layer formed along the depth direction of the semiconductor structure between the diffusion barrier layer and the second active III-N layer. According to the diffusion barrier layer of this disclosure, there is no need to increase the amount of physical separation between 2DEG and the second active III-N layer.

[0019] In the context of this disclosure, mole fraction (or molar fraction) is defined as the unit obtained by dividing the amount of an element expressed in moles by the total amount of all elements in a mixture expressed in moles. According to a first exemplary aspect of this disclosure, the diffusion barrier layer has an aluminum mole fraction of less than 0.20 (e.g., 0.19, 0.18, 0.17, 0.16, 0.15, 0.14, 0.13, 0.12, 0.11, 0.10, etc.). In other words, the aluminum content of the diffusion barrier layer is in the range of 0% to 20%. The aluminum content in a layer is defined as the ratio of the number of aluminum atoms in that layer to the total number of all group III atoms in that layer. According to a first exemplary aspect of this disclosure, the diffusion barrier layer does not contain indium.

[0020] In the context of this disclosure, for example, the second active III-N layer is an electron-induced barrier layer. The second active III-N layer contains, for example, indium aluminum nitride having an indium mole fraction of less than 0.22. In the context of this disclosure, for example, the second active III-N layer is an electron-induced barrier layer and contains, for example, indium aluminum nitride having an indium mole fraction of 0.17 or 0.18. The second active III-N layer having an indium mole fraction of 0.17 and an aluminum mole fraction of 0.83 is lattice-matched to GaN, for example. Preferably, the second active III-N layer is an electron-induced barrier layer and contains indium aluminum nitride having an indium mole fraction in the range of, for example, 0.14 to 0.22. In an exemplary embodiment, if the indium aluminum nitride of the second active III-N layer has an indium mole fraction of 0.20, the indium aluminum nitride has an aluminum mole fraction of 0.80. In another exemplary embodiment, if the indium aluminum nitride of the second active III-N layer has an indium mole fraction of 0.14, then the indium aluminum nitride has an aluminum mole fraction of 0.86. In other words, the indium aluminum nitride of the second active III-N layer has an aluminum mole fraction in the range of, for example, 0.80 to 0.86. In this case, the second active III-N layer is compressible relative to the first active III-N layer. On the other hand, the first active III-N layer has an indium mole fraction of 0.20 or 0.21 and is tensile. Alternatively, the second active III-N layer is an electron induction barrier layer and contains indium aluminum gallium nitride. In this case, for example, the gallium mole fraction can take values ​​up to 0.20.

[0021] An epitaxial III-N semiconductor layer stack includes an epitaxial active layer. This epitaxial active layer comprises (i) a first active III-N layer, (ii) a spacer layer, (ii) a diffusion barrier layer, and a second active III-N layer. The epitaxial active layer is formed in situ within an organometallic chemical vapor deposition (MOCVD) epitaxial chamber. This is also known as MOVPE. Alternatively, the epitaxial active layer is formed in situ within an organometallic vapor phase (MOVPE) epitaxial chamber. Alternatively, the epitaxial active layer is formed in situ within a molecular beam (MBE) epitaxial chamber. Alternatively, the epitaxial active layer is formed in situ within a chemical beam (CBE) epitaxial chamber.

[0022] The semiconductor structure may be formed by epitaxial growth using metal-organic chemical vapor deposition (MOCVD) or metal-organic vapor phase epitaxy (MOVPE). Alternatively, the semiconductor structure may be formed by molecular beam epitaxy (MBE) or chemical beam epitaxy (CBE). In the MOVPE or MOCVD process, the epitaxial III-N semiconductor layer stack is typically grown epitaxially on a substrate at a pressure of, for example, 5 mBar to 1 Bar and a temperature of, for example, 600°C to 1200°C. The precursor may be (i) ammonia (NH3) for nitrogen, (ii) trimethyl-Ga (TMGa) or triethyl-Ga (TEGa) for gallium, (iii) trimethyl-Al (TMAl) or triethyl-Al (TEAl) for aluminum, (iv) trimethyl-Indium (TMIn) for indium, or (v) silane (SiH4) or disilane (SiH3)2 for silicon. However, the precursor is not limited to these.

[0023] Group III nitrides refer to semiconductor compounds formed by (i) elements of Group III in the periodic table and (ii) nitrogen, also known as N. Examples of Group III elements include boron (also known as B), aluminum (also known as Al), gallium (also known as Ga), and indium (also known as In). Examples of binary Group III nitride compounds include GaN, AlN, and BN. Group III nitrides also refer to ternary and quaternary compounds such as InAlN, AlGaN, and InAlGaN.

[0024] A two-dimensional electron gas is a gas of electrons that are free to move in two dimensions but tightly confined in a first dimension. This tight confinement results in quantized energy levels (bands) for motion in that direction. The electrons are observed as if they were a 2D sheet embedded in a 3D world. A device of particular interest for high power and / or high frequency applications is the high electron mobility transistor (HEMT), also known as a HEMT. According to the present invention, a passivation stack is formed between an epitaxial III-V semiconductor layer stack and a gate. The passivation stack may be formed only under the gate. The passivation stack may additionally function as a gate dielectric. Alternatively, the passivation stack may be formed on top of the epitaxial III-V semiconductor layer stack. The passivation stack may completely cover the epitaxial III-V semiconductor layer stack. Alternatively, the passivation stack may be formed on top of the epitaxial III-V semiconductor layer stack and may partially cover the surface of the epitaxial III-V semiconductor layer stack. For example, the passivation stack may be formed inside a non-gate region between the source and drain of a high mobility electron transistor according to the present invention. In this case, the passivation stack functions as a passivation and prevents depletion of the underlying 2DEG.

[0025] In a semiconductor structure according to a first exemplary aspect of the present disclosure, a diffusion barrier layer containing GaN reduces the tensile strain component of a spacer layer and thus exhibits a maximum compressive strain.

[0026] According to an exemplary embodiment, the semiconductor structure is growing epitaxially on a wafer. And the sheet resistance value of the semiconductor structure is not different between near the edge of the wafer and near the center of the wafer During and.

[0027] According to an exemplary embodiment, the diffusion barrier layer is a single layer.

[0028] In this case, at the interface with the second active III-N layer, the bottom of the conduction band of the diffusion barrier layer does not drop below the Fermi level. This is because the discontinuity of the conduction band is not large and the charge induced by the spontaneous polarization of the second active III-N layer is not large. Furthermore, the aluminum content of the diffusion barrier layer is constant across the single layer.

[0029] According to an exemplary embodiment, the first active III-N layer contains gallium nitride.

[0030] Preferably, the first active III-N layer grows epitaxially. The first active III-N layer contains pure gallium nitride and preferably contains a single layer of gallium nitride.

[0031] Preferably, the spacer layer grows epitaxially. The spacer layer contains pure aluminum nitride.

[0032] According to an exemplary embodiment, the thickness of the spacer layer is less than 2 nm.

[0033] In this case, the spacer layer is maintained thin enough to minimize the roughness of the spacer layer. By minimizing the roughness, the spacer layer prevents at least the diffusion or migration of indium atoms into the first active III-N layer. In this case, the thermal stability of the semiconductor structure is further improved. In other words, the thinner the spacer layer, the better the thermal stability of the semiconductor structure. Preferably, the thickness of the spacer layer is 0.5 nm to 1.5 nm. More preferably, the thickness of the spacer layer is 0.8 nm to 1 nm.

[0034] The substrate of the semiconductor structure according to the first exemplary embodiment of this disclosure comprises one or more of Si, silicon-on-insulator, silicon carbide, and sapphire. In this case, the manufacturing of the semiconductor structure according to the first exemplary embodiment of this disclosure is compatible with existing manufacturing techniques developed for complementary metal-oxide-semiconductor technologies and processes. In other words, the manufacturing of the semiconductor structure has CMOS compatibility by current means, and current process steps can be integrated without requiring significant additional effort. This reduces the complexity and cost associated with the manufacturing of the semiconductor structure described above. Preferably, the substrate is <111> These include Si substrates such as Si substrates, and combinations thereof. These substrates include initial layers such as stacked layers. Alternatively, semiconductor substrates may include germanium, also known as Ge, or germanium-on-insulators (Ge-On-Insulators). Alternatively, semiconductor substrates may include free-standing GaN substrates and free-standing AlN substrates.

[0035] Alternatively, the epitaxial III-N semiconductor layer stack comprises an epitaxially grown buffer layer grown between the substrate and the first active III-N layer. The buffer layer may have different properties from the substrate. For example, the band gap of the substrate and the band gap of the buffer layer are relatively far apart (e.g., 1.1 eV and 6.2 eV, respectively). In this case, the buffer layer has a high band gap. This can result in the current properties such as a high breakdown voltage. The breakdown voltage may be, for example, higher than 250 V, preferably higher than 500 V, more preferably higher than 1000 V (e.g., higher than 2000 V), or even much higher. As an example, the buffer layer is a III-V buffer layer having a high band gap. In this specification, III refers to group III elements. Group III elements are group 13 and group 3 elements. These elements include, for example, B, Al, Ga, In, Tl, Sc, Y, the lanthanide series, and the actinide series. In this specification, V refers to group V elements. Group V elements are group N elements such as N, P, As, Sb, and Bi. The buffer layer contains a stack of multiple layers. Typically, the first layer in such a stack is a nucleating layer.

[0036] Alternatively, the semiconductor structure further comprises a silicon-based wafer, in which case the buffer layer stack is isolated from the silicon-based wafer by an AlN nucleation layer that is in direct contact with the silicon-based wafer and the buffer layer. Alternatively, the total thickness of the nucleation layer is in the range of 10 nm to 200 nm. According to a preferred embodiment, the buffer layer stack has an upper buffer layer and a lower buffer layer. In this case, the lower buffer layer is in direct contact with the AlN nucleation layer, and the upper buffer layer is in direct contact with the active layer. According to a preferred embodiment, the total thickness of the buffer layer stack is in the range of 500 nm to 10 μm. Preferably, all layers of the buffer layer stack are (In)AlGaN layers.

[0037] According to an exemplary embodiment, the semiconductor structure further comprises a passivation layer located on top of the second active III-N layer.

[0038] The passivation layer is formed in situ along with the formation of the epitaxial III-N semiconductor layer stack. In this case, a fully crystalline passivation layer (a completely crystalline passivation layer) is epitaxially grown on the epitaxial III-N semiconductor layer stack. Alternatively, a partially crystalline passivation layer (a partially crystalline passivation layer) is epitaxially grown on the epitaxial III-N semiconductor layer stack. The passivation layer may be formed by ex-situ deposition with the assistance of epitaxy tools such as atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD). Alternatively, the passivation layer may be formed by in-situ deposition in an MOCVD or MBE chamber. Alternatively, a passivation layer may be formed by depositing an amorphous film of the same material and recrystallizing the amorphous film using thermal annealing. The passivation layer located on the second active III-N layer contains, for example, gallium nitride. Alternatively, the passivation layer located on the second active III-N layer contains gallium nitride and silicon nitride.

[0039] According to an exemplary embodiment, the passivation layer includes a silicon nitride and / or oxide layer.

[0040] In this case, the passivation layer of the semiconductor structure according to the first exemplary embodiment of the present disclosure comprises a layer of silicon nitride and / or oxide that functions as a passivation layer. The oxide layer exhibits (i) an electrically clean interface to the second active III-N layer and (ii) a high dielectric constant to maximize the electrostatic coupling between the electrical contacts formed on the semiconductor structure and 2DEG. This results in, for example, an increase in the transconductance of a high electron-mobility transistor manufactured to have the above semiconductor structure, and provides sufficient thickness to avoid dielectric breakdown and leakage due to quantum tunneling.

[0041] According to an exemplary embodiment, the sheet resistance is , along the radius of the wafer, 225Ω / sq~ 230Ω / sq It is within the range.

[0042] According to exemplary embodiments, a high electron-mobility transistor is provided which has a semiconductor structure according to an exemplary first embodiment of the present invention. The high electron-mobility transistor is - circuit board and, - comprising an epitaxial III-N semiconductor layer stack located on the substrate, The epitaxial III-N semiconductor layer stack is • The first active III-N layer, • A spacer layer located on the first activated III-N layer and containing aluminum nitride, • A diffusion barrier layer located on top of the spacer layer, The device comprises a second active III-N layer located on the diffusion barrier layer, in direct contact with the diffusion barrier layer, and containing aluminum indium nitride. A two-dimensional electron gas is located between the first active III-N layer and the second active III-N layer. The diffusion barrier layer contains gallium nitride, and the thickness of the diffusion barrier layer is less than 1 nm. The high electron mobility transistor further comprises a gate contact that is in direct contact with the second active III-N layer in the gate region.

[0043] In the context of this disclosure, when the thickness of the diffusion barrier layer is less than 1 nm, the bottom of the conduction band of the diffusion barrier layer does not drop below the Fermi level at the interface with the second active III-N layer. This is because the discontinuity of the conduction band is not large, and the charge induced by the spontaneous polarization of the second active III-N layer is not large. For example, the thickness of the diffusion barrier layer is 1 nm or 0.5 nm. For example, the thickness of the diffusion barrier layer is 0.85 nm. For example, the diffusion barrier layer contains multiple monolayers of gallium nitride. For example, the diffusion barrier layer contains four or fewer monolayers of gallium nitride. By reducing the thickness of the diffusion barrier layer to less than 1 nm, the number of charges inside the diffusion barrier layer is minimized, and leakage is minimized. When the thickness of the diffusion barrier layer is reduced to less than 1 nm, alloy scattering may increase as the 2DEG approaches the second active III-N layer more closely. Therefore, a technical challenge that can be solved by the high electron mobility transistor according to this disclosure may be minimizing leakage in a high electron mobility transistor having a second active III-N layer containing aluminum indium nitride.

[0044] According to the high electron mobility transistor of this disclosure, there is no layer formed along the depth direction of the semiconductor structure between the diffusion barrier layer and the second active III-N layer. With the diffusion barrier layer of this disclosure, there is no need to increase the amount of physical isolation between 2DEG and the second active III-N layer.

[0045] A gate electrode is provided inside the gate region, forming a high-electron-mobility transistor. The gate electrode is in direct contact with the second active III-N layer within the gate region. In other words, no other layers are formed between the gate contact and the second active III-N layer, along the direction of the depth of the semiconductor structure. The formation of the gate electrode inside the gate region involves several steps. For example, these steps include (i) depositing a photoresist and (ii) performing a lithography step to define the foot of the gate contact by partially removing, for example, a passivation layer, if one is present. In this way, some of the passivation layers remain below the gate of the high-electron-mobility transistor, forming a gate dielectric to reduce trapping effects and leakage current. For example, the gate electrode is a metal-oxide-semiconductor gate, also known as a MOS gate. For example, the gate electrode may be created by depositing a metal stack. The metal stack (i) contains Ni, Pt, W, WN, or TiN, and (ii) is capped with Al, Au, or Cu. The metal pattern is defined continuously by lifting off the metal on top of the photoresist. Alternatively, for example, the gate metal stack is deposited to contain (i) Ni, Pt, W, WN, or TiN, and (ii) is capped with Al, Au, or Cu. The photoresist step and lithography step are then performed. The thus defined photoresist pattern acts as a mask against dry etching in areas where dry etching of the metal stack is undesirable. The photoresist is then removed.

[0046] According to an exemplary embodiment, the second active III-N layer includes recesses that extend within the gate region so as to partially penetrate the second active III-N layer.

[0047] The recess of the second active III-N layer within the gate region allows the gate contact to be brought closer to 2DEG, thereby improving the electron depletion effect from 2DEG when the gate is biased. In the high electron mobility transistor according to this disclosure, it is not necessary to completely remove the second active III-N layer within the gate region to form the gate, nor is it necessary to partially remove the diffusion barrier layer within the gate region. In other words, the gate contact within the gate region is not in direct contact with the diffusion barrier layer.

[0048] According to an exemplary embodiment, a high electron mobility transistor is - Source contacts in the source region that are in contact with the second active III-N layer, and / or -Drain contacts in the drain region that are in contact with the second active III-N layer, It also has the following features.

[0049] For example, ohmic contacts are formed in the source region and / or drain region, respectively. The source and drain contacts are ohmic contacts to 2DEG. The source and drain contacts may be created by depositing metal stacks such as (i)Ti / Al / Ni / Au, (ii)Ti / Al / Mo / Au, (iii)Ti / Al / Ti / Au, (iv)Ti / Al / Ti / W, (v)Ti / Al / W, (vi)Ti / Al / W / Cr, (vii)Ta / Al / Ta, (viii)V / Al / Ni / Au in contact with a second active III-N layer. The second active III-N layer may be recessed prior to metal deposition. Contact properties can be further improved by thermal annealing in a nitrogen atmosphere or a foaming gas atmosphere at temperatures typically in the range of 800°C to 900°C (e.g., 850°C). Alternatively, additional metal interconnection layers are defined using methods known to those skilled in the art. This enables low-resistance current paths for gate, source, and drain currents. If a passivation layer is present, it is preferably etched away in the source and drain regions. In other words, by etching away the passivation layer in the source and drain regions, the second active III-N layer can be exposed in the source and drain regions. According to an alternative embodiment, the second active III-N layer is partially etched by wet etching, for example, in an alkaline solution or a resist developer. In this case, it is possible to partially form ohmic contacts in the second active III-N layer in the source and drain regions. Once the regions of ohmic contacts are defined (i.e., the source and drain regions are defined), a metal layer or a stack of metal layers may be deposited, for example, by thermal deposition, sputtering, or electron beam deposition. The metal pattern is continuously defined by performing a lift-off of metals that are located on the photoresist and not in contact with the second active III-N layer.Alternatively, the photoresist is first removed, and then a metal stack containing, for example, Ti and Al is deposited. Subsequently, a second photoresist deposition step and a photolithography step are performed. This enables dry etching of the metal stack in areas where the metal stack is not desired, thereby removing the photoresist.

[0050] According to a second exemplary embodiment, a method for manufacturing a semiconductor structure is provided. This method is - Steps include setting up the substrate, - The step of providing an epitaxial III-N semiconductor layer stack on the substrate, The step of providing the epitaxial III-N semiconductor layer stack is, • The step of providing the first active III-N layer, The step of providing a spacer layer containing aluminum nitride on the first activated III-N layer, The step of providing a diffusion barrier layer containing gallium nitride and having a thickness of less than 1 nm on the spacer layer, The step of providing a second active III-N layer on the diffusion barrier layer, which is in direct contact with the diffusion barrier layer and contains aluminum indium nitride, By including, A two-dimensional electron gas is formed between the first active III-N layer and the second active III-N layer.

[0051] A method for manufacturing a semiconductor structure according to a second aspect of this disclosure is suitable for manufacturing devices for high-power and high-frequency applications. For example, by manufacturing a device containing a lattice-matched InAlN / GaN heterostructure, a high-density two-dimensional electron gas can be generated without any doping due to the difference in spontaneous polarization at the interface between the InAlN barrier layer and GaN. By using InAlN as a lattice-matched barrier layer to the first active III-N layer, the effects of misfit-induced defects in nitride heterostructure devices can be minimized, resulting in a very high sheet carrier density while providing a heteroepitaxial interface with low strain and low defect density. A spacer layer epitaxially grown between the first active III-N layer and the diffusion barrier layer further increases the electron mobility of the semiconductor structure.

[0052] For example, when a semiconductor structure is exposed to high temperatures, such as during thermal annealing, a diffusion barrier layer that epitaxially grows on the spacer layer and on which a second active III-N layer epitaxially grows prevents the diffusion or migration of indium atoms from the second active III-N layer to at least the spacer layer. Preferably, when a semiconductor structure is exposed to high temperatures, such as during thermal annealing, the diffusion barrier layer prevents the diffusion or migration of indium atoms from the second active III-N layer to the spacer layer and the first active III-N layer. Preferably, when a semiconductor structure is exposed to high temperatures, such as during thermal annealing, the diffusion barrier layer prevents the diffusion or migration of indium atoms from the second active III-N layer to the spacer layer, the first active III-N layer, and the substrate.

[0053] Therefore, compared to a semiconductor structure having an epitaxial III-N semiconductor layer stack without a diffusion barrier layer grown between the spacer layer and the second active III-N layer, the diffusion barrier layer ensures improved thermal stability, improved electron mobility, and improved sheet resistance within the semiconductor structure. In other words, the diffusion barrier layer according to the first exemplary embodiment of this disclosure allows strain-mediated diffusion of indium atoms into the spacer layer of the semiconductor structure.

[0054] Preferably, providing a first activated III-N layer corresponds to growing a monolayer of pure gallium nitride. Preferably, providing a spacer layer on top of the first activated III-N layer corresponds to growing a monolayer of pure aluminum nitride.

[0055] According to an exemplary embodiment, the manufacturing of the semiconductor structure corresponds to epitaxial growth of the semiconductor structure on a wafer. The method further includes the step of thermal annealing the semiconductor structure.

[0056] According to an exemplary embodiment, thermal annealing of the semiconductor structure corresponds to thermal annealing of the semiconductor structure at 750°C.

[0057] According to exemplary embodiments, a method for manufacturing a high electron-mobility transistor is provided. This method is - Steps include setting up the substrate, - The step of providing an epitaxial III-N semiconductor layer stack on the substrate, The step of providing the epitaxial III-N semiconductor layer stack is, • The step of providing the first active III-N layer, The step of providing a spacer layer containing aluminum nitride on the first activated III-N layer, The step of providing a diffusion barrier layer containing gallium nitride and having a thickness of less than 1 nm on the spacer layer, The step of providing a second active III-N layer on the diffusion barrier layer, which is in direct contact with the diffusion barrier layer and contains aluminum indium nitride, By including, A two-dimensional electron gas is formed between the first active III-N layer and the second active III-N layer. The aforementioned method, - The step includes providing a gate contact that directly contacts the second active III-N layer in the gate region.

[0058] According to an exemplary embodiment, a surface temperature in the range of 725°C to 825°C is used to provide a diffusion barrier layer on top of the spacer layer.

[0059] In this case, according to the method for manufacturing a semiconductor structure according to a second exemplary embodiment of the present disclosure, there is no growth interruption between the growth of the diffusion barrier layer and the growth of the second active III-N layer. In other words, both the diffusion barrier layer and the second active III-N layer are grown under the same process conditions. The growth of the diffusion barrier layer is carried out such that the temperature of the actual growth surface of the diffusion barrier layer formed on the spacer is in the range of 725 to 825°C. In other words, the surface temperature of the spacer layer before growing the diffusion barrier layer is in the range of 725 to 825°C. And, during the period in which the diffusion barrier layer is grown on the spacer layer, the temperature of the growth surface of the diffusion barrier layer opposite to the surface in contact with the spacer layer is in the range of 725 to 825°C. Alternatively, the diffusion barrier layer is grown on the spacer layer at a temperature higher than 825°C. In the essence of the present disclosure, the spacer layer may be grown at a temperature lower than 800°C. Or, the spacer layer may be grown at a temperature higher than 800°C.

[0060] [Brief description of the drawing] Several exemplary embodiments are described below with reference to the accompanying drawings.

[0061] Figure 1 shows an exemplary embodiment of the measurement of the sheet resistance of a semiconductor structure according to the prior art.

[0062] Figure 2 shows an exemplary embodiment of the semiconductor structure according to this disclosure.

[0063] Figure 3 shows an exemplary embodiment for measuring the sheet resistance of a semiconductor structure according to this disclosure.

[0064] Figure 4 shows an exemplary embodiment of a method for manufacturing a semiconductor structure according to the present disclosure.

[0065] Figure 5 shows an exemplary embodiment of a high electron mobility transistor according to the present disclosure.

[0066] Figure 6 shows an exemplary embodiment of a high electron mobility transistor according to the present disclosure.

[0067] Figure 7 shows an exemplary embodiment of a high electron mobility transistor according to the present disclosure, wherein the second active III-N layer includes a recess that extends in the gate region so as to partially penetrate the second active III-N layer.

[0068] Figure 8 shows an exemplary embodiment of a high electron mobility transistor according to the present disclosure, in which the second active III-N layer includes a recess that extends in the gate region so as to partially penetrate the second active III-N layer.

[0069] [Detailed description of one or more embodiments] Figures 1A and 1B illustrate exemplary embodiments for measuring the sheet resistance of a prior art semiconductor structure. Figures 1A and 1B show the change in sheet resistance 91 of a wafer undergoing epitaxial growth of an InAlN / AlN / GaN heterostructure as a function of the rounded radius 92 from the center 93 of the wafer. Therefore, in both Figures 1A and 1B, point 93 corresponds to the center of the wafer, and point 94 corresponds to the edge of the wafer. Figure 1A shows the sheet resistance 95 of the wafer before thermal annealing. Figure 1B, on the other hand, shows the sheet resistance 96 of the wafer after thermal annealing, for example, when the wafer is annealed at 750°C for 30 minutes. The sheet resistance 95 reaches 225 Ω / sq along the radius of the wafer before thermal annealing. Meanwhile, the sheet resistance 96 increases from 250 Ω / sq to 425 Ω / sq along the radius of the wafer after thermal annealing. It is clear that the sheet resistance 96 of the wafer after thermal annealing is much higher than the sheet resistance 95 of the wafer before thermal annealing. For example, exposing the InAlN / AlN / GaN heterostructure to high temperatures during thermal annealing leads to a decrease in its sheet resistance. Furthermore, it can be seen from Figure 1B that the decrease in the sheet resistance 96 of the InAlN / AlN / GaN heterostructure after thermal annealing is more pronounced near the edges 94 of the wafer than near the center 93 of the wafer.

[0070] Figure 2 shows an exemplary embodiment of semiconductor structure 1 according to the present disclosure. Semiconductor structure 1 comprises a substrate 100 and an epitaxial III-N semiconductor layer stack 200 located on the substrate 100. In an alternative embodiment, the epitaxial III-N semiconductor layer stack comprises an epitaxial growth buffer layer grown between the substrate and a first active III-N layer. The epitaxial III-N semiconductor layer stack 200 comprises (i) a first active III-N layer 201, (ii) a spacer layer 202 grown on the first active III-N layer 201, (iii) a diffusion barrier layer 203 grown on the space layer 202, and (iv) a second active III-N layer 204 grown on the diffusion barrier layer 203. The second active III-N layer 204 contains aluminum indium nitride. A two-dimensional electron gas 20 is formed between the first active III-N layer 201 and the second active III-N layer 204. The diffusion barrier layer 203 contains gallium nitride. The thickness of the diffusion barrier layer 203 is less than 1 nm. Optionally, the diffusion barrier layer 203 is a single layer. According to any exemplary embodiment, the first active III-N layer 201 contains gallium nitride. The spacer layer 202 contains aluminum nitride. According to any exemplary embodiment, the thickness of the spacer layer 202 is less than 2 nm. According to any exemplary embodiment, the semiconductor structure 1 further comprises a passivation layer 300 formed on the second active III-N structure 204. According to any exemplary embodiment, the passivation layer 300 contains a layer of silicon nitride and / or oxide. According to another embodiment, the passivation layer 300 contains gallium nitride. According to a further alternative embodiment, the passivation layer 300 contains gallium nitride and silicon nitride. The second active III-N layer 204 is formed on the diffusion barrier layer 203 and is in direct contact with the diffusion barrier layer 203.

[0071] Figures 3A and 3B illustrate exemplary embodiments for measuring the sheet resistance of the semiconductor structure 1 according to the present disclosure. Figures 3A and 3B show the change in sheet resistance 91 of a wafer on which the InAlN / AlN / GaN heterostructure 1 according to the present disclosure is epitaxially grown, as a function of the radius 92, rounded down from the center 93 of the wafer. Thus, in both Figures 3A and 3B, point 93 corresponds to the center of the wafer, and point 94 corresponds to the edge of the wafer. Figure 3A shows the sheet resistance 97 of the semiconductor structure 1 according to the present disclosure after growth of the semiconductor structure 1 and before thermal annealing of the wafer. On the other hand, Figure 3B shows the sheet resistance 97 of the semiconductor structure 1 according to the present disclosure after annealing, for example, at 750°C for 30 minutes. The sheet resistance 97 is in the range of 225 Ω / sq to 230 Ω / sq along the radius of the wafer before thermal annealing. The sheet resistance 98 is also in the range of 225 Ω / sq to 230 Ω / sq along the radius of the wafer after thermal annealing. It is clear that the sheet resistance of the wafer 98 after the growth of the semiconductor structure 1 according to this disclosure does not change after thermal annealing compared to before thermal annealing. In other words, for example, exposing the semiconductor structure 1 according to this disclosure to a high temperature for a certain period of time during thermal annealing does not cause a decrease in the sheet resistance of the semiconductor structure. In addition, it can be seen from Figure 3B that there is no difference in the value of the sheet resistance 98 of the semiconductor structure 1 according to this disclosure after thermal annealing between the wafer edge 94 and the vicinity of the center 93 of the wafer.

[0072] Figure 4 shows an exemplary embodiment of a method for manufacturing a semiconductor structure according to the present disclosure. The method includes providing a substrate 100 in a first main step 901. The method includes providing an epitaxial III-N semiconductor layer stack 200 on the substrate 100 in a second main step 902 following the first step 901. The step of providing the epitaxial III-N semiconductor layer stack 200 on the substrate 100 includes a first step 903 providing a first active III-N layer 201. The step of providing the epitaxial III-N semiconductor layer stack 200 on the substrate 100 further includes a second step 904 following the first step 903. The second step 904 includes providing a spacer layer 202 on the first active III-N layer 201. The spacer layer 202 contains aluminum nitride. The steps of the method for providing an epitaxial III-N semiconductor layer stack 200 on a substrate 100 further include a third step 905 following the second step 904. The third step 905 includes providing a diffusion barrier layer 203 on a spacer layer 202. The diffusion barrier layer 203 contains gallium nitride. The thickness of the diffusion barrier layer 203 is less than 1 nm. The steps of the method for providing an epitaxial III-N semiconductor layer stack 200 on a substrate 100 further include a fourth step 906 following the third step 905. The fourth step 906 includes providing a second active III-N layer 204 on the diffusion barrier layer 203 so as to be in direct contact with the diffusion barrier layer 203. The second active III-N layer 204 contains aluminum indium nitride. In this case, a two-dimensional electron gas 20 can be formed between the first active III-N layer 201 and the second active III-N layer 204. According to any exemplary embodiment, a surface temperature in the range of 725°C to 825°C is used for the step of the method of providing a diffusion barrier layer 203 on top of a spacer layer. According to a further exemplary embodiment, the method further includes the step of providing a gate contact 401 that is in direct contact with the second active III-N layer 204 in the gate region 400.

[0073] Figure 5 shows an exemplary embodiment of a high electron mobility transistor 2 according to the present disclosure. The high electron mobility transistor 2 comprises a substrate 100 and an epitaxial III-N semiconductor layer stack 200 located on the substrate 100. According to an alternative embodiment, the epitaxial III-N semiconductor layer stack comprises an epitaxial growth buffer layer grown between the substrate and a first active III-N layer. The epitaxial III-N semiconductor layer stack 200 comprises (i) a first active III-N layer 201, (ii) a spacer layer 202 grown on the first active III-N layer 201, (iii) a diffusion barrier layer 203 grown on the spacer layer 202, and (iv) a second active III-N layer 204 grown on the diffusion barrier layer 203. The second active III-N layer 204 contains aluminum indium nitride. A two-dimensional electron gas 20 is formed between the first active III-N layer 201 and the second active III-N layer 204. The diffusion barrier layer 203 contains gallium nitride. The thickness of the diffusion barrier layer 203 is less than 1 nm. Optionally, the diffusion barrier layer 203 is a single layer. According to any exemplary embodiment, the first active III-N layer 201 contains gallium nitride. The spacer layer 202 contains aluminum nitride. According to any exemplary embodiment, the thickness of the spacer layer 202 is less than 2 nm. According to any exemplary embodiment, the semiconductor structure 1 further comprises a passivation layer 300 formed on the second active III-N structure 204. According to any exemplary embodiment, the passivation layer 300 contains a layer of silicon nitride and / or oxide. According to another embodiment, the passivation layer 300 contains gallium nitride. According to a further alternative embodiment, the passivation layer 300 contains gallium nitride and silicon nitride. The second active III-N layer 204 is formed on the diffusion barrier layer 203 and in direct contact with the diffusion barrier layer 203. The high electron mobility transistor 2 further includes a gate contact 401 that is in direct contact with the second active III-N layer 204 in the gate region 400.

[0074] Figure 6 shows an exemplary embodiment of a high electron mobility transistor 2 according to the present disclosure. The high electron mobility transistor 2 comprises a substrate 100 and an epitaxial III-N semiconductor layer stack 200 located on the substrate 100. According to an alternative embodiment, the epitaxial III-N semiconductor layer stack comprises an epitaxial growth buffer layer grown between the substrate and a first active III-N layer. The epitaxial III-N semiconductor layer stack 200 comprises (i) a first active III-N layer 201, (ii) a spacer layer 202 grown on the first active III-N layer 201, (iii) a diffusion barrier layer grown on the spacer layer 202, and (iv) a second active III-N layer 204 grown on the diffusion barrier layer 203. The second active III-N layer 204 contains aluminum indium nitride. A two-dimensional electron gas 20 is formed between the first active III-N layer 201 and the second active III-N layer 204. The diffusion barrier layer 203 contains gallium nitride. The thickness of the diffusion barrier layer 203 is less than 1 nm. Optionally, the diffusion barrier layer 203 is a single layer. According to any exemplary embodiment, the first active III-N layer 201 contains gallium nitride. The spacer layer 202 contains aluminum nitride. According to any exemplary embodiment, the thickness of the spacer layer 202 is less than 2 nm. According to any exemplary embodiment, the semiconductor structure 1 further comprises a passivation layer 300 formed on the second active III-N structure 204. According to any exemplary embodiment, the passivation layer 300 contains a layer of silicon nitride and / or oxide. According to an alternative embodiment, the passivation layer 300 contains gallium nitride. According to a further alternative embodiment, the passivation layer 300 contains gallium nitride and silicon nitride. The second active III-N layer 204 is formed on the diffusion barrier layer 203 and in direct contact with the diffusion barrier layer 203. The high electron mobility transistor 2 further includes a gate contact 401 that is in direct contact with the second active III-N layer 204 in the gate region 400.The high electron mobility transistor 2 further comprises (i) a source contact 403 in contact with the second active III-N layer 204 in the source region 43, and / or (ii) a drain contact 404 in contact with the second active III-N layer 204 in the drain region 44.

[0075] Figure 7 shows an exemplary embodiment of a high electron mobility transistor 2 according to the present disclosure. The high electron mobility transistor 2 comprises a substrate 100 and an epitaxial III-N semiconductor layer stack 200 located on the substrate 100. According to an alternative embodiment, the epitaxial III-N semiconductor layer stack comprises an epitaxial growth buffer layer grown between the substrate and a first active III-N layer. The epitaxial III-N semiconductor layer stack 200 comprises (i) a first active III-N layer 201, (ii) a spacer layer 202 grown on the first active III-N layer 201, (iii) a diffusion barrier layer grown on the spacer layer 202, and (iv) a second active III-N layer 204 grown on the diffusion barrier layer 203. The second active III-N layer 204 contains aluminum indium nitride. A two-dimensional electron gas 20 is formed between the first active III-N layer 201 and the second active III-N layer 204. The diffusion barrier layer 203 contains gallium nitride. The thickness of the diffusion barrier layer 203 is less than 1 nm. Optionally, the diffusion barrier layer 203 is a single layer. According to any exemplary embodiment, the first active III-N layer 201 contains gallium nitride. The spacer layer 202 contains aluminum nitride. According to any exemplary embodiment, the thickness of the spacer layer 202 is less than 2 nm. According to any exemplary embodiment, the semiconductor structure 1 further comprises a passivation layer 300 formed on the second active III-N structure 204. According to any exemplary embodiment, the passivation layer 300 contains a layer of silicon nitride and / or oxide. According to another embodiment, the passivation layer 300 contains gallium nitride. According to a further alternative embodiment, the passivation layer 300 contains gallium nitride and silicon nitride. The second active III-N layer 204 is formed on the diffusion barrier layer 203 and in direct contact with the diffusion barrier layer 203. The second active III-N layer 204 includes a recess 402 that extends in the gate region 400 so as to partially penetrate the second active III-N layer 204.The high electron mobility transistor 2 further includes a gate contact 401 that is in direct contact with the second active III-N layer 204 in the gate region 400.

[0076] Figure 8 shows an exemplary embodiment of a high electron mobility transistor 2 according to the present disclosure. The high electron mobility transistor 2 comprises a substrate 100 and an epitaxial III-N semiconductor layer stack 200 located on the substrate 100. According to an alternative embodiment, the epitaxial III-N semiconductor layer stack comprises an epitaxial growth buffer layer grown between the substrate and a first active III-N layer. The epitaxial III-N semiconductor layer stack 200 comprises (i) a first active III-N layer 201, (ii) a spacer layer 202 grown on the first active III-N layer 201, (iii) a diffusion barrier layer grown on the spacer layer 202, and (iv) a second active III-N layer 204 grown on the diffusion barrier layer 203. The second active III-N layer 204 contains aluminum indium nitride. A two-dimensional electron gas 20 is formed between the first active III-N layer 201 and the second active III-N layer 204. The diffusion barrier layer 203 contains gallium nitride. The thickness of the diffusion barrier layer 203 is less than 1 nm. Optionally, the diffusion barrier layer 203 is a single layer. According to any exemplary embodiment, the first active III-N layer 201 contains gallium nitride. The spacer layer 202 contains aluminum nitride. According to any exemplary embodiment, the thickness of the spacer layer 202 is less than 2 nm. According to any exemplary embodiment, the semiconductor structure 1 further comprises a passivation layer 300 formed on the second active III-N structure 204. According to any exemplary embodiment, the passivation layer 300 contains a layer of silicon nitride and / or oxide. According to another embodiment, the passivation layer 300 contains gallium nitride. According to a further alternative embodiment, the passivation layer 300 contains gallium nitride and silicon nitride. The second active III-N layer 204 is formed on the diffusion barrier layer 203 and in direct contact with the diffusion barrier layer 203. The second active III-N layer 204 includes a recess 402 that extends in the gate region 400 so as to partially penetrate the second active III-N layer 204.The high electron mobility transistor 2 further comprises a gate contact 401 that is in direct contact with the second active III-N layer 204 in the gate region 400. The high electron mobility transistor 2 further comprises (i) a source contact 403 that is in contact with the second active III-N layer 204 in the source region 43, and / or (ii) a drain contact 404 that is in contact with the second active III-N layer 204 in the drain region 44.

[0077] As described above, the present invention has been explained with reference to specific embodiments, but it will be apparent to those skilled in the art that the present invention should not be limited to the details of the exemplary embodiments described above, and that the present invention may be embodied with various changes and modifications without departing from the scope of the invention. Accordingly, these embodiments should be considered in all respects to be illustrative and not limiting. The scope of the present invention is not indicated by the above description but by the appended claims. Accordingly, all changes included in the claims are intended to be included within the scope of the invention.

[0078] Furthermore, readers of this patent application will understand that (i) the words “comprising” or “comprise” do not preclude other elements or steps, (ii) the words “a” or “an” do not preclude plural, and (iii) a single element, such as a computer system, processor, or another integrated unit, may perform the functions of multiple means described in the claims. No reference numeral in the claims should be construed as limiting the respective claims relating thereto. Terms such as “first,” “second,” “third,” “a,” “b,” and “c,” when used herein or in the claims, are introduced to distinguish similar elements or steps and do not necessarily represent a sequential or chronological order. Similarly, terms such as “top,” “bottom,” “over,” and “under” are introduced for descriptive purposes and do not necessarily indicate relative positions. It should be understood that the terms used in this manner are interchangeable under appropriate circumstances. Therefore, it should be understood that embodiments of the present invention may be implemented in a different order or orientation from one or more of the above descriptions or illustrations. [Brief explanation of the drawing]

[0079] [Figure 1A] This document illustrates an exemplary embodiment for measuring the sheet resistance of a semiconductor structure according to the prior art. [Figure 1B] This document illustrates an exemplary embodiment for measuring the sheet resistance of a semiconductor structure according to the prior art. [Figure 2] Exemplary embodiments of the semiconductor structure relating to this disclosure are shown. [Figure 3A] This disclosure provides an exemplary embodiment for measuring the sheet resistance of a semiconductor structure. [Figure 3B] This disclosure provides an exemplary embodiment for measuring the sheet resistance of a semiconductor structure. [Figure 4] Exemplary embodiments of a method for manufacturing a semiconductor structure relating to this disclosure are shown. [Figure 5] This disclosure shows exemplary embodiments of high electron mobility transistors. [Figure 6] This disclosure shows exemplary embodiments of high electron mobility transistors. [Figure 7] An exemplary embodiment of a high electron mobility transistor according to this disclosure is shown, wherein the second active III-N layer includes a recess that extends in the gate region so as to partially penetrate the second active III-N layer. [Figure 8] An exemplary embodiment of a high electron mobility transistor according to this disclosure is shown, wherein the second active III-N layer includes a recess that extends in the gate region so as to partially penetrate the second active III-N layer.

Claims

1. Semiconductor structure (1), A substrate (100) and The system comprises an epitaxial III-N semiconductor layer stack (200) located on the substrate (100), The epitaxial III-N semiconductor layer stack (200) is The first active III-N layer (201), Located on the first activated III-N layer (201), and comprising a spacer layer (202) made of aluminum nitride, The gallium nitride layer (203) is located on the spacer layer (202), The material comprises a second active III-N layer (204) made of aluminum indium nitride, located on the gallium nitride layer (203) and in direct contact with the gallium nitride layer (203), A two-dimensional electron gas (20) is located between the first active III-N layer (201) and the second active III-N layer (204), The gallium nitride layer (203) is made of gallium nitride. The thickness of the gallium nitride layer (203) is less than 1 nm. The semiconductor structure (1) is epitaxially grown on a wafer. The semiconductor structure (1) wherein the sheet resistance value of the semiconductor structure (1) is not different between the edge of the wafer and the vicinity of the center of the wafer.

2. The semiconductor structure (1) according to claim 1, wherein the sheet resistance is in the range of 225 Ω / sq to 230 Ω / sq along the radius of the wafer.

3. The semiconductor structure (1) according to claim 1, wherein the gallium nitride layer (203) is a single layer.

4. The semiconductor structure (1) according to claim 1, wherein the first active III-N layer (201) contains gallium nitride.

5. The semiconductor structure (1) according to claim 1, wherein the thickness of the spacer layer (202) is less than 2 nm.

6. The semiconductor structure (1) according to claim 1, further comprising a passivation layer (300) located on the second active III-N layer (204).

7. The semiconductor structure (1) according to claim 6, wherein the passivation layer (300) comprises a layer of silicon nitride and / or oxide.

8. A high electron-mobility transistor (2) comprising the semiconductor structure (1) described in claim 1, The high electron mobility transistor (2) further comprises a gate contact (401) that is in direct contact with the second active III-N layer (204) in the gate region (400).

9. The high electron mobility transistor (2) according to claim 8, wherein the second active III-N layer (204) includes a recess (402) that extends in the gate region (400) so as to partially penetrate the second active III-N layer (204).

10. The aforementioned high electron mobility transistor (2) is Source contact (403) in contact with the second active III-N layer (204) in the source region (43), and / or In the drain region (44), the drain contact (404) is in contact with the second active III-N layer (204), A high electron-mobility transistor (2) according to claim 8 or 9, further comprising the above.

11. A method for manufacturing a semiconductor structure (1), The steps include providing a substrate (100), The method includes the step of providing an epitaxial III-N semiconductor layer stack (200) on the substrate (100), The step of providing the epitaxial III-N semiconductor layer stack (200) is, The step of providing the first active III-N layer (201), The steps include providing a spacer layer (202) made of aluminum nitride on the first activated III-N layer (201), The step of providing a gallium nitride layer (203) made of gallium nitride and having a thickness of less than 1 nm on the spacer layer (202), The step of providing a second active III-N layer (204) made of aluminum indium nitride on the gallium nitride layer (203), which is in direct contact with the gallium nitride layer (203), By including, A two-dimensional electron gas is formed between the first active III-N layer (201) and the second active III-N layer (204). Manufacturing the semiconductor structure (1) corresponds to epitaxially growing the semiconductor structure (1) on a wafer. The method further includes the step of thermal annealing the semiconductor structure (1), A method wherein the sheet resistance value of the semiconductor structure (1) is not different between the edge of the wafer and the vicinity of the center of the wafer.

12. The method according to claim 11, wherein thermal annealing of the semiconductor structure (1) corresponds to thermal annealing of the semiconductor structure (1) at 750°C.

13. A method for manufacturing a high electron mobility transistor (2), The steps include providing a substrate (100), The method includes the step of providing a semiconductor structure (1) by providing an epitaxial III-N semiconductor layer stack (200) on the substrate (100), The step of providing the epitaxial III-N semiconductor layer stack (200) is, The step of providing the first active III-N layer (201), The steps include providing a spacer layer (202) made of aluminum nitride on the first activated III-N layer (201), The step of providing a gallium nitride layer (203) made of gallium nitride and having a thickness of less than 1 nm on the spacer layer (202), The step of providing a second active III-N layer (204) made of aluminum indium nitride on the gallium nitride layer (203), which is in direct contact with the gallium nitride layer (203), By including, A two-dimensional electron gas is formed between the first active III-N layer (201) and the second active III-N layer (204). The aforementioned method, The method includes the step of providing a gate contact (401) in the gate region (400) that directly contacts the second active III-N layer (204), The semiconductor structure (1) corresponds to epitaxial growth of the semiconductor structure (1) on a wafer. A method wherein the sheet resistance value of the semiconductor structure (1) is not different between the edge of the wafer and the vicinity of the center of the wafer.

14. The method according to claim 11 or 13, wherein a surface temperature in the range of 725°C to 825°C is used to provide the gallium nitride layer (203) on the spacer layer (202).

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