Battery management chip and system, and vehicle

Abstract

The vehicle includes a battery management chip and a battery management system. The battery management chip comprises a battery cell data sampling module, a data processing module, a first communication module, and a first power module. The battery cell data sampling module is used to acquire the battery cell data of the battery cell. The data processing module is connected to the battery cell data sampling module and is used to process the battery cell data. The first communication module is connected to the data processing module and is used to send the processed battery cell data to the control module. The first power module is connected to the battery cell and the data processing module, receives the initial voltage output by the battery cell, and is used to perform a boost process on the initial voltage to provide an operating voltage to the data processing module.

Description

Technical Field

[0001] Cross - reference to Related Applications This disclosure claims priority to Chinese Patent Application No. 202210756825.0, titled "BATTERY MANAGEMENT CHIP AND SYSTEM, AND VEHICLE", filed on June 30, 2022, which is hereby incorporated by reference in its entirety.

[0002] This disclosure relates to the field of vehicle technology, and more particularly, to battery management chips and systems, and vehicles.

Background Art

[0003] A battery management system (BMS) mainly acquires the voltage, current, temperature, dynamic internal resistance, and other data of a battery pack, and transmits the data using a conventional wiring harness communication mode to an upper - level control module to realize interactive control of data transmission.

[0004] Currently, battery packs, which consist of multiple battery cells, are monitored by a battery management chip. The high voltage of the battery pack presents significant challenges to the process and safety of the battery management chip. Secondly, the normal operation of the battery management chip requires low voltage, and in order to ensure the consistency of the electrical quantities of all battery cells in the battery pack, it is necessary to obtain power from the total voltage and then obtain a voltage that the chip can use after step-down processing, which increases unnecessary energy loss in the battery cells. In addition, the battery management chip monitors multiple battery cells simultaneously, and there is a risk that if the chip fails during long-term vehicle operation, as a result, cell data of multiple battery cells will be lost, increasing the vehicle's failure rate. Finally, although multiple battery cells are monitored by the management chip, the management chip requires the use of complex sampling wiring harnesses and connectors, which simultaneously complicates the design of the battery management chip's sampling board, leading to a sharp increase in costs on the one hand, and on the other hand, the stability and reliability of the harness connectors increase the vehicle's failure rate. At the same time, the boost circuit of electronic power technology cannot guarantee the normal operation of the chip under a wide range of low voltages. [Overview of the project] [Problems that the invention aims to solve]

[0005] This disclosure aims to solve, at least to some extent, one of the technical problems in the related technology. [Means for solving the problem]

[0006] Therefore, the first object of this disclosure is to propose a battery management chip that provides an operating voltage to a data processing module by arranging a first power module and boosting the initial voltage output by the battery cells, ensuring that the battery management chip can operate over a wide range of low voltages and correspondingly monitors one battery cell through one battery management chip. In the first aspect, the battery management chip does not need to face the high voltage generated by multiple battery cells in series, avoiding unnecessary energy loss by preventing the battery cells from operating under high voltage, thereby reducing the process requirements for chip manufacturing and saving energy consumption. In the second aspect, the risk of chip failure can be reduced, avoiding the loss of data from multiple battery cells in one go and reducing the vehicle failure rate. In the third aspect, the flexibility of the battery management chip can be improved, reducing the use of numerous wiring harnesses and connectors, reducing the complexity of the battery management chip, and improving the stability and reliability of the battery management chip.

[0007] Therefore, a second object of this disclosure is to propose a battery management system.

[0008] Therefore, a third object of this disclosure is to propose a vehicle.

[0009] To achieve the above objectives, embodiments of the first aspect of the present disclosure propose a battery management chip connected to a single battery cell, the battery management chip including a battery cell data sampling module for acquiring battery cell data of the battery cell, a data processing module connected to the battery cell data sampling module and used for processing the battery cell data, a first communication module connected to the data processing module and used for transmitting the processed battery cell data to a control module, and a first power module connected to the battery cell and the data processing module and used for receiving an initial voltage output by the battery cell and performing a boost operation on the initial voltage to provide an operating voltage to the data processing module.

[0010] A battery management chip according to one embodiment of the present disclosure boosts the initial voltage output by a battery cell via a first power module, provides an operating voltage to a data processing module, ensures that the battery management chip can operate over a wide range of low voltages, and monitors one battery cell in correspondence via one battery management chip. In the first embodiment, the battery management chip does not need to face the high voltage generated by multiple battery cells in series, avoiding unnecessary energy loss by preventing the battery cells from operating under high voltage, thereby reducing the process requirements for chip manufacturing and saving energy consumption. In the second embodiment, the risk of chip failure can be reduced, avoiding the loss of data from multiple battery cells in one go, and reducing the vehicle failure rate. In the third embodiment, the flexibility of the battery management chip can be improved, reducing the use of numerous wiring harnesses and connectors, reducing the complexity of the battery management chip, and improving the stability and reliability of the battery management chip.

[0011] In some embodiments, the first power module includes a boost circuit unit connected to a battery cell, which is used to perform a boosting process on the initial voltage output by the battery cell to output an initial target voltage.

[0012] In some embodiments, the first power module further includes an input filtering voltage stabilization circuit unit, the input terminals of which are connected to the voltage output terminals of a battery cell and are used to reduce voltage ripple interference of the initial voltage output by the battery cell and to output a DC voltage.

[0013] In some embodiments, the first power module further includes an output filtering voltage stabilization circuit unit, which is connected to a boost circuit unit and used to perform filtering and voltage stabilization processing on an initial target voltage to obtain a target voltage, output the target voltage, and provide an operating voltage to a data processing module.

[0014] In some embodiments, the first power module further includes a sampling feedback unit, which is connected to an output filtering voltage stabilization circuit unit and a boost circuit unit, respectively, and is used to acquire a target voltage value and to feed back the target voltage value to the boost circuit unit.

[0015] In some embodiments, the boost circuit unit is further configured to receive a target voltage value and adjust the boost action based on the target voltage value, so that the adjusted initial target voltage of the output is filtered and stabilized by an output filtering voltage stabilization circuit unit (132) to output a target voltage within a preset voltage range.

[0016] In some embodiments, the boost circuit unit includes a PWM generation circuit subunit, the first terminal of which is connected to the output terminal of an input filtering voltage stabilization circuit unit, the second terminal of which is grounded, and the third terminal of which is used to output a PWM (pulse width modulation) signal; and a charge pump boost subunit, the first terminal of which is connected to the third terminal of the PWM generation circuit subunit, and which is used to adjust the frequency and duty cycle of the PWM signal in real time until an initial target voltage is obtained.

[0017] In some embodiments, the PWM generation circuit subunit includes an energy storage subunit, one terminal of which is connected to the output terminal of the input filtering voltage stabilization circuit unit and the other terminal of which is grounded; a waveform generation subunit, the first terminal of which is connected to the output terminal of the input filtering voltage stabilization circuit unit and the second terminal of which is grounded; a voltage follower circuit, the first terminal of which is connected to the output terminal of the input filtering voltage stabilization circuit unit and the third terminal of which is grounded; a first comparator, the positive-sequence input terminal of which is connected to the first terminal of the waveform generation subunit; and a second The system includes a second comparator, the positive-sequence input terminal of which is connected to a third terminal of a voltage follower circuit, the inverting input terminal of which is connected to the inverting input terminal of which is connected to a first comparator, and the output terminal of which is connected to a first terminal of a charge pump boost subunit; a charge / discharge capacitor, the charge / discharge capacitor, the charge / discharge capacitor, one terminal of which is connected to the inverting input terminal of which is connected to the inverting input terminal of which is connected to both the first and second comparators, and the other terminal of which is grounded; and a duty cycle adjustment resistor, the duty cycle adjustment resistor, the duty cycle adjustment resistor, one terminal of which is connected to the output terminal of an input filtering voltage stabilization circuit unit, and the other terminal of which is connected to a second terminal of a voltage follower circuit.

[0018] In some embodiments, the waveform generation subunit includes a voltage adjustment subunit, the first terminal of which is connected to the output terminal of an input filtering voltage stabilization circuit unit, and the second terminal of which is grounded; and a charge / discharge subunit, the first terminal of which is connected to the output terminal of a first comparator, and the second terminal of which is connected to the first terminal of a charge / discharge capacitor.

[0019] In some embodiments, the voltage adjustment subunit includes: a first resistor, one terminal of which is connected to the output terminal of an input filtering voltage stabilization circuit unit; a second resistor, one terminal of which is connected to the output terminal of an input filtering voltage stabilization circuit unit; a third resistor, one terminal of which is connected to the other terminal of the first resistor, and the other terminal of which is connected to the other terminal of the second resistor; and a fourth resistor, one terminal of which is connected to the positive-sequence input terminal of a first comparator, and the other terminal of which is grounded.

[0020] In some embodiments, the charge / discharge subunit includes a fifth resistor.

[0021] In some embodiments, the voltage follower circuit includes a voltage divider subunit, one terminal of which is connected to the other terminal of a duty cycle adjustment resistor and the other terminal of which is grounded, and a voltage difference output unit, the first terminal of which is connected to the output terminal of an input filtering voltage stabilization circuit unit and the second terminal of which is connected to one terminal of the voltage divider subunit.

[0022] In some embodiments, the voltage difference output unit includes a seventh resistor, one terminal of which is connected to one terminal of a duty cycle adjustment resistor; a triode, the base electrode of which is connected to the other terminal of the duty cycle adjustment resistor and the collector electrode of which is connected to the other terminal of the seventh resistor; and a voltage stabilization energy storage capacitor, the one terminal of which is connected to the emitter electrode of the triode and the other terminal of which is grounded.

[0023] In some embodiments, the charge pump boost subunit includes a filtering voltage stabilization capacitor, one terminal of which is connected to the output terminal of an input filtering voltage stabilization circuit unit and the other terminal of which is grounded; a feedback adjustment subunit, the first terminal of which is connected to one terminal of the filtering voltage stabilization capacitor and the second terminal of which is grounded; a charge / discharge control subunit, the first terminal of which is connected to one terminal of the filtering voltage stabilization capacitor and the second terminal of which is connected to the output terminal of a second comparator; and an energy storage capacitor, the first terminal of which is connected to a third terminal of the charge / discharge control subunit and the other terminal of which is grounded, and the energy storage capacitor is used for charging when the second and fourth switching transistors are switched on.

[0024] In some embodiments, the charge / discharge control subunit includes a first switching transistor, the gate electrode of which is connected to the output terminal of a second comparator; an inverter, the input terminal of which is connected to the output terminal of a second comparator; a second switch transistor, the gate electrode of which is connected to the output terminal of which is connected; and a third switch transistor, the drain electrode of which is connected to the source electrode of the second switch transistor, and the gate electrode of which is connected to the first switch transistor. The inverter includes a third switch transistor connected to the gate electrode of the inverter, a fourth switch transistor whose source electrode is connected to the source electrode of the third switch transistor and whose gate is connected to the output terminal of the inverter, and a pump capacitor whose one terminal is connected to the drain electrode of the second switch transistor and whose other terminal is connected to the source electrode of the fourth switch transistor, and which is used for charging when the first switch transistor and the third switch transistor are switched on.

[0025] In some embodiments, the feedback adjustment subunit includes a tuning resistor, where the first terminal of the tuning resistor is connected to the output terminal of the input filtering voltage stabilization circuit unit, and the second terminal of the tuning resistor is connected to the first terminal of the charge and discharge control subunit; a first feedback resistor, where one terminal of the first feedback resistor is connected to one terminal of the energy storage capacitor; a second feedback resistor, where one terminal of the second feedback resistor is connected to the other terminal of the first feedback resistor, and the other terminal of the second feedback resistor is grounded; an eighth resistor, where one terminal of the eighth resistor is connected to one terminal of the first feedback resistor, and the other terminal of the eighth resistor is connected to the other terminal of the second feedback resistor; a feedback comparator, where the inverting input terminal of the feedback comparator is connected to the other terminal of the first feedback resistor, and the non-inverting input terminal of the feedback comparator is connected to the output terminal of the sampling feedback unit; and a logic subunit, where the input terminal of the logic subunit is connected to the output terminal of the feedback comparator, and the output terminal of the logic subunit is connected to the adjustment terminal of the tuning resistor.

[0026] In some embodiments, the first communication module includes a first wireless communication unit.

[0027] In some embodiments, the first power module is connected to the first wireless communication unit and is used to supply power to the first wireless communication unit.

[0028] In some embodiments, the data processing module includes a multiplexing switch module connected to the battery cell data sampling module and configured to select battery cell data, a conversion module connected to the multiplexing switch module and configured to perform analog / digital conversion or digital / analog conversion on the selected battery cell data to obtain digital information and / or analog information of the battery cell data, a filtering module connected to the conversion module and configured to remove interference information in the digital information and / or analog information, and an arithmetic storage module connected to the filtering module and configured to perform arithmetic and storage of the filtered digital information and / or analog signal.

[0029] In some embodiments, the battery cell data sampling module includes at least one of a voltage sampling module configured to obtain voltage data of the battery cell, a current sampling module configured to obtain power data of the battery cell, a temperature acquisition module configured to obtain temperature data of the battery cell, and a resistance sampling module configured to obtain resistance data of the battery cell.

[0030] In some embodiments, the battery management chip further includes an equalization module connected to the battery cell and configured to perform consistency processing on the voltage of the battery cell so that the difference between the voltage of the battery cell and the minimum voltage of the remaining battery cells is within a preset voltage range.

[0031] In some embodiments, the temperature acquisition module includes a temperature sensor integrally arranged within the temperature acquisition module.

[0032] To achieve the above objectives, one embodiment of a second aspect of the present disclosure proposes a battery management system. The battery management system includes at least one battery management chip as described in the above embodiments, at least one battery cell connected in a one-to-one correspondence to at least one of the battery management chips, and a control module that communicates with the battery management chip.

[0033] In some embodiments, the control module includes a second communication module that communicates with a first communication module of a battery management chip; a microcontrol unit that receives battery cell data transmitted by the battery management chip via the second communication module and transmits control signals to the battery management chip via the second communication module, so that the battery management chip can control the battery cells connected to the battery management chip; and a second power supply module connected to the microcontrol unit and configured to supply power to the microcontrol unit.

[0034] In some embodiments, the second communication module includes a second wireless communication unit, and the second power module is connected to the second wireless communication unit and used to supply power to the second wireless communication unit.

[0035] To achieve the above objectives, one embodiment of a third aspect of this disclosure provides a vehicle including the battery management system described in the above embodiments.

[0036] Additional aspects and benefits of this disclosure are provided in part in the following description, some of which may be evident from the following description or learned from the practice of this disclosure.

[0037] The above and / or additional aspects and advantages of this disclosure will become apparent and readily apparent from the description of embodiments used in conjunction with the following drawings. [Brief explanation of the drawing]

[0038] [Figure 1]This is a block diagram of a battery management chip according to one embodiment of the present disclosure. [Figure 2] This is a block diagram of a first power module according to one embodiment of the present disclosure. [Figure 3] This is a schematic diagram of the circuit structure of a boost circuit unit according to a specific embodiment of the present disclosure. [Figure 4] This is a schematic diagram of the voltage waveform in a charge / discharge capacitor C2 according to one embodiment of the present disclosure. [Figure 5] This is a schematic diagram of the pulse waveform output by the second comparator Q2 according to one embodiment of the present disclosure. [Figure 6] This is a block diagram of communication between a battery management chip and a control module according to one embodiment of the present disclosure. [Figure 7] This is a schematic diagram of the structure of a battery management system according to one embodiment of the present disclosure. [Figure 8] This is a block diagram of a vehicle according to one embodiment of the present disclosure. [Modes for carrying out the invention]

[0039] Embodiments of the present disclosure are described in detail below, and embodiments described with reference to the accompanying drawings are illustrative.

[0040] The battery management chip acquires voltage, current, temperature, and resistance data from the battery cells and transmits this data to the control module. The control module then analyzes and processes the data to control the operation of the battery cells.

[0041] Hereinafter, a battery management chip according to one embodiment of the present disclosure will be described as an example with reference to Figures 1 to 4.

[0042] As shown in Figure 1, a battery management chip 1 according to one embodiment of the present disclosure includes a battery cell data sampling module 10, a data processing module 11, a first communication module 12, and a first power module 13.

[0043] The battery cell data sampling module 10 is configured to acquire battery cell data from battery cells (BC), the data processing module 11 is connected to the battery cell data sampling module 10 and used to process the battery cell data, the first communication module 12 is connected to the data processing module 11 and used to transmit the processed battery cell data to the control module, and the first power module 13 is connected to the battery cells and the data processing module 11 and is used to receive the initial voltage output by the battery cells and perform a boosting process on the initial voltage to provide the operating voltage to the data processing module 11. It can be understood that the battery management chip 1 is connected in correspondence to a single battery cell to avoid the battery cell operating under high voltage, thereby avoiding the problem of the battery cell needing to be bucked to supply power to the battery management chip 1, and reducing unnecessary energy loss. Furthermore, the battery management chip is connected to a single battery cell to detect a single battery cell, which significantly reduces the risk of the battery management chip failing during long-term operation of the vehicle and lowers the vehicle's failure rate. Finally, since the battery management chip is connected to a single battery cell, the use of wiring harnesses and connectors is significantly reduced, which can lessen the complexity of the chip design and make the design more flexible.

[0044] In one embodiment, when the battery management chip 1 receives a valid operation command, such as a voltage acquisition command, the battery cell data sampling module 10 acquires battery cell data from the battery cell according to the received corresponding operation command. The initial voltage of the battery cell is a wide range of low voltage signals, for example, the initial voltage of the battery cell is between 2.5V and 5.5V, so the normal operation of the battery management chip 1 cannot be guaranteed. At this point, in order to provide an operating voltage for the normal operation of the data processing module 11, the initial voltage of the battery cell is boosted by the first power module 13, for example, the operating voltage after boosting is between 3.3V and 5V. As a result, the data processing module 11 processes the battery cell data after receiving it from the battery cell data sampling module 10 and transmits the processed battery cell data to the control module via the first communication module 12. The control module analyzes and processes the received battery cell data and issues corresponding operation commands to the battery cell. By configuring the first power module 13, the initial voltage output from the battery cell is boosted to provide an operating voltage to the data processing module 11, and as a result, the battery management chip 1 can operate normally under a wide range of low voltages.

[0045] A battery management chip according to one embodiment of the present disclosure boosts the initial voltage output by a battery cell via a first power module, provides an operating voltage to a data processing module, ensures that the battery management chip can operate over a wide range of low voltages, and monitors one battery cell in correspondence via one battery management chip. In the first embodiment, the battery management chip does not need to face the high voltage generated by multiple battery cells in series, avoiding unnecessary energy loss by preventing the battery cells from operating under high voltage, thereby reducing the process requirements for chip manufacturing and saving energy consumption. In the second embodiment, the risk of chip failure can be reduced, avoiding the loss of data from multiple battery cells in one go, and reducing the vehicle failure rate. In the third embodiment, the flexibility of the battery management chip can be improved, reducing the use of numerous wiring harnesses and connectors, reducing the complexity of the battery management chip, and improving the stability and reliability of the battery management chip.

[0046] For example, Figure 2 shows a block diagram of a first power module 13 according to one embodiment of the present disclosure. The first power module 13 includes an input filtering voltage stabilization circuit unit 130, a boost circuit unit 131, and an output filtering voltage stabilization circuit unit 132. The input terminal of the input filtering voltage stabilization circuit unit 130 is connected to the voltage output terminal of a battery cell and is used to reduce voltage ripple interference of the initial voltage output by the battery cell and to output a DC voltage. The boost circuit unit 131 is connected to the output terminal of the input filtering voltage stabilization circuit unit 130 and is used to boost the DC voltage to obtain an initial target voltage. The output filtering voltage stabilization circuit unit 132 is connected to the boost circuit unit 131 and is used to filter and stabilize the initial target voltage to obtain a target voltage, output the target voltage, and provide an operating voltage to the data processing module 11.

[0047] In this embodiment, the initial voltage is provided by a single battery cell. After the single battery cell outputs the initial voltage, the input filtering voltage stabilization circuit unit 130 receives the initial voltage, reduces voltage ripple interference in the initial voltage to obtain a relatively stable DC voltage, and outputs the DC voltage. The output DC voltage is boosted by the boost circuit unit 131 to obtain an initial target voltage, which is then sent to the output filtering voltage stabilization circuit unit 132. The output filtering voltage stabilization circuit unit 132 performs filtering and stabilization on the received initial target voltage to obtain a target voltage, which is then output to the data processing module 11, providing the data processing module 11 with an operating voltage. It can be understood that the initial voltage is a wide range of low voltages, and that the DC voltage, which is the initial voltage with voltage ripple interference removed, is processed by the boost circuit unit 131 to obtain the initial target voltage. The initial target voltage provides the operating voltage for the normal operation of the battery management chip 1. The initial target voltage is stabilized and filtered to obtain a relatively stable initial target voltage, which is then adopted as the target voltage. The initial voltage output from the battery cell is boosted by the boost circuit unit 131 to provide the operating voltage to the data processing module 11, ensuring that the battery management chip can operate over a wide range of low voltages.

[0048] In some embodiments, as shown in Figure 2, the boost circuit unit 131 is integrally located within the first power module 13. Integrating the boost circuit unit 131 within the first power module 13 saves space and reduces costs compared to using devices that cannot be integrated, such as inductors and transformers.

[0049] In some embodiments, as shown in Figure 2, the first power module 13 further includes a sampling feedback unit 133. The sampling feedback unit 133 is connected to an output filtering voltage stabilization circuit unit 132 and a boost circuit unit 131, respectively, and is used to acquire a target voltage value and feed back the target voltage value to the boost circuit unit 131. The boost circuit unit 131 is further used to receive the target voltage value and adjust the boost operation of the DC voltage based on the target voltage value, so that the initial target voltage output after adjustment is filtered and stabilized by the output filtering stabilization circuit unit 132, and the output target voltage is within a preset voltage range.

[0050] In one embodiment, the preset voltage range is a voltage range that ensures the normal operation of the battery management chip 1, for example, 3.3V to 5V. Considering that the current consumption of the battery management chip 1 differs depending on the operating mode and the target voltage changes significantly, after the output filtering voltage stabilization circuit unit 132 outputs the target voltage, the sampling feedback unit 133 detects the initial target voltage at this point, and the boost operation of the boost circuit unit 131 is adjusted in real time based on the voltage value of the target voltage to ensure that the output target voltage is within the preset voltage range, in other words, it is ensured that the output target voltage does not change significantly due to changes in the operating mode.

[0051] In some embodiments, Figure 3 shows a schematic diagram of the circuit structure of a boost circuit unit 131 according to one embodiment of the present disclosure. The boost circuit unit 131 includes a PWM generation circuit subunit 134, the first terminal of which is connected to the output terminal of an input filtering voltage stabilization circuit unit 130, the second terminal of which is grounded, and the third terminal of which is used to output a PWM signal; and a charge pump boost subunit 135, the first terminal of which is connected to the third terminal of which is used to adjust the frequency and duty cycle of the PWM signal in real time until an initial target voltage is obtained. Of these, the charge pump boost subunit 135 employs the principle of charge pump circuit boosting and operates by charge transfer. A pump-capacitor can transfer charge from the input terminal to the output terminal to provide the current required by the load, employing a capacitor for energy storage, and can provide high-current operation with no EMI interference, low noise, low cost, low quiescent current, low output voltage ripple, and feedback adjustment.

[0052] In one embodiment, the boost circuit unit 131 is preceded by a PWM generation circuit subunit 134 and followed by a charge pump boost subunit 135. The charge pump boost subunit 135 controls the frequency and duty cycle of the PWM signal. The boost circuit unit 131 continuously boosts the DC voltage through the PWM generation circuit subunit 134 and the charge pump boost subunit 135 until an initial target voltage is obtained.

[0053] In some embodiments, as shown in Figure 3, the PWM generation circuit subunit 134 includes an energy storage subunit C1, a waveform generation subunit 136, a voltage follower circuit 137, a first comparator Q1, a second comparator Q2, a charge / discharge capacitor C2, and a duty cycle adjustment resistor RE1. Of these, one terminal of the energy storage subunit C1 is connected to the output terminal of the input filtering voltage stabilization circuit unit 130, and the other terminal of the energy storage subunit C1 is grounded. The first terminal of the waveform generation subunit 136 is connected to the output terminal of the input filtering voltage stabilization circuit unit 130, and the second terminal of the waveform generation subunit 136 is grounded. The first terminal of the voltage follower circuit 137 is connected to the output terminal of the input filtering voltage stabilization circuit unit 130, and the third terminal of the voltage follower circuit 137 is grounded. The positive-sequence input terminal of the first comparator Q1 is connected to the first terminal of the waveform generation subunit 136. The positive-sequence input terminal of the second comparator Q2 is connected to the third terminal of the voltage follower circuit 137, the inverting input terminal of the second comparator Q2 is connected to the inverting input terminal of the first comparator Q1, and the output terminal of the second comparator Q2 is connected to the first terminal of the charge pump boost subunit 135. One terminal of the charge / discharge capacitor C2 is connected to the inverting input terminal of the first comparator Q1 and the inverting input terminal of the second comparator Q2, and the other terminal of the charge / discharge capacitor C2 is grounded. One terminal of the duty cycle adjustment resistor RE1 is connected to the output terminal of the input filtering voltage stabilization circuit unit 130, and the other terminal of the duty cycle adjustment resistor RE1 is connected to the second terminal of the voltage follower circuit 137.

[0054] In this embodiment, the charge / discharge capacitor C2 and the first comparator Q1 in the PWM generation circuit subunit 134 output a sawtooth wave, and the duty cycle adjustment resistor RE1 is adjusted to output a PWM signal for use in subsequent circuits via the voltage follower circuit 137 and the second comparator Q2.

[0055] For example, as shown in Figure 3, the waveform generation subunit 136 includes a voltage adjustment subunit and a charge / discharge subunit. The voltage adjustment subunit includes a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4. The charge / discharge subunit includes a fifth resistor R5. One terminal of the first resistor R1 is connected to the output terminal of the input filtering voltage stabilization circuit unit 130. One terminal of the second resistor R2 is connected to the output terminal of the input filtering voltage stabilization circuit unit 130. One terminal of the third resistor R3 is connected to the other terminal of the first resistor R1, and the other terminal of the third resistor R3 is connected to the other terminal of the second resistor R2. One terminal of the fourth resistor R4 is connected to the positive-sequence input terminal of the first comparator Q1, and the other terminal of the fourth resistor R4 is grounded. One terminal of the fifth resistor R5 is connected to the output terminal of the first comparator Q1, and the other terminal of the fifth resistor R5 is connected to one terminal of the charge / discharge capacitor C2.

[0056] It is understood that the PWM generation circuit subunit 134 can be divided into three stages when outputting a PWM pulse waveform. In the first stage, the voltage at the inverting input terminal of the first comparator Q1 is 0, and the voltage at the positive-sequence input terminal is R4*VBAT / (R4+((R2+R3) / / R1)). At this point, the first comparator Q1 outputs a high level and charges the charge / discharge capacitor C2 via the fifth resistor R5. In the second stage, when the charging voltage of the charge / discharge capacitor C2 reaches the voltage at the positive-sequence input terminal of the first comparator Q1, i.e., R4*VBAT / (R4+((R2+R3) / / R1)), the first comparator Q1 outputs a low level, and the voltage at the positive-sequence input terminal of the first comparator Q1 is (R3 / / The voltage is (R4)*VBAT / ((R3 / / R4)+R1), and the charge / discharge capacitor C2 is discharged through the fifth resistor R5. In the third stage, when the voltage discharged by the charge / discharge capacitor C2 to the positive-sequence input terminal of the first comparator Q1 is lower than (R3 / / R4)*VBAT / ((R3 / / R4)+R1), the first comparator Q1 outputs a high level, returning to the first stage and thereby realizing the output PWM pulse waveform.

[0057] Figure 4 is a schematic diagram of the voltage waveform of a charge / discharge capacitor C2 according to one embodiment of the present disclosure. As can be seen from Figure 4, the waveform in the charge / discharge capacitor C2 differs depending on the stage.

[0058] In some embodiments, as shown in Figure 3, the voltage follower circuit 137 includes a voltage divider subunit and a voltage difference output unit. One terminal of the voltage divider subunit is connected to the other terminal of a duty cycle adjustment resistor RE1, and the other terminal of the voltage divider subunit is grounded. Specifically, the voltage divider subunit includes a sixth resistor, and the voltage difference output unit includes a triode Q3, a seventh resistor R7, and a voltage stabilization energy storage capacitor C3. One terminal of the seventh resistor R7 is connected to one terminal of the duty cycle adjustment resistor RE1. The base electrode of the triode Q3 is connected to the other terminal of the duty cycle adjustment resistor RE1, and the collector electrode of the triode Q3 is connected to the other terminal of the seventh resistor R7. One terminal of the voltage stabilization energy storage capacitor C3 is connected to the emitter electrode of the triode Q3, and the other terminal of the voltage stabilization energy storage capacitor C3 is grounded.

[0059] In this embodiment, the duty cycle adjustment resistor RE1 is an adjustable resistor, and the duty cycle adjustment resistor RE1 and the sixth resistor R6 are connected in series to adjust the voltage of the base electrode of the triode Q3. The voltage of the voltage stabilizing energy storage capacitor C3 changes in accordance with the change in the voltage of the base electrode of the triode Q3, and the voltage at the positive-sequence input terminal of the second comparator Q2 is R6*VBAT / (R6+RE1-0.7V), of which the seventh resistor R7 provides the load capacitance of the triode Q3. The load capacitance is understood to be the magnitude of the output resistance in the circuit.

[0060] Figure 5 is a schematic diagram of the pulse waveform output by the second comparator Q2 according to one embodiment of the present disclosure. As can be seen from Figure 5, the second comparator Q2 outputs a PWM waveform, and the duty cycle of the PWM waveform is adjusted by adjusting the duty cycle adjustment resistor RE1.

[0061] In some embodiments, as shown in Figure 3, the charge pump boost subunit includes a filtering voltage stabilization capacitor C4, a feedback adjustment subunit, a charge / discharge control subunit, and an energy storage capacitor C5. One terminal of the filtering voltage stabilization capacitor C4 is connected to the output terminal of the input filtering voltage stabilization circuit unit 130, and the other terminal of the filtering voltage stabilization capacitor C4 is grounded. The first terminal of the feedback adjustment subunit is connected to one terminal of the filtering voltage stabilization capacitor C4, and the second terminal of the feedback adjustment subunit is grounded. The first terminal of the charge / discharge control subunit is connected to one terminal of the filtering voltage stabilization capacitor C4, and the second terminal of the charge / discharge control subunit is connected to the output terminal of the second comparator Q2. One terminal of the energy storage capacitor C5 is connected to the third terminal of the charge / discharge control subunit, and the other terminal of the energy storage capacitor C5 is grounded, and the energy storage capacitor C5 is used for charging when the second switch transistor Q5 and the fourth switch transistor Q7 are switched on.

[0062] Of these, the charge / discharge control subunit includes a first switch transistor Q4, an inverter 138, a second switch transistor Q5, a third switch transistor Q6, a fourth switch transistor Q7, and a pump capacitor CE1. The feedback adjustment subunit includes a tuning resistor RON, a first feedback resistor Rf1, a second feedback resistor Rf2, a feedback comparator Q3', an eighth resistor Rload, and a logic subunit 139. Specifically, the gate electrode of the first switch transistor Q4 is connected to the output terminal of the second comparator Q2, the input terminal of the inverter 138 is connected to the output terminal of the second comparator Q2, the gate electrode of the second switch transistor Q5 is connected to the output terminal of the inverter 138, the drain electrode of the third switch transistor Q6 is connected to the source electrode of the second switch transistor Q5, and the gate electrode of the third switch transistor Q6 is connected to the gate of the first switch transistor Q4. The source electrode of the fourth switch transistor Q7 is connected to the source electrode of the third switch transistor Q6, the gate electrode of the fourth switch transistor Q7 is connected to the output terminal of inverter 138, one terminal of the pump capacitor is connected to the drain electrode of the second switch transistor Q5, and the other terminal of the pump capacitor CE1 is connected to the source of the fourth switch transistor Q7, and the pump capacitor is used for charging when the first switch transistor Q4 and the third switch transistor Q6 are switched on.The first terminal of the adjustment resistor RON is connected to the output terminal of the input filtering voltage stabilization circuit unit 130, the second terminal of the adjustment resistor RON is connected to the first terminal of the charge / discharge control subunit, one terminal of the first feedback resistor Rf1 is connected to one terminal of the energy storage capacitor C5, one terminal of the second feedback resistor Rf2 is connected to the other terminal of the first feedback resistor Rf1, the other terminal of the second feedback resistor Rf2 is grounded, and one terminal of the eighth resistor Rload is connected to one end of the first feedback resistor. The other terminal of the eighth resistor Rload is connected to the other terminal of the second feedback resistor Rf2, the inverting input terminal of the feedback comparator Q3' is connected to the other terminal of the first feedback resistor Rf1, the positive-phase input terminal of the feedback comparator Q3' is connected to the output terminal of the sampling feedback unit 133, the input terminal of the logic subunit 139 is connected to the output terminal of the feedback comparator Q3', and the output terminal of the logic subunit 139 is connected to the adjustment terminal of the tuning resistor RON.

[0063] It will be understood that the PWM wave outputs a PWM1 waveform via inverter 138, and a PWM2 waveform on another path that does not pass through inverter 138, and that the waveform that passes through inverter 138 is the inverse of the waveform that does not pass through inverter 138.

[0064] In this embodiment, after the boost circuit unit 131 is activated, in the first half cycle, PWM2 is low, and the PWM generation circuit subunit 134 is low, controlling the first switch transistor Q4 and the third switch transistor Q6 to be switched on to charge the pump capacitor CE1. At this point, the PWM signal is PWM1, which is output via the inverter 138 to high, controlling the second switch transistor Q5 and the fourth switch transistor Q7 to be closed. In the second half cycle, the second switch transistor Q5 and the fourth switch transistor Q7 are switched on, the first switch transistor Q4 and the third switch transistor Q6 are closed, the third capacitor C5 is charged by the pump capacitor CE1, the current required by the load is supplied, and the voltage is continuously boosted to the voltage and current required by the battery management chip by controlling the PWM frequency and duty cycle, and the charging current to the pump capacitor CE1 is controlled by the output feedback adjustment circuit to further control the output.

[0065] Of these, the third switch transistor Q6 is closed, charging the energy storage capacitor C5 via the pump capacitor CE1 and supplying the required amount of electricity to the load. The energy storage capacitor C5 is the energy storage capacitor of the charge pump boost subunit and supplies current to the eighth resistor Rload. The feedback comparator Q3' is the boosted feedback adjustment voltage output and is realized by a series voltage divider of the high-precision first feedback resistor Rf1 and the second feedback resistor Rf2. The voltage at the inverting input terminal of the feedback comparator Q3' is Rf2*Vout / (Rf1+Rf2). If the voltage at the inverting input terminal of the feedback comparator Q3' is lower than the voltage at the output terminal of the sampling feedback unit 133, the feedback comparator Q3' sends a signal to the logic subunit 139 indicating that the output voltage is too low, and the logic subunit 139 adjusts the tuning resistor RON after the determination process to control the charge pump boost subunit to boost the voltage to reach the target voltage.

[0066] If the voltage at the inverting input terminal of the feedback comparator Q3' is greater than the voltage at the output terminal of the sampling feedback unit 133, the feedback comparator Q3' sends a signal to the logic subunit 139 indicating that the output voltage is too high. The logic subunit 139 then adjusts the tuning resistor RON after the decision process and controls the charge pump boost subunit to step down the voltage to reach the target voltage.

[0067] Currently, the communication mode employed by common battery management chips is primarily twisted-pair daisy-chain cables. This wired communication mode using twisted-pair daisy-chain cables requires the addition of isolation devices and electromagnetic compatibility protection devices to the communication terminals to ensure the reliability and stability of vehicle communication in complex interference environments. Secondly, when the twisted-pair daisy-chain cable wired communication mode synchronously monitors battery cell information, the requirements of serial transmission mode and bidirectional transmission result in delays in data reception, increasing the demand for timing processing in synchronous monitoring. Finally, wired communication methods require wiring harnesses and connectors, which also present significant challenges to the reliability, stability, and cost of the wiring harnesses and connectors.

[0068] Therefore, as shown in Figure 1, the first communication module 12 of the embodiment of this disclosure employs a first wireless communication unit, and wireless communication transmission of the battery management chip 1 is realized by using the first wireless communication unit. Firstly, this wireless communication transmission reduces the number of isolation and protection devices required for coupled interference of wired communication harness noise, thereby improving communication quality, ensuring accurate data transmission and interaction, reducing the complexity of the sampling board, and enabling more flexible application. Secondly, the communication mode of the first wireless communication unit is adopted, and compared to the wired communication mode using twisted-pair daisy-chain cables, the wireless communication mode makes information interaction more flexible and convenient, realizes natural time-synchronous measurement, and supports more synchronous induction functions. Furthermore, it can avoid the problem of battery information loss caused by wiring harnesses and improve the overall safety of the vehicle. Finally, by reducing complex wiring harnesses and connectors, the overall weight and complexity of the vehicle can be reduced, design flexibility can be improved, and maintenance can be made simpler and more convenient.

[0069] In some embodiments, as shown in Figure 1, the first power module 13 is connected to the first wireless communication unit and used to supply power to the first wireless communication unit. The first power module 13 supplies power to the first wireless communication unit to ensure normal communication of the first wireless communication unit.

[0070] In some embodiments, the first wireless communication unit includes at least one of Bluetooth, RFID (radio frequency identification) unit, electromagnetic wireless communication unit, and SparkLink communication unit. In other words, the first wireless communication unit can achieve wireless communication by at least one of the Bluetooth communication method, RFID communication method, electromagnetic communication method, and SparkLink communication method, but is not limited to these. It is understood that the SparkLink communication method uses SparkLink technology for wireless communication. SparkLink technology is a short-range communication technology that can be used to achieve wireless interconnection for carrying out data interaction and transmission in vehicle application scenarios. SparkLink technology has the advantages of ultra-low latency, ultra-high reliability, and precise synchronization.

[0071] In some embodiments, as shown in conjunction with Figures 1 and 6, the data processing module 11 includes a multiplexing switch module 110, a conversion module 111, a filtering module 112, and an arithmetic memory module 113. The multiplexing switch module 110 is connected to the battery cell data sampling module 10 and is used to select battery cell data. The conversion module 111 is connected to the multiplexing switch module 110 and is used to perform analog-to-digital or digital-to-analog conversion on the selected battery cell data to obtain digital and / or analog information of the battery cell data. The filtering module 112 is connected to the conversion module 111 and is used to remove interference information in the digital and / or analog information. The arithmetic memory module 113 is connected to the filtering module 112 and is used for calculations and storage of the filtered digital and / or analog signals.

[0072] In one embodiment, battery cell data is processed by a multiplexing switch module 110, a conversion module 111, a filtering module 112, and an arithmetic memory module 113 in order to transmit battery cell data via a first wireless communication unit, thereby obtaining processed battery cell data.

[0073] In some embodiments, as shown in Figure 6, the battery cell data sampling module 10 includes at least one of the following: a voltage sampling module (VSM) for acquiring voltage data of the battery cell, a current sampling module (CSM) for acquiring power data of the battery cell, a temperature acquisition module (TAM) for acquiring temperature data of the battery cell, and a resistance sampling module (RSM) for acquiring resistance data of the battery cell. Battery cell data acquisition is achieved by configuring the corresponding sampling module.

[0074] In some embodiments, as shown in Figure 6, the battery management chip 1 further includes an equalization module 14, which is connected to the battery cells and used to perform a voltage matching process on the battery cells so that the difference between the voltage of one battery cell and the minimum voltage of the remaining battery cells is within a preset voltage range. It can be understood that by configuring the equalization module 14, if the voltage matching of the battery cells is abnormal, i.e., if the voltage of one battery cell is high, the equalization module 14 will reduce the voltage of that battery cell, and as a result the difference between the voltage of one battery cell and the minimum voltage of the remaining battery cells will be reduced, thereby ensuring voltage matching between individual battery cells.

[0075] In some embodiments, as shown in Figure 6, the battery management chip 1 further includes a clock module 15, which is connected to a first power module 13 to determine the timing for transmitting and receiving battery cell data. By configuring the clock module 15, the timing for transmitting and receiving battery cell data is controlled so that the battery cell data is transmitted and received according to a specific timing sequence.

[0076] Currently, temperature monitoring of battery packs, chips, and the environment primarily relies on calculating and determining temperature through changes in the resistance of temperature-sensitive resistors. This method is time-consuming, leading to insufficient timely temperature information and resulting in premature thermal failures and detection and monitoring failures. Therefore, as shown in Figure 6, one embodiment of this disclosure includes a temperature sensor in the temperature acquisition module. By placing the temperature sensor within the temperature acquisition module to acquire temperature data from battery cells, the temperature sensor responds more sensitively and quickly to the temperature data compared to using temperature-sensitive resistors, thus significantly improving the temperature response processing speed.

[0077] In some embodiments, the temperature sensor is integrated into the temperature acquisition module, thereby saving space and cost for the battery management chip 1.

[0078] A battery management chip 1 according to one embodiment of the present disclosure boosts the initial voltage output by a battery cell via a first power module, provides an operating voltage to a data processing module, ensures that the battery management chip can operate over a wide range of low voltages, and monitors one battery cell in correspondence via one battery management chip. In the first embodiment, the battery management chip does not need to face the high voltage generated by multiple battery cells in series, avoiding unnecessary energy loss by preventing the battery cells from operating under high voltage, thereby reducing the process requirements for chip manufacturing and saving energy consumption. In the second embodiment, the risk of chip failure can be reduced, avoiding the loss of data from multiple battery cells in one go, and reducing the vehicle failure rate. In the third embodiment, the flexibility of the battery management chip can be improved, reducing the use of numerous wiring harnesses and connectors, reducing the complexity of the battery management chip, and improving the stability and reliability of the battery management chip.

[0079] A battery management system according to one embodiment of the present disclosure is described below.

[0080] As illustrated in Figure 7, a battery management system 2 according to one embodiment of the present disclosure includes at least one battery management chip 1 as described in the above embodiment, at least one battery cell (not shown) connected in a one-to-one correspondence to at least one of the battery management chips, and a control module 21 that communicates with the battery management chip 1.

[0081] A battery management system 2 according to one embodiment of the present disclosure boosts the initial voltage output by a battery cell via a first power module, provides an operating voltage to a data processing module, ensures that the battery management chip can operate over a wide range of low voltages, and monitors one battery cell in correspondence via one battery management chip. In the first embodiment, the battery management chip does not need to face the high voltage generated by multiple battery cells in series, avoiding unnecessary energy loss by preventing the battery cells from operating under high voltage, thereby reducing the process requirements for chip manufacturing and saving energy consumption. In the second embodiment, the risk of chip failure can be reduced, preventing the loss of data from multiple battery cells in one go, and reducing the vehicle failure rate. In the third embodiment, the flexibility of the battery management chip can be improved, reducing the use of numerous wiring harnesses and connectors, reducing the complexity of the battery management chip, and improving the stability and reliability of the battery management chip.

[0082] In some embodiments, the control module 21 includes a second communication module 22 that communicates with a first communication module of the battery management chip 1, a microcontrol unit 23 that receives battery cell data transmitted by the battery management chip 1 via the second communication module 22 and transmits control signals to the battery management chip 1 via the second communication module 22 so that the battery management chip 1 can control the battery cells connected to the battery management chip 1, and a second power module 24 connected to the microcontrol unit 23 and used to supply power to the microcontrol unit 23. One battery management chip 1 manages one battery cell, and the control module 22 can perform data interaction processing simultaneously with multiple battery management chips 1. The control module 22 sends a valid operation command, and when the battery management chip 1 receives the command via wireless communication, it starts acquiring and monitoring battery cell data of a single battery cell, and then transmits that battery cell data to the control module 21 via wireless communication for data analysis and processing, and awaits the next operation.

[0083] In some embodiments, the second communication module 22 includes a second wireless communication unit. Wireless communication can be implemented between the first and second wireless communication units, supporting more synchronous sensing functions, and consequently making the use of communication more free and flexible. Wireless data transmission is another major innovation in twisted-pair daisy-chain wired communication methods. Firstly, wireless data transmission reduces the number of isolation devices and electromagnetic compatibility protection devices required for coupled interference of wired communication harness noise. On the one hand, wireless data transmission reduces the complexity of the battery sampling board, and on the other hand, makes the application more flexible. Secondly, compared to twisted-pair daisy-chain serial wired communication, wireless communication makes information exchange more flexible and convenient, can naturally realize time-synchronous measurement, can support more synchronous induction functions, avoids the problem of multi-string battery information loss in serial communication caused by the wiring harness, and thereby can improve the overall safety of the vehicle. Finally, from a structural standpoint, the absence of complex wiring harnesses and connectors reduces the overall weight and complexity of the vehicle, improves design flexibility, and makes maintenance simpler and more convenient.

[0084] In some embodiments, the second power module 24 is connected to the second wireless communication unit and used to supply power to the second wireless communication unit. The second power module is a workpiece of the second wireless communication unit to ensure the normal operation of the wireless communication unit.

[0085] A vehicle according to one embodiment of this disclosure is described below.

[0086] As illustrated in Figure 8, a vehicle 3 according to one embodiment of the present disclosure includes the battery management system 2 described in the above embodiment.

[0087] Vehicle 3 according to one embodiment of the present disclosure boosts the initial voltage output by the battery cells via a first power module, provides an operating voltage to a data processing module, ensures that the battery management chip can operate over a wide range of low voltages, and monitors one battery cell in correspondence via one battery management chip. In the first embodiment, the battery management chip does not need to face the high voltage generated by multiple battery cells in series, avoids unnecessary energy loss by preventing the battery cells from operating under high voltage, thereby reducing the process requirements for chip manufacturing and saving energy consumption. In the second embodiment, the risk of chip failure can be reduced, avoiding the loss of data from multiple battery cells in one go, and reducing the vehicle failure rate. In the third embodiment, the flexibility of the battery management chip can be improved, reducing the use of numerous wiring harnesses and connectors, reducing the complexity of the battery management chip, and improving the stability and reliability of the battery management chip.

[0088] In this specification, any reference to terms such as “one embodiment,” “several embodiments,” “exemplary embodiment,” “example,” “specific example,” or “several examples” means that a particular feature, structure, material, or property described in relation to an embodiment or example is included in at least one embodiment or example of this disclosure. In this specification, exemplary expressions of the above terms do not necessarily refer to the same embodiment or example.

[0089] While embodiments of the present disclosure are shown and described above, it will be understood by those skilled in the art that various modifications, alterations, substitutions, and variations may be made to the above embodiments without departing from the principles and ideas of the present disclosure, the extent of which such modifications and variations are defined by the claims and their equivalents. [Explanation of Symbols]

[0090] 1. Battery Management Chip (BMC) 10. Battery Cell Data Sampling Module (BCDSM) 11. Data Processing Module (DPM) 12. First Communication Module (FCM) 13. First Power Module (FPM) 130 Input Filtering Voltage Stabilization Circuit Unit (IFVSCU) 131 Boost Circuit Unit (BCU) 132 Output Filtering Voltage Stabilization Circuit Unit (OFVSCU) 133 Sampling Feedback Unit (SFU) 134 PWM Generation Circuit Subunit 135 Charge Pump Boost Subunit 136 Waveform Generation Subunit 137 Voltage Follower Circuit 138 Inverter 139 Logical Subunits 110 Multiplexed Switch Modules (MSM) 111 Conversion Module (CONVM) 112 Filtering Module (FLTM) 113. Arithmetic Memory Module (ASM) 14. Equalization Module (EQM) 15 Clock Module (CLKM) 2. Battery Management System (BMC) 21 Control Module (CTRLM) 22 Second Communication Module (SCM) 23 Microcontroller Unit (MCU) 24. Second Power Module (SPM) 3 vehicles

Claims

1. A battery management chip (1), wherein the battery management chip (1) is connected to a single battery cell, and the battery management chip (1) A battery cell data sampling module (10) used to acquire battery cell data of the aforementioned battery cell, A data processing module (11) is connected to the battery cell data sampling module (10) and used to process the battery cell data, A first communication module (12) is connected to the data processing module (11) and used to transmit the processed battery cell data to the control module, A first power module (13) is connected to the battery cell and the data processing module (11), and is used to receive the initial voltage output by the battery cell, perform a boosting process on the initial voltage, and provide an operating voltage to the data processing module (11). Equipped with, The first power module (13) The system includes a boost circuit unit (131), which is connected to the battery cell and used to perform a boosting process on the initial voltage output from the battery cell to obtain an initial target voltage. The first power module (13) The system further comprises an input filtering voltage stabilization circuit unit (130), the input terminal of which is connected to the voltage output terminal of the battery cell, and is used to reduce voltage ripple interference of the initial voltage output by the battery cell and to output a DC voltage. The aforementioned boost circuit unit (131) A PWM generation circuit subunit (134) wherein the first terminal of the PWM generation circuit subunit (134) is connected to the output terminal of the input filtering voltage stabilization circuit unit (130), the second terminal of the PWM generation circuit subunit (134) is grounded, and the third terminal of the PWM generation circuit subunit (134) is used to output a PWM signal. A charge pump boost subunit (135) is provided, wherein the first terminal of the charge pump boost subunit (135) is connected to the third terminal of the PWM generation circuit subunit (134), and is used to adjust the frequency and duty cycle of the PWM signal in real time until the initial target voltage is obtained. Equipped with, The PWM generation circuit subunit (134) An energy storage subunit (C1) wherein one terminal of the energy storage subunit (C1) is connected to the output terminal of the input filtering voltage stabilization circuit unit (130), and the other terminal of the energy storage subunit (C1) is grounded, A waveform generation subunit (136) wherein the first terminal of the waveform generation subunit (136) is connected to the output terminal of the input filtering voltage stabilization circuit unit (130), and the second terminal of the waveform generation subunit (136) is grounded, A voltage follower circuit (137) wherein the first terminal of the voltage follower circuit (137) is connected to the output terminal of the input filtering voltage stabilization circuit unit (130), and the third terminal of the voltage follower circuit (137) is grounded. A first comparator (Q1), wherein the positive-sequence input terminal of the first comparator (Q1) is connected to the first terminal of the waveform generation subunit (136), A second comparator (Q2), wherein the positive-sequence input terminal of the second comparator (Q2) is connected to the third terminal of the voltage follower circuit (137), the inverting input terminal of the second comparator (Q2) is connected to the inverting input terminal of the first comparator (Q1), and the output terminal of the second comparator (Q2) is connected to the first terminal of the charge pump boost subunit (135), A charge / discharge capacitor (C2) wherein one terminal of the charge / discharge capacitor (C2) is connected to the inverting input terminal of the first comparator (Q1) and the inverting input terminal of the second comparator (Q2), and the other terminal of the charge / discharge capacitor (C2) is grounded, A duty cycle adjustment resistor (RE1) wherein one terminal of the duty cycle adjustment resistor (RE1) is connected to the output terminal of the input filtering voltage stabilization circuit unit (130), and the other terminal of the duty cycle adjustment resistor (RE1) is connected to the second terminal of the voltage follower circuit (137). A battery management chip (1) is provided.

2. The first power module (13) The battery management chip (1) according to claim 1, further comprising an output filtering voltage stabilization circuit unit (132), wherein the output filtering voltage stabilization circuit unit (132) is connected to the boost circuit unit (131) and is used to perform filtering and stabilization on the initial target voltage to obtain a target voltage, output the target voltage, and provide an operating voltage to the data processing module (11).

3. The first power module (13) The battery management chip (1) according to claim 2, further comprising a sampling feedback unit (133), the sampling feedback unit (133) being connected to the output filtering voltage stabilization circuit unit (132) and the boost circuit unit (131), and used to acquire the voltage value of the target voltage and to feed back the voltage value of the target voltage to the boost circuit unit (131).

4. The battery management chip (1) according to claim 3, wherein the boost circuit unit (131) is further configured to receive the voltage value of the target voltage and adjust the boost action based on the voltage value of the target voltage, and as a result the initial target voltage output after adjustment is filtered and stabilized by the output filtering voltage stabilization circuit unit (132) so that the output target voltage is within a preset voltage range.

5. The waveform generation subunit (136) A voltage adjustment subunit, wherein the first terminal of the voltage adjustment subunit is connected to the output terminal of the input filtering voltage stabilization circuit unit (130), and the second terminal of the voltage adjustment subunit is grounded, A charge / discharge subunit, wherein one terminal of the charge / discharge subunit is connected to the output terminal of the first comparator (Q1), and the other terminal of the charge / discharge subunit is connected to one terminal of the charge / discharge capacitor (C2), and A battery management chip (1) according to claim 1, comprising:

6. The aforementioned voltage adjustment subunit, A first resistor (R1), wherein one terminal of the first resistor (R1) is connected to the output terminal of the input filtering voltage stabilization circuit unit (130), A second resistor (R2), wherein one terminal of the second resistor (R2) is connected to the output terminal of the input filtering voltage stabilization circuit unit (130), A third resistor (R3), wherein one terminal of the third resistor (R3) is connected to the other terminal of the first resistor (R1), and the other terminal of the third resistor (R3) is connected to the other terminal of the second resistor (R2), A fourth resistor (R4), wherein one terminal of the fourth resistor (R4) is connected to the positive-sequence input terminal of the first comparator (Q1), and the other terminal of the fourth resistor (R4) is grounded. The battery management chip (1) according to claim 5, comprising:

7. The battery management chip (1) according to claim 5, wherein the charge / discharge subunit includes a fifth resistor (R5).

8. The voltage follower circuit (137) A voltage divider subunit, wherein one terminal of the voltage divider subunit is connected to the other terminal of the duty cycle adjustment resistor (RE1), and the other terminal of the voltage divider subunit is grounded. A voltage difference output unit wherein the first terminal of the voltage difference output unit is connected to the output terminal of the input filtering voltage stabilization circuit unit (130), and the second terminal of the voltage difference output unit is connected to one terminal of the voltage division subunit. A battery management chip (1) according to claim 1, comprising:

9. The aforementioned voltage difference output unit A seventh resistor (R7), wherein one terminal of the seventh resistor (R7) is connected to one terminal of the duty cycle adjustment resistor (RE1), A triode (Q3) wherein the base electrode of the triode (Q3) is connected to the other terminal of the duty cycle adjustment resistor (RE1), and the collector electrode of the triode (Q3) is connected to the other terminal of the seventh resistor (R7), A voltage-stabilized energy storage capacitor, wherein one terminal of the voltage-stabilized energy storage capacitor is connected to the emitter electrode of the triode, and the other terminal of the voltage-stabilized energy storage capacitor is grounded. The battery management chip (1) according to claim 8, comprising:

10. The charge pump boost subunit (135) A filtering voltage stabilizing capacitor (C4), wherein one terminal of the filtering voltage stabilizing capacitor (C4) is connected to the output terminal of the input filtering voltage stabilizing circuit unit (130), and the other terminal of the filtering voltage stabilizing capacitor (C4) is grounded, A feedback adjustment subunit, wherein the first terminal of the feedback adjustment subunit is connected to one terminal of the filtering voltage stabilizing capacitor (C4), and the second terminal of the feedback adjustment subunit is grounded. A charge / discharge control subunit, wherein a first terminal of the charge / discharge control subunit is connected to one terminal of the filtering voltage stabilizing capacitor (C4), and a second terminal of the charge / discharge control subunit is connected to the output terminal of the second comparator (Q2), An energy storage capacitor (C5) wherein one terminal of the energy storage capacitor (C5) is connected to the third terminal of the charge / discharge control subunit, the other terminal of the energy storage capacitor (C5) is grounded, and the energy storage capacitor (C5) is used for charging when the second switch transistor (Q5) and the fourth switch transistor (Q7) are switched on. A battery management chip (1) according to claim 1, comprising:

11. The charge / discharge control subunit, A first switch transistor (Q4), wherein the gate electrode of the first switch transistor (Q4) is connected to the output terminal of the second comparator (Q2), An inverter (138) wherein the input terminal of the inverter (138) is connected to the output terminal of the second comparator (Q2), A second switch transistor (Q5), wherein the gate electrode of the second switch transistor (Q5) is connected to the output terminal of the inverter (138), A third switch transistor (Q6), wherein the drain electrode of the third switch transistor (Q6) is connected to the source electrode of the second switch transistor (Q5), and the gate electrode of the third switch transistor (Q6) is connected to the gate electrode of the first switch transistor (Q4), A fourth switch transistor (Q7), wherein the source electrode of the fourth switch transistor (Q7) is connected to the source electrode of the third switch transistor (Q6), and the gate electrode of the fourth switch transistor (Q7) is connected to the output terminal of the inverter (138), A pump capacitor (CE1) wherein one terminal of the pump capacitor (CE1) is connected to the drain electrode of the second switch transistor (Q5), and the other terminal of the pump capacitor (CE1) is connected to the source electrode of the fourth switch transistor (Q7), and the pump capacitor (CE1) is used for charging when the first switch transistor (Q4) and the third switch transistor (Q6) are switched on. The battery management chip (1) according to claim 10, comprising:

12. A battery management chip (1) according to any one of claims 1 to 11, At least one battery cell connected in a one-to-one correspondence to at least one of the battery management chips (1), A control module (21) that communicates with the aforementioned battery management chip (1) and A battery management system equipped with this feature.

13. The control module (21) A second communication module (22) communicates with the first communication module (12) of the battery management chip (1), A microcontrol unit (23) receives battery cell data transmitted by the battery management chip (1) via the second communication module (22) and transmits control signals to the battery management chip (1) via the second communication module (22), so that the battery management chip (1) can control the battery cells connected to the battery management chip (1). A second power module (24) is connected to the microcontrol unit (23) and used to supply power to the microcontrol unit (23). The battery management system according to claim 12, comprising:

14. The battery management system according to claim 13, wherein the second communication module (22) comprises a second wireless communication unit, and the second power module (24) is connected to the second wireless communication unit and used to supply power to the second wireless communication unit.

15. A vehicle (3) equipped with the battery management system described in claim 12.

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