Delay analysis system, delay analysis method, and delay analysis program

Abstract

To analyze a delay of a host machine with higher accuracy.SOLUTION: A delay analysis system includes: a host machine that executes both a virtualized controller and a host communication unit which manages communication between the controller and another apparatus; and a delay analysis device that inputs a delay investigation packet for measuring a delay of processing of the host machine, into the host machine, analyzes the delay investigation packet processed by the host machine, and measures the delay of processing of the host machine. The controller processes the delay investigation packet, writes a time stamp on the delay investigation packet, and outputs the packet to the host communication unit. The host communication unit processes the delay investigation packet, writes a time stamp on the delay investigation packet, and outputs the packet to the delay analysis device. The delay analysis device calculates processing time for each unit, based on the time stamp of the controller and the time stamp of the host communication unit which are written on the delay investigation packet.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present disclosure relates to a delay analysis system, a delay analysis method, and a delay analysis program.

Background Art

[0002] As a device for controlling the operation of a control target, there is a host machine (control device) that uses a virtual controller in which a single arithmetic unit virtualizes a plurality of control functions. The control device executes a plurality of control functions with the control software of a plurality of virtual controllers, and processes the data of the plurality of virtual controllers by a virtualization control unit of operating system software (OS (Operating System) software) or virtualization software (such as a hypervisor) on or independent of the OS, and outputs a control signal to the device to be controlled (see Patent Document 1). Further, Patent Document 1 describes predicting the loads of a plurality of virtualized controls and performing load distribution processing.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] <{ Here, even when performing load-distributed processing, it may not be possible to improve the efficiency of the virtual controller. Here, as a process for evaluating the communication delay of an Internet communication network, there is a method of monitoring the processes in each part with a separate monitoring device. When a monitoring device is provided in the virtual controller, a certain processing load occurs in the host machine, and the evaluation is performed in a state different from the actual processing state.

[0005] This disclosure has been made in view of the above-mentioned problems and aims to provide a delay analysis system, a delay analysis method, and a delay analysis program that can analyze the delay of a host machine with higher accuracy. [Means for solving the problem]

[0006] This disclosure provides a delay analysis system comprising: a virtualized controller; a host machine that executes a host communication unit that manages communication between the controller and other devices; and a delay analysis device that inputs delay investigation packets to the host machine to measure the processing delay of the host machine, analyzes the delay investigation packets processed by the host machine, and measures the processing delay of the host machine. The controller processes the delay investigation packets, writes a timestamp to the delay investigation packets, and outputs them to the host communication unit. The host communication unit processes the delay investigation packets, writes a timestamp to the delay investigation packets, and outputs them to the delay analysis device. The delay analysis device calculates the processing time of each unit based on the timestamp of the controller and the timestamp of the host communication unit written to the delay investigation packets.

[0007] This disclosure provides a delay analysis method for analyzing the control delay of a host machine that executes a virtualized controller and a host communication unit that manages communication between the controller and other devices, using a delay measurement device, the method comprising: inputting a delay investigation packet for measuring the processing delay of the host machine to the host machine; the controller processing the delay investigation packet, writing a timestamp to the delay investigation packet, and outputting it to the host communication unit; the host communication unit processing the delay investigation packet, writing a timestamp to the delay investigation packet, and outputting it to the delay analysis device; and calculating the processing time of each unit based on the timestamp of the controller and the timestamp of the host communication unit written to the delay investigation packet.

[0008] This disclosure provides a delay analysis program that causes a delay analysis system, which uses a delay measurement device to analyze the control delay of a host machine running a virtualized controller and a host communication unit that manages communication between the controller and other devices, to perform the following steps: input a delay investigation packet to the host machine to measure the processing delay of the host machine; have the controller process the delay investigation packet, write a timestamp to the delay investigation packet, and output it to the host communication unit; have the host communication unit process the delay investigation packet, write a timestamp to the delay investigation packet, and output it to the delay analysis device; and calculate the processing time of each unit based on the timestamp of the controller and the timestamp of the host communication unit written to the delay investigation packet. [Effects of the Invention]

[0009] This configuration allows for a more accurate analysis of the host machine's latency. [Brief explanation of the drawing]

[0010] [Figure 1] Figure 1 is a block diagram showing an example of the configuration of a delay analysis system. [Figure 2] Figure 2 is a block diagram showing an example of the functional configuration of a delay analysis system. [Figure 3] Figure 3 is an explanatory diagram illustrating an example of the processing of a delay analysis system. [Figure 4] Figure 4 is an explanatory diagram showing an example of the data structure of a packet used for delay investigation. [Figure 5] Figure 5 is a conceptual diagram illustrating an example of delay time evaluation. [Figure 6] Figure 6 is a conceptual diagram illustrating an example of delay time evaluation. [Figure 7] Figure 7 is a conceptual diagram illustrating an example of delay time evaluation. [Figure 8]Figure 8 is a conceptual diagram illustrating an example of delay time evaluation. [Figure 9] Figure 9 is an explanatory diagram illustrating an example of the processing of a delay analysis system. [Figure 10] Figure 10 is an explanatory diagram showing an example of the processing of a delay analysis system. [Modes for carrying out the invention]

[0011] Embodiments relating to this disclosure will be described in detail below with reference to the drawings. However, the present invention is not limited by these embodiments. Furthermore, some of the components in the embodiments described below are substituted or substantially identical to those easily substituted by those skilled in the art. Moreover, the components described below can be combined as appropriate, and if there are multiple embodiments, each embodiment can be combined.

[0012] Figure 1 is a block diagram showing an example of the configuration of a delay analysis system. The delay analysis system 10 includes a host machine 12, a delay analysis device 14, and a synchronization device 16. The delay analysis system 10 analyzes the processing time of each part of the host machine 12 using the delay analysis device 14.

[0013] The host machine 12 performs the function of a virtualization controller that executes multiple controls. The host machine 12 communicates with the controlled devices and outputs control signals generated by the virtualization controller to the controlled devices. The host machine 12 has an arithmetic unit 20, a storage unit 22, and a communication unit 24.

[0014] The arithmetic unit 20 includes integrated circuits (processors) such as a CPU (Central Processing Unit) and a GPU (Graphics Processing Unit), and a memory serving as a work area, and executes various processes by executing various programs using these hardware resources. Specifically, the arithmetic unit 20 reads out the programs stored in the storage unit 22, expands them in the memory, and causes the processor to execute the instructions included in the programs expanded in the memory, thereby executing various processes.

[0015] The storage unit 22 consists of a non-volatile storage device such as a magnetic storage device or a semiconductor storage device, and stores various programs and data. The communication unit 24 transmits data using a communication interface. The communication unit 24 communicates with an external device, and sends and stores various data and programs obtained through the communication to the storage unit 22. The communication unit 24 may be connected to the external device via a wired communication line or a wireless communication line.

[0016] The delay analysis device 14 is a device that acquires information on the processing time of each part executed inside the host machine 12 and analyzes the occurrence of processing delays. The delay analysis device 14 includes an input unit 30, an output unit 32, an arithmetic unit 34, a storage unit 36, and a communication unit 38.

[0017] The input unit 30 includes input devices such as a keyboard, a mouse, a touch panel, or a microphone that collects the speech of the operator, and outputs a signal corresponding to the operation performed by the operator on the input device to the arithmetic unit 34. The output unit 32 includes a display device such as a display, and displays a screen including various information such as a processing result and an image of a processing target based on the display signal output from the arithmetic unit 34. Further, the output unit 32 may include a recording device that outputs data to a recording medium. The communication unit 38 performs transmission and reception of data using a communication interface.

[0018] The arithmetic unit 34 includes integrated circuits (processors) such as a CPU (Central Processing Unit) and a GPU (Graphics Processing Unit), and a memory serving as a working area, and executes various processes by executing various programs using these hardware resources. Specifically, the arithmetic unit 34 reads out the programs stored in the storage unit 36, expands them in the memory, and causes the processor to execute the instructions included in the programs expanded in the memory, thereby executing various processes.

[0019] The storage unit 36 consists of a non-volatile storage device such as a magnetic storage device or a semiconductor storage device, and stores various programs and data. The communication unit 38 communicates with an external device and sends and stores the various data and programs obtained through the communication to the storage unit 36. The communication unit 38 may be connected to the external device through a wired communication line or a wireless communication line.

[0020] The synchronization device 16 communicates with the host machine 12 and the delay analysis device 14, and synchronizes the time functions of the host machine 12 and the delay analysis device 14. The synchronization device 16 synchronizes the time functions of the host machine 12 and the delay analysis device 14 using a high-precision absolute time synchronization method such as PTP (Precision Time Protocol). The host machine 12 and the delay analysis device 14 are input with software (program) for performing time synchronization based on the information obtained from the synchronization device 16, and the synchronization process is performed.

[0021] Figure 2 is a block diagram showing an example of the functional configuration of a latency analysis system. The host machine 12 has multiple virtualization controllers 40, a virtualization host OS unit 42, and a NIC (Network Interface Card) 44. Here, the virtualization OS refers to a host OS having a virtualization control unit, or system software including virtualization software (hypervisor, etc.) independent of the host OS. The multiple virtualization controllers 40 and the virtualization host OS unit 42 are functions realized by executing programs stored in the storage unit 22 in the arithmetic unit 20. The NIC 44 is a function realized in the communication unit 24. The NIC 44 is the host communication unit that manages communication between the virtualization controllers 40 and other devices.

[0022] The virtualization controller 40 includes multiple control software programs 50, a delay investigation packet transmission program 51, and a communication interface 52. In this embodiment, multiple control software programs 50 are used, but one may be used. Also, the control software programs 50 executed on each virtualization controller 40 may be the same or different.

[0023] The control software 50 is a program that executes the functions set on the virtualization controller 40. Multiple control software 50s each execute their respective functions to realize the controller's functionality. The control software 50 executes processing based on data acquired via the virtualization host OS unit 42 and outputs calculated control information. The virtualization controller 40 may process multiple control software 50s in parallel or in conjunction with each other.

[0024] The delay investigation packet transmission program 51 is a program that creates and transmits delay investigation packets used to measure the processing delay of the host machine 12. The delay investigation packet transmission program 51 is the investigation packet creation unit. The delay investigation packet includes an instruction to execute a process to measure the processing delay of the host machine 12, and an area to store information for evaluating the delays acquired by each unit. The delay investigation packet transmission program 51 creates a delay investigation packet that executes a process to evaluate the processing time delay of the control performed by the virtualization controller 40.

[0025] The communication interface 52 is a connection point for virtualized communication and communicates with the virtualized host OS unit 42.

[0026] The virtualization host OS unit 42 communicates with the communication interface 52 of each virtualization controller 40 and with the NIC 44. The virtualization host OS unit 42 is a network in which the virtual bridge 60 and the communication line 62 are software-connected, and it processes the transmission and reception of data between the virtualization controllers 40 and between each virtualization controller 40 and the NIC 44. The virtual bridge 60 acts as a relay for the communication line 62. The virtualization host OS unit 42 can change the connection relationships of the communication line 62, and can change the paths between the virtualization controllers 40 and between each virtualization controller 40 and the NIC 44.

[0027] NIC44 is a connection unit that transmits and receives data with external devices. NIC44 may communicate with external devices via wired or wireless connections. NIC44 also performs processes to establish a connection, such as exchanging IDs with external devices, based on the communication protocol. NIC44 connects to the delay analysis device 14 and devices controlled by the host machine 12.

[0028] The delay analysis device 14 includes a packet receiving unit 70, an analysis unit 72, a delay investigation packet transmission program 74, and a NIC 76. The functions of the packet receiving unit 70, the analysis unit 72, and the delay investigation packet transmission program 74 are realized by executing a program stored in the storage unit 36 ​​in the calculation unit 34. The NIC 76 is a function realized in the communication unit 38.

[0029] The packet receiving unit 70 receives delay investigation packets that have passed through the route to be evaluated. The packet receiving unit 70 outputs the received delay investigation packets to the analysis unit 72.

[0030] The analysis unit 72 analyzes the delay investigation packets output from the packet receiving unit 70 and obtains information on the processing timing at each part through which the delay investigation packets pass. Based on the obtained information on the processing timing at each part, the analysis unit 72 analyzes the processing delay at each part of the host machine 12, including the virtualization controller 40, and at each part of the equipment that communicates with the host machine 12.

[0031] The delay investigation packet transmission program 74 is a program that creates and transmits delay investigation packets used to measure the processing delay of the host machine 12. The delay investigation packet transmission program 74 is the investigation packet creation unit. The delay investigation packet transmission program 74 creates delay investigation packets that measure the time of each process, which are output from the delay analysis device 14 to the host machine 12, reach the virtualization controller 40, and are output from the virtualization controller 40 to the delay analysis device 14.

[0032] NIC76 is a connection unit that transmits and receives data with external devices. NIC76 can communicate with external devices via either wired or wireless connections. NIC76 also performs processes to establish a connection, such as exchanging IDs with external devices, based on the communication protocol. NIC76 connects to the host machine 12.

[0033] Next, we will explain an example of the processing of the delay analysis system using Figure 3. Figure 3 is an explanatory diagram showing an example of the processing of the delay analysis system. Figure 3 shows the case where only the delay (processing time) of one virtualization controller is evaluated, but similar processing can be performed for each of multiple virtualization controllers.

[0034] In the example shown in Figure 3, the delay investigation packet transmission program 51 of the virtualization controller 40 creates a delay investigation packet and executes processing. The host machine 12 and delay analysis device 14 have timestamp units 82, 84, 86, and 88 in each part that processes the delay investigation packet. The timestamp units 82, 84, 86, and 88 are part of the control functions of each part. The timestamp unit 82 is included in the delay investigation packet transmission program 51. The timestamp unit 84 is included in the communication interface 52. The timestamp unit 86 is included in the NIC 44. The timestamp unit 88 is included in the NIC 76. Note that the timestamp unit can be placed in the target for which you want to measure the processing time. For example, it may also be provided in the virtual bridge of the virtualization host OS unit 42. The timestamp units 82, 84, 86, and 88 write information indicating the time of passage to the delay investigation packet as it passes through.

[0035] In the example shown in Figure 3, the delay investigation packet is created by the delay investigation packet transmission program 51, passes through each part of the data path 100, and reaches the packet receiving unit 70. Specifically, after the delay investigation packet is created by the delay investigation packet transmission program 51, it passes through the communication interface 52, then through the virtualization host OS unit 42, and is output from the NIC 44 to the delay analysis device 14. The delay investigation packet is received by the NIC 76 and reaches the packet receiving unit 70.

[0036] The timestamp unit 82 is created by the delay investigation packet transmission program and performs timestamping 102 on delay investigation packets output to the communication interface 52. The timestamp unit 84 performs timestamping 104 on delay investigation packets output from the communication interface 52 to the virtualization host OS unit 42. The timestamp unit 86 performs timestamping 106 on delay investigation packets output from NIC 44 to NIC 76. The timestamp unit 88 performs timestamping 108 on delay investigation packets output from NIC 76 to the packet receiving unit 70.

[0037] Figure 4 is an explanatory diagram showing an example of the data structure of a delay investigation packet. The delay investigation packet 90 passes through the data path 100, and through time stamping processes 102, 104, 106, and 108, multiple timestamps 92, 94, 96, and 98 are stored. The timestamps 92, 94, 96, and 98 include the time when time stamping processes 102, 104, 106, and 108 were performed. Since the data path 100 is defined, the delay investigation packet does not need to include identification information for the stamped timestamp section. By processing the identification information in chronological order, the passage time of each section can be detected. Here, the delay investigation packet may be configured so that the payload of the packet to which a timestamp is added is pre-emptively set aside for adding timestamps, and the packet is added to a predetermined area at each timestamp acquisition point. The method for identifying packets to which timestamps are added can be to add a code for identification to the payload when the socket is created. This allows each timestamp acquisition point to refer to that code and make a determination.

[0038] The delay analysis system 10 repeatedly executes the process shown in Figure 3 and acquires a predetermined number of delay investigation packets containing information on the processing time of each part. Here, the number of repetitions is not particularly limited, but for example, it can be several thousand to tens of thousands of times. The delay analysis device 14 calculates the processing time at each part based on the information obtained by repeatedly executing the same route and the same process. Specifically, it calculates the processing time at each part based on the time difference of the timestamps at each part.

[0039] Figures 5 to 8 are conceptual diagrams illustrating examples of delay time evaluation. The delay analysis device 14 calculates the processing time for each part from the timestamps of each part in the analysis unit 72. Specifically, it calculates the processing time of the processes executed between timestamps from the time difference of the timestamps. The delay analysis device 14 calculates processing time statistics for each process. The calculation results are as shown in Figures 5 to 8, for example. In Figures 5 to 8, the horizontal axis is processing time and the vertical axis is frequency (number of times), respectively. As shown in Figures 5 and 6, if there is little variation in processing time, it can be determined that appropriate processing is being performed. It can also be determined that the process in Figure 6 takes longer than the process in Figure 5. On the other hand, as shown in Figure 7, if there is a lot of variation in processing time, it can be determined that delays may occur. It can also detect sudden delays, as shown in the measurement points within range 120 in Figure 8. The delay analysis device 14 may also set a threshold for delay time and determine the delay based on the threshold. For example, the delay analysis device 14 determines that a delay has occurred if the number of processes in which a delay exceeding a threshold has occurred is greater than or equal to a set number. Alternatively, a threshold may be set for the average delay time, and the determination may be made based on the total delay time. Furthermore, if the delay analysis device 14 determines that a delay has occurred based on the analysis results, it may output a warning. In addition, the delay analysis device 14 may calculate the processing time in real time and output a warning if the measured delay time exceeds a threshold. In other words, it is not limited to multiple processes, but may also determine the delay based on a single process.

[0040] The delay analysis system 10 inputs a delay investigation packet for analyzing delay time to the host machine 12 to be analyzed, processes the delay investigation packet in the processing unit to be analyzed, and writes a timestamp of the processing time to the delay investigation packet in the processing unit. Here, the processing unit includes both a part that processes data and a part that sends and receives data. The delay analysis system 10 can calculate the time taken for processing between the timestamps of the delay investigation packet, which has its timestamp stored in the delay analysis device 14, and can calculate the time taken in each processing unit. This makes it possible to detect the delay time of processing in each part of the host machine 12.

[0041] The delay analysis system 10 can calculate the delay time of each virtualized processing unit on the host machine 12 simply by stamping a timestamp. Furthermore, the delay time analysis device 12 can analyze the delay time of the host machine 12 by analyzing information from delay investigation packets. This eliminates the need for processing time calculation and log acquisition on the host machine, as in conventional processes, thus suppressing the increase in processing load on the host machine 12's arithmetic unit 20 while still allowing for delay time calculation. Additionally, reducing the processing load on the host machine 12's arithmetic unit 20 allows for more accurate analysis of the processing in each part of the host machine 12. By analyzing the delay state in each processing unit with high accuracy and identifying the locations of delays, it becomes easier to appropriately adjust the connection relationships, placement, and settings of the virtualized control units in the virtualization controller and virtualized host OS, thereby making improvements to reduce the delay of the host machine 12 easier.

[0042] Furthermore, the delay analysis system 10 is equipped with timestamp units 82 and 88, which store timestamps at the start and end of processing of delay investigation packets used for determining delay time. This allows for more accurate detection of processing times in each part of the host machine 12.

[0043] Furthermore, the processing time, including the time stamping process of the timestamp section, is sufficiently small compared to the processing time in each processing unit and the processing involved in the passage of data along the data path 100. Therefore, as described above, the processing time of the delay investigation packets can be measured with high accuracy. When considering the impact of the processing time of the timestamp section, timestamps can be obtained before and after the timestamp section, and the packet discrimination and timestamp addition processing can be measured from the difference. Alternatively, delay investigation packets can be obtained when the time stamping process of the timestamp section under evaluation is performed, and when the time stamping process of the timestamp section under evaluation is not performed, and the difference in the total processing time can be calculated as the processing time of the time stamping process of the timestamp section under evaluation.

[0044] The delay analysis device 14 can identify the source of the delay by acquiring delay investigation packets multiple times, detecting the distribution of processing times, and analyzing fluctuations (jitter) in processing timing at each stage of the process.

[0045] Note that the location for acquiring the timestamp is not limited to this embodiment. Furthermore, each processing unit may stamp a timestamp both upon receiving and transmitting the delay investigation packet. This allows for evaluation of the time taken for processing by a single processing unit.

[0046] Furthermore, in this embodiment, a timestamp, which is time information, is written to the delay investigation packet, but delay cause investigation information may also be added to the delay investigation packet. The delay cause investigation information may be written by the delay investigation packet transmission program when the delay investigation packet is created, or it may be written by the timestamp section of each processing unit of the host machine 12 and the delay analysis device 14 along with the time stamping process. Examples of delay cause investigation information include the number of software loops, variable values, CPU usage, and internal error codes. By adding delay cause investigation information to the delay investigation packet, the delay analysis device 14 can analyze the delay state in each processing unit with higher accuracy. For example, if software loop count information is added to the packet as delay cause investigation information, and the number of loops is large in areas with large delays, the analysis results can output delay reduction measures such as reducing the number of loops and distributing the amount processed at once. In addition, by acquiring delay cause investigation information from both the virtualization controller of the host machine and the delay analysis device, if a processing delay occurs, the virtualization controller, the delay analysis device, or both can analyze the related delay causes from the delay cause investigation information.

[0047] The delay investigation packet transmission program may create delay investigation packets that do not include instructions for processing executed by the control software 50, in order to measure the processing time of data transmission and reception in each part. Alternatively, the delay investigation packet transmission program may create delay investigation packets that include instructions executed by the control software 50, in order to compare the processing times in each part.

[0048] Figure 9 is an explanatory diagram illustrating an example of the processing of a delay analysis system. In the example shown in Figure 9, the delay investigation packet transmission program 51 of the virtualization controller 40 creates a delay investigation packet, and the control software executes the processing.

[0049] In the example shown in Figure 9, the delay investigation packet is created by the delay investigation packet transmission program 51, passes through each part of the data path 140, and reaches the packet receiving unit 70. Specifically, the delay investigation packet is created by the delay investigation packet transmission program 51 and input to the control software 50. The delay investigation packet is processed by the control software 50, passes through the delay investigation packet transmission program 51 and the communication interface 52, passes through the virtualization host OS unit 42, and is output from the NIC 44 to the delay analysis device 14. The delay investigation packet is received by the NIC 76 and reaches the packet receiving unit 70.

[0050] Timestamp units 82, 84, 86, and 88, upon detecting a delay investigation packet, determine whether it is a delay investigation packet that should be timed or not. Timestamp units 82, 84, 86, and 88 determine that delay investigation packets created by the delay investigation packet transmission program 51 are delay investigation packets that should be timed. Timestamp unit 82 performs timed processing 102 on delay investigation packets created by the delay investigation packet transmission program 51 and output to the communication interface 52. Timestamp unit 84 performs timed processing 104 on delay investigation packets output from the communication interface 52 to the virtualization host OS unit 42. Timestamp unit 86 performs timed processing 106 on delay investigation packets output from NIC 44 to NIC 76. Timestamp unit 88 performs timed processing 108 on delay investigation packets output from NIC 76 to the packet receiving unit 76.

[0051] By analyzing the delay time of the data path 140 shown in Figure 9, it is possible to analyze the delay time of the data path 142 to which delay investigation packets for processing executed by the control software 51 are sent. Here, the data path 142 consists of control packets that are processed by the control software 50, pass through the communication interface 52, pass through the virtualization host OS unit 42, and are output to the controlled object from the NIC 44, i.e., packets that are not for delay investigation.

[0052] In this way, by using a delay investigation packet that is processed by the control software 50, the delay time of the control software 50 can also be analyzed.

[0053] It is preferable that the delay investigation packets transmitted via data path 140 are packets in which the processing performed by the control software 50 is the same as that performed by the control packets transmitted via data path 142. This makes it possible to analyze the delay of the control software 50 in actual processing.

[0054] The delay analysis system 10 determines in the time stamping units 82, 84, 86, and 88 whether or not a packet is a delay investigation packet for which time stamping is to be performed. This prevents the virtualization controller 40 from performing time stamping on delay investigation packets that control the target, i.e., delay investigation packets passing through the data path 142, thereby reducing the impact on control of the host machine 12 when delay analysis is not being performed.

[0055] In the above embodiment, only the delay (processing time) of one virtualization controller was evaluated, but the delay time can be evaluated in the same way when multiple virtualization controllers are used for coordinated control. For example, a delay investigation packet can pass through one virtualization controller 40, be output to the virtualization host OS unit 42, then input to another virtualization controller 40, pass through it, be output to the virtualization host OS unit 42, and then be output to the packet receiving unit 70. In this case as well, by writing a timestamp to the delay investigation packet as it passes through, the analysis unit 72 can analyze the delay time of each process.

[0056] Figure 10 is an explanatory diagram showing an example of the processing of the delay analysis system. The processing shown in Figure 10 shows an example in which the delay analysis device 14 creates a delay investigation packet using the delay investigation packet creation program 74 and analyzes the delay of the host machine 12. The host machine 12 and the delay analysis device 14 each have timestamp units 84, 86, 88, and 89 in the parts that process the delay investigation packets. The timestamp unit 89 is included in the control software 50.

[0057] In the example shown in Figure 10, the delay investigation packet is created by the delay investigation packet transmission program 74, passes through each part of the data path 150, passes through the host machine 12, and then reaches the packet receiving unit 70. Specifically, after the delay investigation packet is created by the delay investigation packet transmission program 74, it is output from NIC 76 to NIC 44, passes through the virtualization host OS unit 42, passes through the communication interface 52, and reaches the control software 51. After being processed by the control software 51, the delay investigation packet passes through the communication interface 52, passes through the virtualization host OS unit 42, and is output from NIC 44 to the delay analysis device 14. The delay investigation packet is received by NIC 76 and reaches the packet receiving unit 70.

[0058] The timestamp unit 88 performs time stamping 151 on delay investigation packets output from NIC76 to NIC44. The timestamp unit 86 performs time stamping 152 on delay investigation packets output from NIC44 to virtualization host OS unit 42. The timestamp unit 84 performs time stamping 154 on delay investigation packets output from communication interface 52 to control software 50. The timestamp unit 140 performs time stamping 156 on delay investigation packets received by control software 50. The timestamp unit 140 performs time stamping 158 on delay investigation packets output from control software 50 to communication interface 52. The timestamp unit 84 performs time stamping 160 on delay investigation packets output from communication interface 52 to OS unit 42. The timestamp unit 86 performs time stamping 162 on delay investigation packets output from NIC44 to NIC76. The timestamp unit 88 performs time stamping 164 on delay investigation packets output from NIC76 to packet receiving unit 70.

[0059] The delay analysis system 10 creates delay investigation packets using the delay investigation packet transmission program 74 of the analysis processing device 12, inputs them to the host machine 12, processes them in the host machine 12, and outputs the delay investigation packets from the host machine 12 to the analysis processing device 12 via a data path 150 to obtain a timestamp. This allows the system to measure the delay time that occurs in a process similar to the one in the virtualization controller 40, where delay investigation packets are input from the controlled device, processed by the virtualization controller 40, and output to the controlled device. Furthermore, the system can also analyze the delay time between the input of delay investigation packets from the controlled device and their arrival at the virtualization controller 40. This allows for a wider-ranging analysis of delay times that occur in processing between the virtualization controller 40 and the controlled device. The delay analysis system 10 can analyze not only the processing delay of output commands to the controlled device, but also the processing delay of sensor input signals and other signals from the controlled device.

[0060] The delay analysis system 10 of this embodiment can synchronize the time between the host machine 12 and the delay analysis device 14 with high precision by using a synchronization device 16. This eliminates the need to consider differences in the precision of the time set in each processing unit of the virtualization control controller 40, the host machine 12, and the delay analysis device 14, making it easier to calculate the processing time. In this embodiment, the synchronization device 16 is provided separately from the host machine 12 and the delay analysis device 14, but it may be integrated with either the host machine 12 or the delay analysis device 14. In other words, the function for synchronizing the time may be provided in the host machine 12 or the delay analysis device 14. Furthermore, while it is preferable to provide the synchronization device 16 in the delay analysis system 10, it may also be configured without it.

[0061] This disclosure discloses the following inventions, but is not limited to those described below. (1) A delay analysis system comprising: a host machine that executes a virtualized controller and a host communication unit that manages communication between the controller and other devices; a delay analysis device that inputs delay investigation packets to the host machine to measure the processing delay of the host machine, analyzes the delay investigation packets processed by the host machine, and measures the processing delay of the host machine, wherein the controller processes the delay investigation packets, writes a timestamp to the delay investigation packets, and outputs them to the host communication unit; the host communication unit processes the delay investigation packets, writes a timestamp to the delay investigation packets, and outputs them to the delay analysis device; and the delay analysis device calculates the processing time of each unit based on the timestamp of the controller and the timestamp of the host communication unit written to the delay investigation packets.

[0062] This allows each virtualized processing unit on the host machine to calculate its delay time simply by stamping a timestamp. Furthermore, the delay time analysis device can analyze the host machine's delay time by analyzing information from delay investigation packets. This eliminates the need for processing time calculations and log acquisition processes on the host machine, as required in conventional methods, thus suppressing the increase in processing load on the host machine's arithmetic unit while still allowing for delay time calculation.

[0063] (2) The delay analysis device is the delay analysis system described in (1) which acquires a timestamp when the delay investigation packet output from the host machine is received. This makes it possible to more appropriately detect the processing time in each part.

[0064] (3) The delay analysis system according to (1) or (2), wherein the controller, upon receiving the delay investigation packet, creates an area in the delay investigation packet to store a timestamp, and writes the timestamp at the time of creation to the area to store the timestamp. This makes it possible to more appropriately detect the processing time in each part.

[0065] (4) The controller is virtualized and has a virtual communication interface for sending and receiving data with other devices, and the virtual communication interface writes a timestamp of the time of communication to the delay investigation packet when the delay investigation packet is communicated, as described in any of (1) to (3). This makes it possible to detect the processing time in each part more appropriately.

[0066] (5) The delay analysis system according to (1) or (2), wherein the controller has a packet creation unit that creates the delay investigation packet, the packet creation unit creates an area for storing a timestamp in the delay investigation packet, and writes the timestamp at the time the delay investigation packet was created to the area for storing the timestamp. This makes it possible to detect the processing time in each unit more appropriately.

[0067] (6) The delay analysis device has a research packet creation unit that creates the delay investigation packet, the research packet creation unit creates an area for storing a timestamp in the delay investigation packet, and writes the timestamp at the time the delay investigation packet was created to the area for storing the timestamp, the delay analysis system according to (1) or (2). This makes it possible to detect the processing time in each unit more appropriately.

[0068] (7) The delay analysis system according to any one of (1) to (6), wherein the controller determines whether or not it is the delay investigation packet on which a timestamp is written, and the host communication unit determines whether or not it is the delay investigation packet on which a timestamp is written. This reduces the impact on control of the host machine at times other than when delay analysis is being performed.

[0069] (8) The delay analysis system according to any one of (1) to (7), wherein the host machine has a communication unit that transmits and receives data with the delay analysis device, and the communication unit writes a timestamp of the time of communication to the delay analysis packet when the delay analysis packet is transmitted. This makes it possible to detect the processing time in each unit over a wider range.

[0070] (9) A delay analysis system according to any one of (1) to (8), wherein at least one of the timestamps is written together with delay cause investigation information, and the delay analysis device evaluates the processing delay in each part based on the timestamp and delay cause investigation information written in the delay investigation packet. This makes it possible to analyze the processing time in each part with higher accuracy.

[0071] (10) The delay analysis system according to any one of (1) to (9), further comprising a synchronization device that connects to the host machine and the delay analysis device and synchronizes time information with the host machine and the delay analysis device. This allows for more accurate analysis of the processing time in each part.

[0072] (11) A delay analysis method for analyzing the control delay of a host machine that executes a virtualized controller and a host communication unit that manages communication between the controller and other devices, the method comprising: inputting a delay investigation packet for measuring the processing delay of the host machine to the host machine; the controller processing the delay investigation packet and writing a timestamp to the delay investigation packet and outputting it to the host communication unit; the host communication unit processing the delay investigation packet and writing a timestamp to the delay investigation packet and outputting it to the delay analysis device; and calculating the processing time of each unit based on the timestamp of the controller and the timestamp of the host communication unit written to the delay investigation packet.

[0073] This allows each virtualized processing unit on the host machine to calculate its delay time simply by stamping a timestamp. Furthermore, the delay time analysis device can analyze the host machine's delay time by analyzing information from delay investigation packets. This eliminates the need for processing time calculations and log acquisition processes on the host machine, as required in conventional methods, thus suppressing the increase in processing load on the host machine's arithmetic unit while still allowing for delay time calculation.

[0074] (12) A delay analysis program that causes a delay analysis system to perform the following steps: input a delay investigation packet to the host machine to measure the processing delay of the host machine; have the controller process the delay investigation packet, write a timestamp to the delay investigation packet, and output it to the host communication unit; have the host communication unit process the delay investigation packet, write a timestamp to the delay investigation packet, and output it to the delay analysis device; and calculate the processing time of each unit based on the timestamp of the controller and the timestamp of the host communication unit written to the delay investigation packet.

[0075] This allows each virtualized processing unit on the host machine to calculate its delay time simply by stamping a timestamp. Furthermore, the delay time analysis device can analyze the host machine's delay time by analyzing information from delay investigation packets. This eliminates the need for processing time calculations and log acquisition processes on the host machine, as required in conventional methods, thus suppressing the increase in processing load on the host machine's arithmetic unit while still allowing for delay time calculation. [Explanation of Symbols]

[0076] 10. Delay Analysis System 12 Host Machines 14. Delay analyzer 16 Synchronizing device 20, 34 Arithmetic section 22, 36 Storage section 24, 38 Communications Department 30 Input section 32 Output section 40 Virtualization Controllers 42 Virtualization Host OS Section 44, 76 NIC 50. Control software (virtualization control unit) 51, 74 Packet transmission program for delay investigation 52. Communication Interface (Virtualized Communication Interface) 60 Virtual Bridges 62 Communication lines 70 Packet receiving section 72 Analysis Department 82, 84, 86, 88, 89 Timestamp section 90 Packets for Delay Investigation 92, 94, 96 Timestamp data 100, 142, 150 data paths 102, 104, 106, 108, 151, 152, 154, 156, 158, 160, 162, 164 Stamping process

Claims

1. A host machine that executes a virtualized controller and a host communication unit that communicates with the virtualized controller via system software and manages communication between the controller and other devices, The system includes a delay analysis device that inputs delay investigation packets to the host machine to measure the processing delay of the host machine, and analyzes the delay investigation packets processed by the host machine to measure the processing delay of the host machine. The controller processes the delay investigation packet, writes a timestamp to the delay investigation packet, and outputs it to the host communication unit. The host communication unit processes the delay investigation packet, writes a timestamp to the delay investigation packet, and outputs it to the delay analysis device. The delay analysis device is a delay analysis system that calculates the processing time of each part of the host machine through which the delay analysis packet passed, based on the timestamp of the controller and the timestamp of the host communication unit written in the delay analysis packet.

2. The delay analysis system according to claim 1, wherein the delay analysis device acquires a timestamp at the time of reception of the delay investigation packet output from the host machine.

3. The delay analysis system according to claim 1, wherein the controller, upon receiving the delay investigation packet, creates an area in the delay investigation packet for storing a timestamp, and writes the timestamp at the time of creation to the area for storing the timestamp.

4. The controller is virtualized and has a virtual communication interface for sending and receiving data with other devices. The delay analysis system according to claim 1, wherein the virtual communication interface writes a timestamp of the time of communication to the delay investigation packet when the delay investigation packet is communicated.

5. The controller has a survey packet creation unit that creates the delay survey packets, The delay analysis system according to claim 1, wherein the investigation packet creation unit creates an area for storing a timestamp in the delay investigation packet, and writes the timestamp at the time of creation of the delay investigation packet to the area for storing the timestamp.

6. The delay analysis device has a survey packet creation unit that creates the delay survey packets, The delay analysis system according to claim 1, wherein the investigation packet creation unit creates an area for storing a timestamp in the delay investigation packet, and writes the timestamp at the time of creation of the delay investigation packet to the area for storing the timestamp.

7. The controller determines whether or not it is the delay investigation packet on which a timestamp is written. The delay analysis system according to any one of claims 1 to 6, wherein the host communication unit determines whether or not the packet is the delay investigation packet on which a timestamp is written.

8. The host machine has a communication unit that transmits and receives data with the delay analysis device. The delay analysis system according to any one of claims 1 to 6, wherein the communication unit writes a timestamp of the time of communication to the delay investigation packet when the delay investigation packet is communicated.

9. At least one of the aforementioned timestamps is written together with delay cause investigation information. The delay analysis system according to any one of claims 1 to 6, wherein the delay analysis device evaluates the delay of processing in each part based on the delay cause investigation information in addition to the timestamp written in the delay investigation packet.

10. The delay analysis system according to any one of claims 1 to 6, further comprising a synchronization device that connects to the host machine and the delay analysis device and synchronizes time information with the host machine and the delay analysis device.

11. A delay analysis method for analyzing the control delay of a host machine that executes a virtualized controller and a host communication unit that communicates with the virtualized controller via system software and manages communication between the controller and other devices, using a delay analysis device, wherein the delay of the control of the host machine is analyzed by a delay analysis device. The steps include inputting a delay investigation packet to the host machine to measure the processing delay of the host machine, The controller processes the delay investigation packet, writes a timestamp to the delay investigation packet, and outputs it to the host communication unit. The host communication unit processes the delay investigation packet, writes a timestamp to the delay investigation packet, and outputs it to the delay analysis device. A delay analysis method comprising the step of calculating the processing time of each part of the host machine through which the delay investigation packet passed, based on the timestamp of the controller and the timestamp of the host communication unit written in the delay investigation packet.

12. A delay analysis system that uses a delay analysis device to analyze the control delay of a host machine that runs a virtualized controller and a host communication unit that communicates with the virtualized controller via system software and manages communication between the controller and other devices, The steps include inputting a delay investigation packet to the host machine to measure the processing delay of the host machine, The controller processes the delay investigation packet, writes a timestamp to the delay investigation packet, and outputs it to the host communication unit. The host communication unit processes the delay investigation packet, writes a timestamp to the delay investigation packet, and outputs it to the delay analysis device. A delay analysis program that performs the step of calculating the processing time of each part of the host machine through which the delay investigation packet passed, based on the timestamp of the controller and the timestamp of the host communication unit written in the delay investigation packet.

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