Signal generating device and signal generating method

Abstract

It generates a signal with data and frequency transition patterns defined by the standard. [Solution] The signal generator 1 comprises a clock source 2 that generates a clock of a reference frequency, a jitter modulation source 3 that generates a jitter clock modulated with the reference frequency clock generated by the clock source 2, and a signal generator 4 that generates time-series pattern data of a Test Flow defined by a predetermined standard at the timing of the jitter clock in order to perform a Receiver Frequency variation test. The jitter modulation source 3 includes a synchronization signal generation unit 3c that generates a synchronization signal and transmits it to the signal generator 4 when there is an instruction for a frequency transition of the jitter clock. The signal generator 4 generates the jitter clock as a frequency transition pattern in which the frequency of the jitter clock is transitioned in a waveform pattern shape of a clock switch as defined by the standard, at a timing synchronized with the synchronization signal.

Description

Technical Field

[0001] The present invention relates to a signal generation device and a signal generation method for generating a signal for performing a Receiver Frequency variation test defined in the CTS (Compliance Test Specification) of the USB4 v2 Gen4 standard.

Background Art

[0002] An error rate measurement device that inputs a known pattern signal to a measurement object and measures the bit error rate of input data received from the measurement object along with the input of this pattern signal by comparison with the pattern signal has been conventionally known.

[0003] And among this type of error rate measurement devices, for example, as disclosed in Patent Document 1 below, it is composed of a plurality of modules such as a pattern generation module, an error measurement module, a modulation signal generation module, a jitter module, an emphasis module, a multiplexing conversion module, a demultiplexing conversion module, etc., and combines desired modules according to the measurement content to perform various measurements of a measurement object based on the standard in various forms. There is an error rate measurement device.

[0004] Incidentally, the USB standard speed used for communication between computers and devices is constantly increasing. Along with this increase in speed, the testing methods for product devices defined in the standard are also becoming more complex. One such test is the Receiver Frequency Variation Test, which tests the clock fluctuation tolerance of a device in the USB4 v2 Gen4 standard's CTS (Compliance Test Specification). This test is defined in sections 4.3.4, 4.3.5, and 6.3.3 of CTS Revision 0.9. The Test Flow for this test, as shown in the Appendix-Receiver Frequency Variation Test Flow Diagram of CTS Revision 0.9, defines two patterns, TYPE I and TYPE II. The sequence involves successively switching the transmission pattern according to the time series, and while changing the input pattern to the device, the clock frequency transition (clock switch) is performed at specific timings.

[0005] Here, a signal source is necessary for device manufacturers to perform the above tests. The role of a signal source is to generate a signal, but it cannot operate on its own and often requires a separate clock source. When the frequency transition of the clock is required, as in the above test, a device that modulates the clock is also needed in addition to the clock source. One example of such a device is a jitter modulation source. Jitter is a fluctuation in phase, and a jitter modulation source can apply a jitter pattern and fluctuation amount specified by the standard to the input clock and output it. In other words, an error rate measurement device equipped with a clock source, jitter modulation source, and signal source can meet the demand with a single device.

[0006] In the error rate measurement device disclosed in Patent Document 1, the clock source, jitter modulation source, and signal generation source are incorporated as modules into the same device, and therefore, naturally, a certain degree of coordinated operation is possible. Since the control device of the error rate measurement device controls each module, there are no technical challenges here. [Prior art documents] [Patent Documents]

[0007] [Patent Document 1] Patent No. 6651432 [Overview of the project] [Problems that the invention aims to solve]

[0008] However, this control is on the order of hundreds of milliseconds to several seconds. This is because the system structure of the control device is the same as that of a typical computer, and therefore the module is controlled using common communication methods such as Ethernet®, PCIe, and USB. These communication methods do not have mechanisms for finely controlling the timing.

[0009] However, the clock switch is specified in the standard as having a unique pattern shape for its clock waveform (the rising and falling edges of an arc-shaped waveform), and it takes 1.5 μs from start to finish. Therefore, the timing deviation from the data for starting the clock switch can only be up to 6.5 μs.

[0010] However, as mentioned above, the conventional error rate measurement device disclosed in Patent Document 1 cannot coordinate the operation of multiple modules with timing on the order of microseconds. As a result, there was a problem in that the timing data for starting the clock switch was shifted, making it impossible to generate a test signal with data and frequency transition patterns specified in the standard while satisfying the requirements on the order of several microseconds.

[0011] As a result, if a test signal with data and frequency transition patterns specified by the standard is not generated, it becomes difficult for users developing devices under test using the USB standard, etc., to perform smooth testing and debugging, and a solution to this problem was needed.

[0012] Therefore, the present invention has been made in view of the above problems, and aims to provide a signal generating device and a signal generating method that can generate a signal having data and frequency transition patterns specified in a standard. [Means for solving the problem]

[0013] To achieve the above objective, the signal generating device described in claim 1 of the present invention includes a clock source 2 that generates a clock of a reference frequency, A jitter modulation source 3 generates a jitter clock that modulates the reference frequency clock generated by the aforementioned clock source, A signal generator 1 comprising a signal source 4 that generates data of a time-series pattern of a Test Flow defined by a predetermined standard at the timing of the jitter clock in order to perform a receiver frequency variation test, The jitter modulation source includes a synchronization signal generation unit 3c that generates a synchronization signal when there is an instruction for a frequency transition of the jitter clock and transmits it to the signal generation source. The signal source is characterized in that it generates the jitter clock as a frequency transition pattern, with the pattern shape of the waveform of the clock switch defined in the standard, at a timing synchronized with the synchronization signal.

[0014] The signal generating device described in claim 2 of the present invention is the signal generating device of claim 1, The system includes an operation unit 5 for setting the type of pattern for each Flow of the time-series data, the manual or automatic switching method for each Flow, and the transmission time of the pattern for each Flow in the automatic switching method in a tabular pattern setting list 21. The signal source 4 is characterized in that, based on the settings of the operation unit, it generates the time-series pattern data at the timing of the jitter clock and generates the frequency transition pattern at a timing synchronized with the synchronization signal.

[0015] The signal generating device described in claim 3 of the present invention is a signal generating device according to claim 1 or 2, The clock source 2, the jitter modulation source 3, and the signal generation source 4 are characterized by being composed of modules that can be selectively attached to and detached from a plurality of slots 1c provided in the main body 1a of the device.

[0016] The signal generation method described in claim 4 of the present invention includes the step of generating a clock of a reference frequency using a clock source 2, The steps include: generating a jitter clock by a jitter modulation source 3, which modulates the reference frequency clock generated by the aforementioned clock source; To perform a receiver frequency variation test, the signal source 4 generates time-series pattern data of a Test Flow defined by a predetermined standard at the timing of the jitter clock, and The steps include: generating a synchronization signal using the synchronization signal generation unit 3c when an instruction for frequency transition of the jitter clock is given and transmitting it to the signal source, The system is characterized by including a step generated from the signal source as a frequency transition pattern in which the jitter clock is frequency-transformed in a waveform pattern shape of the clock switch as defined in the standard, at a timing synchronized with the aforementioned synchronization signal.

[0017] The signal generation method described in claim 5 of the present invention is the signal generation method of claim 4, The steps include setting the pattern type for each Flow of the time-series data, the manual or automatic switching method for each Flow, and the transmission time of the pattern for each Flow in the automatic switching method in a tabular pattern setting list 21 using the operation unit 5, Based on the settings of the operation unit, generating the data of the time series pattern from the signal generation source 4 at the timing of the jitter clock, and generating the frequency transition pattern from the signal generation source at the timing synchronized with the synchronization signal.

[0018] The signal generation method according to claim 6 of the present invention is the signal generation method according to claim 4 or 5, The clock source 2, the jitter modulation source 3, and the signal generation source 4 , equipped It includes the step of arranging them as modules that can be selectively attached to and detached from a plurality of slots 1c provided in the housing body 1a.

Advantages of the Invention

[0019] According to the present invention, while satisfying the requirement of the order of several μs for the device under test, a test signal having data and a frequency transition pattern defined by a desired standard can be generated, enabling a user developing a device under test using a USB standard or the like to perform smooth testing and debugging.

Brief Description of the Drawings

[0020] [Figure 1] It is a block diagram showing a schematic configuration of a signal generation device according to the present invention. [Figure 2] It is a perspective view showing the appearance of a signal generation device according to the present invention. [Figure 3] It is an example of a pattern setting screen of a signal generation device according to the present invention, showing a pattern setting screen regarding TYPE II of the Test Flow of the CTS standard of USB4 v2 Gen4. [Figure 4] It is a timing chart showing the input / output relationship of the operation unit, the device control unit, the jitter modulation source, and the signal generation source when generating data and a frequency transition pattern defined by the USB4 v2 Gen4 standard by the signal generation device according to the present invention.

Embodiments for Carrying Out the Invention

[0021] The embodiments for carrying out the present invention will be described in detail below with reference to the attached drawings.

[0022] As shown in Figure 1, the signal generator 1 of this embodiment is generally configured to include a clock source 2, a jitter modulation source 3, a signal generation source 4, an operation unit 5, a display unit 6, and a device control unit 7. In order to realize the sequence of the Receiver Frequency variation test, it has the function of generating two patterns of time-series signals (data such as PRBS and PRTS, and a frequency transition pattern in which the clock frequency changes at a specific timing by a clock switch) of Test Flow TYPE I or TYPE II as defined in Appendix - Receiver Frequency variation test flow diagram in the USB4 v2 Gen4 standard CTS.

[0023] Furthermore, this embodiment is not limited to the USB4 v2 Gen4 standard, and the present invention can also be applied to high-speed bus standards (for example, USB4 v2 Gen4 and later standards) that define time-series signals equivalent to the TYPE I and TYPE II signals of the Test Flow described above.

[0024] Furthermore, the object under measurement W incorporates an error detection unit W1 that detects whether or not there are errors in the time-series signal input from the signal source 4 of the signal generator 1.

[0025] As shown in Figure 2, the signal generator 1 consists of a rectangular housing 1a, with an opening 1b formed on the side of the housing 1a. Multiple slots (eight slots in the example in Figure 2) 1c are provided within the opening 1b of the housing 1a.

[0026] The clock source 2, jitter modulation source 3, and signal generation source 4 are composed of modules that can be selectively attached to and detached from slots 1c of the device body 1a. In the example in Figure 2, modules are shown installed in all slots 1c of the device body 1a. In practice, the signal generator 1 functions by selectively installing each of the three modules (clock source 2, jitter modulation source 3, and signal generation source 4) into slots 1c of the device body 1a. Modules necessary to generate signals defined by desired standards (data such as PRBS and PRTS, and frequency transition patterns in which the frequency changes at specific timings due to the clock switch) are installed in appropriate combinations in slots 1c of the device body 1a, and modules can be added, removed, and rearranged.

[0027] Furthermore, by installing an error detector module in slot 1c of the main unit 1a of the device, it can also function as an error rate measuring device that receives the folded signal when a test signal is input to the object under test W and measures the error rate.

[0028] Clock source 2 generates a reference clock (a clock with a reference frequency) under the control of the device control unit 7, which is connected via Ethernet (registered trademark), and consists of FPGA 2a and clock generation unit 2b.

[0029] FPGA2a comprises a module control unit 2aa and a control circuit 2ab. The module control unit 2aa also serves as an interface connecting the device control unit 7 and the control circuit 2ab, outputting instructions (commands) from the device control unit 7 to the control circuit 2ab, and also executing some processing and control within the clock source 2.

[0030] The control circuit 2ab controls the clock generation unit 2b to generate a clock of a reference frequency based on instructions (commands) from the device control unit 7.

[0031] The clock generation unit 2b generates a clock of a reference frequency under the control of the control circuit 2ab based on instructions (commands) from the device control unit 7.

[0032] The jitter modulation source 3 generates a jitter clock with desired modulation applied to the reference frequency clock generated by the clock source 2, under the control of the device control unit 7 which is connected via Ethernet (registered trademark). It consists of an FPGA 3a, a jitter modulation unit 3b, and a synchronization signal generation unit 3c.

[0033] FPGA3a comprises a module control unit 3aa and a control circuit 3ab. The module control unit 3aa also serves as an interface connecting the device control unit 7 and the control circuit 3ab, outputting instructions (commands) from the device control unit 7 to the control circuit 3ab, and also executing some processing and control within the jitter modulation source 3.

[0034] The control circuit 3ab controls the jitter modulation unit 3b in order to generate a jitter clock with a desired modulation applied to the reference frequency clock generated by the clock source 2, based on instructions (commands) from the device control unit 7.

[0035] The jitter modulation unit 3b generates a jitter clock with a desired modulation applied to the reference frequency clock generated by the clock source 2, under the control of the control circuit 3ab based on instructions (commands) from the device control unit 7.

[0036] The synchronization signal generation unit 3c is connected between an unused signal output port of the jitter modulation source 3 and an unused signal input port of the signal generation source 4. These unused ports can be any ports that are not used in the tests specified in the USB4 v2 Gen4 standard, which is the objective of this invention. Specifically, as an unused signal output port of the jitter modulation source 3, for example, the Q Output of the I / Q Output can be used. Also, as an unused signal input port of the signal generation source 4, an input terminal (auxiliary terminal, spare terminal) that can connect to an external device can be used, for example, the Aux Input.

[0037] When the operation unit 5 controls the device control unit 7 and instructs the device control unit 7 to change the frequency of the jitter clock, the synchronization signal generation unit 3c generates a clock switch synchronization signal to synchronize the timing of the modulation start by controlling the FPGA 3a based on the instructions from the device control unit 7 (control of the control circuit 3ab via the module control unit 3aa), and transmits it from an available signal output port of the jitter modulation source 3 to an available signal input port of the signal generation source 4.

[0038] The signal source 4, controlled by the device control unit 7 connected via Ethernet (registered trademark), generates signals defined by the USB4 v2 Gen4 standard (such as pulse pattern signals like PRBS and PRTS based on a desired repeating pattern, and frequency transition patterns whose frequency changes at specific timings due to a jitter clock) for input to the object under test W, using a jitter clock generated by the jitter modulation source 3. The signal source 4 consists of an FPGA 4a and a data multiplexing unit 4b.

[0039] FPGA4a comprises a module control unit 4aa and a control circuit 4ab. The module control unit 4aa also serves as an interface connecting the device control unit 7 and the control circuit 4ab, outputting instructions (commands) from the device control unit 7 to the control circuit 4ab, and also executing some processing and control within the signal source 4.

[0040] The control circuit 4ab outputs a parallel signal, which is the basis for the pattern signal (serial signal) defined in the USB4 v2 Gen4 standard, to the data multiplexing unit 4b, based on instructions (commands) from the device control unit 7.

[0041] The data multiplexing unit 4b multiplexes the parallel signal input from the control circuit 4ab according to the timing of the jitter clock generated by the jitter modulation source 3 to generate a desired serial signal (a signal defined in the USB4 v2 Gen4 standard) and a frequency transition pattern in which the frequency changes at specific timings due to the jitter clock.

[0042] The operation unit 5 consists of various keys, switches, buttons, and soft keys on the display screen of the display unit 6, for example, equipped on the main body of the signal generator 1. The user inputs various information necessary for the signal generator 1 to generate the desired signal (data such as PRBS and PRTS as defined by the USB4 v2 Gen4 standard, and frequency transition patterns in which the frequency changes at specific timings by the clock switch).

[0043] The display unit 6 is composed of display devices such as a liquid crystal display, an EL (electroluminescent) display, or a CRT, and is controlled by the device control unit 7 to display setting items screens related to the generation of desired signals (including the pattern setting screen shown in Figure 3, which will be described later), as well as buttons, soft keys, pull-down menus, input boxes, and other objects for setting various conditions on the setting items screen.

[0044] Here, Figure 3 shows an example of the pattern setting screen 11 for signal source 4. To further explain, Figure 3 is the pattern setting screen 11 for Test Flow TYPE II of the USB4 v2 Gen4 CTS standard.

[0045] At the top of the pattern setting screen 11 in Figure 3, a pull-down menu 12 is displayed for setting the type of signal to be generated. In the pattern setting screen 11 in Figure 3, "PAM3" is selected from the pull-down menu 12. Below this pull-down menu 12, tabs related to signal generation are displayed: "Output," "Emphasis," "Pattern," "Error Addition," "Misc1," and "Misc2." In the pattern setting screen 11 in Figure 3, the "Pattern" tab is selected to set the signal generated by the signal source 4. Below this "Pattern" tab, the item "Test Pattern" related to the test pattern is displayed. In this "Test Pattern," the specification of the signal to be generated is selected from a predetermined list using pull-down menus 13 and 14. In the pattern setting screen 11 in Figure 3, "All List" is selected from the "Test Pattern" pull-down menu 13, and "USB4 Gen4 Rx Frequency Variation Training Sequence" is selected from the pull-down menu 14.

[0046] In the pattern setting screen 11 of Figure 3, the Transmit button 15, Manual button 16, Precoder toggle button (default: OFF) 17, and Polarity Inverse toggle button (default: OFF) 18 are displayed below "Test Pattern".

[0047] The Transmit button 15 starts and stops the transmission of patterns. When pressed from its initial unpressed state, it starts transmitting the pattern, and when pressed again, it stops transmitting the pattern that is currently being sent.

[0048] The Manual button 16 transitions the currently transmitted pattern to the next flow; pressing it will move the currently transmitted pattern to the next flow.

[0049] The Precoder toggle button 17 switches the Precoder ON / OFF. Its initial value is OFF, and each time the Precoder toggle button 17 is pressed, it switches between ON and OFF.

[0050] The Polarity Inverse toggle button 18 switches Polarity Inverse (polarity reversal) ON / OFF. It is initially set to OFF, and each time the Precoder toggle button 18 is pressed, it switches between ON and OFF.

[0051] Below the Transmit button 15, a pull-down menu 19 is displayed for selecting which of the two Test Flow patterns (TYPE I and TYPE II) defined in the CTS standard to use. Note that the pattern setting screen 11 in Figure 3 shows the state when "TYPE II" is selected from the pull-down menu 19.

[0052] In the center of the pattern setting screen 11 in Figure 3, the test sequence configuration 20 is displayed. This test sequence configuration 20 displays the Flow numbers (hereinafter referred to as Flow No.) sequentially in numerical order, and the Clock Freq.Variation (frequency deviation [PPM]) with time on the horizontal axis is displayed on the vertical axis corresponding to the Flow No.

[0053] At the bottom of the pattern setting screen 11 in Figure 3, a tabular pattern setting list 21 corresponding to the test sequence configuration 20 is displayed. The pattern setting list 21 consists of multiple items such as "Flow No." 21a, "Break" 21b, "Pattern" 21c, and "Transmission Time" 21d, and these multiple items are set for each flow.

[0054] "Flow No." 21a indicates the flow number of the entire sequence, corresponding to the test sequence configuration 20, and is displayed in ascending order from #1. In the pattern setting screen 11 of Figure 3, the flow numbers #1, #2, #3, and #4 are displayed in the order of Flow No. #1, Flow #2, TS2clksw, and Flow #4 in the test sequence configuration 20.

[0055] "Break" 21b sets the condition for transitioning to the next flow signal for the target flow to "Manual" or "Auto". "Break" is initially set to "Manual". When "Manual" is set, pressing the Manual button will transition to the next flow. In contrast, when "Auto" is set, the next flow will be transitioned after the time set in "Transmission Time" has elapsed since the start of the flow.

[0056] "Pattern" 21c is set by selecting the pattern to be transmitted from the pull-down menu 22 (22a, 22b, 22c, 22d) for each flow. In the pattern setting screen 11 of Figure 3, the setting ranges for Flow #1, #2, and #4 are PRBSn (n=7, 9, 10, 11, 13, 15, 20, 23, 31) and PRTSn (n=7, 19), the setting range for Flow #3 is fixed to TS2clksw, the initial value of Flow #1 is set to PRBS11, the initial values ​​of Flow #2 and Flow #4 are set to PRTS7, and the initial value of Flow #3 is set to TS2clksw.

[0057] The "Transmission Time" 21d setting determines how long it takes for a Flow to transition to the next Flow after the start of transmitting the Flow signal, for Flows where "Break" is set to "Auto". This is set by entering a numerical value in the input box 23 (23a, 23b, 23c, 23d) for each Flow. In the pattern setting screen 11 in Figure 3, the setting range for Flow #1 to #3 is 10.0 to 20.0 μs (0.1 μs steps), and the setting range for Flow #4 is 1 to 10000 ms (1 ms steps). The initial value for Flow #1 to #3 set to "Auto" is set to 10.0 μs, and the initial value for Flow #4 set to "Auto" is set to 2000 ms.

[0058] In the test sequence configuration 20 in Figure 3, the flow that includes the point where the clock frequency deviation changes (Event Start in the figure) is highlighted so that it can be distinguished from other flows. In the test sequence configuration 20 in Figure 3, TS2clksw, which is shown with diagonal lines, is highlighted so that it can be distinguished.

[0059] Furthermore, in the pattern setting list 21 in Figure 3, to make it clear which Flow pattern is currently being sent, the background of the Flow item to which the sent pattern belongs (the entire row of the relevant Flow: all items) is highlighted.

[0060] Furthermore, in the pattern setting screen 11 in Figure 3, the "Pattern" pull-down menu 22 (22a, 22b, 22c, 22d) allows users to select patterns from a set of PRBS or PRTS with a predetermined number of stages according to the standard, as well as from pseudo-random patterns that the user has arbitrarily set and registered in advance.

[0061] The device control unit 7 provides overall control over the clock source 2, jitter modulation source 3, signal generation source 4, operation unit 5, and display unit 6. Specifically, the device control unit 7 controls the display unit 6 for displaying various setting screens, including the setting screen for the signal generation source 4 shown in Figure 3, and controls the clock source 2, jitter modulation source 3, and signal generation source 4 to generate a reference frequency clock, generate a jitter clock, and generate a desired signal (for example, data and frequency transition patterns defined by a desired standard as shown in Figure 3) based on the operation input of the operation unit 5.

[0062] Next, we will explain the operation when the signal generator 1 configured as described above generates a test signal with data and frequency transition patterns as defined by the USB4 v2 Gen4 standard. Here, we will explain using the case where the signal type defined in the Test Flow of the CTS standard is TYREII as an example.

[0063] To generate a TYPE II signal, select "PAM3" from the pull-down menu 12 as the type of signal to generate in the pattern setting screen 11 shown in Figure 3.

[0064] Next, in the "Test Pattern" section of the pattern setting screen 11 in Figure 3, select "All List" from the pull-down menu 13, and then select "USB4 Gen4 Rx Frequency Variation Training Sequence" from the pull-down menu 14 to set the specifications of the signal to be generated.

[0065] Next, in the pattern setting screen 11 shown in Figure 3, select "TYPE II" from the pull-down menu 19 as the signal type and set it.

[0066] Then, if necessary, press the Precoder switch button 17 and the Polarity Inverse switch button 18 to switch from "OFF" to "ON".

[0067] Next, in the pattern setting list 21 of the pattern setting screen 11 in Figure 3, set Break21b for each Flow No. 21 to "Manual" or "Auto". Here, we set Flow #1, Flow #2, and Flow #4 to "Manual" and Flow #3 to "Auto".

[0068] Next, select and set the "Pattern" 21c for each "Flow No." 21 from the pull-down menu 22 (22a, 22b, 22c, 22d). Here, set Flow #1 to "PRBS11", Flow #2 and Flow #4 to "PRTS7", and Flow #3 to "TSclksw".

[0069] Then, set the "Transmission Time" 21d of the "Flow No." for which "Break" 21b is set to "Auto" by entering numerical values ​​into the input boxes 23 (23a, 23b, 23c, 23d). Here, we set it by entering the numerical value "10.000" μs into the input box 23c of the "Transmission Time" 21d of Flow #3 which is set to "Auto".

[0070] The setup is now complete. After that, when the Transmit button 15 is pressed, the device control unit 7 controls the clock source 2, jitter modulation source 3, and signal generation source 4 according to the settings and transmits a TYPE II signal as defined in the Test Flow of the CTS standard.

[0071] Specifically, when the Transmit button 15 is pressed, signal transmission from the signal source 4 begins, and the PRBS11 signal is transmitted first in Flow #1. This signal transmission starts with the PRBS11 signal in Flow #1 and continues sequentially up to the PRTS7 signal in Flow #4.

[0072] In the pattern setting screen 11 of Figure 3, for rows where the Break column is set to "Manual," pressing the Manual button 16 will trigger the transmission of the signal for the next row. In contrast, for rows where the Break column is set to "Auto," the next transition will occur automatically at the time set by entering a numerical value in the "Transmission Time" input box 23 (23c) 21d.

[0073] Therefore, when the PRBS11 signal in Flow #1 is sent, pressing the Manual button 16 then sends the PRTS7 signal in Flow #2. Furthermore, pressing the Manual button 16 again sends the TS2clksw signal in Flow #3, and within 10μs from the start of sending this TS2clksw signal, the Event Start (clock switch) automatically changes the clock frequency deviation. Then, after 10μs has elapsed, the PRTS7 signal in Flow #4 is sent.

[0074] Thus, in this embodiment, from the user's perspective, it appears as though all control is performed on the signal source 4 side based on the settings in the pattern setting screen 11 of Figure 3. However, in reality, as described above, the clock switch synchronization signal is transmitted from the jitter modulation source 3 to the signal source 4.

[0075] The internal processing related to this will be explained below with reference to Figure 4. Figure 4 is a timing chart showing the input / output relationship between the operation unit, device control unit, jitter modulation source, and signal generator when the signal generator 1 generates data and frequency transition patterns as defined by the USB4 v2 Gen4 standard. Note that in Figure 4, time (vertical axis) progresses from bottom to top, and the horizontal axis of the clock output from the jitter modulation source is frequency.

[0076] In Figure 4, the arrow from the control unit 5 to the device control unit 7 indicates that the control unit 7 receives a press of the Transmit button 15 or Manual button 16 from the control unit 5 due to user operation. When the device control unit 7 receives a press of the Transmit button 15 or Manual button 16 from the control unit 5, it sends a Transmit or Manual signal to the signal source 4. However, this only happens when the "Flow No." is anything other than #2, i.e., when the next Flow is not TS2clksw.

[0077] When the signal source 4 receives a Transmit or Manual signal from the device control unit 7, it begins transmitting a preset pattern. At that time, a certain amount of time is required between receiving the Transmit or Manual signal from the device control unit 7 and the actual transmission of the pattern. Here, we assume this time is set to 10 μs.

[0078] Here, we will explain the operation when the next flow is TS2clksw. When the next flow is TS2clksw, the device control unit 7 sends a signal to the jitter source 3 instead of the signal source 4. This signal is a signal instructing the start of the clock switch. When the jitter source 3 receives the signal from the device control unit 7 instructing the start of the clock switch, it starts the operation of the clock switch.

[0079] However, the clock switch does not occur immediately at this time. FPGA3a, the jitter source 3, has an internal timer, and the clock switch is generated when this timer has elapsed for a specified period of time. In other words, the signal from the device control unit 7 acts as the start trigger for this timer.

[0080] Specifically, let's assume the timer is set to 13μs. Also, as soon as the timer is started, the synchronization signal generation unit 3c of the jitter source 3 transmits the generated clock switch synchronization signal to the FPGA 4a of the signal source 4.

[0081] As a result, FPGA4a of signal source 4 switches its pattern to TS2clksw after 10μs, similar to when it receives a Transmit or Manual signal from the device control unit 7, and a clock switch occurs 13μs after a certain point in time. Therefore, the clock switch occurs 3μs after switching to TS2clksw.

[0082] Furthermore, when the signal source 4 generates signals in the order of Flow No. (PRBS11 → PRTS7 → TS2clksw → PRTS7), this fact is notified to the device control unit 7 (in Figure 4, arrows #1, #2, #3, and #4 point from the signal source 4 to the device control unit 7). Also, since the above value of 13μs can be changed on the pattern setting screen 11, the clock switch can be generated at any desired timing.

[0083] Furthermore, the delay caused by the additional path that transmits the clock switch synchronization signal from the synchronization signal generation unit 3c of the jitter modulation source 3 to the FPGA 4a of the signal generation source 4 is only tens to hundreds of nanoseconds, even including the internal operation delay of FPGA 4a. Therefore, it is possible to generate a signal with data and frequency transition patterns as defined by the USB4 v2 Gen4 standard while satisfying the USB4 v2 Gen4 standard's requirement of several microseconds.

[0084] Thus, according to this embodiment, multiple modules (clock source 2, jitter modulation source 3, signal generation source 4) can be operated in coordination with timing in the microsecond range. Therefore, manufacturers (users) developing devices under test using the USB standard, etc., can obtain test signals with data and frequency transition patterns specified by the desired standard while satisfying the requirements of several microseconds for the device under test, using one or more measuring instruments that use common communication means such as Ethernet®, PCIe, or USB for control.

[0085] Furthermore, according to this embodiment, it is possible to generate a test signal with data and frequency transition patterns defined by a desired standard, enabling users developing devices under test using the USB standard or the like to perform smooth testing and debugging.

[0086] Furthermore, according to this embodiment, from the user's perspective, all control appears to be performed on the signal source 4 side based on the settings in the pattern setting screen 11 of Figure 3. Therefore, the operating mechanism, in which the clock switch synchronization signal is transmitted from the jitter modulation source 3 to the signal source 4, allows the system to be used without the user being aware of its internal operation, resulting in a synergistic effect that improves user convenience.

[0087] The best mode of the signal generating device and signal generating method according to the present invention has been described above, but the present invention is not limited by this description and drawings. That is to say, all other modes, examples, and operating techniques based on this mode by those skilled in the art are of course included in the scope of the present invention. [Explanation of Symbols]

[0088] 1. Signal Generator 1a Main unit of the device 1b opening 1c slot 2 clock sources 2a FPGA 2aa Module Control Unit 2ab control circuit 2b Clock generation unit 3. Jitter Modulation Source 3a FPGA 3aa Module Control Unit 3ab control circuit 3b Jitter Modulation Section 3c Synchronization signal generation section 4. Signal source 4a FPGA 4aa Module Control Unit 4ab control circuit 4b Data Multiplexing Unit 5 Control section 6 Display section 7. Device Control Unit 11 Pattern setting screen 12, 13, 14 Pull-down menu 15 Transmit button 16 Manual buttons 17 Precoder Switch Button 18 Polarity Inverse toggle button 19. Pull-down menu 20 Test Sequence Configuration 21 Pattern Settings List 21a Flow No. (Flow Number) 21b Break 21c Pattern 21d Transmission Time 22 (22a, 22b, 22c, 22d) Pull-down menu 23(23a,23b,23c,23d) Input Box W Object to be measured W1 Error detection unit

Claims

1. A clock source (2) that generates a clock of a reference frequency, A jitter modulation source (3) generates a jitter clock that modulates the reference frequency clock generated by the aforementioned clock source, A signal generator (1) comprising a signal source (4) that generates data of a time-series pattern of a Test Flow defined by a predetermined standard at the timing of the jitter clock in order to perform a Receiver Frequency variation test, The jitter modulation source includes a synchronization signal generation unit (3c) that generates a synchronization signal when there is an instruction for a frequency transition of the jitter clock and transmits it to the signal generation source. The signal generator is characterized in that the signal source generates the jitter clock as a frequency transition pattern, with the pattern shape of the waveform of a clock switch as defined in the standard, at a timing synchronized with the synchronization signal.

2. The system includes an operation unit (5) for setting the type of pattern for each flow of the time-series data, the manual or automatic switching method for each flow, and the transmission time of the pattern for each flow in the automatic switching method in a tabular pattern setting list (21). The signal generating device according to claim 1, characterized in that the signal generating source (4) generates data of the time series pattern at the timing of the jitter clock based on the settings of the operation unit, and generates the frequency transition pattern at a timing synchronized with the synchronization signal.

3. The signal generating device according to claim 1 or 2, characterized in that the clock source (2), the jitter modulation source (3), and the signal generating source (4) are composed of modules that can be selectively attached to and detached from a plurality of slots (1c) provided in the main body of the device (1a).

4. The steps include generating a clock of reference frequency using a clock source (2), The steps include: generating a jitter clock by a jitter modulation source (3) which modulates the reference frequency clock generated by the aforementioned clock source; A step in which, in order to perform a Receiver Frequency variation test, data of a time-series pattern of a Test Flow defined by a predetermined standard is generated by a signal source (4) at the timing of the jitter clock, The steps include: generating a synchronization signal using a synchronization signal generation unit (3c) when an instruction for frequency transition of the jitter clock is given and transmitting it to the signal source; A signal generation method characterized by including a step generated from the signal source as a frequency transition pattern in which the jitter clock is frequency-transformed in the waveform pattern shape of a clock switch as defined in the standard, at a timing synchronized with the aforementioned synchronization signal.

5. The steps include setting the pattern type for each Flow of the time-series data, the manual or automatic switching method for each Flow, and the transmission time of the pattern for each Flow of the automatic switching method in a tabular pattern setting list (21) using the operation unit (5), The signal generation method according to claim 4, characterized in that it includes the steps of generating time-series pattern data from the signal source (4) at the timing of the jitter clock based on the settings of the operation unit, and generating the frequency transition pattern from the signal source at a timing synchronized with the synchronization signal.

6. The signal generation method according to claim 4 or 5, characterized in that it includes the step of arranging the clock source (2), the jitter modulation source (3), and the signal generation source (4) as modules that can be selectively attached to and detached from a plurality of slots (1c) provided in the main body of the device (1a).

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