Silicon carbide planar MOSFET element and method for manufacturing the same

Abstract

The present invention provides a planar silicon carbide MOSFET element and a manufacturing method thereof, which can effectively use the crystal planes of the SiC crystal with high channel mobility, such as the (1120) crystal plane, (1100) crystal plane, or (0338) crystal plane, by providing several shallow trenches while the channel current is still parallel to the (0001) crystal plane of the SiC crystal, and can effectively reduce the channel resistance of the planar silicon carbide MOS element. In addition, the formation of the source region, well region, and channel does not require protection by an additional ion implantation layer (IMP layer), and the process is simplified.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices and their manufacturing, and particularly to planar silicon carbide MOSFET devices and their manufacturing methods.

Background Art

[0002] Silicon carbide (SiC) MOSFET (Metal Oxide Semiconductor Field Effect Transistor) devices have advantages such as fast switching speed and low on-resistance. Moreover, a high breakdown voltage level can be achieved with a small drift layer thickness, reducing the volume of power switch modules, reducing energy consumption, and showing obvious advantages in application fields such as power switches and converters.

[0003] Planar SiC-MOSFET devices are widely applied due to advantages such as simple processes, high cell alignment, and relatively high avalanche energy. However, how to further improve the performance of planar SiC-MOSFET devices has become one of the hot issues being studied by those skilled in the art.

Summary of the Invention

[0004] An object of the present invention is to provide a planar silicon carbide MOSFET device and its manufacturing method that can improve the performance of planar SiC-MOSFET devices.

[0005] To achieve the above object, the present invention provides a silicon carbide drift layer of the first conductivity type with the top surface being the (0001) crystal plane, a gate oxide layer and a gate electrode sequentially stacked on the top surface of the silicon carbide drift layer, A second conductivity type well region formed on the surface layer of the silicon carbide drift layer on both sides of the gate electrode, and a first conductivity type source region formed within the surface layer of the well region on both sides of the gate electrode, The trench includes, formed in the silicon carbide drift layer at the bottom of the gate electrode, and extending toward both sides of the gate electrode to the boundary between the source region and the well region, wherein the bottom of the trench is shallower than the bottom of the well region, and the two sidewall surfaces extending in the width direction of the gate electrode are both crystal planes where the channel mobility is higher than the (0001) crystal plane, The invention provides a planar silicon carbide MOSFET element in which the gate oxide layer covers at least the inner surface of the trench, and the gate electrode fills the trench.

[0006] Selectively, crystal planes in which the channel mobility is higher than that of the (0001) crystal plane include the (112-0) crystal plane, the (11-00) crystal plane, or the (03-38) crystal plane.

[0007] Selectively, the multiple trenches are arranged in parallel in sequence along the length of the gate electrode, spaced apart, and any two trenches do not communicate with each other, or at least two trenches communicate in corresponding regions.

[0008] Selectively, the bottom depth of the trench is smaller than the bottom depth of the source region.

[0009] Selectively, the planar silicon carbide MOSFET element further includes a medium structure formed in a portion of the trench, the gate oxide layer covers the inner surface of the trench on the outer periphery of the medium structure, and the gate electrode further embeds the medium structure.

[0010] Selectively, the uppermost part of the media structure is higher than the uppermost part of the gate oxide layer on the outer circumference of the trench, and the gate electrode covers the media structure to conform to its shape, forming a projection or having a flat upper surface.

[0011] Selectively, the planar type silicon carbide MOSFET element is Source electrodes formed on the (0001) crystal planes of the silicon carbide drift layer on both sides of the gate electrode and electrically connected to the source region, A first conductive buffer layer is laminated on the bottom surface of the silicon carbide drift layer, A first conductive base laminated on the bottom surface of the buffer layer, The base further includes a drain electrode stacked on the bottom surface of the base.

[0012] Based on the same inventive concept, the present invention is A step of preparing a substrate having a first-type conductive silicon carbide drift layer, wherein the uppermost surface of the silicon carbide drift layer is a (0001) crystal plane, A step of etching the uppermost surface of the silicon carbide drift layer in the region where a gate electrode is to be formed to form at least one trench, wherein the trench extends toward both sides of the gate electrode to be formed to the boundary between the source region boundary and the well region boundary, the bottom of the trench is shallower than the bottom of the well region, and the two sidewall surfaces of the trench extending in the width direction of the gate electrode to be formed are both crystal planes in which the channel mobility is higher than the (0001) crystal plane, The present invention further provides a method for manufacturing a planar silicon carbide MOSFET element, comprising the steps of sequentially forming a gate oxide layer and a gate electrode on the uppermost surface of the silicon carbide drift layer, wherein the gate oxide layer covers at least the inner surface of the trench and the gate electrode fills the trench.

[0013] Selectively, before etching the uppermost surface of the silicon carbide drift layer in the region where the gate electrode is to be formed to form at least one trench, first, the well region of the second conductivity type and the source region of the first conductivity type are formed on the uppermost surface of the silicon carbide drift layer, the well region being formed within the surface layer of the uppermost surface of the silicon carbide drift layer on both sides of the gate electrode, and the source region being formed within the surface layer of the well region on both sides of the gate electrode. Alternatively, after the formation of at least one trench, and before or after the formation of the gate electrode, the well region and the source region are formed on the uppermost surface of the silicon carbide drift layer.

[0014] Selectively, the substrate further comprises a buffer layer of a first conductivity type and a base of a first conductivity type, which are sequentially laminated on the bottom surface of the silicon carbide drift layer, and the manufacturing method is The step of forming a source electrode electrically connected to the source region on the uppermost surface of the silicon carbide drift layer, The further step includes forming a drain electrode on the bottom surface of the base.

[0015] Compared to the prior art, the technical solution of the present invention has at least one of the following beneficial effects.

[0016] 1. In addition to ensuring that the device remains a planar silicon carbide MOSFET device, primarily using the (0001) crystal plane of the silicon carbide crystal as the channel, and that the channel current remains parallel to the (0001) crystal plane of the SiC crystal, by providing several shallow trenches, crystal planes with high channel mobility of the silicon carbide crystal, such as the (112-0) crystal plane, the (11-00) crystal plane, or the (03-38) crystal plane, can be utilized more effectively, and the channel resistance of the planar silicon carbide MOS device can be effectively reduced.

[0017] 2. The trench bottom depth is shallower than the source or well area, eliminating the need for protection by an additional ion implantation layer (IMP layer), thus simplifying the process.

[0018] 3. The degree of reduction in the channel resistance Ron or Rsp is associated with the trench density and has a more obvious beneficial effect on planar MOSFET elements applied at 1700V or less. For example, when the solution of the present invention is applied to a 750V planar silicon carbide MOSFET element, the channel resistance Ron or Rsp can be reduced by 30%.

Brief Description of the Drawings

[0019] As can be understood by those skilled in the art, the provided drawings are for better understanding of the present invention and do not limit the scope of the present invention in any way. [Figure 1] It is a schematic plan view of the planar structure of a conventional planar SiC MOSFET element. [Figure 2] It is a schematic cross-sectional structure view along the line AA' in FIG. 1. [Figure 3] It is a schematic view of the crystal plane of the SiC crystal. [Figure 4] It is a schematic graph view of the relationship between the channel mobility and the gate voltage of different crystal planes of the SiC crystal. [Figure 5] It is a schematic plan view of the planar structure of a planar silicon carbide MOSFET element according to an embodiment of the present invention. [Figure 6] It is a schematic cross-sectional structure view along the line AA' in FIG. 5. [Figure 7] It is a schematic cross-sectional structure view along the line BB' in FIG. 5. [Figure 8] It is a schematic cross-sectional structure view along the line CC' in FIG. 5. [Figure 9] It is a schematic cross-sectional structure view of a planar silicon carbide MOSFET element according to another embodiment of the present invention. [Figure 10] It is a schematic cross-sectional structure view of a planar silicon carbide MOSFET element according to yet another embodiment of the present invention. [Figure 11]This is a schematic diagram of the trench structure in a planar silicon carbide MOSFET device according to yet another embodiment of the present invention. [Figure 12] This is a schematic diagram of the cross-sectional structure of a multi-stage trench in a planar-type silicon carbide MOSFET element of another embodiment of the present invention. [Figure 13] This is a schematic diagram of the cross-sectional structure of a multi-stage trench in a planar-type silicon carbide MOSFET element of another embodiment of the present invention. [Figure 14] This is a flowchart showing a method for manufacturing a planar silicon carbide MOSFET element, a specific embodiment of the present invention. [Figure 15] This is a schematic diagram of the cross-sectional structure of a planar silicon carbide MOSFET device in a manufacturing method for a specific embodiment of the present invention. [Modes for carrying out the invention]

[0020] The following descriptions provide many specific details to further enhance the understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, some technical features well known in the art are omitted to avoid confusion with the present invention. It should be understood that the present invention can be implemented in various forms and should not be construed as being limited to the embodiments shown herein. Rather, these embodiments are provided to make the disclosure sufficient and complete and to fully convey the scope of the present invention to those skilled in the art. In the drawings, for clarity, the dimensions of layers and areas and relative dimensions may be exaggerated. The same reference numerals represent the same element from beginning to end. It should be understood that when an element or layer is said to be "on top of" or "connected to" another element or layer, it may be directly on or connected to the other element or layer, or there may be an intermediate element or layer. Conversely, when an element is said to be "directly on top of" or "directly connected to" another element or layer, there is no intermediate element or layer. Various elements, components, regions, layers, and / or parts can be described using terms such as the first, second, etc., but these elements, components, regions, layers, and / or parts should not be limited to these terms. These terms are merely for distinguishing one element, component, region, layer, or part from another. Therefore, without departing from the implications of the present invention, the first element, component, region, layer, or part considered below may be represented as the second element, component, region, layer, or part. Spatial terms, such as "below...", "on the bottom," "on the bottom," "on top," "on the top," "on the top surface," "on the bottom," "on the front," "on the back," etc., are used here to facilitate explanation and can describe the relationship between one element or feature shown in the figure and another element or feature. It should be understood that spatial terms are intended to include other orientations of the element during use and operation, other than the orientation shown in the figure.For example, if an element in a drawing is inverted, an element or feature described as "below...", "on the bottom," "on the bottom," "on the back," or "on the top" of another element or feature will have an orientation that is "on top," "top," or "positive" of the other element or feature. The element may have a different orientation (rotated 90 degrees or another orientation), and the spatial descriptive terms used herein will be interpreted accordingly. The terms used herein are merely for the purpose of describing specific embodiments and do not limit the invention. Where used herein, the singular forms "one," "one," and "the / the" are also intended to include the plural unless otherwise specified in the context. It should be further understood that the term "includes" clarifies the presence of features, steps, operations, elements, and / or members, but does not exclude the presence or addition of one or more other features, steps, operations, elements, members, and / or groups. Where used herein, the term "and / or" includes any and all combinations of the related items listed.

[0021] The technical solutions of the present invention will be described in more detail below with reference to the drawings and specific embodiments. The advantages and features of the present invention will become clearer with the following description. It should be noted that the drawings are all in a highly simplified form and use imprecise proportions, and are used solely to easily and clearly illustrate embodiments of the present invention.

[0022] Referring to Figures 1 and 2, the structure of a conventional planar SiC-MOSFET element includes, in order from bottom to top, a drain electrode 107, an N++ base 100a, an N+ buffer layer 100b, an N-drift layer 100c, a gate oxide layer 104, and a gate electrode 105. It further includes a P-well 101 formed within the N-drift layer 100c, an N+ source region 102 and a P+ contact region 103 formed within the P-well 101 (also called the P-base region), and a source electrode 106 formed on the N-drift layer 100c. The source electrode 106 electrically contacts the N+ source region 102 and the P+ contact region 103, thereby short-circuiting the N+ source region 102 and the P+ contact region 103.

[0023] In the above-described planar SiC-MOSFET device, the channel (unsigned) is located in the region overlapping with the P-well 101 at the bottom of the gate electrode 105. When operating in the forward direction, if the gate voltage is forward-biased and exceeds its threshold, an inversion layer is formed, the channel is turned on, and electrons flow sequentially from the source electrode 106 through the N+ source region 102 and the channel, reaching the depletion region (also called the JFET region, i.e., located below the bottom of the gate electrode 105 and in the N-drift layer 100c between the two P-wells 101), then flowing downward through the N-drift layer 100c, the N+ buffer layer 100b and the N++ base 100a, finally reaching the drain electrode 107. When the gate electrode 105 and the source electrode 106 are short-circuited and the drain electrode 107 is forward-biased, a reverse-bias depletion region is formed by the P-well 101 and the N-drift layer 100c. Since the P-type ion doping concentration in the P-well 101 is greater than the N-type ion doping concentration in the N-drift layer 100c, the reverse-bias depletion region mainly extends to the N-drift layer 100c, reaching a high breakdown voltage.

[0024] However, the above-mentioned planar type SiC-MOSFET element has several drawbacks. Specifically, conventional planar type SiC-MOSFET elements are usually manufactured from 4H-SiC crystals, and the distribution of crystal planes and orientations of the 4H-SiC crystal is shown in Figure 3. Due to the influence of the 4H-SiC epitaxial (EPI) crystal orientation, the gate electrode 105 of the above-mentioned planar type SiC-MOSFET element is always on the (0001) crystal plane of the SiC crystal. The (0001) crystal plane has many interface states, and as shown in Figure 4, the channel mobility is only 1 / 3 of that of the (112-0) crystal plane and the (11-00) crystal plane. For this reason, planar type SiC-MOSFET elements have high channel resistance. Furthermore, the stray capacitance of such a structure is also large. The (112-0) crystal plane and the (11-00) crystal plane are pyramidal planes perpendicular to the (0001) crystal plane.

[0025] Furthermore, in conventional technology, there are very few wafers in which crystal planes with high channel mobility, such as the (112°0), (11°00), and (03°38°) crystal planes of SiC crystals, have been epitaxially formed. Even if it is possible to epitaxially form crystal planes with high channel mobility, such as the (112°0), (11°00), and (03°38°) crystal planes of SiC crystals, the epitaxial defects spread directly across the entire wafer surface, resulting in large leakage currents in the fabricated devices and degraded electrical performance.

[0026] Therefore, the present invention provides a novel planar-type SiC-MOSFET device structure design and manufacturing method, which, in addition to the gate electrode being on the (0001) crystal plane of the SiC crystal, can more effectively utilize other crystal planes with high channel mobility of the SiC crystal, such as the (112-0), (11-00), and (03-38) crystal planes, thereby reducing channel resistance and improving device performance. Furthermore, the stray capacitance of the device is also further reduced.

[0027] Referring to Figures 5 to 8, one embodiment of the present invention provides a planar silicon carbide MOSFET element comprising a drain electrode 107 stacked in order from bottom to top (i.e., from the bottom surface to the top surface), a base 100a, a buffer layer 100b, a silicon carbide drift layer 100c, a gate oxide layer 104, and a gate electrode 105.

[0028] Here, the base 100a, the buffer layer 100b, and the silicon carbide drift layer 100c are all of the first conductivity type (e.g., N-type), and the doping concentration of the first conductivity type impurities decreases sequentially.

[0029] The SiC crystal in the silicon carbide drift layer 100c is a hexagonal crystal such as 4H-SiC or 6H-SiC, and the uppermost surface (which may also be called the front) of the silicon carbide drift layer 100c is the (0001) crystal plane of the SiC crystal. A well region 101 of a second conductivity type (e.g., P-type) is formed in the surface layer of the uppermost surface of the silicon carbide drift layer 100c on both sides of the gate electrode 105, a source region 102 of a first conductivity type is formed in the surface layer of the uppermost surface of each well region 101, and a body contact region 103 of a second conductivity type is formed in the well region 101 on the outer periphery of the source region 102. The doping concentration of the first conductivity type impurity in the source region 102 and the doping concentration of the second conductivity type impurity in the body contact region 103 are greater than the doping concentration of the second conductivity type impurity in the well region 101.

[0030] The source electrode 106 is formed on the surface of the source region 102 and the main body contact region 103, and electrically connects the main body contact region 103 and the source region 102, making them equipotential. The drain electrode 107 is laminated on the bottom surface of the base 100a (i.e., the back surface of the base 100a). Both the source electrode 106 and the drain electrode 107 may be made mainly of metal, and the material may be selected from Al, AlCu, or AlSiCu.

[0031] In this embodiment, the gate electrode 105, source region 102, and well region 101 are all arranged to exhibit a parallel, stripe-like structure. The material of the gate electrode 105 may include doped polysilicon, and the conductivity type of the gate electrode 105 may be opposite to that of the silicon carbide drift layer 100c.

[0032] At least one trench 100d is provided within the silicon carbide drift layer 100c below the bottom of the gate electrode 105, and all of these trenches 100d are located in the direction of the crossing of the channel currents (for example, as shown by the dotted arrows in Figure 6). If there are multiple trenches 100d, they are formed at intervals in the direction of the crossing of the channel currents (for example, as shown by the dotted arrows in Figure 6). The bottom of each trench 100d is shallower than the bottom of the well region 101, and selectively, the bottom of each trench 100d is shallower than the bottom of the source region 102. For example, the bottom depth of each trench 100d (i.e., the height from the top surface of the silicon carbide drift layer to the bottom surface of the trench 100d) is less than 1000 Å.

[0033] The shape of each trench 100d may be any suitable shape, such as a rectangular prism or a trapezoid. Each trench 100d extends toward both sides of the gate electrode 105 to the boundary between the source region 102 and the boundary of the well region 101, that is, the length w of the trench 100d extending in the width direction of the gate electrode (i.e., the AA' or BB' direction in Figure 5) is between the gap a between the well regions 101 and the gap b between the source regions 102 on both sides of the gate electrode 105, i.e., a <w<bである。

[0034] The crystal planes of the two sidewall surfaces S1 and S2 extending in the width direction of the gate electrode 105 of each trench 100d are all crystal planes in the SiC crystal where the channel mobility is higher than that of the (0001) crystal plane, such as the (112-0) crystal plane, (11-00) crystal plane, or (03-38) crystal plane of the SiC crystal. In other words, the sidewall surfaces S1 and S2 are parallel to the (112-0) crystal plane, (11-00) crystal plane, or (03-38) crystal plane of the SiC crystal in the silicon carbide drift layer 100c. Referring to Figure 3, the (112-0) crystal plane and the (11-00) crystal plane of the SiC crystal are both pyramidal planes perpendicular to the (0001) crystal plane of the SiC crystal, and the channel mobility of the (112-0) crystal plane and the (11-00) crystal plane is about three times that of the (0001) crystal plane. The (03-38) crystal plane of a SiC crystal is a crystal plane that makes an angle of approximately 55° or 54.74° with the (101-0) crystal plane of a SiC crystal. The (101-0) crystal plane of a SiC crystal is parallel to the (0001) crystal plane of a SiC crystal.

[0035] It should be understood that the two sidewall surfaces S1 and S2 of each trench 100d may be parallel to the width direction AA' of the gate electrode, or they may intersect due to process errors, but the angle between them may be limited to an acceptable range. In other words, the angle between the two sidewall surfaces S1 and S2 of trench 100d and the AA' direction is 90, as long as it is guaranteed that the crystal planes of the sidewall surfaces S1 and S2 are crystal planes with high channel mobility, such as the (112-0) crystal plane, the (11-00) crystal plane, or the (03-38) crystal plane. o It doesn't have to be that way.

[0036] Selectively, in other embodiments of the present invention, to reduce the stray capacitance of the gate electrode 105, referring to Figure 9, the planar silicon carbide MOSFET element further includes a media structure 108, which is formed in a portion of the trench 100d and used to raise the bottom of the gate electrode 105, and a gate oxide layer 104 covers the inner surface of the trench 100d on the outer periphery of the media structure 108 and the exposed surface of the source region 102, and the gate electrode 105 further embeds the media structure 108. The media structure 108 is made of an insulating media material, which is selected from one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, high-K materials, spin-coated dielectric materials (e.g., spin-coated phosphate silicate glass, borosilicate glass, or fluorine-doped silica glass, etc.), and low dielectric constant dielectric materials. By installing the media structure 108 described above, the distance between the gate electrode 105 and the drain electrode 107 increases, which directly corresponds to an increase in the distance between the two electrodes of the gate-drain capacitance (Cgd). This effectively reduces Cgd, i.e., the feedback capacitance or Miller capacitance, thereby reducing application losses. As an example, as shown in Figure 9, the top of the media structure 108 is higher than the top of the gate oxide layer 104 on the outer periphery of the trench 100d, and the gate electrode 105 covers the media structure 108 and the gate oxide layer 104 to conform to its shape, and further forms a protrusion (not indicated). As another example, as shown in Figure 10, the top of the media structure 108 is higher than the top of the gate oxide layer 104 on the outer periphery of the trench 100d, and the gate electrode 105 further embeds the media structure 108 and has a flat top.

[0037] Referring to Figures 5 to 10, in each of the above embodiments, the formed trenches 100d are arranged in parallel in order along the length of the gate electrode 105 and may be provided at equal or unequal intervals, provided that no two trenches 100d are in communication with each other, and in this case, these trenches 100d are formed at intervals in the direction of the crossing of the channel currents. However, the technical solutions of the present invention are not limited to this. In another embodiment of the present invention, referring to Figure 11, these trenches 100d are arranged in parallel in order along the length of the gate electrode 105 and may be provided at intervals, provided that at least two trenches 100d are in communication with each other in corresponding regions (e.g., end or intermediate portion). These communicating trenches 100d may be adjacent, or there may be at least one trench 100d between them.

[0038] Referring further to Figures 5 to 10, in each of the above embodiments, each trench 100d formed is a single-stage trench, but the technical solutions of the present invention are not limited thereto. In other embodiments of the present invention, where permitted by the overall depth design of the trenches 100d, at least one trench 100d may be a double-stage trench, a triple-stage trench, or more. Of these, the cross-sectional structure of a double-stage trench 100d may have two steps in the side wall surface including S1 and S2 of the trench 100d, as shown in Figure 12, and the cross-sectional structure of a triple-stage trench 100d may have three steps in the side wall surface including S1 and S2 of the trench 100d, as shown in Figure 13.

[0039] Referring to Figure 14, based on the same inventive concept, one embodiment of the present invention further provides a method for manufacturing a planar silicon carbide MOSFET element that can produce the planar silicon carbide MOSFET element of the present invention, and this manufacturing method specifically includes: Step s11 is to prepare a substrate having a first-conductivity silicon carbide drift layer, wherein the uppermost surface of the silicon carbide drift layer is a (0001) crystal plane, Step s12: Etching the uppermost surface of the silicon carbide drift layer in the region where a gate electrode is to be formed to form at least one trench, wherein the trench extends toward both sides of the gate electrode to be formed to the boundary between the source region boundary and the well region boundary, the bottom of the trench is shallower than the bottom of the well region, and the two sidewall surfaces of the trench extending in the width direction of the gate electrode to be formed are both crystal planes in which the channel mobility is higher than the (0001) crystal plane, Step s13 is to sequentially form a gate oxide layer and a gate electrode on the uppermost surface of the silicon carbide drift layer, the gate oxide layer covering at least the inner surface of the trench and the gate electrode filling the trench.

[0040] In step s11, referring to (A) in Figure 15, a base 100a is prepared, and a first conductive buffer layer 100b and a silicon carbide drift layer 100c are sequentially formed on the base 100a by any suitable process such as an epitaxial growth process, with the uppermost surface of the silicon carbide drift layer 100c being the (0001) crystal plane. The thickness and doping concentration of the base 100a, buffer layer 100b, and silicon carbide drift layer 100c are all designed according to the requirements of the device and are not specifically limited in this embodiment.

[0041] In step s12, referring to (A) in Figure 15, first, the surface of the region in the silicon carbide drift layer 100c where the channel and depletion region are to be formed is dry-etched to form at least one trench 100d, and the two sidewall surfaces extending in the width direction of the gate electrode to be formed in the trench 100d are both crystal planes in which the channel mobility is higher than that of the (0001) crystal plane.

[0042] Optionally, by an appropriate process such as wet etching or performing wet etching after oxidation, the crystal plane of the trench 100d is corrected and adjusted to form a crystal plane with high channel mobility such as (112￣0) crystal plane, (11￣00) crystal plane or (03￣38￣) crystal plane, or the trench 100d can be corrected and adjusted from a single-stage trench to a two-stage trench as shown in FIG. 12, a three-stage trench as shown in FIG. 13 or more trenches.

[0043] In an example of this embodiment, referring to (A) in FIG. 15, before executing step s12, that is, before etching the uppermost surface of the silicon carbide drift layer 100c in the region where the gate electrode is to be formed to form at least one trench 100d, first, a second-conductivity-type well region 101 is formed on the uppermost surface of the silicon carbide drift layer 110c by a series of processes such as mask deposition, patterning and ion implantation. Then, a first-conductivity-type source region 102 and a second-conductivity-type body contact region 10 are formed. The formed trench 100d extends from one well region 101 used as a boundary region of the channel to the other well region 101 used as a boundary region of the channel. The source regions 102 are formed in the surface layers of the well regions 101 on both sides respectively, and there is a gap between the trench 100d and the boundary of the source region 102. That is, as shown in FIGS. 5 and 6, the length w extending in the width direction of the gate electrode of the trench 100d (that is, the AA' direction or the BB' direction in FIG. 5) is between the gap a between the well regions 101 and the gap b between the source regions 102 on both sides of the gate electrode 105, that is, a < w < b. Further, after forming the well region 101, the source region 102 and the body contact region 103, the corresponding mask is removed, and the implanted impurities are activated by a high-temperature annealing process. The bottom depth of the trench 100d is shallower than the bottom depth of the source region 102 or the bottom depth of the well region 101.

[0044] In another example of this embodiment, referring to (A) in Figure 15, after step s12 is performed, a series of processes including mask deposition, patterning, and ion implantation first form well regions 101 on the uppermost surfaces of the silicon carbide drift layer 100c on both sides of the trench 100d, and then form a source region 102 of the first conductivity type and a body contact region 103 of the second conductivity type. After forming the well regions 101, source regions 102, and body contact regions 103, the corresponding masks are removed and the implanted impurities are activated by a high-temperature annealing process. The bottom depth of the trench 100d is shallower than the bottom depth of the source region 102 or the bottom depth of the well region 101. Each trench 100d extends toward both sides of the gate electrode 105 to the boundary between the source region 102 and the boundary of the well region 101, that is, as shown in Figures 5 and 6, the length w of the trench 100d extending in the width direction of the gate electrode (i.e., the AA' or BB' direction in Figure 5) is between the gap a between the well regions 101 and the gap b between the source regions 102 on both sides of the gate electrode 105, i.e., a <w<bである。

[0045] In step s13, referring to (D) and (E) in Figure 15, the gate oxide layer 104 can be formed by a thermal oxidation process or a deposition process, polysilicon is deposited on the gate oxide layer 104, a second conductivity type impurity is injected and activated to form a highly doped polysilicon gate electrode material layer, and then the polysilicon gate electrode material layer and the gate oxide layer 104 are patterned to form the gate electrode 105 and the coated gate oxide layer 104.

[0046] In one example of this embodiment, referring to (B) and (C) in Figure 15, after step s12 and before step s13, the trench 100d, source region 102, and main body contact region 103 are first covered with a medium layer 108' by an appropriate process such as deposition or spin coating, and the medium layer 108' may have a flat upper surface or an uneven upper surface. Its uppermost height is higher than the uppermost surface of the silicon carbide drift layer 100c. Subsequently, a patterned mask 200 is formed by a process such as resist coating, exposure, and development, and then the medium layer 108' is etched under the masking effect of the patterned mask 200 to form a medium structure 108 in the trench 100d. The gate electrode 105 formed in step s13 can be covered with the medium structure 108 and gate oxide layer 104 to conform to its shape, and the gate electrode 105 may have a flat upper surface or a relatively protruding upper surface.

[0047] It should be noted that, compared to conventional techniques, the manufacturing method of this embodiment is simpler and easier to implement because it does not require protection by an ion implantation layer (IMP layer) added by the formation of trench 100d for the formation of the source region, well region, and channel.

[0048] Furthermore, referring to (E) and (F) in Figure 15, after step s13, a blunting layer (not shown) may be deposited on the gate electrode 105 and the surface of its exposed element, and the blunting layer may be etched to form a surface that exposes the source region 102 and the body contact region 103. Then, source electrode metal may be grown on the source region 102 and the body contact region 103, and annealing may be performed to form the source electrode 106, and the source electrode 106 may be electrically connected to the source region 102 and the body contact region 103. Subsequently, drain electrode metal may be deposited on the bottom surface of the base 100a and annealing may be performed to form the drain electrode 107.

[0049] As described above, the planar silicon carbide MOSFET element and its manufacturing method of the present invention, in addition to the channel current still being parallel to the (0001) crystal plane of the SiC crystal, allows for more effective use of crystal planes with high channel mobility of the SiC crystal, such as the (112-0) crystal plane, the (11-00) crystal plane, or the (03-38) crystal plane, by providing several shallow trenches, thereby effectively reducing the channel resistance of the planar silicon carbide MOS element. Furthermore, the formation of the source region, well region, and channel does not require protection by an additional ion implantation layer (IMP layer), simplifying the process. The degree of reduction in channel resistance Ron or Rsp is related to the trench density and has a more clearly beneficial effect on planar MOSFET elements applied at 1700V or below. For example, when the solution of the present invention is applied to a 750V planar silicon carbide MOSFET element, the channel resistance Ron or Rsp can be reduced by 30%.

[0050] The above description is merely an explanation of preferred embodiments of the present invention and does not limit the scope of the invention in any way. Any modifications or changes made by those skilled in the art based on the above disclosure are all within the scope of protection of the technical solutions of the present invention.

Claims

1. A first-conductivity type silicon carbide drift layer whose uppermost surface is a (0001) crystal plane, A gate oxide layer and a gate electrode are sequentially stacked on the uppermost surface of the silicon carbide drift layer, A second conductivity type well region formed on the surface layer of the silicon carbide drift layer on both sides of the gate electrode, and a first conductivity type source region formed within the surface layer of the well region on both sides of the gate electrode, The trench includes, formed in the silicon carbide drift layer at the bottom of the gate electrode, and extending toward both sides of the gate electrode to the boundary between the source region and the well region, wherein the bottom of the trench is shallower than the bottom of the well region, and the two sidewall surfaces extending in the width direction of the gate electrode are both crystal planes where the channel mobility is higher than the (0001) crystal plane, The gate oxide layer covers at least the inner surface of the trench, and the gate electrode fills the trench, in a planar silicon carbide MOSFET element, The planar silicon carbide MOSFET element further comprises a medium structure, the medium structure being formed in a portion of the trench, the gate oxide layer covering the inner surface of the trench on the outer periphery of the medium structure, and the uppermost part of the medium structure being higher than the uppermost part of the gate oxide layer on the outer periphery of the trench. A planar-type silicon carbide MOSFET element characterized by the following features.

2. The planar silicon carbide MOSFET element according to claim 1, characterized in that the crystal planes with a higher channel mobility than the (0001) crystal plane include the (112-0) crystal plane, the (11-00) crystal plane, or the (03-38) crystal plane.

3. The planar silicon carbide MOSFET element according to claim 1, characterized in that the plurality of trenches are arranged in parallel in order along the length direction of the gate electrode, spaced apart, and any two of the trenches do not communicate with each other, or at least two of the trenches communicate in corresponding regions.

4. The planar silicon carbide MOSFET element according to claim 1, characterized in that the bottom depth of the trench is smaller than the bottom depth of the source region.

5. The planar silicon carbide MOSFET element according to claim 1, wherein the gate electrode further embeds the medium structure.

6. The planar silicon carbide MOSFET element according to claim 5, characterized in that the gate electrode has a projection formed by covering the medium structure to conform to its shape, or has a flat upper part.

7. Source electrodes formed on the (0001) crystal planes of the silicon carbide drift layer on both sides of the gate electrode and electrically connected to the source region, A first conductive buffer layer is laminated on the bottom surface of the silicon carbide drift layer, A first conductive base laminated on the bottom surface of the buffer layer, The planar silicon carbide MOSFET element according to claim 1, further comprising a drain electrode stacked on the bottom surface of the base.

8. A step of preparing a substrate having a first-type conductive silicon carbide drift layer, wherein the uppermost surface of the silicon carbide drift layer is a (0001) crystal plane, A step of etching the uppermost surface of the silicon carbide drift layer in the region where a gate electrode is to be formed to form at least one trench, wherein the trench extends toward both sides of the gate electrode to be formed to the boundary between the source region boundary and the well region boundary, the bottom of the trench is shallower than the bottom of the well region, and the two sidewall surfaces of the trench extending in the width direction of the gate electrode to be formed are both crystal planes in which the channel mobility is higher than the (0001) crystal plane, A method for manufacturing a planar silicon carbide MOSFET element according to claim 1, characterized by comprising the step of sequentially forming a gate oxide layer and a gate electrode on the uppermost surface of the silicon carbide drift layer, wherein the gate oxide layer covers at least the inner surface of the trench and the gate electrode fills the trench.

9. Before etching the uppermost surface of the silicon carbide drift layer in the region where the gate electrode is to be formed to form at least one trench, first, the well region of the second conductivity type and the source region of the first conductivity type are formed on the uppermost surface of the silicon carbide drift layer, the well region is formed within the surface layer of the uppermost surface of the silicon carbide drift layer on both sides of the gate electrode, and the source region is formed within the surface layer of the well region on both sides of the gate electrode. Alternatively, the manufacturing method according to claim 8, characterized in that, after the formation of at least one trench, and before or after the formation of the gate electrode, the well region and the source region are formed on the uppermost surface of the silicon carbide drift layer.

10. The substrate further includes a first conductivity type buffer layer and a first conductivity type base, which are sequentially laminated on the bottom surface of the silicon carbide drift layer. The step of forming a source electrode electrically connected to the source region on the uppermost surface of the silicon carbide drift layer, The manufacturing method according to claim 8, further comprising the step of forming a drain electrode on the bottom surface of the base.

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