Semiconductor equipment

Abstract

To provide a semiconductor device capable of reducing a recovery loss of a parasitic diode while maintaining an on-resistance low.SOLUTION: A semiconductor device according to the present embodiment includes: a first electrode; a first semiconductor region of a first conductivity type disposed above the first electrode; an insulating film disposed in the first semiconductor region; a second electrode disposed in the insulating film; a second semiconductor region of a second conductivity type adjacent to the second electrode via the insulating film; a third semiconductor region of the first conductivity type disposed on the second semiconductor region; and a third electrode electrically coupled to a contact portion, the contact portion being in contact with the first semiconductor region to form a Schottky junction on a first side surface, being in contact with the second semiconductor region and the third semiconductor region on a second side surface opposite to the first side surface, and having a bottom surface located above a bottom surface of the second semiconductor region.SELECTED DRAWING: Figure 1A

Description

[Technical Field]

[0001] Embodiments of the present invention relate to semiconductor devices. [Background technology]

[0002] In a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a PN junction diode (parasitic diode) is formed between the source and drain. To reduce the losses (recovery losses) in the reverse recovery operation of this parasitic diode, a semiconductor device is known that is equipped with a Schottky barrier diode (SBD), which has a lower forward voltage than a typical PN junction diode, separately from the MOSFET.

[0003] However, in the semiconductor device described above, a Schottky barrier diode is provided in a region separate from the MOSFET, which reduces the region that operates as a MOSFET and increases the on-resistance. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2017-55005 [Patent Document 2] Japanese Patent Publication No. 2014-127555 [Patent Document 3] Japanese Patent Publication No. 2019-106425 [Patent Document 4] Japanese Patent Publication No. 2012-59841 [Overview of the Initiative] [Problems that the invention aims to solve]

[0005] Embodiments of the present invention provide a semiconductor device that can reduce parasitic diode recovery losses while maintaining low on-resistance. [Means for solving the problem]

[0006] The semiconductor device according to this embodiment includes a first electrode, a first semiconductor region of a first conductivity type disposed above the first electrode, an insulating film disposed within the first semiconductor region, a second electrode disposed within the insulating film, a second semiconductor region of a second conductivity type adjacent to the second electrode via the insulating film, a third semiconductor region of a first conductivity type disposed above the second semiconductor region, and a third electrode including a contact portion and electrically connected to the contact portion. The contact portion is in contact with the first semiconductor region on a first side surface to form a Schottky junction, in contact with the second and third semiconductor regions on a second side surface opposite to the first side surface, and its bottom surface is located above the bottom surface of the second semiconductor region. [Brief explanation of the drawing]

[0007] [Figure 1A] This is a cross-sectional view of a semiconductor device according to one embodiment. [Figure 1B] This is an enlarged view of the region between semiconductor elements in a semiconductor device according to one embodiment. [Figure 2] This is a cross-sectional view of a semiconductor device according to a modified example of one embodiment. [Figure 3A] This is a cross-sectional view illustrating an example of a process for manufacturing a semiconductor device according to one embodiment. [Figure 3B] This is a cross-sectional view following Figure 3A, illustrating an example of the steps in a semiconductor device manufacturing method according to one embodiment. [Figure 3C] Figure 3B is a cross-sectional view illustrating an example of the steps in a semiconductor device manufacturing method according to one embodiment. [Figure 3D] Figure 3C is a cross-sectional view illustrating an example of the steps in a semiconductor device manufacturing method according to one embodiment. [Figure 3E] This is a cross-sectional view illustrating an example of a process for manufacturing a semiconductor device according to a modified embodiment. [Modes for carrying out the invention]

[0008] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The embodiments do not limit the present invention. The drawings are schematic or conceptual, and the ratios of each part are not necessarily the same as the actual ones. In the specification and drawings, the same elements as those described above with respect to the previous drawings are denoted by the same reference numerals, and detailed descriptions thereof are omitted as appropriate.

[0009] For convenience of explanation, as shown in the drawing, an XYZ orthogonal coordinate system is adopted. The Z-axis direction is the stacking direction (thickness direction) of the semiconductor device. Also, in the Z-axis direction, the source electrode side is also referred to as "up", and the drain electrode side is also referred to as "down". However, this expression is for convenience and has nothing to do with the direction of gravity.

[0010] Also, in the following description, in order to represent the relative high and low of the impurity concentration in each conductivity type, n n, n - And, p + p, p - Are sometimes used. That is, n + Indicates that the n-type impurity concentration is relatively higher than that of n, and n - Indicates that the n-type impurity concentration is relatively lower than that of n. Also, p + Indicates that the p-type impurity concentration is relatively higher than that of p, and p - Indicates that the p-type impurity concentration is relatively lower than that of p. The n-type, n + Type and n - Type is an example of the first conductivity type in the claims. The p-type, p + Type and p - Type is an example of the second conductivity type in the claims. In the following description, the n-type and the p-type may be reversed. That is, the first conductivity type may be the p-type.

[0011] (One embodiment) Referring to FIGS. 1A and 1B, a semiconductor device 1 according to an embodiment will be described. In this embodiment, the semiconductor device 1 includes one or more vertical MOSFETs as semiconductor elements.

[0012] As shown in FIG. 1A, the semiconductor device 1 includes a drain electrode 2, a semiconductor region 3, a gate electrode 4, a gate insulating film 5, a field plate electrode (FP electrode) 6, a metal 7, and a source electrode 8.

[0013] The drain electrode 2 is an electrode that functions as the drain electrode of the MOSFET. The drain electrode 2 is disposed under the semiconductor region 3. The drain electrode 2 is electrically connected to a drain region 31 included in the semiconductor region 3. The drain electrode 2 is an example of the first electrode in the claims. The drain electrode 2 is composed of a metal such as titanium (Ti), nickel (Ni), silver (Ag), etc.

[0014] The semiconductor region 3 is disposed above the drain electrode 2. The semiconductor region 3 includes, for example, a drain region 31, a drift region 32, a contact region 33, a base region 34, and a source region 35.

[0015] The drain region 31 is a semiconductor region that functions as the drain of the MOSFET. The drain region 31 is disposed above the drain electrode 2 and is electrically connected to the drain electrode 2. The drain region 31 is located between the drain electrode 2 and the drift region 32. The drain region 31 is, for example, an n + -type semiconductor region.

[0016] The drift region 32 is a semiconductor region that functions as the drift region of the MOSFET. The drift region 32 is disposed above the drain electrode 2 and above the drain region 31. The drift region 32 is, for example, an n - -type semiconductor region. As shown in FIG. 1B, the drift region 32 has a protruding portion 32a extending in the Z-axis direction. The drift region 32 is an example of the first semiconductor region in the claims.

[0017] The contact region 33 is positioned to form an ohmic bond with the metal 7. In this embodiment, the contact region 33 is positioned between the bottom surface B1 of the trench contact portion 7a and the base region 34 in the Z-axis direction. The contact region 33 only needs to be in contact with the trench contact portion 7a and the base region 34, and may be positioned, for example, between the side surface of the trench contact portion 7a and the base region 34. The contact region 33 is, for example, p + This is a semiconductor region of a certain shape. The contact region 33 is an example of the fourth semiconductor region in the claims. The contact region 33 has the function of suppressing device failure by parasitic transistors formed in the drift region 32, base region 34, and source region 35 by preventing the generation of a potential difference between the base region 34 and the source electrode 8 (trench contact portion 7a) when a reverse voltage is applied to the MOSFET.

[0018] The base region 34 is a semiconductor region that functions as the base of the MOSFET. The base region 34 is adjacent to the gate electrode 4 via the gate insulating film 5. The base region 34 is located between a portion of the drift region 32 and the gate insulating film 5 in the Y-axis direction, which is perpendicular to the Z-axis direction. Also, the base region 34 is located between the trench contact portion 7a and the contact region 33 and the gate insulating film 5 in the Y-axis direction. When a voltage is applied to the gate electrode 4, the base region 34 forms a channel, allowing carriers to flow between the drain region 31 and the source region 35. The base region 34 is, for example, p - This is a semiconductor region of a certain shape. The base region 34 is an example of a second semiconductor region in the claims.

[0019] The source region 35 is a semiconductor region that functions as the source of the MOSFET. The source region 35 is located on top of the base region 34. In this embodiment, the source region 35 is located between the gate insulating film 5 and the trench contact portion 7a in the Y-axis direction. The source region 35 is, for example, n +This is a semiconductor region of a certain shape. Source region 35 is an example of a third semiconductor region in the claims.

[0020] The semiconductor region 3 may be an epitaxial layer, a semiconductor substrate, or a semiconductor substrate with an epitaxial layer placed thereon. In this embodiment, the semiconductor region 3 is made of silicon (Si) containing impurities, for example. In this case, n-type impurities may include arsenic (As), phosphorus (P), or antimony (Sb). P-type impurities may include boron (B). The material of the semiconductor region 3 is not limited to silicon; the semiconductor region 3 may be made of silicon carbide (SiC), for example. Furthermore, each of the semiconductor regions included in the semiconductor region 3 extends in the X-axis direction, which is perpendicular to the Y-axis and Z-axis directions, respectively.

[0021] The gate electrode 4 is an electrode that functions as the gate electrode of a MOSFET. The gate electrode 4 is located in the gate insulating film 5. In the Y-axis direction, the gate electrode 4 is positioned adjacent to (facing) the base region 34 and the source region 35 via the gate insulating film 5. The gate electrode 4 also extends in the X-axis direction. The gate electrode 4 is made of, for example, polysilicon. The gate electrode 4 is an example of the second electrode in the claims.

[0022] The gate insulating film 5 is positioned in the drift region 32 and electrically insulates the gate electrode 4 from the semiconductor region 3 and the metal 7. The gate insulating film 5 also electrically insulates the FP electrode 6 from the semiconductor region 3. The gate insulating film 5 is composed of an insulating material such as silicon oxide or silicon nitride. The gate insulating film 5 is an example of an insulating film within the claims.

[0023] The FP electrode 6 is positioned below the gate electrode 4 within the gate insulating film 5 and is electrically connected to the source electrode 8. The FP electrode 6 also extends in the X-axis direction. The FP electrode 6 is positioned to mitigate the concentration of the reverse electric field between the gate electrode 4 and the drain electrode 2, thereby increasing the breakdown voltage of the MOSFET. The FP electrode 6 is made of, for example, polysilicon. The FP electrode 6 is an example of the fourth electrode in the claims.

[0024] Metal 7 is provided on the semiconductor region 3 and the gate insulating film 5. Metal 7 also partially includes a trench contact portion 7a extending toward the drift region 32 (negative Z-axis direction). The trench contact portion 7a is in contact with the contact region 33, the base region 34, and the source region 35 in the Y-axis direction. A Schottky junction is formed between the trench contact portion 7a and the drift region 32 (protrusion 32a). Metal 7 may function as a barrier metal used to prevent reaction between the metallic material of the source electrode 8 and the semiconductor material of the semiconductor region 3. Metal 7 includes, for example, titanium (Ti), cobalt (Co), nickel (Ni), platinum (Pt), or tungsten (W). The trench contact portion 7a and the rest of Metal 7 may be made of different materials. Metal 7 is an example of the third electrode in the claims. The trench contact portion 7a is an example of the contact portion in the claims.

[0025] As shown in Figure 1A, the bottom surface (lower end) B1 of the trench contact portion 7a is located above the bottom surface (lower end) B2 of the base region 34. That is, the distance D1 from the upper main surface 2s of the drain electrode 2 to the bottom surface B1 is greater than the distance D2 from the main surface 2s to the bottom surface B2.

[0026] The source electrode 8 is an electrode that functions as the source electrode of the MOSFET. The source electrode 8 is provided on the metal 7 and is electrically connected to the metal 7 (trench contact portion 7a). The source electrode 8 is made of, for example, copper, aluminum, or the like.

[0027] Referring to Figure 1B, the configuration of the trench contact portion 7a and its surrounding area will be described in more detail. Figure 1B is an enlarged view of the vicinity of the boundary between the first region 1a and the second region 1b, which are adjacent in the Y-axis direction, of the semiconductor device 1. Both the first region 1a and the second region 1b include the MOSFET operating region. As shown in Figure 1B, the trench contact portion 7a has a side surface 71 and a side surface 72 opposite to side surface 71. On side surface 71, the trench contact portion 7a is in contact with the drift region 32 (more specifically, the protruding portion 32a of the drift region 32) to form a Schottky junction. This reduces the recovery loss of the parasitic diode formed in the base region 34 (p-type) and the drift region 32 (n-type). Also, on side surface 72, the trench contact portion 7a is in contact with the base region 34 and the source region 35.

[0028] As shown in Figure 1B, the trench contact portion 7a may form a Schottky junction by contacting the drift region 32 over the entire surface area 71. This allows for a larger area of ​​the Schottky junction, thereby more effectively reducing the recovery loss of the parasitic diode.

[0029] As shown in Figure 1B, the protrusion 32a has a side surface 321 and a side surface 322 opposite to side surface 321. Side surface 321 is in contact with side surface 71 of the trench contact portion 7a of the first region 1a, forming a Schottky junction, and side surface 322 is in contact with side surface 71 of the trench contact portion 7a of the second region 1b (i.e., another trench contact portion), forming a Schottky junction. In other words, the protrusion 32a is sandwiched between two trench contact portions 7a of the two adjacent first regions 1a and 1b, and forms a Schottky junction with each of the trench contact portions 7a. Note that the impurity concentration of the protrusion 32a may be lower than the impurity concentration of the drift region 32 other than the protrusion 32a.

[0030] As described above, in this embodiment, the trench contact portion 7a contacts the drift region 32 (protrusion 32a) on the side surface 71 to form a Schottky junction, and contacts the base region 34 and the source region 35 on the side surface 72. This allows a Schottky barrier diode to be provided in the narrow region between the MOSFET operating regions. Therefore, a wider area of ​​the MOSFET operating region can be secured. Thus, according to this embodiment, the recovery loss of the parasitic diode can be reduced without increasing the on-resistance. Furthermore, the semiconductor device can be miniaturized.

[0031] Furthermore, in this embodiment, as previously described, the bottom surface (lower end) B1 of the trench contact portion 7a is located above the bottom surface (lower end) B2 of the base region 34 (i.e., bottom surface B1 is at a shallower position than bottom surface B2). As a result, the depletion layer extending from the trench contact portion 7a to the lower part of the drift region 32 is suppressed compared to the case where bottom surface B1 is at a deeper position than bottom surface B2. Therefore, it is not necessary to thicken the drift region 32, and an increase in on-resistance can be prevented.

[0032] In detail, if the trench contact portion 7a is made deeper (the bottom surface B1 is made deeper), the depletion layer that forms below the trench contact portion 7a extends to the bottom of the drift region 32, requiring the drift region 32 to be thickened. However, thickening the drift region 32 increases the on-resistance. In contrast, in this embodiment, since the bottom surface B1 is located above the bottom surface B2, the depletion layer that forms below the trench contact portion 7a does not extend to the bottom of the drift region 32. Therefore, there is no need to thicken the drift region 32, and an increase in on-resistance can be prevented. Note that because the bottom surface B1 is shallow, the electric field concentration at the bottom of the gate electrode 4 may not be sufficiently mitigated. However, this is not a particular problem if the electric field concentration at the bottom of the gate electrode 4 is not so large (for example, when the semiconductor region 3 is made of silicon).

[0033] Furthermore, if the trench contact portion 7a is made deeper, the electric field generated below the trench contact portion 7a extends to the bottom of the drift region 32, thus reducing the avalanche withstand capability. To prevent this, the drift region 32 needs to be made thicker. In contrast, in this embodiment, since the bottom surface B1 is located above the bottom surface B2, the electric field generated below the trench contact portion 7a does not extend to the bottom of the drift region 32. Therefore, the recovery loss of the parasitic diode can be reduced without thickening the drift region 32 to prevent a decrease in avalanche withstand capability.

[0034] As described above, this embodiment makes it possible to reduce the recovery loss of parasitic diodes while keeping the on-resistance of the semiconductor element low. Furthermore, it is possible to reduce the recovery loss of parasitic diodes while preventing a decrease in the avalanche withstand capability of the semiconductor element.

[0035] In addition, the field plate electrode 6 and / or contact region 33 may be omitted in the semiconductor device 1.

[0036] (modified version) Now, with reference to Figure 2, a modified example of the semiconductor device 1 according to this embodiment will be described. Figure 2 is a cross-sectional view of the semiconductor device 1A according to this modified example. As shown in Figure 2, the semiconductor device 1A according to this modified example includes insulating film 9 and insulating film 10 disposed on the protruding portion 32a. According to this modified example, the same effects as those of the above-described embodiment can be obtained. Furthermore, in the semiconductor device manufacturing method described later, the etching step to remove the insulating films 9 and 10 can be omitted (see Figure 3D(1)).

[0037] <Manufacturing method for semiconductor devices> An example of a manufacturing method for the semiconductor device 1 described above will be explained with reference to Figures 3A to 3D. Although the semiconductor device 1 comprises one or more semiconductor elements, only one semiconductor element is shown in Figures 3A to 3D to avoid complexity.

[0038] First, as shown in Figure 3A(1), a wafer 3A is prepared in which insulating film 9 and insulating film 10 are placed on the upper surface of a semiconductor layer 30 including a drain region 31 and a drift region 32. The insulating film 9 is made of, for example, silicon oxide. The insulating film 10 is made of, for example, silicon nitride. The insulating film 9 is placed on the semiconductor layer 30, and the insulating film 10 is placed on the insulating film 9.

[0039] Next, as shown in Figure 3A(2), a trench T is formed in the semiconductor layer 30 (drift region 32) by combining, for example, RIE (Reactive Ion Etching) with wet etching. Specifically, first, a resist mask (not shown) is formed on the insulating film 10, and a trench is formed by removing the insulating films 9, 10 and a part of the drift region 32 using RIE. Then, the trench T is formed by expanding the trench using wet etching.

[0040] Next, as shown in Figure 3A(3), an insulating film 5 is formed by depositing an insulating material on the inner surface (bottom and sides) of the trench T by physical vapor deposition (PVD) or chemical vapor deposition (CVD), etc. The insulating material is, for example, silicon oxide. This process forms the FP trench FT. In this embodiment, since the insulating film 9 and the insulating film 5 are made of the same material, the insulating film 9 becomes integrated with the insulating film 5.

[0041] Next, a conductive material, such as polysilicon, is deposited onto the insulating film 5 to fill the FP trench FT. Then, a portion of the deposited polysilicon is removed by a combination of CMP (Chemical Mechanical Polishing), CDE (Chemical Dry Etching), wet etching, etc. This forms the FP electrode 6 as shown in Figure 3A(4).

[0042] Next, as shown in Figure 3B(1), the FP electrode 6 is embedded in the insulating film 5 by depositing an insulating material such as silicon oxide in the trench T by physical vapor deposition (PVD) or chemical vapor deposition (CVD). In this process, the insulating material is also deposited on the sides of the trench T, forming a gate trench GT.

[0043] Next, for example, p-type impurity ions are implanted into the drift region 32 through the side of the gate trench GT. Then, as shown in Figure 3B(2), the impurities are activated and diffused by heat treatment to form a base region 34 within the drift region 32 surrounding the gate trench GT.

[0044] Next, a conductive material, such as polysilicon, is deposited to fill the gate trench GT. Then, by removing a portion of the deposited polysilicon using a combination of CMP, CDE, etc., the gate electrode 4 is formed as shown in Figure 3B(3).

[0045] Next, for example, n-type impurity ions are ion-implanted into the upper part of the base region 34 through the gate trench GT. Then, as shown in Figure 3B(4), the source region 35 is formed by activating the impurities through heat treatment. Note that the source region 35 and the base region 34 may be formed simultaneously. That is, p-type and n-type impurity ions may be ion-implanted into the drift region 32, and then the source region 35 and the base region 34 may be formed by simultaneous heat treatment.

[0046] Next, the gate electrode 4 is embedded in the insulating film 5 by depositing an insulating material such as silicon oxide onto the gate electrode 4 using physical vapor deposition (PVD) or chemical vapor deposition (CVD). Then, as shown in Figure 3C(1), a portion of the insulating film 5 is removed by RIE or the like to form an opening OP above the electrode 4.

[0047] Next, as shown in Figure 3C(2), the opening OP is widened by wet etching, removing a portion of the insulating film 5 and insulating film 10. Specifically, the opening OP is widened until the drift region 32 is exposed on the bottom surface of the opening OP. The width of the widened opening OP determines the width of the trench contact portion 7a. At the same time, the final shape of the insulating film 5 is determined.

[0048] Next, as shown in Figure 3C(3), a portion of the drift region 32 is removed by RIE or the like, using the insulating film 10 and insulating film 5 as masks (etching stoppers). This forms contact trench CTs on both sides of the insulating film 5. Specifically, the trench contact CTs are formed so that their depth is shallower than the base region 34. Furthermore, the formation of the contact trench CTs in this process determines the final extent of the source region 35.

[0049] Next, for example, p-type impurity ions are ion-implanted into the bottom surface of the contact trench CT. Then, as shown in Figure 3C(4), the impurities are activated by heat treatment to form the contact region 33. Furthermore, the formation of the contact region 33 in this process determines the final range of the base region 34.

[0050] Next, as shown in Figure 3D(1), insulating films 9 and 10 are removed, for example, by dry etching or wet etching.

[0051] Next, as shown in Figure 3D(2), metal 7 is formed by depositing a first metallic material to fill the contact trench CT. For depositing the first metallic material, methods such as vapor deposition or sputtering are used. The first metallic material includes, for example, titanium, cobalt, nickel, platinum, or tungsten. The first metallic material that fills the trench contact CT becomes the trench contact portion 7a.

[0052] Subsequently, as shown in Figure 3D(3), a source electrode 8 is formed by depositing a second metallic material on the metal 7. For depositing the second metallic material, methods such as vapor deposition or sputtering are used. The second metallic material includes, for example, copper or aluminum. Furthermore, a drain electrode 2 is formed by depositing a third metallic material on the lower surface of the drain region 31. For depositing the third metallic material, methods such as vapor deposition or sputtering are used. The third metallic material includes, for example, titanium, nickel, or silver.

[0053] Through the above process, a semiconductor device 1 according to one embodiment is manufactured. Note that the above description is merely one example of a method for manufacturing the semiconductor device 1, and it is possible to manufacture the semiconductor device 1 by other methods as well. For example, in the step of filling the trench contacts CT with a metal material, the first metal material may be deposited only within each contact trench CT. In this case, the source electrode 8 is formed on the insulating film 5.

[0054] Furthermore, as previously described, in the manufacturing of the semiconductor device 1A according to a modified example of one embodiment, some steps can be omitted. Here, the manufacturing method of the semiconductor device 1A according to a modified example of one embodiment will be explained with reference to Figure 3E.

[0055] After the process shown in Figure 3C(4), as shown in Figure 3E(1), the first metal material is laminated while the insulating films 9 and 10 are left in place, to form the metal 7. Then, as shown in Figure 3E(2), the second metal material is laminated on the metal 7 to form the source electrode 8. In addition, the second metal material is deposited on the lower surface of the semiconductor region 3 (drain region 31) to form the drain electrode 2. Through the above process, a semiconductor device 1A according to a modified embodiment is manufactured.

[0056] While embodiments of the present invention have been described, these embodiments and examples are presented as examples only and are not intended to limit the scope of the invention. These embodiments and examples can be carried out in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and examples and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of symbols]

[0057] 1 Semiconductor device 1a 1st area 1b 2nd area 2 Drain electrodes 2s main surface 3. Semiconductor Domain 30 Semiconductor Layers 4 gate 5 Gate insulating film 5A insulation film layer 6. Field plate electrodes (FP electrodes) 7 Metal 7a Trench contact area 8 Source electrodes 9. Insulating film 10 Insulating Film 31 Drain area 32 Drift region 32a Protrusion 33 Contact Area 34 Base area 35 Source Area 71, 72 Side view 321, 322 Side view B1, B2 bottom D1, D2 distance CT Contact Trench FT FP Trench GT Gate Trench OP opening

Claims

1. First electrode and, A first semiconductor region of a first conductivity type is positioned above the first electrode, An insulating film disposed in the first semiconductor region, A second electrode disposed in the insulating film, A second semiconductor region of a second conductivity type adjacent to the second electrode, via the insulating film, A third semiconductor region of a first conductivity type is disposed on the second semiconductor region, A Schottky junction is formed on the first side surface in contact with the first semiconductor region, and a contact portion is included on the second side surface opposite the first side surface in contact with the second semiconductor region and the third semiconductor region, with the bottom surface located above the bottom surface of the second semiconductor region, and a third electrode is electrically connected to the contact portion, A semiconductor device equipped with a semiconductor device.

2. The first semiconductor region has a protruding portion having a third surface that is in contact with the first surface of the contact portion. The protruding portion contacts another contact portion on the fourth side opposite to the third side to form a Schottky junction. The semiconductor device according to claim 1.

3. The contact portion is in contact with the first semiconductor region over the entire area of ​​the first side surface and forms a Schottky junction. The semiconductor device according to claim 1.

4. The contact portion and the second semiconductor region are in contact with each other, and the fourth semiconductor region has a second conductivity type with a higher impurity concentration than the second semiconductor region. The semiconductor device according to claim 1.

5. The fourth semiconductor region is located between the bottom surface of the contact portion and the first semiconductor region. The semiconductor device according to claim 4.

6. The insulating film further comprises a fourth electrode positioned below the second electrode and electrically connected to the third electrode. The semiconductor device according to claim 1.

7. The first semiconductor region has a protrusion that contacts the first side surface of the contact portion, The facility further comprises an insulating film disposed on the aforementioned protrusion. The semiconductor device according to claim 1.

8. The first semiconductor region, the second semiconductor region, and the third semiconductor region are made of silicon containing impurities. A semiconductor device according to any one of claims 1 to 7.

9. The contact portion contains titanium, cobalt, nickel, platinum, or tungsten. The semiconductor device according to claim 8.

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