Integrated circuits, substrates, and electronic equipment

Abstract

To improve the functionality.SOLUTION: A semiconductor integrated circuit 3 having a terminal 11 to which a resistor 6 having different characteristics is connected and which can be connected to Vcc and GND, and a plurality of setting conditions are read and stored in a storage unit 18 from changes in the electrical characteristics of a terminal 11 based on the characteristics of a resistor 6 when the potential of any terminal of the resistor 6 is changed, and the plurality of setting conditions that are stored in the storage unit 18 are used as setting conditions when the semiconductor integrated circuit 3 is used.SELECTED DRAWING: Figure 7

Description

Technical Field

[0001] The present invention relates to an integrated circuit, a substrate, and an electronic device, and is suitable for application to an integrated circuit mounted on a substrate mounted in, for example, an image forming apparatus.

Background Art

[0002] Conventionally, in a semiconductor integrated circuit, a terminal that is originally used as an output is made high-impedance when power is turned on, and the potential (1 or 0) of the terminal due to a pull-up resistor or a pull-down resistor connected to the terminal is read and used as a set value inside an IC (Integrated Circuit) chip of the semiconductor integrated circuit. This is generally done (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In such a semiconductor integrated circuit, depending on the circuit configuration, there may be a case where the number of terminals available for information capture cannot be sufficiently secured. However, even in such a case, the semiconductor integrated circuit can capture only 1 bit of information per terminal, and there may be a case where a sufficient number of settings cannot be secured.

[0005] The present invention has been made in consideration of the above points, and intends to propose an integrated circuit, a substrate, and an electronic device capable of improving functionality.

Means for Solving the Problems

[0006] To solve the above problem, the present invention provides an integrated circuit having an integrated circuit to which impedance elements with different characteristics are connected and which has a terminal that can be connected to a power supply unit at a predetermined potential, The system includes a signal input unit that receives signals from terminals, and a control unit that controls a signal output unit that electrically connects to any of the resistor terminals of an impedance element and outputs a signal that changes the potential. The control unit receives a first signal from the signal input unit with the output of the signal output unit turned off, then causes the signal output unit to output a second signal having different electrical characteristics from the first signal, then turns off the output of the signal output unit and receives a third signal from the signal input unit after a predetermined condition has been met, and stores the setting conditions corresponding to the first signal and the setting conditions corresponding to the third signal in the memory unit. Multiple setting conditions stored in the memory unit are used as setting conditions when using an integrated circuit.

[0007] Furthermore, the substrate of the present invention has the above-described integrated circuit, and is provided with an impedance element connected to the terminals of the integrated circuit and a power supply unit connected to the impedance element.

[0008] Furthermore, the substrate of the present invention is provided with the above-mentioned substrate.

[0009] This invention allows for the reading of multiple setting conditions corresponding to the electrical characteristics of the impedance elements, by selecting and mounting one impedance element from among impedance elements with different electrical characteristics at the same impedance element mounting position. [Effects of the Invention]

[0010] According to the present invention, it is possible to realize integrated circuits, substrates, and electronic devices that can improve functionality. [Brief explanation of the drawing]

[0011] [Figure 1] This is a diagram showing the printer configuration. [Figure 2] This is a block diagram showing the configuration of the substrate according to the first embodiment. [Figure 3] This is a block diagram showing the combination of resistor mounting position and resistance constant according to the first embodiment, where (A) is a setting value of 3, (B) is a setting value of 2, (C) is a setting value of 1, and (D) is a setting value of 0. [Figure 4] This graph shows the relationship between the elapsed time and the potential Vc of the signal line L when a resistor is mounted at the resistor mounting position MPu according to the first embodiment. [Figure 5]This graph shows the relationship between the elapsed time and the potential Vc of the signal line L when a resistor is mounted at the resistor mounting position MPl according to the first embodiment. [Figure 6] This is a timing chart showing the signals between the IO buffer control unit and the IO buffer according to the first embodiment, where (A) is a setting value of 3, (B) is a setting value of 2, (C) is a setting value of 1, and (D) is a setting value of 0. [Figure 7] This flowchart shows the procedure for reading the set value according to the first embodiment. [Figure 8] This is a block diagram showing the configuration of the substrate according to the second embodiment. [Figure 9] This is a block diagram showing the configuration of the substrate according to the second embodiment, in which the capacitor and the opposing device are replaced with a capacitor having an equivalent load capacitance. [Figure 10] This is a block diagram showing combinations of resistor mounting positions and resistance constants according to the second and third embodiments, where (A) is a setting value of 7, (B) is a setting value of 6, (C) is a setting value of 5, (D) is a setting value of 4, (E) is a setting value of 3, (F) is a setting value of 2, (G) is a setting value of 1, and (H) is a setting value of 0. [Figure 11] This graph shows the relationship between the elapsed time and the potential Vc of the signal line L when a resistor is mounted at the resistor mounting position MPu according to the second and third embodiments. [Figure 12] This graph shows the relationship between the elapsed time and the potential Vc of the signal line L when a resistor is mounted at the resistor mounting position MPl according to the second and third embodiments. [Figure 13] The timing chart (1) shows the signals between the IO buffer control unit and the IO buffer according to the second and third embodiments, where (A) is set to a value of 7, (B) is set to a value of 6, (C) is set to a value of 5, and (D) is set to a value of 4. [Figure 14] The timing chart (2) shows the signals between the IO buffer control unit and the IO buffer according to the second and third embodiments, where (A) is set to a value of 3, (B) is set to a value of 2, (C) is set to a value of 1, and (D) is set to a value of 0. [Figure 15]It is a flowchart showing the set value reading process procedure according to the second embodiment. [Figure 16] It is a set value reading replacement correspondence table according to the second embodiment. [Figure 17] It is a block diagram showing the configuration of a substrate according to the third embodiment. [Figure 18] In the configuration of the substrate according to the third embodiment, it is a block diagram showing a state where a capacitor and an opposing device are replaced with a capacitor having an equivalent load capacitance. [Figure 19] It is a flowchart showing the set value reading process procedure according to the third embodiment. [Figure 20] It is a set value reading replacement correspondence table according to the third embodiment.

Embodiments for Carrying Out the Invention

[0012] Hereinafter, embodiments for carrying out the invention (hereinafter referred to as embodiments) will be described with reference to the drawings. [1. First Embodiment] [1-1. Configuration of Printer] As shown in FIG. 1, the printer 1 is, for example, a color electrophotographic printer that prints a desired image on paper. In the printer 1, various components such as a substrate 2 shown in FIG. 2 are arranged inside the housing. The printer 1 is overall controlled by, for example, a semiconductor integrated circuit 3 mounted on the substrate 2.

[0013] [1-2. Configuration of Substrate] As shown in FIG. 2, on the substrate 2, a semiconductor integrated circuit 3, an OSC 4, a resistor 6 (resistor 6s or 6w), a capacitor 8, and an opposing device 10 are mounted. One terminal 11 of the plurality of formed terminals of the semiconductor integrated circuit 3 is connected to a signal line L, and the signal line L is connected to the opposing device 10. Therefore, the semiconductor integrated circuit 3 and the opposing device 10 are connected by the signal line L.

[0014] The semiconductor integrated circuit 3 is, for example, an ASIC (Application Specific Integrated Circuit) and has an IO buffer 12, an IO buffer control unit 14, a transmission unit 16, and a storage unit 18. The IO buffer 12 is an LVTTL (Low Voltage TTL) input / output buffer. The input potential thresholds for the LVTTL are Vil, which is the threshold for determining a low level, at 0.8[V], and Vih, which is the threshold for determining a high level, at 2.0[V].

[0015] The IO buffer control unit 14, acting as a control unit, is a logic circuit that controls the IO buffer 12. It is interconnected with the IO buffer 12 by three signal lines: signal line Loe, signal line Lout, and signal line Lin. It outputs the oe signal and the out signal to signal line Loe and signal line Lout, respectively, and receives the in signal from signal line Lin, which acts as a signal input. When the IO buffer 12 is put into a high-impedance state (hereinafter also referred to as the Hi-z state), the IO buffer control unit 14 outputs a low level "0" as the oe signal to signal line Loe, regardless of the out signal (hereinafter also referred to as setting oe=0). Hereinafter, putting the IO buffer 12 into a high-impedance state will also be referred to as disconnecting (i.e., opening) the output of signal line L. On the other hand, when the IO buffer control unit 14 outputs "1" to signal line L via IO buffer 12, it outputs a high-level "1" as the oe signal to signal line Loe (hereinafter also referred to as oe=1), and also outputs a high-level "1" as the out signal to signal line Lout, which is the signal output unit (hereinafter also referred to as out=1). On the other hand, when the IO buffer control unit 14 outputs "0" to signal line L via IO buffer 12, it sets oe=1 and outputs a low-level "0" as the out signal to signal line Lout (hereinafter also referred to as out=0). Furthermore, the IO buffer control unit 14 reads the value of the in signal by inputting the in signal from signal line Lin via IO buffer 12 from signal line L.

[0016] The transmitter 16 is a logic circuit that transmits an output signal tx to the opposing device 10 in the intended use of the semiconductor integrated circuit 3. When the IO buffer control unit 14 outputs the output signal tx to the signal line L via the IO buffer 12, it outputs tx as an out signal to the signal line Lout (hereinafter also referred to as out=tx) and, by setting oe=1, transfers the signal control rights of the IO buffer 12 to the transmitter 16.

[0017] The memory unit 18 stores one of the following setting values ​​used during initial operation of the semiconductor integrated circuit 3, which is read by the IO buffer control unit 14 from terminal 11: setting value 3, setting value 2, setting value 1, or setting value 0. OSC4 is an oscillator or resonator that supplies a clock to the semiconductor integrated circuit 3. The clock frequency is 10 [MHz] (period 0.1 [μs]).

[0018] Resistor 6 is a resistive element such as a chip resistor, and only one of either resistor 6s or 6w is mounted at either resistor mounting position MPu or MPl. In other words, resistor 6 is never mounted at both resistor mounting positions MPu and MPl. Hereafter, resistors 6s and 6w will be collectively referred to as resistor 6, and resistor mounting positions MPu and MPl will be collectively referred to as resistor mounting position MP as an impedance element mounting position. When resistor 6 is mounted at resistor mounting position MPu, one external electrode is connected to the signal line L, and the other external electrode is connected to Vcc, which is 3.3[V]. On the other hand, when resistor 6 is mounted at resistor mounting position MPl, one external electrode is connected to the signal line L, and the other external electrode is connected to GND, which is 0[V]. The constant resistance constant Rs of resistor 6s is, for example, 2[kΩ]. The constant resistance constant Rw of resistor 6w is, for example, 10[kΩ].

[0019] Capacitor 8 is composed of a chip capacitor or the like, and functions as a capacitive component between signal line L and 0[V] by connecting one external electrode to signal line L and the other external electrode to 0[V]. The capacitance value of capacitor 8 is set to C=50[pF]. Opposite device 10 is a device that receives data output by semiconductor integrated circuit 3.

[0020] [1-3. Regarding the combination of resistor mounting position and resistance constant] Figures 3(A), 3(B), 3(C), and 3(D) show combinations of resistor mounting positions MPu and MPl on the substrate 2 where the resistor 6 can be mounted, and the resistance constants Rs and Rw of the resistor 6. The semiconductor integrated circuit 3 reads four types of set values, set value 3, set value 2, set value 1, or set value 0, from the signal line L, according to four different patterns resulting from the combination of resistor mounting position MP and resistance constant R. The resistor mounting position MP and resistance constant R in each figure of Figure 3, and the set values ​​read by the semiconductor integrated circuit 3 are as follows.

[0021] Figure 3(A): Resistor mounting position MPu, resistance constant Rs, set value = 3 Figure 3(B): Resistor mounting position MPu, resistance constant Rw, set value = 2 Figure 3(C): Resistor mounting position MPl, resistance constant Rw, set value = 1 Figure 3(D): Resistor mounting position MPl, resistance constant Rs, set value = 0

[0022] In other words, for example, in Figure 3(A), when a resistor 6s with resistance constant Rs is mounted at resistor mounting position MPu, and nothing is mounted at resistor mounting position MPl, the semiconductor integrated circuit 3 reads the set value 3.

[0023] Furthermore, as mentioned above, the resistor mounting positions MPu and MPl are as follows: Resistor mounting location MPu: Between signal line L and 3.3[V] Resistor mounting position MPl: Between signal line L and 0[V]

[0024] Furthermore, as mentioned above, the resistance constants Rs and Rw are as follows: Resistance constant Rs:2[kΩ] Resistance constant Rw:10[kΩ]

[0025] [1-4. Relationship between elapsed time and signal line potential] [1-4-1. Resistor mounting location: When a 6s or 6w resistor is mounted on MPu] Figure 4 is a graph showing the potential change of the signal line L potential Vc [V] starting from signal line L = 0 [V] when resistor 6s or 6w is mounted at resistor mounting position MPu, and the IO buffer 12 is in a high-impedance state (oe = 0), using the step response calculation formula for an RC circuit. In this graph, the constants of resistor 6 that can be mounted at resistor mounting position MPu are either the resistance constant Rs (2 [kΩ]) or the resistance constant Rw (10 [kΩ]), and the potential change in these two cases is shown. The potential Vc [V] of the signal line L is expressed by the following equation (1) using time t (seconds) from the start.

[0026]

number

[0027] Here, e is Napier's number (2.718...) and τ is the time constant (in seconds). For resistance constants Rs (2 [kΩ]) and Rw (10 [kΩ]), the value of τ is given by equation (2) when the resistance constant Rs is 2 [kΩ] and by equation (3) when the resistance constant Rw is 10 [kΩ].

[0028]

number

[0029]

number

[0030] From this graph, we can see that when the resistance constant Rs is 2 kΩ, the potential Vc of the signal line L exceeds Vih (2 V) at the latest after 95 μs, which means that the IO buffer 12 will read "1" from the signal line L at the latest after 95 μs. On the other hand, when the resistance constant Rw is 10 kΩ, the potential Vc of the signal line L does not exceed Vil (0.8 V) at the earliest after 135 μs, which means that the IO buffer 12 will read "0" from the signal line L at the earliest after 135 μs. For example, 115 μs after the IO buffer 12 enters a high-impedance state (oe=0), the IO buffer 12 will read "1" from the signal line L when the resistance constant Rs is 2 kΩ, and when the resistance constant Rw is 10 kΩ, the IO buffer 12 will read "0" from the signal line L.

[0031] [1-4-2. When a 6s or 6w resistor is mounted at resistor mounting position MPl] Figure 5 is a graph showing the potential change of the signal line L potential Vc [V] starting from signal line L = 3.3 [V] when resistor 6s or 6w is mounted at resistor mounting position MPl, and the IO buffer 12 is in a high-impedance state (oe=0), using the step response calculation formula for an RC circuit. In this graph, the constants of resistor 6 that can be mounted at resistor mounting position MPl are either the resistance constant Rs (2 [kΩ]) or the resistance constant Rw (10 [kΩ]), and the potential change in these two cases is shown. The potential Vc [V] of the signal line L is expressed by the following equation (4) using time t (seconds) from the start.

[0032]

number

[0033] Here, e and τ are the same as described in Figure 4.

[0034] From this graph, we can see that when the resistance constant Rs is 2 kΩ, the potential Vc of the signal line L falls below Vil (0.8 V) at the latest after 145 μs, which means that the IO buffer 12 reads "0" from the signal line L at the latest after 145 μs. On the other hand, when the resistance constant Rw is 10 kΩ, the potential Vc of the signal line L remains above Vih (2 V) at the earliest after 250 μs, which means that the IO buffer 12 reads "1" from the signal line L at the earliest after 250 μs. For example, 200 μs after the IO buffer 12 enters a high-impedance state (oe=0), the IO buffer 12 reads "0" from the signal line L when the resistance constant Rs is 2 kΩ, and reads "1" from the signal line L when the resistance constant Rw is 10 kΩ.

[0035] [1-5. About Timing Charts] Figure 6 shows the timing charts of the signals (out signal, oe signal, and in signal) between the IO buffer control unit 14 and the IO buffer 12 for each combination of resistor mounting position MP and resistance constant R. Figure 6(A) shows the timing chart TC3 for setting value 3 shown in Figure 3(A), Figure 6(B) shows the timing chart TC2 for setting value 2 shown in Figure 3(B), Figure 6(C) shows the timing chart TC1 for setting value 1 shown in Figure 3(C), and Figure 6(D) shows the timing chart TC0 for setting value 0 shown in Figure 3(D).

[0036] Here, the in signal is the result of the IO buffer 12, which is an LVTTL buffer, reading "0" or "1" from the potential Vc [V] of the signal line L shown in FIGS. 4 and 5. When Vc > Vih (2.0 [V]), the IO buffer 12 determines that the in signal is "1" (hereinafter also referred to as in = 1). Also, when Vil (0.8 [V]) < Vc < Vih (2.0 [V]), the IO buffer 12 determines that the in signal is indeterminate (not certain whether it is "0" or "1"). Further, when Vc < Vil (0.8 [V]), the IO buffer 12 determines that the in signal is "0" (hereinafter also referred to as in = 0).

[0037] [1-6. Setting value reading process] Next, regarding the setting value reading process procedure RT1, which is the process of the IO buffer control unit 14 reading the setting value before the firmware starts up when the semiconductor integrated circuit 3 is powered on, the timing chart of FIG. 6 and the flowchart of FIG. 7 are used to explain for four patterns according to the combination of the resistor mounting position MP and the resistance constant R. The IO buffer control unit 14 starts the setting value reading process procedure RT1 and moves to step SP1.

[0038] [1-6-1. Case of setting value 3] First, as shown in FIG. 3(A), for the case where the setting value = 3, which is a pattern in which a resistor 6s with a resistance constant Rs is mounted at the resistor mounting position MPu and nothing is mounted at the resistor mounting position MPl, it will be explained using the timing chart TC3 shown in FIG. 6(A).

[0039] When power is turned on, in step SP1 the IO buffer control unit 14 sets out=0 / oe=0 to put the IO buffer 12 into a high-impedance state, reads the value of the in signal as the first signal at the first time point in time T0 after a certain period of time has elapsed, and moves to step SP2. In reality, when power is turned on to the semiconductor integrated circuit 3 and the reset signal of the semiconductor integrated circuit 3 is turned from on to off, the IO buffer control unit 14 reads the value of the in signal at time T0. Here, since resistor 6s is mounted at resistor mounting position MPu and signal line L is pulled up to 3.3[V], the in signal = "1". In step SP2 the IO buffer control unit 14 determines whether the value of the in signal read in step SP1 is "1". Here, the value of the in signal was "1", so the IO buffer control unit 14 obtains a positive result in step SP2 and moves to step SP3.

[0040] In step SP3, the IO buffer control unit 14 sets the IO buffer 12 to output "0" as the second signal at the second time point in time, with out=0 / oe=1 at time T1, and after a certain period of time has elapsed, proceeds to step SP4. In step SP3, the IO buffer control unit 14 outputs a value from the out signal that has a different logic level from the value of the in signal read in step SP1.

[0041] In step SP4, the IO buffer control unit 14 sets out=0 / oe=0 again at time T2 to put the IO buffer 12 into a high-impedance state, reads the value of the in signal as the third signal at the third time point at time T4, 115 [μs] after the time has elapsed, and moves to step SP7. Note that the IO buffer control unit 14 counts the elapsed time by waiting 1150 clock cycles because the clock frequency of OSC4 is 10 [MHz] (period 0.1 [μs]). Here, the resistance constant is Rs. In this case, after 95 [μs] from time T2 (t=0 [μs] in Figure 4), the potential of the signal line L with resistance constant Rs becomes Vc>Vih (2.0 [V]) and in = "1", so in = "1" is also true at time T4, which is more than 95 [μs] after time T2.

[0042] In step SP7, the IO buffer control unit 14 transfers the signal control rights of the IO buffer 12 to the transmission unit 16 by setting out=tx / oe=1 at time T8, and then proceeds to step SP8.

[0043] In step SP8, the IO buffer control unit 14 determines the current setting value based on the value of the in signal read in step SP1 and the value of the in signal read in step SP4, and then proceeds to step SP9. Specifically, the IO buffer control unit 14 uses the value of the in signal read in step SP1 as the most significant bit of the two bits in the binary representation of the setting value, and the value of the in signal read in step SP4 as the least significant bit of the two bits in the binary representation of the setting value. In this case, since the value of the in signal read in step SP1 is "1", the most significant bit of the setting value is "1", and since the value of the in signal read in step SP4 is "1", the least significant bit of the setting value is "1", so the IO buffer control unit 14 determines that the current setting value is "11b" in binary representation, and from this "11b", it determines that the setting value is 3.

[0044] In step SP9, the IO buffer control unit 14 stores the determined setting value in the storage unit 18, then moves to step SP10 and terminates the setting value reading procedure RT1. In this way, the IO buffer control unit 14 reads the value of the in signal twice, treating the value of the in signal read the first time and the value of the in signal read the second time as the most significant bit and the least significant bit in the binary representation of the setting value, and determines the setting value.

[0045] [1-6-2. When setting value is 2] Next, we will explain the case where the setting value is 2, as shown in Figure 3(B), where a resistor 6w with resistance constant Rw is mounted at resistor mounting position MPu, and nothing is mounted at resistor mounting position MPl, using the timing chart TC2 shown in Figure 6(B).

[0046] When power is turned on, in step SP1 the IO buffer control unit 14 sets out=0 / oe=0 to put the IO buffer 12 into a high-impedance state, reads the value of the in signal at time T0 after a certain period of time has elapsed, and moves to step SP2. Here, since resistor 6w is mounted at resistor mounting position MPu and signal line L is pulled up to 3.3[V], the in signal becomes "1". In step SP2 the IO buffer control unit 14 determines whether the value of the in signal read in step SP1 is "1". Here, the value of the in signal is "1", so the IO buffer control unit 14 obtains a positive result in step SP2 and moves to step SP3.

[0047] In step SP3, the IO buffer control unit 14 sets the IO buffer 12 to output "0" at time T1 by setting out=0 / oe=1, and after a certain period of time has elapsed, proceeds to step SP4.

[0048] In step SP4, the IO buffer control unit 14 sets out = 0 / oe = 0 again at time T2 to put the IO buffer 12 in a high-impedance state, reads the value of the in signal at time T4 after 115 [μs] has elapsed, and proceeds to step SP7. Here, it is the resistance constant Rw. In this case, since the potential Vc of the signal line L in the case of the resistance constant Rw is < Vil (0.8 [V]) and in = "0" is maintained until 135 [μs] has elapsed from time T2 (t = 0 [μs] in FIG. 4), in = "0" also holds at time T4 before 135 [μs] has elapsed from time T2.

[0049] In step SP7, the IO buffer control unit 14 sets out = tx / oe = 1 at time T8 to transfer the signal control right of the IO buffer 12 to the transmission unit 16 and proceeds to step SP8.

[0050] In step SP8, the IO buffer control unit 14 determines the current set value based on the value of the in signal read in step SP1 and the value of the in signal read in step SP4, and proceeds to step SP9. In this case, since the value of the in signal read in step SP1 is "1", the most significant bit of the set value is "1", and since the value of the in signal read in step SP4 is "0", the least significant bit of the set value is "0". Thus, the IO buffer control unit 14 determines that the current set value is "10b" in binary notation, and determines from this "10b" that the set value is 2.

[0051] In step SP9, the IO buffer control unit 14 stores the determined set value in the storage unit 18, proceeds to step SP10, and ends the set value reading processing procedure RT1.

[0052] [Case of Set Value 1] Next, as shown in FIG. 3(C), for the case of a set value of 1 where a resistor 6w with a resistance constant Rw is mounted at the resistor mounting position MPl and nothing is mounted at the resistor mounting position MPu, it will be described using the timing chart TC1 shown in FIG. 6(C).

[0053] When power is turned on, in step SP1 the IO buffer control unit 14 sets out=0 / oe=0 to put the IO buffer 12 into a high-impedance state, reads the value of the in signal at time T0 after a certain period of time has elapsed, and moves to step SP2. Here, since resistor 6w is mounted at resistor mounting position MPl and signal line L is pulled down to 0[V], the in signal = "0". In step SP2 the IO buffer control unit 14 determines whether the value of the in signal read in step SP1 is "1" or not. Here, the value of the in signal was "0", so the IO buffer control unit 14 obtains a negative result in step SP2 and moves to step SP5.

[0054] In step SP5, the IO buffer control unit 14 sets the IO buffer 12 to output "1" at time T1 by setting out=1 / oe=1, and after a certain period of time has elapsed, proceeds to step SP6. In step SP5, the IO buffer control unit 14 outputs a value from the out signal that has a different logic level from the value of the in signal read in step SP1.

[0055] In step SP6, the IO buffer control unit 14 sets out=0 / oe=0 again at time T2 to put the IO buffer 12 into a high-impedance state, reads the value of the in signal as the third signal at the third time point at time T7 after 200 [μs] has elapsed, and moves to step SP7. Note that the IO buffer control unit 14 counts the elapsed time by waiting 2000 clock cycles because the clock frequency of OSC4 is 10 [MHz] (period 0.1 [μs]). Here, the resistance constant is Rw. In this case, until 250 [μs] has elapsed from time T2 (t=0 [μs] in Figure 5), the potential of the signal line L with resistance constant Rw is Vc>Vih (2.0 [V]), and in = "1" is maintained. Therefore, even at time T7, before 250 [μs] has elapsed from time T2, in = "1".

[0056] In step SP7, the IO buffer control unit 14 transfers the signal control rights of the IO buffer 12 to the transmission unit 16 by setting out=tx / oe=1 at time T8, and then proceeds to step SP8.

[0057] In step SP8, the IO buffer control unit 14 determines the current setting value based on the value of the in signal read in step SP1 and the value of the in signal read in step SP6, and then proceeds to step SP9. In this case, since the value of the in signal read in step SP1 is "0", the most significant bit of the setting value is "0", and since the value of the in signal read in step SP6 is "1", the least significant bit of the setting value is "1". The IO buffer control unit 14 determines that the current setting value is "01b" in binary representation, and from this "01b", it determines that the setting value is 1.

[0058] In step SP9, the IO buffer control unit 14 stores the determined setting value in the storage unit 18, then moves to step SP10 and terminates the setting value reading procedure RT1.

[0059] [1-6-4. When the setting value is 0] Next, we will explain the case where the setting value = 0, as shown in Figure 3(D), where a resistor 6s with resistance constant Rs is mounted at resistor mounting position MPl, and nothing is mounted at resistor mounting position MPu, using the timing chart TC0 shown in Figure 6(D).

[0060] When the power is turned on, in step SP1, the IO buffer control unit 14 sets out = 0 / oe = 0 to put the IO buffer 12 in a high-impedance state, reads the value of the in signal at time T0 after a certain period of time has elapsed, and moves to step SP2. Here, since the resistor 6s is mounted at the resistor mounting position MPl and the signal line L is pulled down to 0 [V], the in signal = "0". In step SP2, the IO buffer control unit 14 determines whether the value of the in signal read in step SP1 is "1". Here, since the value of the in signal was "0", the IO buffer control unit 14 obtains a negative result in step SP2 and moves to step SP5.

[0061] In step SP5, at time T1, the IO buffer control unit 14 sets out = 1 / oe = 1 to put the IO buffer 12 in a state of outputting "1", and after a certain period of time has elapsed, moves to step SP6.

[0062] In step SP6, at time T2, the IO buffer control unit 14 again sets out = 0 / oe = 0 to put the IO buffer 12 in a high-impedance state, reads the value of the in signal at time T7 after 200 [μs] has elapsed, and moves to step SP7. Here, it is the resistance constant Rs. In this case, since the potential Vc of the signal line L in the case of the resistance constant Rs becomes <Vil (0.8 [V]) and in = "0" after 145 [μs] has elapsed from time T2 (t = 0 [μs] in FIG. 5), in = "0" also at time T7 when 145 [μs] or more has elapsed from time T2.

[0063] In step SP7, at time T8, the IO buffer control unit 14 transfers the signal control right of the IO buffer 12 to the transmission unit 16 by setting out = tx / oe = 1 and moves to step SP8.

[0064] In step SP8, the IO buffer control unit 14 determines the current setting value based on the value of the in signal read in step SP1 and the value of the in signal read in step SP6, and then proceeds to step SP9. In this case, since the value of the in signal read in step SP1 is "0", the most significant bit of the setting value is "0", and since the value of the in signal read in step SP6 is "0", the least significant bit of the setting value is "0", so the IO buffer control unit 14 determines that the current setting value is "00b" in binary representation, and from this "00b", it determines that the setting value is 0.

[0065] In step SP9, the IO buffer control unit 14 stores the determined setting value in the storage unit 18, then moves to step SP10 and terminates the setting value reading procedure RT1.

[0066] [1-7. Effects, etc.] In the above configuration, the substrate 2 is configured to mount either resistor 6s or 6w, which have different resistance values, at either resistor mounting position MPu or MPl, depending on the setting value used during initial operation of the semiconductor integrated circuit 3. In other words, the substrate 2 is configured to have varying resistance values ​​for pull-up resistors and pull-down resistors.

[0067] Furthermore, the semiconductor integrated circuit 3 first reads the state of terminal 11 in a high-impedance state and acquires a 1-bit setting. Next, it sets terminal 11 to a state with a logic level different from the state read earlier, either 0 output or 1 output, then returns it to a high-impedance state, reads the state of terminal 11 again after a certain period of time, and acquires another 1-bit setting value. As a result, the semiconductor integrated circuit 3 can acquire a 2-bit setting value at terminal 11, which is a single terminal.

[0068] As a result, the semiconductor integrated circuit 3 can acquire twice the amount of setting information compared to the conventional method, even if the number of terminals available for acquiring setting information remains the same, compared to the conventional method where one bit of setting value per terminal is read in a high-impedance state using a pull-up resistor or pull-down resistor composed of one type of resistance value.

[0069] Here, it is conceivable that resistor 6 could be omitted and a serial interface IC connected to signal line L, thereby inputting a binary value representing the set value as an "in" signal from the serial interface IC to the semiconductor integrated circuit 3, allowing the semiconductor integrated circuit 3 to read the set value. However, in that case, an additional serial interface IC would be required, which would complicate the configuration of board 2 and increase costs.

[0070] In contrast, board 2 is designed to mount either resistor 6s or 6w at either resistor mounting position MPu or MPl. Therefore, board 2 can be simplified in its configuration and reduced in cost.

[0071] According to the above configuration, the semiconductor integrated circuit 3 is a semiconductor integrated circuit 3 to which resistors 6, which are impedance elements with different resistance values ​​as characteristics, are connected, and which have terminals 11 that can be connected to Vcc and GND, which are power supply units with predetermined potentials. Multiple setting conditions are stored in the reading and storage unit 18 from the change in the electrical characteristics of the terminals 11 based on the characteristics of the resistors 6 when the potential of any terminal of the resistors 6 is changed, and the multiple setting conditions stored in the storage unit 18 are used as setting conditions when using the semiconductor integrated circuit 3.

[0072] As a result, the semiconductor integrated circuit 3 can read multiple setting conditions according to the electrical characteristics of the resistor 6, by selecting and mounting one of the resistors 6 with different electrical characteristics from each other at the same resistor mounting position MP.

[0073] [2. Second Embodiment] [2-1. Printer Configuration] As shown in Figure 1 and Figure 8, which uses the same reference numerals for components corresponding to those in Figure 2, the printer 101 according to the second embodiment differs from the printer 1 according to the first embodiment in that a circuit board 102 is provided instead of a circuit board 2, but is otherwise configured similarly.

[0074] [2-2. Circuit Board Configuration] As shown in Figure 8, the substrate 102 according to the second embodiment differs from the substrate 2 according to the first embodiment in that a semiconductor integrated circuit 103 is provided instead of the semiconductor integrated circuit 3, and resistors 6 (resistors 6a, 6b, 6c, or 6d) are provided instead of resistors 6 (resistors 6s or 6w), but it is otherwise configured similarly. The semiconductor integrated circuit 103 according to the second embodiment differs from the semiconductor integrated circuit 3 according to the first embodiment in that an IO buffer control unit 114 is provided instead of the IO buffer control unit 14, but it is otherwise configured similarly.

[0075] The memory unit 18 has pre-stored the setting value conversion correspondence table TB1 (described later), as shown in Figure 16. The memory unit 18 also stores the value of the in signal received from the IO buffer control unit 114. The IO buffer control unit 14 determines the setting value by referring to the setting value conversion correspondence table TB1 (Figure 16) based on the multiple in signal values ​​stored in the memory unit 18. Furthermore, the memory unit 18 stores one of the setting values ​​used in the initial operation of the semiconductor integrated circuit 103, which is read by the IO buffer control unit 114 from terminal 11: setting value 7, setting value 6, setting value 5, setting value 4, setting value 3, setting value 2, setting value 1, or setting value 0.

[0076] Figure 9 shows the circuit board 102 with capacitor 8 and the opposing device 10 replaced by capacitor 9 having an equivalent load capacitance. The capacitance value of capacitor 9 is set to C = 50 [pF]. Capacitor 8 may include parasitic capacitance between the signal line L and 0 [V].

[0077] Resistor 6 is a resistive element such as a chip resistor, and only one of resistors 6a, 6b, 6c, or 6d is mounted at either resistor mounting position MPu or MPl. In other words, resistor 6 is never mounted at both resistor mounting positions MPu and MPl. Hereafter, resistors 6a, 6b, 6c, and 6d will be collectively referred to as resistor 6. The resistance constants Ra, Rb, Rc, and Rd of resistors 6a, 6b, 6c, and 6d are, for example, 1 [kΩ], 5.1 [kΩ], 20 [kΩ], and 100 [kΩ].

[0078] [2-3. Regarding the combination of resistor mounting position and resistance constant] Figures 10(A), 10(B), 10(C), 10(D), 10(E), 10(F), 10(G), and 10(H) show combinations of resistor mounting positions MPu and MPl where the resistor 6 can be mounted on the substrate 102, and the resistance constants Ra, Rb, Rc, and Rd of the resistor 6. The semiconductor integrated circuit 103 reads eight different set values ​​from the signal line L, namely set value 7, set value 6, set value 5, set value 4, set value 3, set value 2, set value 1, or set value 0, according to eight different patterns resulting from the combination of resistor mounting position MP and resistance constant R. The resistor mounting position MP and resistance constant R in each figure of Figure 10, and the set values ​​read by the semiconductor integrated circuit 103 are as follows.

[0079] Figure 10(A): Resistor mounting position MPu, resistance constant Ra, set value = 7 Figure 10(B): Resistor mounting position MPu, resistance constant Rb, set value = 6 Figure 10(C): Resistor mounting position MPu, resistance constant Rc, set value = 5 Figure 10(D): Resistor mounting position MPu, resistance constant Rd, set value = 4 Figure 10(E): Resistor mounting position MPl, resistance constant Rd, set value = 3 Figure 10(F): Resistor mounting position MPl, resistance constant Rc, set value = 2 Figure 10(G): Resistor mounting position MPl, resistance constant Rb, set value = 1 Figure 10(H): Resistor mounting position MPl, resistance constant Ra, set value = 0

[0080] In other words, for example, in Figure 10(A), when a resistor 6a with resistance constant Ra is mounted at resistor mounting position MPu, and nothing is mounted at resistor mounting position MPl, the semiconductor integrated circuit 103 reads the set value 7.

[0081] [2-4. Relationship between elapsed time and signal line potential] [2-4-1. Resistor mounting location: When resistors 6a, 6b, 6c, or 6d are mounted on MPu] Figure 11 is a graph showing the potential change of the signal line L potential Vc[V] starting from signal line L=0[V] when resistors 6a, 6b, 6c, or 6d are mounted at the resistor mounting position MPu, and the IO buffer 12 is in a high-impedance state (oe=0), using the step response calculation formula for an RC circuit. In this graph, the constants of the resistor 6 that can be mounted at the resistor mounting position MPu are one of the resistance constants Ra(1[kΩ]), Rb(5.1[kΩ]), Rc(20[kΩ]), or Rd(100[kΩ]), and the potential change in these four cases is shown. The potential Vc[V] of the signal line L is expressed by equation (1) above, using the time t (seconds) from the start.

[0082] For resistance constants Ra (1 kΩ), Rb (5.1 kΩ), Rc (20 kΩ), and Rd (100 kΩ), the value of τ is given by equation (5) when the resistance constant Ra is 1 kΩ, by equation (6) when the resistance constant Rb is 5.1 kΩ, by equation (7) when the resistance constant Rc is 20 kΩ, and by equation (8) when the resistance constant Rd is 100 kΩ.

[0083]

number

[0084]

number

[0085]

number

[0086]

number

[0087] From this graph, we can see that when the resistance constant Ra is 1 kΩ, the potential Vc of the signal line L exceeds Vih (2 V) at the latest after 47 μs, which means that the IO buffer 12 will read "1" from the signal line L at the latest after 47 μs. On the other hand, when the resistance constant Rb is 5.1 kΩ, the potential Vc of the signal line L does not exceed Vil (0.8 V) at the earliest after 70 μs, which means that the IO buffer 12 will read "0" from the signal line L at the earliest after 70 μs. For example, 60 μs after the IO buffer 12 enters a high-impedance state (oe=0), we can say that when the resistance constant Ra is 1 kΩ, the IO buffer 12 reads "1" from the signal line L, and when the resistance constant Rb is 5.1 kΩ, the IO buffer 12 reads "0" from the signal line L.

[0088] [2-4-2. When resistors 6a, 6b, 6c, or 6d are mounted at resistor mounting position MPl] Figure 12 is a graph showing the potential change of the signal line L potential Vc[V] starting from signal line L=3.3[V] when resistors 6a, 6b, 6c, or 6d are mounted at resistor mounting position MPl, and the IO buffer 12 is in a high-impedance state (oe=0), using the step response calculation formula for an RC circuit. In this graph, the constants of the resistor 6 that can be mounted at resistor mounting position MPl are one of the resistance constants Ra(1[kΩ]), Rb(5.1[kΩ]), Rc(20[kΩ]), or Rd(100[kΩ]), and the potential change in these four cases is shown. The potential Vc[V] of the signal line L is expressed by equation (4) above using the time t (seconds) from the start.

[0089] Here, e and τ are the same as described in Figure 11.

[0090] From this graph, we can see that when the resistance constant Ra is 1 kΩ, the potential Vc of the signal line L falls below Vil (0.8 V) at the latest after 71 μs, which means that the IO buffer 12 will read "0" from the signal line L at the latest after 71 μs. On the other hand, when the resistance constant Rb is 5.1 kΩ, the potential Vc of the signal line L remains above Vih (2 V) at the earliest after 127 μs, which means that the IO buffer 12 will read "1" from the signal line L at the earliest after 127 μs. For example, 100 μs after the IO buffer 12 enters a high-impedance state (oe=0), the IO buffer 12 will read "0" from the signal line L when the resistance constant Ra is 1 kΩ, and the IO buffer 12 will read "1" from the signal line L when the resistance constant Rb is 5.1 kΩ.

[0091] [2-5. About Timing Charts] Figures 13 and 14 show the timing charts of the signals (out signal, oe signal, and in signal) between the IO buffer control unit 114 and the IO buffer 12 for each combination of resistor mounting position MP and resistance constant R. Figure 13(A) shows the timing chart TC7 for the setting value 7 shown in Figure 10(A), Figure 13(B) shows the timing chart TC6 for the setting value 6 shown in Figure 10(B), Figure 13(C) shows the timing chart TC5 for the setting value 5 shown in Figure 10(C), Figure 13(D) shows the timing chart TC4 for the setting value 4 shown in Figure 10(D), Figure 14(A) shows the timing chart TC3 for the setting value 3 shown in Figure 10(E), Figure 14(B) shows the timing chart TC2 for the setting value 2 shown in Figure 10(F), Figure 14(C) shows the timing chart TC1 for the setting value 1 shown in Figure 10(G), and Figure 14(D) shows the timing chart TC0 for the setting value 0 shown in Figure 10(H).

[0092] Here, similar to the first embodiment, the in signal is the result of the IO buffer 12, which is a LVTTL buffer, reading "0" or "1" from the potential Vc [V] of the signal line L shown in FIGS. 11 and 12. When Vc > Vih (2.0 [V]), the IO buffer 12 determines that the in signal is "1" (hereinafter also referred to as in = 1). Also, when Vil (0.8 [V]) < Vc < Vih (2.0 [V]), the IO buffer 12 determines that the in signal is indeterminate (it is not certain whether it is "0" or "1"). Further, when Vc < Vil (0.8 [V]), the IO buffer 12 determines that the in signal is "0" (hereinafter also referred to as in = 0).

[0093] The times Tua, Tub, Tuc, and Tud shown in FIG. 13 are, respectively, the times from time T2 until in = 1 is determined when the resistors 6a, 6b, 6c, and 6d are mounted at the resistor mounting position MPu. Also, the times Tda, Tdb, Tdc, and Tdd shown in FIG. 14 are, respectively, the times from time T2 until in = 0 is determined when the resistors 6a, 6b, 6c, and 6d are mounted at the resistor mounting position MPl.

[0094] The times Tiub, Tiuc, and Tiud shown in FIG. 13 are, respectively, the times from time T2 until the in signal becomes indeterminate when the resistors 6b, 6c, and 6d are mounted at the resistor mounting position MPu. Also, the times Tidb, Tidc, and Tidd shown in FIG. 14 are, respectively, the times from time T2 until the in signal becomes indeterminate when the resistors 6b, 6c, and 6d are mounted at the resistor mounting position MPl.

[0095] From Figures 11 and 12, the following values ​​are obtained in the second embodiment. When resistor 6a is mounted at resistor mounting position MPu, time Tua = 47 [μs]. When resistor 6b is mounted at resistor mounting position MPu, time Tiub = 70 [μs] and time Tub = 238 [μs]. When resistor 6c is mounted at resistor mounting position MPu, time Tiuc = 277 [μs] and time Tuc = 932 [μs]. When resistor 6d is mounted at resistor mounting position MPu, time Tiud = 1388 [μs]. When resistor 6a is mounted at resistor mounting position MPl, time Tda = 71 [μs]. When resistor 6b is mounted at resistor mounting position MPl, time Tidb = 127 [μs] and time Tdb = 362 [μs]. If resistor 6c is installed at resistor mounting position MPl, time Tidc = 500 [μs] and time Tdc = 1417 [μs]. If resistor 6d is installed at resistor mounting position MPl, time Tidd = 2503 [μs].

[0096] The times T3, T4, and T5 shown in Figures 13 and 14 are the times when the IO buffer control unit 114 reads the value of the in signal in steps SP15, SP16, and SP17, or steps SP20, SP21, and SP22, respectively, in the setting value reading processing procedure RT101 shown in Figure 15.

[0097] When resistor 6 is mounted at resistor mounting position MPu, times T3, T4, and T5 are set to times such that time Tua < time T3 < time Tiub, time Tub < time T4 < time Tiuc, and time Tuc < time T5 < time Tiud. Specifically, in the second embodiment, when resistor 6 is mounted at resistor mounting position MPu, time T3 = 60 [μs], time T4 = 260 [μs], and time T5 = 1100 [μs].

[0098] When resistor 6 is mounted at resistor mounting position MPl, times T3, T4, and T5 are set to times such that time Tda < time T3 < time Tidb, time Tdb < time T4 < time Tidc, and time Tdc < time T5 < time Tidd. Specifically, in the second embodiment, when resistor 6 is mounted at resistor mounting position MPl, time T3 = 100 [μs], time T4 = 450 [μs], and time T5 = 1600 [μs].

[0099] [2-6. Regarding the Table of Conversions to Setting Values] Here, the value of the in signal read by the IO buffer control unit 114 at step SP11 (first time point) in the setting value reading process procedure RT101 (Figure 15) is also called the first time point reading value. Furthermore, the value of the in signal read by the IO buffer control unit 114 at step SP15 or SP20 (third time point) in the setting value reading process procedure RT101 is also called the third time point reading value. In addition, the value of the in signal read by the IO buffer control unit 114 at step SP16 or SP21 (fourth time point) in the setting value reading process procedure RT101 is also called the fourth time point reading value. Furthermore, the value of the in signal read by the IO buffer control unit 114 at step SP17 or SP22 (fourth time point) in the setting value reading process procedure RT101 is also called the fifth time point reading value.

[0100] Figure 16 shows the setting value conversion table TB1. The setting value conversion table TB1 is a table that converts (i.e., converts) the values ​​of the in signal read four times by the IO buffer control unit 114 at the 1st, 3rd, 4th, and 5th time points in the setting value reading processing procedure RT101 to the actual current setting value. For example, if the readings at the 1st, 3rd, 4th, and 5th time points are all "1", the current setting value will be 7 (i.e., "111b" in binary).

[0101] [2-7. Setting Value Reading Process] Next, regarding the setting value reading procedure RT101, which is the specific processing procedure for the setting value reading process performed by the IO buffer control unit 114 before the firmware starts up when the semiconductor integrated circuit 103 is powered on, we will explain three representative patterns out of eight possible combinations of resistor mounting position MP and resistance constant R, using the timing charts in Figures 13 and 14 and the flowchart in Figure 15. The IO buffer control unit 114 starts the setting value reading procedure RT101 and moves to step SP11.

[0102] [2-7-1. When the setting value is 7] First, we will explain the case where the setting value is 7, as shown in Figure 10(A), where a resistor 6a with resistance constant Ra is mounted at resistor mounting position MPu, and nothing is mounted at resistor mounting position MPl, using the timing chart TC7 shown in Figure 13(A).

[0103] When power is turned on, in step SP11 the IO buffer control unit 114 sets out=0 / oe=0 to put the IO buffer 12 into a high-impedance state, reads the value of the in signal as the first signal at the first time point at time T0 after a certain period of time has elapsed, stores it in the storage unit 18, and proceeds to step SP12. In reality, when power is turned on to the semiconductor integrated circuit 103 and the reset signal of the semiconductor integrated circuit 103 is turned from on to off, the IO buffer control unit 114 reads the value of the in signal at time T0. Here, since resistor 6a is mounted at resistor mounting position MPu and signal line L is pulled up to 3.3[V], the in signal = "1". In step SP12 the IO buffer control unit 114 determines whether the value of the in signal read in step SP11 is "1". Here, since the value of the in signal is "1", the IO buffer control unit 114 obtains a positive result in step SP12 and proceeds to step SP13.

[0104] In step SP13, the IO buffer control unit 114 sets the IO buffer 12 to output "0" as the second signal at the second time point in time, with out=0 / oe=1 at time T1, and after a certain period of time has elapsed, proceeds to step SP14. In step SP13, the IO buffer control unit 114 outputs a value from the out signal that has a different logic level from the value of the in signal read in step SP11.

[0105] In step SP14, the IO buffer control unit 114 sets out=0 / oe=0 again at time T2, putting the IO buffer 12 into a high-impedance state, and after 60 [μs] has elapsed, proceeds to step SP15. Note that the IO buffer control unit 114 counts the elapsed time of 60 [μs] by waiting 600 clock cycles, since the clock frequency of OSC4 is 10 [MHz] (period 0.1 [μs]).

[0106] In step SP15, the IO buffer control unit 114 reads the third time point reading value, which is the value of the in signal as the third signal at time T3, and stores it in the storage unit 18. Then, 260 [μs] elapsed from the time (time T2) when the IO buffer 12 was put into a high-impedance state in step SP14, the unit proceeds to step SP16.

[0107] In step SP16, the IO buffer control unit 114 reads the fourth time point reading value, which is the value of the in signal as the fourth signal at time T4, and stores it in the storage unit 18. After 1100 [μs] have elapsed since the time (time T2) when the IO buffer 12 was put into a high-impedance state in step SP14, the unit proceeds to step SP17.

[0108] In step SP17, the IO buffer control unit 114 reads the value of the in signal, which is the value of the fifth signal at time T5, stores it in the storage unit 18, and moves to step SP23. Here, the resistance constant is Ra. In this case, 47 μs have elapsed from time T2 (t=0 [μs] in Figure 11), and the potential of the signal line L for the resistance constant Ra is Vc > Vih (2.0 [V]), so in = "1". Therefore, in = "1" will also be the case at times T3, T4, and T5, which are more than 47 μs after time T2.

[0109] In step SP23, the IO buffer control unit 114 transfers the signal control rights of the IO buffer 12 to the transmission unit 16 by setting out=tx / oe=1 at time T6, and proceeds to step SP24.

[0110] In step SP24, the IO buffer control unit 114 determines the current setting value based on the value of the IN signal read in steps SP11, SP15, SP16, and SP17, and proceeds to step SP25. Specifically, since the first, third, fourth, and fifth time point readings read in steps SP11, SP15, SP16, and SP17 were all "1", the IO buffer control unit 114 refers to the setting value conversion correspondence table TB1 (Figure 16) and determines that the current setting value is 7 (i.e., "111b" in binary).

[0111] In step SP25, the IO buffer control unit 114 stores the determined setting value in the storage unit 18, then moves to step SP26 and terminates the setting value reading procedure RT101. In this way, the IO buffer control unit 114 reads the value of the in signal four times, and based on the readings at the first, third, fourth, and fifth points in time, it refers to the setting value conversion correspondence table TB1 (Figure 16) to determine the setting value.

[0112] [2-7-2. When the setting value is 5] Next, we will explain the case where the setting value is 5, as shown in Figure 10(C), where a resistor 6c with resistance constant Rc is mounted at resistor mounting position MPu, and nothing is mounted at resistor mounting position MPl, using the timing chart TC5 shown in Figure 13(C).

[0113] When power is turned on, in step SP11 the IO buffer control unit 114 sets out=0 / oe=0 to put the IO buffer 12 into a high-impedance state, reads the value of the in signal as the first signal at the first time point at time T0 after a certain period of time has elapsed, stores it in the storage unit 18, and moves to step SP12. Here, since resistor 6c is mounted at resistor mounting position MPu and signal line L is pulled up to 3.3[V], the in signal becomes "1". In step SP12 the IO buffer control unit 114 determines whether the value of the in signal read in step SP11 is "1". Here, the value of the in signal was "1", so the IO buffer control unit 114 obtains a positive result in step SP12 and moves to step SP13.

[0114] In step SP13, the IO buffer control unit 114 sets the IO buffer 12 to output "0" as the second signal at the second time point in time, with out=0 / oe=1 at time T1, and after a certain period of time has elapsed, proceeds to step SP14. In step SP13, the IO buffer control unit 114 outputs a value from the out signal that has a different logic level from the value of the in signal read in step SP11.

[0115] In step SP14, the IO buffer control unit 114 sets out=0 / oe=0 again at time T2, putting the IO buffer 12 into a high-impedance state, and after 60 [μs] has elapsed, proceeds to step SP15.

[0116] In step SP15, the IO buffer control unit 114 reads the read value at the third time point, which is the value of the in signal as the third signal at time T3, and stores it in the storage unit 18. After 260 [μs] have elapsed since the time (time T2) when the IO buffer 12 was set to the high-impedance state in step SP14, it proceeds to step SP16.

[0117] In step SP16, the IO buffer control unit 114 reads the read value at the fourth time point, which is the value of the in signal as the fourth signal at time T4, and stores it in the storage unit 18. After 1100 [μs] have elapsed since the time (time T2) when the IO buffer 12 was set to the high-impedance state in step SP14, it proceeds to step SP17.

[0118] In step SP17, the IO buffer control unit 114 reads the read value at the fifth time point, which is the value of the in signal as the fifth signal at time T5, and stores it in the storage unit 18, and then proceeds to step SP23. Here, it is the resistance constant Rc. In this case, until 277 [μs] before the elapse of time from time T2 (t = 0 [μs] in FIG. 11), the potential Vc of the signal line L in the case of the resistance constant Rc is less than Vil (0.8 [V]), and in = "0" is maintained. Therefore, in = "0" also at times T3 and T4 before 277 [μs] have elapsed from time T2. Also in this case, after 1100 [μs] have elapsed from time T2 (t = 0 [μs] in FIG. 11), the potential Vc of the signal line L in the case of the resistance constant Rc is greater than Vih (2.0 [V]), and in = "1". Therefore, in = "1" also at time T5 when 1100 [μs] or more have elapsed from time T2.

[0119] In step SP23, the IO buffer control unit 114 transfers the signal control right of the IO buffer 12 to the transmission unit 16 with out = tx / oe = 1 at time T6, and proceeds to step SP24.

[0120] In step SP24, the IO buffer control unit 114 determines the current setting value based on the values ​​of the IN signals read in steps SP11, SP15, SP16, and SP17, and then proceeds to step SP25. Specifically, the IO buffer control unit 114 determines that the current setting value is 5 (i.e., "101b" in binary representation) because the first reading value read in step SP11 was "1", the third and fourth reading values ​​read in steps SP15 and SP16 were "0", and the fifth reading value read in step SP17 was "1".

[0121] In step SP25, the IO buffer control unit 114 stores the determined setting value in the storage unit 18, then proceeds to step SP26 and terminates the setting value reading procedure RT101.

[0122] [2-7-3. When the setting value is 1] Next, we will explain the case where the setting value = 1, as shown in Figure 10(G), where a resistor 6b with resistance constant Rb is mounted at resistor mounting position MPl, and nothing is mounted at resistor mounting position MPu, using the timing chart TC1 shown in Figure 14(C).

[0123] When power is turned on, in step SP11 the IO buffer control unit 114 sets out=0 / oe=0 to put the IO buffer 12 into a high-impedance state, reads the value of the in signal as the first signal at the first time point at time T0 after a certain period of time has elapsed, stores it in the storage unit 18, and moves to step SP12. Here, since resistor 6b is mounted at resistor mounting position MPl and signal line L is pulled down to 0[V], the in signal = "0". In step SP12 the IO buffer control unit 114 determines whether the value of the in signal read in step SP11 is "1" or not. Here, the value of the in signal was "0", so the IO buffer control unit 114 obtains a negative result in step SP12 and moves to step SP18.

[0124] In step SP18, the IO buffer control unit 114 sets the IO buffer 12 to output "1" as the second signal at the second time point in time, with out=1 / oe=1 at time T1, and after a certain period of time has elapsed, proceeds to step SP19. In step SP18, the IO buffer control unit 114 outputs a value from the out signal that has a different logic level from the value of the in signal read in step SP11.

[0125] In step SP19, the IO buffer control unit 114 sets out=0 / oe=0 again at time T2, putting the IO buffer 12 into a high-impedance state, and after 100 [μs] has elapsed, proceeds to step SP20.

[0126] In step SP20, the IO buffer control unit 114 reads the third time point reading value, which is the value of the in signal as the third signal at time T3, and stores it in the storage unit 18. Then, 450 [μs] elapsed from the time (time T2) when the IO buffer 12 was put into a high-impedance state in step SP19, the unit proceeds to step SP21.

[0127] In step SP21, the IO buffer control unit 114 reads the value of the in signal, which is the value of the fourth signal at time T4, and stores it in the storage unit 18. Then, 1600 [μs] elapsed from the time (time T2) when the IO buffer 12 was put into a high-impedance state in step SP19, the unit proceeds to step SP22.

[0128] In step SP22, the IO buffer control unit 114 reads the read value at the fifth time point, which is the value of the in signal as the fifth signal at time T5, and stores it in the storage unit 18, then moves to step SP23. Here, it is the resistance constant Rb. In this case, from time T2 (t = 0 [μs] in FIG. 12) until 127 [μs] has elapsed, since the potential Vc of the signal line L in the case of the resistance constant Rb is Vc > Vih (2.0 [V]) and in = "1" is maintained, at time T3 before 127 [μs] has elapsed from time T2, in = "1" also holds. Also in this case, after 362 [μs] has elapsed from time T2 (t = 0 [μs] in FIG. 12), since the potential Vc of the signal line L in the case of the resistance constant Rb is Vc < Vil (0.8 [V]) and in = "0", at times T4 and T5 when 362 [μs] or more has elapsed from time T2, in = "0" also holds.

[0129] In step SP23, the IO buffer control unit 114 transfers the signal control right of the IO buffer 12 to the transmission unit 16 with out = tx / oe = 1 at time T6, and moves to step SP24.

[0130] In step SP24, the IO buffer control unit 114 determines the current set value based on the values of the in signal read in steps SP11, SP20, SP21, and SP22, and moves to step SP25. Specifically, since the read value at the first time point read in step SP11 is "0", the read value at the third time point read in step SP15 is "1", and the read values at the fourth and fifth time points read in steps SP16 and SP17 are "0", referring to the set value read substitution correspondence table TB1 (FIG. 16), it is determined that the current set value is 1 (that is, "001b" in binary representation).

[0131] In step SP25, the IO buffer control unit 114 stores the determined set value in the storage unit 18, moves to step SP26, and ends the set value reading processing procedure RT101.

[0132] [2-8. Effects, etc.] In the above configuration, the substrate 102 is configured to mount one of the resistors 6a, 6b, 6c, or 6d, each with different resistance values, at either the MPu or MPl resistor mounting position, depending on the setting value used during initial operation of the semiconductor integrated circuit 103. In other words, the substrate 102 is configured to have varying resistance values ​​for pull-up and pull-down resistors.

[0133] Furthermore, the semiconductor integrated circuit 103 first reads the state of terminal 11 in a high-impedance state and acquires a 1-bit setting. Next, it sets terminal 11 to a state with a logic level different from the state read earlier, either 0 output or 1 output, then returns it to a high-impedance state. After that, it reads the state of terminal 11 three more times at different timings (times T3, T4, and T5) and acquires another 3-bit setting value. As a result, the semiconductor integrated circuit 103 can acquire 3 bits (8 different) setting values ​​for a single terminal, terminal 11.

[0134] As a result, the semiconductor integrated circuit 103 can acquire four times the amount of setting information compared to the conventional method, even if the number of terminals that can be used to acquire setting information remains the same, compared to the conventional method where one bit of setting value per terminal is read in a high-impedance state using a pull-up resistor or pull-down resistor composed of one type of resistance value.

[0135] In other respects, the semiconductor integrated circuit 103 according to the second embodiment can achieve the same effects as the semiconductor integrated circuit 3 according to the first embodiment.

[0136] [3. Third Embodiment] [3-1. Printer Configuration] As shown in Figure 1 and Figure 17, which uses the same reference numerals as Figure 8, the printer 201 according to the third embodiment differs from the printer 101 according to the second embodiment in that it has a circuit board 202 instead of a circuit board 102, but is otherwise configured similarly.

[0137] [3-2. Circuit Board Configuration] As shown in Figure 17, the substrate 202 according to the third embodiment differs from the substrate 102 according to the second embodiment in that a semiconductor integrated circuit 203 is provided instead of the semiconductor integrated circuit 103, but is otherwise configured similarly. The semiconductor integrated circuit 203 according to the third embodiment differs from the semiconductor integrated circuit 103 according to the second embodiment in that an IO buffer control unit 214 is provided instead of the IO buffer control unit 114, and a timing unit 20 is added, but is otherwise configured similarly. Figure 18 shows the substrate 202 in which the capacitor 8 and the opposing device 10 are replaced with a capacitor 9 having an equivalent load capacitance.

[0138] The timing unit 20, under the control of the IO buffer control unit 214, measures the logic level inversion measurement time Tu, which is the time from when the IO buffer 12 is put into a high-impedance state in step SP14 or SP19 of the set value reading processing procedure RT201 (described later) (time T2) until the in signal is inverted in step SP31 or SP32.

[0139] [3-3. Regarding the combination of resistor mounting position and resistance constant] As shown in Figure 10, the combinations of resistor mounting positions MPu and MPl, where the resistor 6 can be mounted on the substrate 202, and the resistance constants Ra, Rb, Rc, and Rd of the resistor 6 are the same as in the second embodiment.

[0140] [3-4. Relationship between elapsed time and signal line potential] [3-4-1. Resistor mounting location: When resistors 6a, 6b, 6c, or 6d are mounted on MPu] As shown in Figure 11, when resistors 6a, 6b, 6c, or 6d are mounted at the resistor mounting position MPu, and the IO buffer 12 is in a high-impedance state (oe=0), the graph showing the potential change of the signal line L potential Vc[V] starting from signal line L=0[V] is the same as in the second embodiment.

[0141] [3-4-2. When resistors 6a, 6b, 6c, or 6d are mounted at resistor mounting position MPl] As shown in Figure 12, when resistors 6a, 6b, 6c, or 6d are mounted at resistor mounting position MPl using the step response calculation formula for the RC circuit, and the IO buffer 12 is in a high-impedance state (oe=0), the graph showing the potential change of the signal line L potential Vc[V] starting from signal line L=3.3[V] is the same as in the second embodiment.

[0142] [3-5. About Timing Charts] As shown in Figures 13 and 14, the timing charts of the signals (out signal, oe signal, and in signal) between the IO buffer control unit 214 and the IO buffer 12 for each combination of resistor mounting position MP and resistance constant R are the same as in the second embodiment.

[0143] [3-6. Regarding the Table of Conversions to Setting Values] Here, the value of the in signal read by the IO buffer control unit 214 in step SP11 (first time point) of the setting value reading processing procedure RT201 (Figure 19) is also called the first time point reading value.

[0144] Figure 20 shows the setting value conversion table TB201. The setting value conversion table TB201 is a table that converts the value of the in signal read once by the IO buffer control unit 214 in the setting value reading processing procedure RT201 and the logic level inversion measurement time Tu to the actual current setting value. In the setting value conversion table TB201, four different judgment ranges for the logic level inversion measurement time Tu are set, each with a predetermined time width corresponding to the four types of resistance values ​​of resistors 6a, 6b, 6c, or 6d. The IO buffer control unit 214 determines which of the four judgment ranges in the setting value conversion table TB201 the measured logic level inversion measurement time Tu corresponds to. In the third embodiment, the four judgment ranges for the logic level inversion measurement time Tu are set to be the same regardless of whether the mounting position of resistor 6 is resistor mounting position MPu or MPl. For example, if the initial reading is "1" and the logic level inversion measurement time Tu is less than 80 [μs], the current setting value will be 7 (i.e., "111b" in binary).

[0145] [3-7. Setting Value Reading Process] Next, regarding the setting value reading procedure RT201, which is the specific processing procedure for the setting value reading process in which the IO buffer control unit 214 reads the setting value before the firmware starts up when the semiconductor integrated circuit 203 is powered on, we will explain three representative patterns out of eight possible combinations of resistor mounting position MP and resistance constant R, using the timing charts in Figures 13 and 14 and the flowchart in Figure 19, in which the steps corresponding to Figure 15 are given the same reference numerals. The setting value reading procedure RT201 differs from the setting value reading procedure RT101 (Figure 15) in that step SP31 is provided instead of steps SP15, SP16, and SP17, step SP32 is provided instead of steps SP20, SP21, and SP22, and step SP224 is provided instead of step SP24, but otherwise it is configured similarly. The IO buffer control unit 214 starts the setting value reading procedure RT201 and moves to step SP11.

[0146] [3-7-1. When the setting value is 7] First, we will explain the case where the setting value is 7, as shown in Figure 10(A), where a resistor 6a with resistance constant Ra is mounted at resistor mounting position MPu, and nothing is mounted at resistor mounting position MPl, using the timing chart TC7 shown in Figure 13(A).

[0147] In steps SP11 to SP13, the IO buffer control unit 214 performs the same processing as the setting value reading procedure RT101 (Figure 15), and then moves to step SP14. In step SP14, the IO buffer control unit 214 sets out=0 / oe=0 again at time T2, putting the IO buffer 12 into a high-impedance state, and then moves to step SP31.

[0148] In step SP31, the IO buffer control unit 214 reads and monitors the value of the in signal as the third signal at the third time point in time, and measures the time from the point in step SP14 when the IO buffer 12 is put into a high-impedance state (time T2) until the in signal changes from in="0" to in="1" (i.e., the logic level of the read value is reversed) using the timing unit 20, stores it in the storage unit 18, and moves to step SP23. The IO buffer control unit 214 monitors the value of the in signal at 0.1 [μs] intervals because the clock frequency of OSC4 is 10 [MHz] (period 0.1 [μs]). Here, the resistance constant is Ra. In this case, 47 μs after time T2 (t=0 [μs] in Figure 11), the potential Vc of the signal line L for the resistance constant Ra becomes Vih (2.0 [V]) and in = "1". Therefore, the logic level inversion measurement time Tu, which is the time measured by the timing unit 20, is 47 [μs].

[0149] In step SP23, the IO buffer control unit 214 performs the same processing as the setting value reading procedure RT101 (Figure 15), and then proceeds to step SP224.

[0150] In step SP224, the IO buffer control unit 214 determines the current setting value based on the value of the in signal read in step SP11 and the time measured in step SP31, and then proceeds to step SP25. Specifically, the IO buffer control unit 214 determines that the current setting value is 7 (i.e., "111b" in binary representation) because the first time point read value read in step SP11 was "1" and the logic level inversion measurement time Tu measured in step SP31 was 47 [μs].

[0151] In step SP25, the IO buffer control unit 214 performs the same processing as the setting value reading procedure RT101 (Figure 15), then moves to step SP26 and terminates the setting value reading procedure RT201. In this way, the IO buffer control unit 214 reads the value of the in signal (first time reading value) once at time T0, outputs a value from the out signal that has a different logic level from the value of this in signal at time T1, sets the IO buffer 12 to a high-impedance state again at time T2, measures the logic level inversion measurement time Tu until the value of the in signal changes to the value read at time T0, and determines the setting value by referring to the setting value conversion correspondence table TB201 (Figure 20) based on the first time reading value and the logic level inversion measurement time Tu.

[0152] [3-7-2. When the setting value is 5] Next, we will explain the case where the setting value is 5, as shown in Figure 10(C), where a resistor 6c with resistance constant Rc is mounted at resistor mounting position MPu, and nothing is mounted at resistor mounting position MPl, using the timing chart TC5 shown in Figure 13(C).

[0153] In steps SP11 to SP13, the IO buffer control unit 214 performs the same processing as the setting value reading procedure RT101 (Figure 15), and then moves to step SP14. In step SP14, the IO buffer control unit 214 sets out=0 / oe=0 again at time T2, putting the IO buffer 12 into a high-impedance state, and then moves to step SP31.

[0154] In step SP31, the IO buffer control unit 214 reads and monitors the value of the in signal as the third signal at the third time point in time, using the clock period. The time measurement unit 20 measures the time from the moment the IO buffer 12 is put into a high-impedance state in step SP14 (time T2) until the in signal changes from in="0" to in="1" (i.e., the logic level of the read value is inverted), stores this time in the storage unit 18, and proceeds to step SP23. Here, the resistance constant is Rc. In this case, after 932 [μs] from time T2 (t=0 [μs] in Figure 11), the potential of the signal line L in the case of resistance constant Rc becomes Vc > Vih (2.0 [V]) and in="1", so the logic level inversion measurement time Tu, which is the time measured by the time measurement unit 20, is 932 [μs].

[0155] In step SP23, the IO buffer control unit 214 performs the same processing as the setting value reading procedure RT101 (Figure 15), and then proceeds to step SP224.

[0156] In step SP224, the IO buffer control unit 214 determines the current setting value based on the value of the in signal read in step SP11 and the time measured in step SP31, and then proceeds to step SP25. Specifically, the IO buffer control unit 214 determines that the current setting value is 5 (i.e., "101b" in binary representation) because the value of the first signal read in step SP11 was "1" and the logic level inversion measurement time Tu measured in step SP31 was 932 [μs], by referring to the setting value conversion correspondence table TB201 (Figure 20).

[0157] In step SP25, the IO buffer control unit 214 performs the same processing as the setting value reading procedure RT101 (Figure 15), then moves to step SP26 and terminates the setting value reading procedure RT201.

[0158] [3-7-3. When the setting value is 1] Next, as shown in FIG. 10(G), for the case where the set value = 1, which is a pattern in which a resistor 6b with a resistance constant Rb is mounted at the resistor mounting position MPl and nothing is mounted at the resistor mounting position MPu, it will be described using the timing chart TC1 shown in FIG. 14(C).

[0159] In steps SP11, SP12, and SP18, the IO buffer control unit 214 performs the same processing as the set value reading processing procedure RT101 (FIG. 15), and moves to step SP19. In step SP19, the IO buffer control unit 214 sets out = 0 / oe = 0 again at time T2 to put the IO buffer 12 in a high-impedance state, and moves to step SP32.

[0160] In step SP32, the IO buffer control unit 214 reads and monitors the value of the in signal as the third signal at the third time point in the clock cycle. From the time (time T2) when the IO buffer 12 was put in the high-impedance state in step SP19, the time measurement unit 20 measures the time until the in signal changes from in = "1" to in = "0" (that is, the logic level of the read value is inverted) and stores it in the storage unit 18, and then moves to step SP23. Here, it is the resistance constant Rb. In this case, since the potential Vc of the signal line L in the case of the resistance constant Rb becomes Vc < Vil (0.8 [V]) and in = "0" after 362 [μs] has elapsed from time T2 (t = 0 [μs] in FIG. 12), the logic level inversion measurement time Tu, which is the time measured by the time measurement unit 20, is 362 [μs].

[0161] In step SP23, the IO buffer control unit 214 performs the same processing as the set value reading processing procedure RT101 (FIG. 15), and moves to step SP224.

[0162] In step SP224, the IO buffer control unit 214 determines the current setting value based on the value of the in signal read in step SP11 and the time measured in step SP32, and then proceeds to step SP25. Specifically, the IO buffer control unit 214 determines that the current setting value is 1 (i.e., "001b" in binary representation) because the first time point read value read in step SP11 was "1" and the logic level inversion measurement time Tu measured in step SP32 was 362 [μs], by referring to the setting value conversion correspondence table TB201 (Figure 20).

[0163] In step SP25, the IO buffer control unit 214 performs the same processing as the setting value reading procedure RT101 (Figure 15), then moves to step SP26 and terminates the setting value reading procedure RT201.

[0164] [3-8. Effects, etc.] In the above configuration, the substrate 202 is configured to mount one of the resistors 6a, 6b, 6c, or 6d, each with different resistance values, at either the resistor mounting position MPu or MPl, depending on the setting value used during initial operation of the semiconductor integrated circuit 203. In other words, the substrate 202 is configured to have varying resistance values ​​for pull-up and pull-down resistors.

[0165] Furthermore, the semiconductor integrated circuit 203 first reads the state of terminal 11 in a high-impedance state and acquires a 1-bit setting. Next, it sets terminal 11 to a state of either 0 output or 1 output so that its logic level is different from the state read earlier, then returns it to a high-impedance state, and then measures the time (logic level inversion measurement time Tu) until the state of terminal 11 changes. As a result, the semiconductor integrated circuit 203 can acquire 3 bits (8 different) setting values ​​for a single terminal, terminal 11.

[0166] As a result, the semiconductor integrated circuit 203 can acquire four times the amount of setting information compared to the conventional method, even if the number of terminals available for acquiring setting information remains the same, compared to the conventional method where one bit of setting value per terminal is read in a high-impedance state using a pull-up resistor or pull-down resistor composed of one type of resistance value.

[0167] Furthermore, the semiconductor integrated circuit 203 determines the set value based on the time (logic level inversion measurement time Tu) between returning terminal 11 to a high-impedance state and the subsequent change in the state of terminal 11. Therefore, the shorter the logic level inversion measurement time Tu, the faster the set value can be determined. For this reason, compared to the method (second embodiment) in which the state of terminal 11 is read multiple times at predetermined time intervals after returning terminal 11 to a high-impedance state, the semiconductor integrated circuit 203 can determine the set value in a shorter time when the logic level inversion measurement time Tu is short.

[0168] In other respects, the semiconductor integrated circuit 203 according to the third embodiment can achieve the same effects as the semiconductor integrated circuit 103 according to the second embodiment.

[0169] [4. Other Embodiments] In the first embodiment described above, the case was described in which either resistor 6s or 6w, each having two different resistance values, is mounted at either resistor mounting position MPu or MPl. The present invention is not limited to this, and any one of a plurality of resistors, each having three or more different resistance values, may be mounted at either resistor mounting position MPu or MPl, thereby allowing the reading of three or more set values ​​per terminal.

[0170] Furthermore, the above-described embodiment mentions the case where a resistor 6 is used as the impedance element. The present invention is not limited to this, and in addition to the resistor 6, a coil may be added in series with the signal line L as an impedance element.

[0171] Furthermore, in the first embodiment described above, the case was described in which either resistor 6s or 6w, which have different resistance values, are mounted at either resistor mounting position MPu or MPl. The present invention is not limited to this, and the semiconductor integrated circuit 3 may read the set value by selecting and mounting a capacitor 8 from a plurality of capacitors 8 having different capacitance values. The same applies to the second and third embodiments.

[0172] Furthermore, the first embodiment described above describes the case in which either a chip resistor, resistor 6s or 6w, is mounted at either the resistor mounting position MPu or MPl. The present invention is not limited to this, and a variable resistor may be mounted at either the resistor mounting position MPu or MPl, and the resistance value of the variable resistor may be switched to 2 [kΩ] or 10 [kΩ] depending on the set value. Similarly, in the second and third embodiments, the resistance value of the variable resistor may be switched to four different values.

[0173] Furthermore, in the first embodiment described above, the case where the value of the in signal read the first time is treated as the most significant bit in the binary representation of the set value, and the value of the in signal read the second time is treated as the least significant bit in the binary representation of the set value was described. The present invention is not limited to this, and the value of the in signal read the first time may be treated as the least significant bit in the binary representation of the set value, and the value of the in signal read the second time may be treated as the most significant bit in the binary representation of the set value.

[0174] Furthermore, in the first embodiment described above, the case was described in which the value of the in signal as the first signal at the first time point in step SP1 of the set value reading procedure RT1 (Figure 7) is read at time T0. The present invention is not limited to this, and the value of the in signal may be read at any time point before time T1. The same applies to the second and third embodiments.

[0175] Furthermore, in the second embodiment described above, one of four resistors 6a, 6b, 6c, or 6d, each having a different resistance value, is mounted at either the resistor mounting position MPu or MPl, and the state of terminal 11 is measured four times to obtain eight different setting values ​​per terminal. The present invention is not limited to this, however, one of a plurality of resistors, each having three different resistance values, may be mounted at either the resistor mounting position MPu or MPl, and the state of terminal 11 is measured three times to obtain six different setting values ​​per terminal. Alternatively, one of a plurality of resistors, each having any number of five or more different resistance values, may be mounted at either the resistor mounting position MPu or MPl, and the state of terminal 11 is measured five or more times to obtain any number of setting values ​​of ten or more per terminal.

[0176] Furthermore, in the third embodiment described above, one of four resistors 6a, 6b, 6c, or 6d, each having a different resistance value, is mounted at either the resistor mounting position MPu or MPl, and the logic level inversion measurement time Tu is classified into four types each for the pull-up resistor and the pull-down resistor, thereby obtaining eight different setting values ​​per terminal. The present invention is not limited to this, however, one of a plurality of resistors, each having three different resistance values, is mounted at either the resistor mounting position MPu or MPl, and the logic level inversion measurement time Tu is classified into three types each for the pull-up resistor and the pull-down resistor, thereby obtaining six different setting values ​​per terminal. Alternatively, one of several resistors having any number of five or more different resistance values ​​may be mounted at either the resistor mounting position MPu or MPl, and the logic level inversion measurement time Tu may be classified into any number of five or more types for each of the pull-up resistor and the pull-down resistor, thereby obtaining any number of arbitrary settings of 10 or more types per terminal.

[0177] Furthermore, in the third embodiment described above, the case was described in which the four determination ranges for the logic level inversion measurement time Tu are set to the same value in the setting value conversion correspondence table TB201 (Figure 20), regardless of whether the mounting position of the resistor 6 is the resistor mounting position MPu or MPl. The present invention is not limited to this, and the four determination ranges for the logic level inversion measurement time Tu may be set to different values ​​depending on whether the mounting position of the resistor 6 is the resistor mounting position MPu or the resistor mounting position MPl.

[0178] Furthermore, the resistance constant R of the resistor 6, the capacitance value of the capacitor 8, and the clock frequency of the OSC 4 in the above-described embodiments are merely examples, and other values ​​may be used. In other words, the present invention is not limited to the embodiments described above, and can be modified in various ways based on the spirit of the present invention, without excluding them from the scope of the present invention.

[0179] Furthermore, the above-described embodiment mentions the case where LVTTL is used as the IO buffer 12. The present invention is not limited to this, and various other forms of buffers, such as LVCMOS (Low Voltage CMOS), may be used.

[0180] Furthermore, the above-described embodiment described the case where the voltage of Vcc is 3.3[V]. The present invention is not limited to this, and the voltage of Vcc may be any other voltage, such as 5.0[V].

[0181] Furthermore, the above-described embodiment described the application of the present invention to semiconductor integrated circuits 3, 103, or 203 on substrates 2, 102, or 202 mounted on printers 1, 101, or 201 as electronic devices. The present invention is not limited to this, and may also be applied to semiconductor integrated circuits on substrates mounted on various other electronic devices, such as MFPs (Multi-Function Peripherals) that have the functions of copiers or facsimile machines.

[0182] Furthermore, the present invention is not limited to the embodiments described above and other embodiments. That is, the scope of the present invention extends to embodiments that arbitrarily combine some or all of the embodiments described above and other embodiments. In addition, the scope of the present invention also extends when a part of the configuration described in any embodiment among the embodiments described above and other embodiments is extracted and substituted or adapted for a part of the configuration of any embodiment among the embodiments described above and other embodiments, or when the extracted part of the configuration is added to any embodiment. [Industrial applicability]

[0183] This invention can be used, for example, in integrated circuits mounted on a circuit board used in a printer. [Explanation of Symbols]

[0184] 1, 101, 201... Printer, 2, 102, 202... Circuit board, 3, 103, 203... Semiconductor integrated circuit, 4... OSC, 6s, 6w, 6a, 6b, 6c, 6d... Resistor, 8, 9... Capacitor, 10... Opposing device, 11... Terminal, 12... IO buffer, 14, 114, 214... IO buffer control unit, 16... Transmitter, 18... Memory unit, 20... Timing unit, TB1, TB201... Setting value conversion table, L, Loe, Lout, Lin... Signal line, tx... Output signal, MPu, MPl... Resistor mounting position, Rs, Rw, Ra, Rb, Rc, Rd... Resistance constant.

Claims

1. An integrated circuit having impedance elements with different characteristics connected to a terminal that can be connected to a power supply unit at a predetermined potential, A signal input section that receives signals from the aforementioned terminals, A control unit capable of controlling a signal output unit that electrically connects to any of the resistor terminals of the impedance element and outputs a signal that changes the potential, and It has, The control unit, After receiving a first signal from the signal input unit with the output of the signal output unit turned off, the signal output unit is made to output a second signal having different electrical characteristics from the first signal, and after outputting the second signal, the output of the signal output unit is turned off, and then a third signal from the signal input unit is received after a predetermined condition has been met, and the setting condition corresponding to the first signal and the setting condition corresponding to the third signal are stored in the storage unit. An integrated circuit that uses a plurality of the setting conditions stored in the memory unit as setting conditions when using the integrated circuit.

2. The impedance element is either a pull-up resistor or a pull-down resistor. The terminal is connected to the power supply voltage via the pull-up resistor, or to ground via the pull-down resistor. The pull-up resistor or the pull-down resistor has multiple different resistance values. The integrated circuit according to feature 1.

3. The control unit, Multiple setting conditions are read from the change in the potential of the terminal based on the resistance value of either the pull-up resistor, which has two different resistance values, or the pull-down resistor, which has two different resistance values, implemented according to the setting conditions. The integrated circuit according to feature 2.

4. The control unit, After receiving the first signal from the signal input unit with the output of the signal output unit turned off, the signal output unit outputs the second signal, which has a different logic level from the first signal. After outputting the second signal, the output of the signal output unit is turned off, and after a predetermined time has elapsed, the third signal from the signal input unit is received, and the setting conditions corresponding to the first signal and the setting conditions corresponding to the third signal are stored in the storage unit. The integrated circuit according to feature 3.

5. The control unit, After receiving the first signal from the signal input unit with the output of the signal output unit turned off, the signal output unit outputs a second signal with a logic level different from the first signal. After the output of the second signal, the signal output unit is turned off, and after a predetermined time has elapsed, the system receives the third signal from the signal input unit, where the higher the resistance value of the pull-up resistor or pull-down resistor, the smaller the change in potential corresponding to the elapsed time since the output of the second signal. The system then stores the setting conditions corresponding to the first signal and the setting conditions corresponding to the third signal in the storage unit. The integrated circuit according to feature 4.

6. The control unit, After receiving the first signal from the signal input unit with the output of the signal output unit turned off, the signal output unit outputs the second signal, which has a different logic level from the first signal. After the output of the second signal is turned off, and a predetermined time has elapsed, the signal input unit receives the third signal, where the higher the resistance value of the pull-up resistor or pull-down resistor, the smaller the change in potential corresponding to the elapsed time since the output of the second signal. The unit then stores in the memory unit a two-bit setting condition per terminal, where one bit corresponding to the potential of the first signal and one bit corresponding to the potential of the third signal are combined as different digits. The integrated circuit according to feature 5.

7. The control unit, The system reads multiple setting conditions from the change in the potential of the terminal based on the resistance value of either the pull-up resistors, which have multiple different resistance values, or the pull-down resistors, which have multiple different resistance values, implemented according to the setting conditions. The integrated circuit according to feature 2.

8. The control unit, After receiving the first signal from the signal input unit with the output of the signal output unit turned off, the signal output unit outputs the second signal, which has a different logic level from the first signal. After outputting the second signal, the output of the signal output unit is turned off, and after a predetermined time has elapsed, the third signal from the signal input unit is received, and the setting conditions corresponding to the first signal and the setting conditions corresponding to the third signal are stored in the storage unit. The integrated circuit according to feature 7.

9. The control unit, After receiving the first signal from the signal input unit with the output of the signal output unit turned off, the signal output unit outputs a second signal with a logic level different from the first signal. After the output of the second signal, the signal output unit is turned off, and after a predetermined time has elapsed, the system receives the third signal from the signal input unit, where the higher the resistance value of the pull-up resistor or pull-down resistor, the smaller the change in potential corresponding to the elapsed time since the output of the second signal. The system then stores the setting conditions corresponding to the first signal and the setting conditions corresponding to the third signal in the storage unit. The integrated circuit according to feature 8.

10. The control unit, After receiving the first signal from the signal input unit with the output of the signal output unit turned off, the signal output unit outputs the second signal, which has a different logic level from the first signal. After the output of the second signal is turned off, and a predetermined time has elapsed, the signal input unit receives the third signal, the higher the resistance value of the pull-up resistor or the pull-down resistor, the smaller the change in potential corresponding to the elapsed time since the second signal was output. After a predetermined time has elapsed since receiving the third signal, the signal input unit receives the fourth signal, the higher the resistance value of the pull-up resistor or the pull-down resistor, the smaller the change in potential corresponding to the elapsed time since the second signal was output. The unit then stores in the memory unit more than two bits per terminal of setting conditions corresponding to the potential of the first signal, the potential of the third signal, and the potential of the fourth signal. The integrated circuit according to feature 9.

11. The control unit, After receiving the first signal from the signal input unit with the output of the signal output unit turned off, the signal output unit outputs a second signal with a logic level different from the first signal. After outputting the second signal, the output of the signal output unit is turned off, and then the third signal from the signal input unit is received, where the higher the resistance value of the pull-up resistor or pull-down resistor, the smaller the change in potential corresponding to the elapsed time since the output of the second signal. The storage unit then stores in the storage unit more than two bits per terminal setting conditions corresponding to the potential of the first signal and the elapsed time from when the output of the signal output unit is turned off after outputting the second signal until the logic level of the third signal changes. The integrated circuit according to feature 9.

12. A substrate having an integrated circuit according to any one of claims 1 to 11, The impedance element connected to the terminal of the integrated circuit, The power supply unit connected to the impedance element A substrate characterized by having the following features.

13. An electronic device having the substrate according to claim 12.

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