Semiconductor equipment

Abstract

To suppress a leakage current from a semiconductor device.SOLUTION: A semiconductor device is provided that comprises a buffer region having one or more doping concentration peaks, the doping concentration of which is higher than a drift region; and a lifetime adjustment part which is provided at a position that overlaps the shallowest concentration peak that is closest to the bottom among the doping concentration peaks provided in the buffer region, and the carrier lifetime of which indicates a minimal value. A semiconductor substrate includes a critical depth position at which the integral value of having integrated doping concentrations from the upper edge of the drift region toward the underside of the semiconductor substrate reaches the critical integrated concentration of the semiconductor substrate, with a depth position where the carrier lifetime becomes a minimal value in the lifetime adjustment part being located on the lower surface side than the critical depth position.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] This invention relates to a semiconductor device. [Background technology]

[0002] Conventionally, in semiconductor devices such as IGBTs, a configuration is known in which a buffer region such as a field stop layer is provided. In addition, a technique is known for adjusting the carrier lifetime by forming defects in the semiconductor substrate (see, for example, Patent Documents 1 and 2). Patent Document 1: Japanese Unexamined Patent Publication No. 2017-126724 Patent Document 2: Japanese Unexamined Patent Publication No. 2016-189465 [Overview of the Initiative] [Problems that the invention aims to solve]

[0003] In semiconductor devices, it is preferable to reduce leakage current. [Means for solving the problem]

[0004] To solve the above problems, a first embodiment of the present invention provides a semiconductor device. The semiconductor device may include a semiconductor substrate having an upper surface and a lower surface, and a drift region of a first conductivity type provided therein. The semiconductor device may include a buffer region provided between the drift region and the lower surface of the semiconductor substrate, having one or more doping concentration peaks with a doping concentration higher than that of the drift region. The semiconductor device may include a lifetime adjustment unit provided in the buffer region at a position overlapping with the shallowest concentration peak closest to the lower surface among the doping concentration peaks, where the carrier lifetime exhibits a minimum value. The semiconductor substrate may have a critical depth position where the integral value obtained by integrating the doping concentration from the upper end of the drift region toward the lower surface of the semiconductor substrate reaches the critical integral concentration of the semiconductor substrate. The depth position in the lifetime adjustment unit where the carrier lifetime exhibits a minimum value may be located on the lower surface side of the critical depth position.

[0005] The shallowest concentration peak may be the phosphorus concentration peak.

[0006] The width in the depth direction of the lifetime adjustment section may be smaller than the width in the depth direction of the shallowest concentration peak.

[0007] The width of the shallowest concentration peak in the depth direction may be 1 μm or more.

[0008] With respect to the range-to-full width at half maximum (FMAX) characteristics corresponding to the material of the semiconductor substrate and the type of impurities contained in the buffer region, if the FMAX determined by taking the depth position of the shallowest concentration peak as the range at the time of impurity injection is defined as the standard FMAX, then the FMAX of the shallowest concentration peak may be 2.2 times or more the standard FMAX.

[0009] The semiconductor device may include a second conductivity type collector region provided between the buffer region and the lower surface of the semiconductor substrate. The buffer region may have a helium concentration peak at a position overlapping with the lifetime adjustment section. The helium concentration at the boundary between the collector region and the buffer region may be 1 / 10 or less of the helium concentration at the peak of the helium concentration peak.

[0010] The buffer region may have a helium concentration peak at a position overlapping with the lifetime adjustment section. The helium concentration at the critical depth position may be 1 / 10 or less of the helium concentration at the peak of the helium concentration peak.

[0011] The semiconductor device may include a second-conductivity collector region provided between the buffer region and the lower surface of the semiconductor substrate. The buffer region may have a helium concentration peak at a position overlapping with the lifetime adjustment section. The helium concentration at the critical depth position may be higher than the helium concentration at the boundary between the collector region and the buffer region.

[0012] The semiconductor device may include a second conductivity type collector region provided between the buffer region and the lower surface of the semiconductor substrate. The buffer region may have a helium concentration peak at a position overlapping with the lifetime adjustment section. The distance between the collector region and the peak of the helium concentration peak may be greater than the distance between the critical depth position and the peak of the helium concentration peak.

[0013] The semiconductor substrate may have a short-circuit reach position reached by the depletion layer extending from the upper end of the drift region toward the lower surface when the semiconductor device is in a short-circuit state. The buffer region may have a helium concentration peak at a position overlapping with the lifetime adjustment section. At least a portion of the helium concentration peak may be located on the upper side of the short-circuit reach position.

[0014] The buffer region may have multiple helium concentration peaks located at different depth positions.

[0015] Of the multiple helium concentration peaks, the helium concentration of the helium concentration peak closest to the bottom surface of the semiconductor substrate may be lower than the helium concentration of the other helium concentration peaks.

[0016] The buffer region may have a first helium concentration peak at a position overlapping with the lifetime adjustment section. The drift region may have a second helium concentration peak on the lower surface side of the semiconductor substrate.

[0017] The second helium concentration peak may have a lower helium concentration than the first helium concentration peak.

[0018] It should be noted that the above summary of the invention does not enumerate all the necessary features of the present invention. Furthermore, subcombinations of these features may also constitute an invention. [Brief explanation of the drawing]

[0019] [Figure 1]This is a top view showing an example of a semiconductor device 100 according to one embodiment of the present invention. [Figure 2] This is a magnified view of region D in Figure 1. [Figure 3] Figure 2 shows an example of an ee cross-section. [Figure 4] Figure 3 shows an example of the doping concentration distribution of 300 along the ff line. [Figure 5] This is a magnified view of the doping concentration distribution 300, the lifetime adjustment section 200, and the helium concentration peak 202 in the buffer region 20. [Figure 6] This figure shows another example of the doping concentration distribution 300. [Figure 7A] This figure shows another example of the shallowest concentration peak, doping concentration peak 252. [Figure 7B] This figure shows an example of the range-to-full width at half maximum characteristic. [Figure 8] This figure shows another example of the shallowest concentration peak, doping concentration peak 252. [Figure 9] This figure shows another example of the shallowest concentration peak, doping concentration peak 252. [Figure 10] This figure shows another example of buffer area 20. [Figure 11] This figure shows other examples of helium concentration distributions. [Figure 12] This figure shows an example of a semiconductor circuit 400. [Figure 13] This figure shows an example of the voltage-current characteristics of semiconductor device 100. [Modes for carrying out the invention]

[0020] The present invention will be described below through embodiments, but these embodiments are not intended to limit the scope of the claims. Furthermore, not all combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0021] In this specification, one side of a semiconductor substrate parallel to its depth direction is referred to as "top," and the other side as "bottom." Of the two main surfaces of a substrate, layer, or other component, one surface is referred to as the top surface, and the other surface as the bottom surface. The directions of "top" and "bottom" are not limited to the direction of gravity or the direction in which the semiconductor device is mounted.

[0022] In this specification, technical matters may be described using the Cartesian coordinate axes, the X, Y, and Z axes. The Cartesian coordinate axes merely specify the relative positions of components and do not limit any particular direction. For example, the Z axis does not limit the direction to height relative to the ground. Note that the +Z axis direction and the -Z axis direction are opposite directions. When the sign is not specified and only the Z axis direction is written, it means the direction parallel to the +Z and -Z axes.

[0023] In this specification, the orthogonal axes parallel to the top and bottom surfaces of the semiconductor substrate are defined as the X and Y axes. The axis perpendicular to the top and bottom surfaces of the semiconductor substrate is defined as the Z axis. In this specification, the direction of the Z axis may be referred to as the depth direction. In this specification, the direction parallel to the top and bottom surfaces of the semiconductor substrate, including the X and Y axes, may be referred to as the horizontal direction.

[0024] Furthermore, the region from the center of the semiconductor substrate in the depth direction to the top surface of the semiconductor substrate is sometimes referred to as the top surface. Similarly, the region from the center of the semiconductor substrate in the depth direction to the bottom surface of the semiconductor substrate is sometimes referred to as the bottom surface.

[0025] In this specification, the terms "identical" or "equal" may include cases where there are errors due to manufacturing variations, etc. Such errors are, for example, within 10%.

[0026] In this specification, the conductivity type of a doped region containing impurities is described as either P-type or N-type. In this specification, impurities may specifically refer to either N-type donors or P-type acceptors, and may be referred to as dopants. In this specification, doping means introducing donors or acceptors into a semiconductor substrate to make it a semiconductor exhibiting either an N-type conductivity or a P-type conductivity.

[0027] In this specification, doping concentration means the concentration of the donor or acceptor at thermal equilibrium. In this specification, net doping concentration means the net concentration obtained by adding up the charge polarity, with the donor concentration being the concentration of positive ions and the acceptor concentration being the concentration of negative ions. As an example, the donor concentration is N D , the acceptor concentration is N A Therefore, the net doping concentration at any given position is N D -N A In this specification, net doping concentration may be simply referred to as doping concentration.

[0028] Donors have the function of supplying electrons to a semiconductor. Acceptors have the function of receiving electrons from a semiconductor. Donors and acceptors are not limited to impurities themselves. For example, VOH defects, which are formed by the bonding of vacancies (V), oxygen (O), and hydrogen (H) in a semiconductor, function as electron donors. In this specification, VOH defects may be referred to as hydrogen donors.

[0029] In this specification, the semiconductor substrate has N-type bulk donors uniformly distributed throughout. The bulk donors are donors formed by dopants contained substantially uniformly in the ingot during the production of the ingot from which the semiconductor substrate is derived. The bulk donors in this example are elements other than hydrogen. The dopants of the bulk donors are, for example, phosphorus, antimony, arsenic, selenium, or sulfur, but are not limited thereto. The bulk donor in this example is phosphorus. The bulk donors are also included in the P-type regions. The semiconductor substrate may be a wafer cut from a semiconductor ingot, or may be a chip obtained by singulating the wafer. The semiconductor ingot may be manufactured by any of the Czochralski method (CZ method), the magnetic field applied Czochralski method (MCZ method), or the float zone method (FZ method). hand This is acceptable. The ingot in this example is manufactured by the MCZ method. The oxygen concentration contained in the substrate manufactured by the MCZ method is 1×10 17 ~7×10 17 / cm 3 The oxygen concentration contained in the substrate manufactured by the FZ method is 1×10 15 ~5×10 16 / cm 3 There is a tendency that a higher oxygen concentration is more likely to generate hydrogen donors. The bulk donor concentration may be determined using the chemical concentration of the bulk donors distributed throughout the semiconductor substrate, and may be a value between 90% and 100% of the chemical concentration. Also, a non-doped substrate that does not contain dopants such as phosphorus may be used as the semiconductor substrate. In that case, the bulk donor concentration (D0) of the non-doping substrate is, for example, 1×10 10 / cm 3 or more and 5×10 12 / cm 3 or less. The bulk donor concentration (D0) of the non-doping substrate is preferably 1×10 11 / cm 3 or more. The bulk donor concentration (D0) of the non-doping substrate is preferably 5×10 12 / cm 3 or less. Incidentally, each concentration in the present invention may be a value at room temperature. The value at room temperature may be, for example, the value at 300 K (Kelvin) (about 26.9 °C).

[0030] In this specification, when P+ type or N+ type is mentioned, it means a higher doping concentration than P type or N type, and when P- type or N- type is mentioned, it means a lower doping concentration than P type or N type. Furthermore, when P++ type or N++ type is mentioned in this specification, it means a higher doping concentration than P+ type or N+ type. Unless otherwise specified, the units used in this specification are SI units. Although units of length may be expressed in cm, calculations may be performed after converting to meters (m).

[0031] In this specification, chemical concentration refers to the atomic density of impurities measured independently of the electrical activation state. Chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The net doping concentration described above can be measured by voltage-capacitance (CV) spectroscopy. Alternatively, the carrier concentration measured by broadened resistance (SR) spectroscopy may be used as the net doping concentration. The carrier concentration measured by CV or SR spectroscopy may be the value at thermal equilibrium. Furthermore, in the N-type region, since the donor concentration is sufficiently larger than the acceptor concentration, the carrier concentration in that region may be used as the donor concentration. Similarly, in the P-type region, the carrier concentration in that region may be used as the acceptor concentration. In this specification, the doping concentration in the N-type region may be referred to as the donor concentration, and the doping concentration in the P-type region may be referred to as the acceptor concentration.

[0032] Furthermore, if the concentration distribution of the donor, acceptor, or net doping has a peak, the peak value may be used as the concentration of the donor, acceptor, or net doping in that region. In cases where the concentrations of the donor, acceptor, or net doping are nearly uniform, the average value of the concentrations of the donor, acceptor, or net doping in that region may be used as the concentration of the donor, acceptor, or net doping. In this specification, concentrations per unit volume are expressed as atoms / cm³. 3 , or / cm 3This unit is used for donor or acceptor concentrations in semiconductor substrates, or for chemical concentrations. The atom notation may be omitted.

[0033] The carrier concentration measured by the SR method may be lower than the donor or acceptor concentration. When measuring spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value for the crystalline state in the range where current flows. The decrease in carrier mobility occurs because carriers are scattered due to disorder in the crystal structure caused by lattice defects, etc.

[0034] The donor or acceptor concentrations calculated from carrier concentrations measured by the CV method or SR method may be lower than the chemical concentrations of the elements that act as donors or acceptors. For example, in silicon semiconductors, the donor concentrations of phosphorus or arsenic, or the acceptor concentration of boron, are approximately 99% of their respective chemical concentrations. On the other hand, the donor concentration of hydrogen, which also acts as a donor in silicon semiconductors, is approximately 0.1% to 10% of the hydrogen chemical concentration.

[0035] Figure 1 is a top view showing an example of a semiconductor device 100 according to one embodiment of the present invention. In Figure 1, the positions of each component projected onto the upper surface of the semiconductor substrate 10 are shown. In Figure 1, only some components of the semiconductor device 100 are shown, and some components are omitted.

[0036] The semiconductor device 100 comprises a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate. The semiconductor substrate 10 has edges 162 when viewed from above. In this specification, when simply referred to as "top view," it means viewing from the top side of the semiconductor substrate 10. In this example, the semiconductor substrate 10 has two pairs of edges 162 that face each other when viewed from above. In Figure 1, the X and Y axes are parallel to either edge 162. The Z axis is perpendicular to the top surface of the semiconductor substrate 10.

[0037] The semiconductor substrate 10 is provided with an active area 160. The active area 160 is a region in which the main current flows in the depth direction between the upper and lower surfaces of the semiconductor substrate 10 when the semiconductor device 100 is operating. An emitter electrode is provided above the active area 160, but it is omitted in Figure 1. The active area 160 is shown above the emitter electrode. and It may refer to overlapping areas. In addition, the area sandwiched between the active parts 160 in a top view may also be included in the active parts 160.

[0038] The active section 160 is provided with a transistor section 70 including a transistor element such as an IGBT (Insulated Gate Bipolar Transistor). The active section 160 may further be provided with a diode section 80 including a diode element such as a freewheeling diode (FWD). In the example shown in Figure 1, the transistor section 70 and the diode section 80 are arranged alternately along a predetermined arrangement direction (in this example, the X-axis direction) on the upper surface of the semiconductor substrate 10. The semiconductor device 100 in this example is a reverse-conducting IGBT (RC-IGBT).

[0039] In Figure 1, the region where the transistor section 70 is located is denoted by the symbol "I," and the region where the diode section 80 is located is denoted by the symbol "F." In this specification, the direction perpendicular to the arrangement direction in a top view may be referred to as the extension direction (Y-axis direction in Figure 1). The transistor section 70 and the diode section 80 may each have their longitudinal length in the extension direction. That is, the length of the transistor section 70 in the Y-axis direction is greater than its width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than its width in the X-axis direction. The extension direction of the transistor section 70 and the diode section 80 may be the same as the longitudinal direction of each trench section described later.

[0040] The diode section 80 has an N+ type cathode region in the area in contact with the lower surface of the semiconductor substrate 10. In this specification, the region in which the cathode region is provided is referred to as the diode section 80. In other words, the diode section 80 is the region that overlaps with the cathode region when viewed from above. A P+ type collector region may be provided on the lower surface of the semiconductor substrate 10 in areas other than the cathode region. In this specification, an extension region 81, which is an extension of the diode section 80 in the Y-axis direction to the gate wiring described later, may also be included in the diode section 80. A collector region is provided on the lower surface of the extension region 81.

[0041] The transistor section 70 has a P+ type collector region in the area in contact with the lower surface of the semiconductor substrate 10. Furthermore, the transistor section 70 has a gate structure periodically arranged on the upper surface side of the semiconductor substrate 10, which includes an N type emitter region, a P type base region, a gate conductive portion, and a gate insulating film.

[0042] The semiconductor device 100 may have one or more pads on the semiconductor substrate 10. In this example, the semiconductor device 100 has a gate pad 164. The semiconductor device 100 may also have pads such as an anode pad, a cathode pad, and a current sensing pad. Each pad is located near the edge 162. The vicinity of the edge 162 refers to the area between the edge 162 and the emitter electrode in a top view. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via wiring such as wires.

[0043] A gate potential is applied to the gate pad 164. The gate pad 164 is electrically connected to the conductive portion of the gate trench of the active portion 160. The semiconductor device 100 is provided with gate wiring that connects the gate pad 164 to the gate trench. In Figure 1, the gate wiring is shown with diagonal hatching.

[0044] The gate wiring in this example has an outer gate wiring 130 and an active gate wiring 131. The outer gate wiring 130 is positioned between the active portion 160 and the edge 162 of the semiconductor substrate 10 in a top view. In this example, the outer gate wiring 130 surrounds the active portion 160 in a top view. The area surrounded by the outer gate wiring 130 in a top view may be considered the active portion 160. Furthermore, a well region is formed below the gate wiring. The well region is a P-type region with a higher density than the base region, which will be described later, and is formed from the top surface of the semiconductor substrate 10 to a position deeper than the base region. The area surrounded by the well region in a top view may be considered the active portion 160.

[0045] The outer perimeter gate wiring 130 is connected to the gate pad 164. The outer perimeter gate wiring 130 is located above the semiconductor substrate 10. The outer perimeter gate wiring 130 may be a metal wiring containing aluminum or the like.

[0046] The active gate wiring 131 is provided in the active section 160. By providing the active gate wiring 131 in the active section 160, variations in the wiring length from the gate pad 164 can be reduced for each region of the semiconductor substrate 10.

[0047] The outer periphery gate wiring 130 and the active side gate wiring 131 are connected to the gate trench portion of the active portion 160. The outer periphery gate wiring 130 and the active side gate wiring 131 are positioned above the semiconductor substrate 10. The outer periphery gate wiring 130 and the active side gate wiring 131 may be wirings formed from a semiconductor such as polysilicon doped with impurities.

[0048] The active gate wiring 131 may be connected to the outer gate wiring 130. In this example, the active gate wiring 131 extends in the X-axis direction from one outer gate wiring 130 to the other outer gate wiring 130 that sandwiches the active section 160, crossing the active section 160 approximately in the center in the Y-axis direction. When the active section 160 is divided by the active gate wiring 131, the transistor section 70 and the diode section 80 may be arranged alternately in the X-axis direction in each divided region.

[0049] Furthermore, the semiconductor device 100 may also include a temperature sensing unit (not shown) which is a PN junction diode made of polysilicon or the like, and a current detection unit (not shown) which simulates the operation of a transistor unit provided in the active unit 160.

[0050] In this example, the semiconductor device 100 includes an edge termination structure 90 between the active portion 160 and the edge 162 when viewed from above. In this example, the edge termination structure 90 is positioned between the outer peripheral gate wiring 130 and the edge 162. The edge termination structure 90 mitigates electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure 90 may include at least one of a guard ring, a field plate, and a resurf, which are provided in an annular shape surrounding the active portion 160.

[0051] Figure 2 is an enlarged view of region D in Figure 1. Region D is the region including the transistor section 70, the diode section 80, and the active-side gate wiring 131. The semiconductor device 100 in this example includes a gate trench section 40, a dummy trench section 30, a well section 11, an emitter section 12, a base section 14, and a contact section 15, which are provided inside the upper surface of the semiconductor substrate 10. The gate trench section 40 and the dummy trench section 30 are examples of trench sections. The semiconductor device 100 in this example also includes an emitter electrode 52 and an active-side gate wiring 131, which are provided above the upper surface of the semiconductor substrate 10. The emitter electrode 52 and the active-side gate wiring 131 are provided separately from each other.

[0052] An interlayer insulating film is provided between the emitter electrode 52 and the active gate wiring 131 and the upper surface of the semiconductor substrate 10, but this is omitted in Figure 2. In this example, contact holes 54 are provided in the interlayer insulating film, penetrating the film. In Figure 2, each contact hole 54 is hatched with diagonal lines.

[0053] The emitter electrode 52 is provided above the gate trench 40, dummy trench 30, well region 11, emitter region 12, base region 14, and contact region 15. The emitter electrode 52 contacts the emitter region 12, contact region 15, and base region 14 on the upper surface of the semiconductor substrate 10 through a contact hole 54. The emitter electrode 52 is also connected to a dummy conductive part in the dummy trench 30 through a contact hole provided in the interlayer insulating film. The emitter electrode 52 may be connected to a dummy conductive part of the dummy trench 30 at its tip in the Y-axis direction. The dummy conductive part of the dummy trench 30 does not need to be connected to the emitter electrode 52 and the gate conductive part, and may be controlled to a potential different from the potential of the emitter electrode 52 and the gate conductive part.

[0054] The active gate wiring 131 connects to the gate trench portion 40 through a contact hole provided in the interlayer insulating film. The active gate wiring 131 may be connected to the gate conductive portion of the gate trench portion 40 at the tip portion 41 of the gate trench portion 40 in the Y-axis direction. The active gate wiring 131 is not connected to the dummy conductive portion in the dummy trench portion 30.

[0055] The emitter electrode 52 is formed from a material containing metal. Figure 2 shows the area in which the emitter electrode 52 is provided. For example, at least a portion of the emitter electrode 52 is formed from aluminum or an aluminum-silicon alloy, such as AlSi or AlSiCu. The emitter electrode 52 may have a barrier metal formed from titanium or a titanium compound in the layer below the region formed from aluminum or the like. Furthermore, it may have a plug formed by embedding tungsten or the like in the contact hole so as to be in contact with the barrier metal and the aluminum or the like.

[0056] The well region 11 is provided overlapping with the active gate wiring 131. The well region 11 also extends to a predetermined width in an area that does not overlap with the active gate wiring 131. In this example, the well region 11 is provided away from the Y-axis end of the contact hole 54 towards the active gate wiring 131. The well region 11 is a second conductivity type region with a higher doping concentration than the base region 14. In this example, the base region 14 is P-type, and the well region 11 is P+ type.

[0057] Each of the transistor section 70 and the diode section 80 has multiple trench sections arranged in the direction of arrangement. In this example, the transistor section 70 has one or more gate trench sections 40 and one or more dummy trench sections 30 alternately provided along the direction of arrangement. In this example, the diode section 80 has multiple dummy trench sections 30 provided along the direction of arrangement. In this example, the diode section 80 does not have gate trench sections 40.

[0058] The gate trench portion 40 in this example may have two linear portions 39 (the trench portion which is linear along the extension direction) that extend along the extension direction perpendicular to the alignment direction, and a tip portion 41 that connects the two linear portions 39. In Figure 2, the extension direction is the Y-axis direction.

[0059] Preferably, at least a portion of the tip portion 41 is provided in a curved shape when viewed from above. By connecting the ends of the two straight portions 39 in the Y-axis direction with the tip portion 41, electric field concentration at the ends of the straight portions 39 can be mitigated.

[0060] In the transistor section 70, the dummy trench section 30 is provided between each of the straight sections 39 of the gate trench section 40. There may be one dummy trench section 30 between each of the straight sections 39, or there may be multiple dummy trench sections 30. The dummy trench section 30 may have a straight shape extending in the extension direction, and like the gate trench section 40, it may have a straight section 29 and a tip section 31. The semiconductor device 100 shown in Figure 2 includes both a dummy trench section 30 with a straight shape without a tip section 31 and a dummy trench section 30 with a tip section 31.

[0061] The diffusion depth of the well region 11 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30. The Y-axis ends of the gate trench portion 40 and the dummy trench portion 30 are located in the well region 11 when viewed from above. In other words, at the Y-axis end of each trench portion, the bottom in the depth direction of each trench portion is covered by the well region 11. This makes it possible to mitigate electric field concentration at the bottom of each trench portion.

[0062] In the arrangement direction, mesa portions are provided between each trench portion. A mesa portion refers to a region within the semiconductor substrate 10 that is sandwiched between trench portions. For example, the upper end of a mesa portion is the upper surface of the semiconductor substrate 10. The depth position of the lower end of a mesa portion is the same as the depth position of the lower end of a trench portion. In this example, the mesa portion is provided on the upper surface of the semiconductor substrate 10, extending along the trench in the extension direction (Y-axis direction). In this example, a mesa portion 60 is provided in the transistor portion 70, and a mesa portion 61 is provided in the diode portion 80. In this specification, when simply referred to as a mesa portion, it refers to mesa portion 60 and mesa portion 61, respectively.

[0063] Each mesa portion is provided with a base region 14. Of the base regions 14 exposed on the upper surface of the semiconductor substrate 10 in the mesa portion, the region closest to the active gate wiring 131 is defined as base region 14-e. Figure 2 shows the base region 14-e located at one end of each mesa portion in the extending direction, but a base region 14-e is also located at the other end of each mesa portion. In each mesa portion, at least one of a first conductivity type emitter region 12 and a second conductivity type contact region 15 may be provided in the region sandwiched between the base regions 14-e in a top view. In this example, the emitter region 12 is N+ type and the contact region 15 is P+ type. The emitter region 12 and the contact region 15 may be provided in the depth direction between the base region 14 and the upper surface of the semiconductor substrate 10.

[0064] The mesa portion 60 of the transistor portion 70 has an emitter region 12 exposed on the upper surface of the semiconductor substrate 10. The emitter region 12 is provided in contact with the gate trench portion 40. The mesa portion 60 in contact with the gate trench portion 40 may have a contact region 15 exposed on the upper surface of the semiconductor substrate 10.

[0065] Each of the contact region 15 and emitter region 12 in the mesa portion 60 extends from one trench portion to the other in the X-axis direction. As an example, the contact region 15 and emitter region 12 of the mesa portion 60 are arranged alternately along the extension direction (Y-axis direction) of the trench portion.

[0066] In other examples, the contact region 15 and emitter region 12 of the mesa portion 60 may be arranged in a stripe pattern along the extension direction (Y-axis direction) of the trench portion. For example, the emitter region 12 may be provided in the region in contact with the trench portion, and the contact region 15 may be provided in the region sandwiched between the emitter regions 12.

[0067] The mesa portion 61 of the diode portion 80 does not have an emitter region 12. A base region 14 and a contact region 15 may be provided on the upper surface of the mesa portion 61. In the region on the upper surface of the mesa portion 61 sandwiched between the base regions 14-e, a contact region 15 may be provided in contact with each base region 14-e. In the region on the upper surface of the mesa portion 61 sandwiched between the contact regions 15, a base region 14 may be provided. The base region 14 may be arranged in the entire region sandwiched between the contact regions 15.

[0068] A contact hole 54 is provided above each mesa portion. The contact holes 54 are located in the region sandwiched between the base region 14-e. In this example, the contact holes 54 are provided above the contact region 15, the base region 14, and the emitter region 12. The contact holes 54 are not provided in the region corresponding to the base region 14-e and the well region 11. The contact holes 54 may be located in the center of the mesa portion 60 in the alignment direction (X-axis direction).

[0069] In the diode section 80, an N+ type cathode region 82 is provided in the region adjacent to the lower surface of the semiconductor substrate 10. In the region on the lower surface of the semiconductor substrate 10 where the cathode region 82 is not provided, a P+ type collector region 22 may be provided. The cathode region 82 and the collector region 22 are provided between the lower surface 23 of the semiconductor substrate 10 and the buffer region 20. In Figure 2, the boundary between the cathode region 82 and the collector region 22 is shown by a dotted line.

[0070] The cathode region 82 is positioned away from the well region 11 in the Y-axis direction. This ensures a distance between the cathode region 82 and the P-type region (well region 11), which has a relatively high doping concentration and is formed to a deep position, thereby improving pressure resistance. In this example, the Y-axis end of the cathode region 82 is positioned further from the well region 11 than the Y-axis end of the contact hole 54. In other examples, the Y-axis end of the cathode region 82 may be positioned between the well region 11 and the contact hole 54.

[0071] Figure 3 shows an example of the ee cross-section in Figure 2. The ee cross-section is the XZ plane passing through the emitter region 12 and the cathode region 82. In this example, the semiconductor device 100 has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in this cross-section.

[0072] The interlayer insulating film 38 is provided on the upper surface of the semiconductor substrate 10. The interlayer insulating film 38 is a film that includes at least one layer of insulating film such as silicate glass with impurities such as boron or phosphorus added, a thermal oxide film, and other insulating films. The interlayer insulating film 38 is provided with contact holes 54 as described in Figure 2.

[0073] The emitter electrode 52 is located above the interlayer insulating film 38. The emitter electrode 52 is in contact with the upper surface 21 of the semiconductor substrate 10 through a contact hole 54 in the interlayer insulating film 38. The collector electrode 24 is located on the lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are made of a metallic material such as aluminum. In this specification, the direction connecting the emitter electrode 52 and the collector electrode 24 (Z-axis direction) is referred to as the depth direction.

[0074] The semiconductor substrate 10 has an N-type or N-type drift region 18. The drift region 18 is provided in both the transistor section 70 and the diode section 80.

[0075] In the mesa portion 60 of the transistor portion 70, an N+ type emitter region 12 and a P- type base region 14 are provided in order from the upper surface 21 side of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. An N+ type storage region 16 may also be provided in the mesa portion 60. The storage region 16 is located between the base region 14 and the drift region 18.

[0076] The emitter region 12 is exposed on the upper surface 21 of the semiconductor substrate 10 and is provided in contact with the gate trench portion 40. The emitter region 12 may be in contact with the trench portions on both sides of the mesa portion 60. The doping concentration of the emitter region 12 is higher than that of the drift region 18.

[0077] The base region 14 is located below the emitter region 12. In this example, the base region 14 is located in contact with the emitter region 12. The base region 14 may be in contact with the trenches on both sides of the mesa region 60.

[0078] The accumulation region 16 is located below the base region 14. The accumulation region 16 is an N+ type region with a higher doping concentration than the drift region 18. In other words, the donor concentration in the accumulation region 16 is higher than that in the drift region 18. By providing a high-concentration accumulation region 16 between the drift region 18 and the base region 14, the carrier injection promotion effect (IE effect) can be enhanced and the on-voltage can be reduced. The accumulation region 16 may be provided so as to cover the entire lower surface of the base region 14 in each mesa portion 60.

[0079] A P-type base region 14 is provided in the mesa portion 61 of the diode portion 80, in contact with the upper surface 21 of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. A storage region 16 may also be provided below the base region 14 in the mesa portion 61.

[0080] In both the transistor section 70 and the diode section 80, an N+ type buffer section 20 may be provided below the drift section 18. The doping concentration in the buffer section 20 is higher than the doping concentration in the drift section 18. The buffer section 20 may have a concentration peak with a higher doping concentration than the drift section 18. The doping concentration of the concentration peak refers to the doping concentration at the peak of the concentration peak. Furthermore, the doping concentration of the drift section 18 may be the average value of the doping concentration in a region where the doping concentration distribution is nearly flat.

[0081] The buffer region 20 may have two or more concentration peaks in the depth direction (Z-axis direction) of the semiconductor substrate 10. The concentration peaks of the buffer region 20 may be located at the same depth as, for example, the chemical concentration peaks of hydrogen (proton) or phosphorus. The buffer region 20 may function as a field stop layer that prevents the depletion layer extending from the lower end of the base region 14 from reaching the P+ type collector region 22 and the N+ type cathode region 82.

[0082] In the transistor section 70, a P+ type collector region 22 is provided below the buffer region 20. The acceptor concentration of the collector region 22 is higher than that of the base region 14. The collector region 22 may contain the same acceptors as the base region 14, or it may contain different acceptors. The acceptors of the collector region 22 are, for example, boron.

[0083] In the diode section 80, an N+ type cathode region 82 is provided below the buffer region 20. The donor concentration of the cathode region 82 is higher than that of the drift region 18. The donor of the cathode region 82 is, for example, hydrogen or phosphorus. Note that the elements that serve as donors and acceptors for each region are not limited to the examples described above. The collector region 22 and the cathode region 82 are exposed to the lower surface 23 of the semiconductor substrate 10 and are connected to the collector electrode 24. The collector electrode 24 may be in contact with the entire lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metallic material such as aluminum.

[0084] One or more gate trenches 40 and one or more dummy trenches 30 are provided on the upper surface 21 of the semiconductor substrate 10. Each trench extends from the upper surface 21 of the semiconductor substrate 10, through the base region 14, and down to below the base region 14. In regions where at least one of the emitter region 12, contact region 15, and storage region 16 is provided, each trench also penetrates these doping regions. The statement that a trench penetrates a doping region is not limited to manufacturing in the order of forming the doping region before forming the trench. Manufacturing in which doping regions are formed between the trenches after the trenches have been formed is also included in the statement that a trench penetrates a doping region.

[0085] As described above, the transistor section 70 is provided with a gate trench section 40 and a dummy trench section 30. The diode section 80 is provided with a dummy trench section 30, but not with a gate trench section 40. In this example, the boundary between the diode section 80 and the transistor section 70 in the X-axis direction is the boundary between the cathode region 82 and the collector region 22.

[0086] The gate trench portion 40 has a gate trench provided on the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided covering the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate trench, on the inside of the gate insulating film 42. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0087] The gate conductive portion 44 may be longer than the base region 14 in the depth direction. The gate trench portion 40 in this cross-section is covered by an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to the gate wiring. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel formed by an electron inversion layer is formed on the surface layer of the interface of the base region 14 that is in contact with the gate trench portion 40.

[0088] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in its cross-section. The dummy trench portion 30 includes a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 provided on the upper surface 21 of the semiconductor substrate 10. The dummy conductive portion 34 is electrically connected to the emitter electrode 52. The dummy insulating film 32 is provided covering the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and is located inside the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed from the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 may be formed from a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length as the gate conductive portion 44 in the depth direction.

[0089] In this example, the gate trench portion 40 and the dummy trench portion 30 are covered by an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The bottom portions of the dummy trench portion 30 and the gate trench portion 40 may be curved (curved in cross-section) with a downward convex shape. In this specification, the depth position of the lower end of the gate trench portion 40 is denoted as Zt.

[0090] The semiconductor device 100 in this example includes a lifetime adjustment unit 200 for adjusting the carrier lifetime. The lifetime adjustment unit 200 is a region in the depth direction of the semiconductor substrate 10 where the carrier lifetime is at its minimum value. In regions where many lattice defects remain, carriers are trapped by the lattice defects, thus shortening the carrier lifetime. By adjusting the carrier lifetime, characteristics such as the turn-off time of the semiconductor device 100 can be adjusted. In this example, a charged particle beam such as a helium ion beam is irradiated at a predetermined depth to form lattice defects near that depth, thereby forming the lifetime adjustment unit 200. In this example, the lifetime adjustment unit 200 is provided in the buffer region 20 of the transistor section 70 and the diode section 80.

[0091] Figure 4 shows an example of the doping concentration distribution 300 at the ff line in Figure 3. In Figure 4, the carrier lifetime distribution at a portion of the ff line is also shown. The ff line is a line parallel to the Z axis that passes through the mesa 60. The horizontal axis in Figure 4 indicates the position in the Z axis direction within the semiconductor substrate 10. In this specification, the lower surface 23 of the semiconductor substrate 10 is used as the reference position in the Z axis direction, and the distance from the lower surface 23 is defined as the position in the Z axis direction.

[0092] As shown in Figure 3, a drift region 18 is provided in the semiconductor substrate 10. The doping concentration in the drift region 18 may be approximately constant. The doping concentration in the drift region 18 may be the same as the bulk donor concentration. In other examples, the doping concentration in the drift region 18 may be higher than the bulk donor concentration. An emitter region 12, a base region 14, and a storage region 16 are provided on the upper surface 21 side of the semiconductor substrate 10. The emitter region 12, the base region 14, and the storage region 16 may each have a peak in doping concentration.

[0093] A buffer region 20 is provided between the drift region 18 and the lower surface 23. The buffer region 20 has one or more doping concentration peaks 252 with higher doping concentrations than the drift region 18. A collector region 22 is provided between the buffer region 20 and the lower surface 23. The collector region 22 may have doping concentration peaks.

[0094] Let Z1 be the depth position at the lower end of the buffer region 20. In this example, depth position Z1 is the position of the PN junction between the buffer region 20 and the collector region 22. Let Z2 be the depth position at the upper end of the buffer region 20. Depth position Z2 is the position of the boundary between the buffer region 20 and the drift region 18. At depth position Z2, in the direction from the drift region 18 toward the lower surface 23, the doping concentration is equal to the doping concentration D of the drift region 18. D It may be a position where the doping concentration begins to rise, and the doping concentration D is in the drift region 18. D The position may be 1.5 times the value, or it may be 2 times the value.

[0095] A lifetime adjustment unit 200 is provided in the buffer region 20. As shown in Figure 4, the lifetime adjustment unit 200 adjusts the carrier lifetime to a minimum value τ in the depth direction. min This is the region where the carrier lifetime is at its minimum value τ. min The depth position indicated by Z L Let's assume that in the depth distribution of carrier lifetime, the depth position Z L Career lifetime is 2 × τ before and after min The following region may be designated as the lifetime adjustment unit 200. In another example, depth position Z L Career lifetime is 5 × τ before and after min The following region may be designated as the lifetime adjustment section 200, and the depth position Z L Career lifetime is 10 × τ before and after min The following region may be designated as the lifetime adjustment unit 200. In another example, depth position Z L The career lifetime before and after is the career lifetime τ in the drift region 18. driftThe region where the value is 80% or less (0.8 times or less) may be designated as the lifetime adjustment unit 200, and the carrier lifetime τ of the drift region 18 drift The region where the value is 50% or less (0.5 times or less) may be designated as the lifetime adjustment unit 200, and the carrier lifetime τ of the drift region 18 drift The region where the value is 20% or less (0.2 times or less) may be designated as the lifetime adjustment section 200. The lifetime adjustment section 200 may be entirely located in the buffer region 20. In another example, a portion of the lifetime adjustment section 200 may be located in the drift region 18. In this case as well, the depth position Z L It is placed in buffer area 20.

[0096] In this example, the buffer region 20 has helium with a helium concentration distribution 210 at a position overlapping with the lifetime adjustment unit 200. The helium concentration distribution 210 is at depth position Z L At this point, there is a helium concentration peak 202. The position of the peak 203 of the helium concentration peak 202 is at depth position Z. L It may or may not match. If they do not match, the peak 203 of helium concentration peak 202 is at depth position Z. L From depth position Z L It may be located in the range of 10% to 30%. In other examples, instead of the helium concentration peak 202, there may be concentration peaks of other impurities such as hydrogen or argon. The impurities should be such that irradiating the semiconductor substrate 10 will cause lattice defects to form, thereby forming the lifetime adjustment section 200. In this specification, the chemical concentration of helium per unit area (atoms / cm³) is used. 3 This is simply called helium concentration.

[0097] The helium concentration peak 202 overlapping with the lifetime adjustment unit 200 means, for example, that the peak 203 of the helium concentration peak 202 is located within the lifetime adjustment unit 200. In another example, the depth position Z is within the full width at half maximum of the helium concentration peak 202. LThis may also refer to the arrangement of the helium concentration peak 202. The lifetime adjustment section 200 may be the region of the full width at half maximum of the helium concentration peak 202. The position of the apex 203 of the helium concentration peak 202 is the minimum value τ of the carrier lifetime. min Depth position Z L It may be used as such.

[0098] The semiconductor substrate 10 has an integral value 302 obtained by integrating the doping concentration from the upper end of the drift region 18 toward the lower surface 23 of the semiconductor substrate 10, which corresponds to the critical integral concentration n of the semiconductor substrate 10. C The critical depth position Z reached C It has the following characteristics. When the drift region 18 and the storage region 16 are in contact, the upper end of the drift region 18 is the boundary between the storage region 16 and the drift region 18. When the drift region 18 and the base region 14 are in contact, the upper end of the drift region 18 is the PN junction portion between the base region 14 and the drift region 18. Also, the lower end position Z of the gate trench portion 40 t The upper end position of the drift region 18 may be taken as the upper end position. In the example in Figure 4, the lower end position Z t This is defined as the upper end position of the drift region 18.

[0099] critical integrated concentration n C This can be shown, for example, by the following equation. n C =εs × Ec / q However, εs is the dielectric constant of the material forming the semiconductor substrate 10, q is the elementary charge, and Ec is the dielectric breakdown field strength of the semiconductor substrate 10. εs is the relative permittivity ε of the material forming the semiconductor substrate 10 relative to the permittivity ε0 of vacuum. r It is the value obtained by multiplying by . For example, if the semiconductor substrate 10 is a silicon substrate, Ec is 1.8 × 10 5 ~2.5×10 5 (V / cm), n C is 1.2 × 10 12 ~1.6×10 12 ( / cm 2 )

[0100] Furthermore, when a forward bias is applied between the collector electrode 24 and the emitter electrode 52 with a gate voltage of 0V or less, and the maximum value of the electric field strength reaches the dielectric breakdown electric field strength of the semiconductor substrate 10, causing avalanche breakdown, and when the drift region 18 becomes depleted (becomes a space charge region) up to a specific position, the value obtained by integrating the donor concentration from the lower end of the gate trench portion 40 to that specific position is the critical integral concentration n C This corresponds to the critical depth position Z. C This is the specific location, and it is also the location to which the depletion layer (space charge region) can reach if avalanche breakdown occurs. Critical depth location Z C Even if an avalanche surrender occurs, the depletion layer will not reach the area below surface 23.

[0101] When the semiconductor device 100 is short-circuited, the depletion layer that spreads from the upper end of the drift region 18 toward the lower surface 23 reaches the short-circuit position Z of the semiconductor substrate 10. S The semiconductor device 100 has the following characteristics. A short-circuit state of the semiconductor device 100 refers to a state in which two semiconductor devices 100 connected in series and complementaryly controlled on / off become ON at the same time. In a short-circuit state, a large collector-emitter voltage is applied to one semiconductor device 100, and a very large current flows. The lower end position of the depletion layer in this state is the short-circuit position Z. S Let's assume the short-circuit condition and the position reached during the short circuit are Z. S This will be discussed later.

[0102] Figure 5 is an enlarged view of the doping concentration distribution 300, the lifetime adjustment section 200, and the helium concentration peak 202 in the buffer region 20. In this example, the lifetime adjustment section 200 is defined as the full width at half maximum region of the helium concentration peak 202 in the helium concentration distribution 210, but the position of the lifetime adjustment section 200 may be determined according to the carrier lifetime distribution as shown in Figure 4.

[0103] The doping concentration peak 252 has a vertex 253, a lower tail 255, and an upper tail 254. The depth position of the vertex 253 is Z D Let's assume the doping concentration at vertex 253 is D.P ( / cm 3 The lower edge 255 is the region where the doping concentration monotonically decreases from the apex 253 toward the bottom surface 23. The lower edge 255 is at depth position Z D It may be the portion from to depth position Z1. The upper edge 254 is the portion in which the doping concentration monotonically decreases from the apex 253 toward the upper surface 21. The upper edge 254 is the portion from depth position Z D It may be the portion from to depth position Z2.

[0104] The helium concentration peak 202 of the helium concentration distribution 210 has a vertex 203, a lower tail 205, and an upper tail 204. The depth position of the vertex 203 is Z L Let's assume the doping concentration at vertex 203 is H P ( / cm 3 The lower edge 205 is the region where the helium concentration decreases monotonically from the apex 203 toward the bottom surface 23. The upper edge 204 is the region where the helium concentration decreases monotonically from the apex 203 toward the top surface 21. helium This is the region where the concentration decreases monotonically.

[0105] The lifetime adjustment unit 200 is positioned in the buffer region 20 at a location that coincides with the shallowest concentration peak among the doping concentration peaks 252 provided in the buffer region 20, which is closest to the lower surface 23 of the semiconductor substrate 10. In this example, the buffer region 20 has a single doping concentration peak 252, so this doping concentration peak 252 is the shallowest concentration peak.

[0106] The lifetime adjustment unit 200 coincides with the doping concentration peak 252, meaning that the doping concentration is α×D around the peak 253 of the doping concentration peak 252. P Within the above range, the depth position Z of the lifetime adjustment unit 200 L This may refer to the arrangement of α. α may be, for example, 5%, 10%, 20%, or 50%. The lower end of the range may be the depth position Z1. In this case, the range extends from the depth position Z1 to the upper edge 254 where the doping concentration is α × D P Up to the point where it becomes that way.

[0107] Depth position Z L This is the critical depth position Z C It is located on the lower surface 23 side. In other words, the peak 203 of the helium concentration peak 202 is at the critical depth position Z C It is positioned closer to the lower surface 23. This results in a depth position Z L The depletion layer can be prevented from reaching the critical depth position Z. When the depletion layer reaches a region with many lattice defects, the leakage current increases, but in this example, the leakage current can be suppressed. The entire lifetime adjustment unit 200 is at the critical depth position Z. C It is preferable that it be positioned closer to the lower surface 23.

[0108] Note that depth position Z L It is positioned on the upper surface 21 side of the depth position Z1 at the lower end of the buffer region 20. If many lattice defects are formed in the collector region 22, it may affect the characteristics of the semiconductor device 100. It is preferable that the entire lifetime adjustment unit 200 is positioned on the upper surface 21 side of the depth position Z1.

[0109] The width of the lifetime adjustment unit 200 in the depth direction may be smaller than the width of the shallowest concentration peak (doping concentration peak 252 in this example). This allows the entire lifetime adjustment unit 200 to be placed within the shallowest concentration peak. The width of the lifetime adjustment unit 200 may be 75% or less of the width of the shallowest concentration peak, or 50% or less. The width of the doping concentration peak 252 is such that the doping concentration is α × D before and after the peak 253 of the doping concentration peak 252. P The width of the range may be greater than or equal to the above. The lower end position of the range may be the depth position Z1.

[0110] The depth of the shallowest concentration peak, doping concentration peak 252, may be 1 μm or more. This width may be 2 μm or more, or 3 μm or more. The depth of the shallowest concentration peak, doping concentration peak 252, may be 10 μm or less, 7 μm or less, or 5 μm or less. The width of the lifetime adjustment section 200 may be less than 1 μm, 0.75 μm or less, or 0.5 μm or less. The width of the lifetime adjustment section 200 may be 0.1 μm or more, 0.2 μm or more, or 0.3 μm or more.

[0111] Let L1 be the distance between the collector region 22 and the peak 203 of the helium concentration peak 202. In this example, the distance L1 is measured from depth position Z1 to Z L This is the distance to the critical depth position Z. C and vertex 203 (depth position Z) L Let L2 be the distance to the collector region 22. Distance L1 may be greater than distance L2. If a lattice defect is formed at the boundary (pn junction) between the collector region 22 and the buffer region 20, the injection of holes from the collector region 22 to the buffer region 20 and the drift region 18 may be suppressed, and the on-voltage may increase. In this example, the formation of a lattice defect in the collector region 22, or at the boundary (pn junction) between the collector region 22 and the buffer region 20, can be suppressed, and the increase in the on-voltage of the semiconductor device 100 can be suppressed. Distance L1 may be 1.5 times or more the distance L2, and may also be 2 times or more. However, distance L1 may be less than or equal to distance L2. Even in this case, it is preferable that the entire lifetime adjustment unit 200 is located on the upper surface 21 side of the depth position Z1.

[0112] As shown in Figure 5, the peak 203 of the helium concentration peak 202 may be located on the upper surface 21 side than the peak 253 of the doping concentration peak 252. In other examples, the peak 203 may be located on the lower surface 23 side than the peak 253.

[0113] Let the helium concentration at the boundary (depth position Z1 in this example) between the collector region 22 and the buffer region 20 be H1. The helium concentration H1 may be 1 / 10 or less of the helium concentration H at the peak 203 of the helium concentration peak 202. Thereby, the lattice defects formed in the collector region 22 can be reduced. The helium concentration H1 may be 1 / 100 or less of the helium concentration H, and may also be 1 / 1000 or less. The helium concentration H1 may be 0 atms / cm. P Let the helium concentration at the critical depth position Z be H. In the critical depth position Z of this example, an upper skirt 204 of the helium concentration peak 202 is provided. The helium concentration H may be 1 / 10 or less of the helium concentration H at the peak 203 of the helium concentration peak 202. Thereby, the lattice defects provided on the upper surface 21 side than the critical depth position Z can be reduced, and the leakage current can be suppressed. The helium concentration H may be 1 / 100 or less of the helium concentration H, and may also be 1 / 1000 or less. The helium concentration H may be 0 atms / cm. P Let the helium concentration at the critical depth position Z be H. In the critical depth position Z of this example, an upper skirt 204 of the helium concentration peak 202 is provided. The helium concentration H may be 1 / 10 or less of the helium concentration H at the peak 203 of the helium concentration peak 202. Thereby, the lattice defects provided on the upper surface 21 side than the critical depth position Z can be reduced, and the leakage current can be suppressed. The helium concentration H may be 1 / 100 or less of the helium concentration H, and may also be 1 / 1000 or less. The helium concentration H may be 0 atms / cm. 3 Let the helium concentration at the critical depth position Z be H. In the critical depth position Z of this example, an upper skirt 204 of the helium concentration peak 202 is provided. The helium concentration H may be 1 / 10 or less of the helium concentration H at the peak 203 of the helium concentration peak 202. Thereby, the lattice defects provided on the upper surface 21 side than the critical depth position Z can be reduced, and the leakage current can be suppressed. The helium concentration H may be 1 / 100 or less of the helium concentration H, and may also be 1 / 1000 or less. The helium concentration H may be 0 atms / cm.

[0114] Let the helium concentration at the critical depth position Z be H. C Let the helium concentration at the critical depth position Z be H. C In the critical depth position Z of this example, an upper skirt 204 of the helium concentration peak 202 is provided. The helium concentration H may be 1 / 10 or less of the helium concentration H at the peak 203 of the helium concentration peak 202. Thereby, the lattice defects provided on the upper surface 21 side than the critical depth position Z can be reduced, and the leakage current can be suppressed. The helium concentration H may be 1 / 100 or less of the helium concentration H, and may also be 1 / 1000 or less. The helium concentration H may be 0 atms / cm. C In the critical depth position Z of this example, an upper skirt 204 of the helium concentration peak 202 is provided. The helium concentration H may be 1 / 10 or less of the helium concentration H at the peak 203 of the helium concentration peak 202. Thereby, the lattice defects provided on the upper surface 21 side than the critical depth position Z can be reduced, and the leakage current can be suppressed. The helium concentration H may be 1 / 100 or less of the helium concentration H, and may also be 1 / 1000 or less. The helium concentration H may be 0 atms / cm. C In the critical depth position Z of this example, an upper skirt 204 of the helium concentration peak 202 is provided. The helium concentration H may be 1 / 10 or less of the helium concentration H at the peak 203 of the helium concentration peak 202. Thereby, the lattice defects provided on the upper surface 21 side than the critical depth position Z can be reduced, and the leakage current can be suppressed. The helium concentration H may be 1 / 100 or less of the helium concentration H, and may also be 1 / 1000 or less. The helium concentration H may be 0 atms / cm. P In the critical depth position Z of this example, an upper skirt 204 of the helium concentration peak 202 is provided. The helium concentration H may be 1 / 10 or less of the helium concentration H at the peak 203 of the helium concentration peak 202. Thereby, the lattice defects provided on the upper surface 21 side than the critical depth position Z can be reduced, and the leakage current can be suppressed. The helium concentration H may be 1 / 100 or less of the helium concentration H, and may also be 1 / 1000 or less. The helium concentration H may be 0 atms / cm. C In the critical depth position Z of this example, an upper skirt 204 of the helium concentration peak 202 is provided. The helium concentration H may be 1 / 10 or less of the helium concentration H at the peak 203 of the helium concentration peak 202. Thereby, the lattice defects provided on the upper surface 21 side than the critical depth position Z can be reduced, and the leakage current can be suppressed. The helium concentration H may be 1 / 100 or less of the helium concentration H, and may also be 1 / 1000 or less. The helium concentration H may be 0 atms / cm. C Let the helium concentration at the critical depth position Z be H. P Let the helium concentration at the critical depth position Z be H. C Let the helium concentration at the critical depth position Z be H. 3 Let the helium concentration at the critical depth position Z be H.

[0115] Let the helium concentration at the critical depth position Z be H. C Let the helium concentration at the critical depth position Z be H. C The helium concentration H at the critical depth position Z may be higher than the helium concentration H1 at the depth position Z1. Thereby, the lattice defects formed in the collector region 22 can be reduced. The helium concentration H1 may be 1 / 2 or less of the helium concentration H, may be 1 / 5 or less of the helium concentration H, and may also be 1 / 10 or less of the helium concentration H. C The helium concentration H at the critical depth position Z may be higher than the helium concentration H1 at the depth position Z1. Thereby, the lattice defects formed in the collector region 22 can be reduced. The helium concentration H1 may be 1 / 2 or less of the helium concentration H, may be 1 / 5 or less of the helium concentration H, and may also be 1 / 10 or less of the helium concentration H.

[0116] Figure 6 shows another example of the doping concentration distribution 300. In this example, the doping concentration distribution 300 has multiple doping concentration peaks 252 in the buffer region 20. Although Figure 6 shows two doping concentration peaks 252-1 and 252-2, the buffer region 20 may have three or more doping concentration peaks 252.

[0117] In the example in Figure 6, doping concentration peak 252-1 is the shallowest concentration peak. The lifetime adjustment unit 200 and helium concentration peak 202 are located in the same positions as the lifetime adjustment unit 200 and helium concentration peak 202 described in Figures 4 and 5. Doping concentration peak 252-1 is the same as doping concentration peak 252 described in Figures 4 and 5.

[0118] Doping concentration peak 252-2 is located on the upper surface 21 side of doping concentration peak 252-1. Each doping concentration peak 252 may be located on the lower surface 23 side of the semiconductor substrate 10. Doping concentration peak 252-1 is the doping concentration D at the peak 203 of the multiple doping concentration peaks 252. P It can be the highest concentration peak.

[0119] Each doping concentration peak 252 described in Figures 4 to 6 may be a hydrogen donor concentration peak or a phosphorus concentration peak. The buffer region 20 may include both the hydrogen donor doping concentration peak 252 and the phosphorus doping concentration peak 252. In this case, the shallowest concentration peak, doping concentration peak 252-1, may be the phosphorus concentration peak.

[0120] Figure 7A shows another example of the shallowest concentration peak, doping concentration peak 252. In this example, doping concentration peak 252 has a flat portion 256. Except for the doping concentration peak 252 having a flat portion 256, it is the same as the examples shown in Figures 4 to 6.

[0121] The flat portion 256 is a region where the doping concentration is approximately constant in the depth direction. "Approximately constant" means that the concentration variation per unit length (1 μm) in the depth direction is 10 times or less, 5 times or less, 3 times or less, or 2 times or less. A concentration variation of 10 times or less means that, within a unit length in the depth direction, the maximum doping concentration is 10 times or less of the minimum doping concentration. The flat portion 256 is located between the lower hem 255 and the upper hem 254. The flat portion 256 may have a length of 0.3 μm or more, 0.5 μm or more, or 1 μm or more in the depth direction. The flat portion 256 may have a length of 10 μm or less, 5 μm or less, or 3 μm or less in the depth direction. Depth position Z L The flat section 256 may be located there. The entire lifetime adjustment section 200 may be located there.

[0122] Let W1 be the full width at half maximum (FMAX) of the doping concentration peak 252, which is the shallowest concentration peak. The lower end of the FMAX region may be at depth position Z1. The FMAX W1 is 2.2 times or more the predetermined standard FMAX. By increasing the FMAX W1 of the doping concentration peak 252, the entire lifetime adjustment unit 200 can be easily placed within the doping concentration peak 252. Also, from depth position Z1 to critical depth position Z C The entire lifetime adjustment unit 200 can be easily installed in between.

[0123] The standard full width at half maximum (FMAX) is the depth position Z of the peak 253 of the doping concentration peak 252, relative to the range-FMAX characteristics depending on the material of the semiconductor substrate 10 and the type of impurities contained in the buffer region 20. D This is the full width at half maximum, determined by the range at the time of impurity injection. If the doping concentration peak 252 has a flat section 256, the central position of the flat section 256 in the depth direction is defined as depth position Z. D It may be used as such.

[0124] When impurities are injected into a semiconductor substrate 10 at a predetermined distance (i.e., a depth position in the semiconductor substrate 10), the impurities are distributed with a certain degree of variation in the depth direction. The amount of variation in the depth position where the impurities are injected (struggle) is determined by the distance of the impurities (i.e., the acceleration energy when the impurities are injected). However, this amount of variation depends on the material of the semiconductor substrate 10 and the type of impurities injected.

[0125] In other words, the standard full width at half maximum (FMAX) corresponds to the FMAX in a normal state where impurities are injected with the range fixed at depth position Zp and no heat treatment is performed. The standard FMAX may be the FMAX when impurities are injected perpendicularly to the upper surface of the semiconductor substrate 10. In contrast, in the semiconductor device 100, the FMAX W1 of the doping concentration distribution at doping concentration peak 252 is made sufficiently larger than the standard FMAX. The FMAX W1 may be three times or more, four times or more, or five times or more of the standard FMAX.

[0126] A doping concentration peak 252 with a large full width at half maximum can be formed by injecting impurities into the semiconductor substrate 10 at multiple different ranges. After injecting the impurities, a doping concentration peak 252 like the one shown in Figure 7A can be formed by appropriately performing heat treatment such as annealing at a predetermined temperature and time. However, the method for forming the doping concentration peak 252 is not limited to this. When forming the doping concentration peak 252 in each example described in Figures 4 to 7A, the impurities may be injected obliquely into the lower surface 23 of the semiconductor substrate 10, or they may be injected vertically.

[0127] Figure 7B shows an example of the range-to-full width at half maximum (FWHM) characteristics. In Figure 7B, the semiconductor substrate 10 is a silicon substrate, and the impurity being injected is phosphorus. The standard FWHM at each range is obtained by injecting the impurity into the semiconductor substrate 10 at that range and measuring the distribution of the impurity without heat treatment. As an example, the range-to-FWHM characteristics when phosphorus is injected into a silicon substrate can be approximated by the following equation.

number

[0128] Figure 8 shows another example of the shallowest concentration peak, doping concentration peak 252. In this example, doping concentration peak 252 has a sloped portion 257. Except for the doping concentration peak 252 having a sloped portion 257, it is the same as the example shown in Figures 4 to 7B.

[0129] The inclined portion 257 is a region in which the doping concentration increases monotonically little by little from the lower surface 23 to the upper surface 21. The ratio of the doping concentration at the upper end of the inclined portion 257 to the doping concentration at the lower end of the inclined portion 257 may be 10 times or less, 5 times or less, 3 times or less, or 2 times or less. The inclined portion 257 is located between the lower hem 255 and the upper hem 254. The inclined portion 257 may have a length of 0.3 μm or more, 0.5 μm or more, or 1 μm or more in the depth direction. The inclined portion 257 may have a length of 10 μm or less, 5 μm or less, or 3 μm or less in the depth direction. The boundary between the inclined portion 257 and the upper hem 254 may be the apex 253. Depth position Z L The inclined portion 257 may be located there. The entire lifetime adjustment unit 200 may be located there.

[0130] Figure 9 shows another example of the shallowest concentration peak, doping concentration peak 252. In this example, doping concentration peak 252 has a sloped portion 258. Except for the doping concentration peak 252 having a sloped portion 258, it is the same as the example shown in Figures 4 to 7B.

[0131] The inclined portion 258 is a region where the doping concentration decreases monotonically little by little from the lower surface 23 to the upper surface 21. The ratio of the doping concentration at the lower end of the inclined portion 258 to the doping concentration at the upper end of the inclined portion 258 may be 10 times or less, 5 times or less, 3 times or less, or 2 times or less. The inclined portion 258 is located between the lower hem 255 and the upper hem 254. The inclined portion 258 may have a length of 0.3 μm or more, 0.5 μm or more, or 1 μm or more in the depth direction. The inclined portion 258 may have a length of 10 μm or less, 5 μm or less, or 3 μm or less in the depth direction. The boundary between the inclined portion 258 and the lower hem 255 may be the apex 253. Depth position Z L The inclined portion 258 may be located there. The entire lifetime adjustment unit 200 may be located there.

[0132] In the example described in Figures 7A to 9, the depth position Z L The doping concentration in D L The maximum doping concentration D at doping concentration peak 252 is considered to be the maximum value of the doping concentration. P doping concentration D L The concentration ratio D obtained by dividing by P / D L It may be 1 or greater. Concentration ratio D P / D L It may be 10 or less, 5 or less, or 3 or less.

[0133] Figure 10 shows another example of the buffer region 20. In this example, the buffer region 20 has multiple helium concentration peaks 202 located at different depths. Although Figure 10 shows two helium concentration peaks 202-1 and 202-2, the buffer region 20 may have three or more helium concentration peaks 202. The doping concentration distribution of the buffer region 20 in Figure 10 is the same as in the example in Figure 7A, but the doping concentration distribution of the buffer region 20 may be the same as in any of the examples from Figures 4 to 9.

[0134] Multiple helium concentration peaks 202 may be positioned to overlap with the shallowest concentration peak, the doping concentration peak 252. All helium concentration peaks 202 in the buffer region 20 may be positioned to overlap with the shallowest concentration peak, the doping concentration peak 252. In another example, at least one helium concentration peak 202 may be positioned on the upper surface 21 side of the shallowest concentration peak, the doping concentration peak 252. Depth positions Z1, Z S , Z C The helium concentration in this case may be the same as in any of the examples described in Figures 4 to 9.

[0135] The helium concentration at the apex 203 of each helium concentration peak 202 may be the same. Alternatively, the helium concentration at the apex 203-1 of the helium concentration peak 202-1 located on the bottom surface 23 may be lower than the helium concentration at the apex 203-2 of the other helium concentration peaks 202-2 adjacent to it on the top surface 21. This can suppress the formation of lattice defects in the collector region 22. The helium concentration at the apex 203-1 of the helium concentration peak 202-1 located on the bottom surface 23 may be lower than the helium concentration at the apex 203 of any other helium concentration peak 202.

[0136] In other examples, the helium concentration at the peak 203-2 of the helium concentration peak 202-2 located on the uppermost surface 21 may be lower than the helium concentration at the peak 203-1 of the other adjacent helium concentration peak 202-1 on the lower surface 23. This allows for a critical depth position Z C This suppresses the formation of lattice defects on the upper surface 21 side. The helium concentration at the peak 203-2 of the helium concentration peak 202-2 located on the uppermost surface 21 side may be lower than the helium concentration at the peak 203 of any other helium concentration peak 202.

[0137] Two adjacent helium concentration peaks 202 in the depth direction may be arranged to overlap each other. For example, the full width at half maximum regions of each helium concentration peak 202 may partially overlap. By providing multiple helium concentration peaks 202, the concentration at each peak of the helium concentration peak 202 can be reduced. Furthermore, by providing multiple helium concentration peaks 202 that overlap, a wide lifetime adjustment section 200 can be formed.

[0138] Furthermore, in each of the examples shown in Figures 4 to 10, the width of the helium concentration peak 202 may be increased by incidenting the helium ion beam irradiating the lower surface 23 of the semiconductor substrate 10 almost perpendicular to the lower surface 23 of the semiconductor substrate 10. Almost perpendicular means, for example, 3 degrees or less.

[0139] Figure 11 shows another example of helium concentration distribution. The semiconductor substrate 10 in this example has a second helium concentration peak 262 in addition to any of the configurations described in Figures 4 to 10. The other structures are the same as those of any of the examples described in Figures 4 to 10.

[0140] The second helium concentration peak 262 is located on the lower surface 23 side of the semiconductor substrate 10 and in the drift region 18. One or more helium concentration peaks 202 (referred to as the first helium concentration peak) are provided in the buffer region 20. The helium concentration at the peak 263 of the second helium concentration peak 262 may be lower than the helium concentration at the peak 203 of the first helium concentration peak. In this case, leakage current when the depletion layer reaches the second helium concentration peak 262 can be suppressed. The helium concentration at the peak 263 of the second helium concentration peak 262 may be 1 / 10 or less, or 1 / 100 or less, of the helium concentration at the peak 203 of the first helium concentration peak. The second helium concentration peak 262 is located at the critical depth position Z C It may be positioned closer to the upper surface 21. In another example, the helium concentration at the peak 263 of the second helium concentration peak 262 may be greater than or equal to the helium concentration at the peak 203 of the first helium concentration peak.

[0141] Figure 12 shows an example of a semiconductor circuit 400. The semiconductor circuit 400 is connected to the high-voltage power line V CC The system includes two semiconductor devices 100 connected in series between the low-voltage power line GND and the low-voltage power line GND. Gate signals are input to the gate electrodes of the two semiconductor devices 100 to turn them on and off complementaryly.

[0142] For example, when the lower semiconductor device 100-2 is ON, the upper semiconductor device 100-1 is controlled to be OFF. However, for some reason, the upper semiconductor device 100-1 may also turn ON, and both semiconductor devices 100 may be ON simultaneously. This state is called a short circuit. In a short circuit, the ON semiconductor devices 100-1 and 100-2 are connected to the power line V CCVoltage V CC Therefore, power is applied. As a result, power line V is applied through semiconductor devices 100-1 and 100-2. CC A large through-current flows from the power line GND. The value of the through-current may be the saturation current determined by the voltage difference between the gate voltage and the gate threshold voltage in the conductor device 100-1 and the semiconductor device 100-2, respectively.

[0143] Figure 13 shows an example of the voltage-current characteristics of semiconductor device 100. The horizontal axis of Figure 13 represents the collector-emitter voltage V CE The vertical axis represents the collector current I. C This shows that the threshold voltage Vth of semiconductor device 100 in this example is less than 8V. Also, the gate voltage V applied to the gate electrode to turn on semiconductor device 100 is GE It is 15V.

[0144] In Figure 13, I rate The rated current of semiconductor device 100 is V sat In the linear region, the rated current I rate This is the corresponding collector-emitter voltage. When the semiconductor device 100 is short-circuited, the power supply voltage V is applied across the collector-emitter. CC A voltage close to this is applied, resulting in a large short-circuit current I S This flows. In this state, the depth position reached by the depletion layer extending from the upper end of the drift region 18 toward the lower surface 23 is the short-circuit position Z explained in Figure 4, etc. S Let's assume that.

[0145] As explained in Figure 4, at least a portion of the helium concentration peak 202 reaches position Z during a short circuit. S It may be positioned closer to the upper surface 21. The peak 203 of the helium concentration peak 202 is reached at the short-circuit position Z. S It may be positioned closer to the upper surface 21. The peak 203 of the helium concentration peak 202 is reached at the short-circuit position Z. S and critical depth position Z C It may be placed between them. Also, the entire region of the full width at half maximum of the helium concentration peak 202 is the short-circuit position Z SIt may be positioned closer to the upper surface 21. The entire region of the full width at half maximum of the helium concentration peak 202 is the position reached during a short circuit Z. S and critical depth position Z C It may be positioned between them. Also, at least a portion of the lifetime adjustment unit 200 is the position reached during a short circuit Z S It may be positioned on the upper surface 21 side. The entire lifetime adjustment unit 200 reaches position Z during short circuit. S It may be positioned on the upper surface 21 side. The entire lifetime adjustment unit 200 reaches position Z during short circuit. S and critical depth position Z C It may be placed between them. In this example, the position reached during a short circuit is Z S This prevents the depletion layer from reaching the short circuit and prevents an increase in through-current due to the synergistic effect of leakage currents.

[0146] Furthermore, as explained in Figure 4, when a lattice defect is formed at the boundary (pn junction) between the collector region 22 and the buffer region 20, the injection of holes from the collector region 22 into the buffer region 20 and the drift region 18 is suppressed. On the other hand, during a short circuit, electrons continue to be injected into the space charge region, so the charge densities of holes and electrons cancel each other out, and the electric field strength distribution becomes relatively flat. When the injection of holes from the collector region 22 into the buffer region 20 and the drift region 18 is suppressed during a short circuit, the electron concentration becomes higher than the hole concentration. As a result, the polarity of the space charge density reverses, and the electric field strength distribution increases toward the collector region 22. Therefore, avalanche breakdown may occur at a depth relatively close to the collector region 22, and the semiconductor device 100 may be destroyed. In this example, the decrease in hole injection can be suppressed even during a short circuit, and the hole concentration can be maintained higher than the electron concentration. This suppresses avalanche breakdown at a depth relatively close to the collector region 22 during a short circuit, and prevents the destruction of the semiconductor device 100.

[0147] Note that the position reached during a short circuit is Z. S This may be determined using a device simulator. Using parameters such as the impurity concentration profile in the depth direction of the semiconductor substrate 10, the power supply voltage, and the gate voltage, the short-circuit position Z is determined.S This may be determined by simulation or other means.

[0148] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. It will be clear from the claims that such modified or improved forms may also be included in the technical scope of the present invention.

[0149] It should be noted that the execution order of operations, procedures, steps, and stages in the apparatus, systems, programs, and methods shown in the claims, specifications, and drawings is not explicitly stated as "before," "prior to," etc., and that these can be implemented in any order unless the output of a previous process is used in a later process. Even if the operation flow in the claims, specifications, and drawings is described using phrases such as "first," "next," etc. for convenience, it does not mean that it is essential to perform the operations in that order. [Explanation of Symbols]

[0150] 10...Semiconductor substrate, 11...Well region, 12...Emitter region, 14...Base region, 15...Contact region, 16...Storage region, 18...Drift region, 20...Buffer region, 21...Top surface, 22...Collector region, 23...Bottom surface, 24...Collector electrode, 29...Straight section, 30...Dummy trench section, 31...Tip section, 3 2...Dummy insulating film, 34...Dummy conductive part, 38...Interlayer insulating film, 39...Straight section, 40...Gate trench section, 41...Tip section, 42...Gate insulating film, 44...Gate conductive part, 52...Emitter electrode, 54...Contact hole, 60, 61...Mesa section, 70...Transistor section, 80...Diode section, 81...Extended region, 82... ...Cathode region, 90...Edge termination structure, 100...Semiconductor device, 110, 112, 113, 114...Curves, 130...Outer periphery gate wiring, 131...Active side gate wiring, 160...Active part, 162...Edge, 164...Gate pad, 200...Lifetime adjustment part, 202...Helium concentration peak, 203...Vertex, 204...Upper side Base, 205...Lower base, 210...Helium concentration distribution, 252...Doping concentration peak, 253...Climax, 254...Upper base, 255...Lower base, 256...Flat section, 257...Sloping section, 258...Sloping section, 262...Second helium concentration peak, 263...Climax, 300...Doping concentration distribution, 302...Integral value, 400...Semiconductor circuit

Claims

1. A semiconductor substrate having an upper surface and a lower surface, and provided with a drift region of a first conductivity type, The semiconductor substrate is provided between the drift region and the lower surface, and has one or more doping concentration peaks with a doping concentration higher than that of the drift region, A lifetime adjustment unit is provided in the buffer region at a position that overlaps with the shallowest concentration peak closest to the lower surface among the doping concentration peaks, and the carrier lifetime exhibits a minimum value. Equipped with, The semiconductor substrate has a critical depth position where the integral value obtained by integrating the doping concentration from the upper end of the drift region toward the lower surface of the semiconductor substrate reaches the critical integral concentration of the semiconductor substrate. In the lifetime adjustment unit, the depth position where the carrier lifetime is minimized is located on the lower side of the critical depth position. With respect to the range-to-full width at half maximum (FMAX) characteristics corresponding to the semiconductor substrate material and the type of impurities contained in the buffer region, if the FMAX determined by setting the depth position of the shallowest concentration peak as the range at the time of impurity injection is defined as the standard FMAX, then the FMAX of the shallowest concentration peak is 2.2 times or more the standard FMAX. Semiconductor equipment.

2. A semiconductor substrate having an upper surface and a lower surface, and provided with a drift region of a first conductivity type, The semiconductor substrate is provided between the drift region and the lower surface, and has one or more doping concentration peaks with a doping concentration higher than that of the drift region, A lifetime adjustment unit is provided in the buffer region at a position that overlaps with the shallowest concentration peak closest to the lower surface among the doping concentration peaks, and the carrier lifetime exhibits a minimum value. A second conductivity type collector region is provided between the buffer region and the lower surface of the semiconductor substrate. Equipped with, The semiconductor substrate has a critical depth position where the integral value obtained by integrating the doping concentration from the upper end of the drift region toward the lower surface of the semiconductor substrate reaches the critical integral concentration of the semiconductor substrate. In the lifetime adjustment unit, the depth position where the carrier lifetime is minimized is located on the lower side of the critical depth position. The buffer region has a helium concentration peak at a position overlapping with the lifetime adjustment section. The distance between the collector region and the peak of the helium concentration peak is greater than the distance between the critical depth position and the peak of the helium concentration peak. Semiconductor equipment.

3. A semiconductor substrate having an upper surface and a lower surface, and provided with a drift region of a first conductivity type, The semiconductor substrate is provided between the drift region and the lower surface, and has one or more doping concentration peaks with a doping concentration higher than that of the drift region, A lifetime adjustment unit is provided in the buffer region at a position that overlaps with the shallowest concentration peak closest to the lower surface among the doping concentration peaks, and the carrier lifetime exhibits a minimum value. Equipped with, The semiconductor substrate has a critical depth position where the integral value obtained by integrating the doping concentration from the upper end of the drift region toward the lower surface of the semiconductor substrate reaches the critical integral concentration of the semiconductor substrate. In the lifetime adjustment unit, the depth position where the carrier lifetime is minimized is located on the lower side of the critical depth position. The semiconductor substrate has a short-circuit reach position to which the depletion layer, which extends from the upper end of the drift region toward the lower surface, reaches when the semiconductor device is in a short-circuit state. The buffer region has a helium concentration peak at a position overlapping with the lifetime adjustment section. At least a portion of the helium concentration peak is located above the position reached during the short circuit. Semiconductor equipment.

4. A semiconductor substrate having an upper surface and a lower surface, and provided with a drift region of a first conductivity type, The semiconductor substrate is provided between the drift region and the lower surface, and has one or more doping concentration peaks with a doping concentration higher than that of the drift region, A lifetime adjustment unit is provided in the buffer region at a position that overlaps with the shallowest concentration peak closest to the lower surface among the doping concentration peaks, and the carrier lifetime exhibits a minimum value. Equipped with, The semiconductor substrate has a critical depth position where the integral value obtained by integrating the doping concentration from the upper end of the drift region toward the lower surface of the semiconductor substrate reaches the critical integral concentration of the semiconductor substrate. In the lifetime adjustment unit, the depth position where the carrier lifetime is minimized is located on the lower side of the critical depth position. The buffer region has multiple helium concentration peaks located at different depth positions. Of the multiple helium concentration peaks, the helium concentration of the peak closest to the bottom surface of the semiconductor substrate is lower than the helium concentration of the other helium concentration peaks. Semiconductor equipment.

5. A semiconductor substrate having an upper surface and a lower surface, and provided with a drift region of a first conductivity type, The semiconductor substrate is provided between the drift region and the lower surface, and has one or more doping concentration peaks with a doping concentration higher than that of the drift region, A lifetime adjustment unit is provided in the buffer region at a position that overlaps with the shallowest concentration peak closest to the lower surface among the doping concentration peaks, and the carrier lifetime exhibits a minimum value. Equipped with, The semiconductor substrate has a critical depth position where the integral value obtained by integrating the doping concentration from the upper end of the drift region toward the lower surface of the semiconductor substrate reaches the critical integral concentration of the semiconductor substrate. In the lifetime adjustment unit, the depth position where the carrier lifetime is minimized is located on the lower side of the critical depth position. The buffer region has a helium concentration peak at a position overlapping with the lifetime adjustment section. The peak of the helium concentration is located above the peak of the shallowest concentration peak. Semiconductor equipment.

6. A semiconductor substrate having an upper surface and a lower surface, and provided with a drift region of a first conductivity type, The semiconductor substrate is provided between the drift region and the lower surface, and has one or more doping concentration peaks with a doping concentration higher than that of the drift region, A lifetime adjustment unit is provided in the buffer region at a position that overlaps with the shallowest concentration peak closest to the lower surface among the doping concentration peaks, and the carrier lifetime exhibits a minimum value. A second conductivity type collector region is provided between the buffer region and the lower surface of the semiconductor substrate. Equipped with, The semiconductor substrate has a critical depth position where the integral value obtained by integrating the doping concentration from the upper end of the drift region toward the lower surface of the semiconductor substrate reaches the critical integral concentration of the semiconductor substrate. In the lifetime adjustment unit, the depth position where the carrier lifetime is minimized is located on the lower side of the critical depth position. The buffer region has a helium concentration peak at a position overlapping with the lifetime adjustment section. The helium concentration at the critical depth is higher than the helium concentration at the boundary between the collector region and the buffer region. Semiconductor equipment.

7. A semiconductor substrate having an upper surface and a lower surface, and provided with a drift region of a first conductivity type, The semiconductor substrate is provided between the drift region and the lower surface, and has one or more doping concentration peaks with a doping concentration higher than that of the drift region, A lifetime adjustment unit is provided in the buffer region at a position that overlaps with the shallowest concentration peak closest to the lower surface among the doping concentration peaks, and the carrier lifetime exhibits a minimum value. Equipped with, The semiconductor substrate has a critical depth position where the integral value obtained by integrating the doping concentration from the upper end of the drift region toward the lower surface of the semiconductor substrate reaches the critical integral concentration of the semiconductor substrate. In the lifetime adjustment unit, the depth position at which the carrier lifetime is minimized is located below the critical depth position and within a range where the peak concentration of the shallowest concentration peak is 50% or more. Semiconductor equipment.

8. The shallowest concentration peak mentioned above is the phosphorus concentration peak. The semiconductor device according to any one of claims 1 to 7.

9. The width in the depth direction of the lifetime adjustment section is smaller than the width in the depth direction of the shallowest concentration peak. The semiconductor device according to any one of claims 1 to 8.

10. The width of the shallowest concentration peak in the depth direction is 1 μm or more. A semiconductor device according to any one of claims 1 to 9.

11. The following further comprises a second conductivity type collector region provided between the buffer region and the lower surface of the semiconductor substrate, The buffer region has a helium concentration peak at a position overlapping with the lifetime adjustment section. The helium concentration at the boundary between the collector region and the buffer region is 1 / 10 or less of the helium concentration at the peak of the helium concentration. The semiconductor device according to any one of claims 1, 3, 5, or 7.

12. The buffer region has a helium concentration peak at a position overlapping with the lifetime adjustment section. The helium concentration at the critical depth is 1 / 10 or less of the helium concentration at the peak of the helium concentration. The semiconductor device according to any one of claims 1, 3, 5, or 7.

13. The buffer region has a first helium concentration peak at a position overlapping with the lifetime adjustment section. The drift region has a second helium concentration peak on the lower surface side of the semiconductor substrate. The semiconductor device according to claim 1 or 7.

14. The second helium concentration peak has a lower helium concentration than the first helium concentration peak. The semiconductor device according to claim 13.

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