Semiconductor equipment

Abstract

To provide semiconductor devices, such as an IGBT device, capable of preferably improving characteristics.SOLUTION: Provided is a semiconductor device including: a semiconductor substrate; gate trench portions; an emitter electrode; a mesa portion; an emitter region of a first conductivity type provided on an upper surface of the mesa portion and in contact with the gate trench portions; a contact region of a second conductivity type provided on the upper surface of the mesa portion; a base region of the second conductivity type provided below the emitter region and the contact region in the semiconductor substrate, in contact with the gate trench portions, and having a lower doping concentration than that of the contact region; a drift region of the first conductivity type provided below the base region in the semiconductor substrate and having a lower doping concentration than that of the emitter region; and a high resistance portion provided between the emitter electrode and the base region in a depth direction of the semiconductor substrate and having a higher resistance than that of the emitter region. The emitter region and the contact region are arranged alternately in an extending direction.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] This invention relates to a semiconductor device. [Background technology]

[0002] Conventionally, techniques have been known for improving the characteristics of semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors) by changing the arrangement of first conductivity type regions such as the emitter region and second conductivity type regions such as the contact region (see, for example, Patent Documents 1-2). Patent Document 1: Japanese Unexamined Patent Publication No. 2008-91491 Patent Document 2 Japanese Patent Application Laid-Open No. 10-173170 [Overview of the Initiative] [Problems that the invention aims to solve]

[0003] In semiconductor devices such as IGBT devices, it is preferable to improve their characteristics. [Means for solving the problem]

[0004] To solve the above problems, a first embodiment of the present invention provides a semiconductor device comprising a semiconductor substrate. The semiconductor device may include a plurality of gate trenches. The plurality of gate trenches may be provided on the upper surface of the semiconductor substrate and may extend along the stretching direction. The semiconductor device may include an emitter electrode. The emitter electrode may be provided above the semiconductor substrate. The semiconductor device may include a mesa. The mesa may be provided between adjacent gate trenches within the plurality of gate trenches. The semiconductor device may include an emitter region of a first conductivity type. The emitter region may be provided on the upper surface of the mesa and may be in contact with the gate trenches. The semiconductor device may include a contact region of a second conductivity type. The contact region may be provided on the upper surface of the mesa. The semiconductor device may include a base region of a second conductivity type. The base region may be provided below the emitter region and the contact region in the semiconductor substrate. The base region may be in contact with the gate trenches. The doping concentration of the base region may be lower than that of the contact region. The semiconductor device may include a drift region of a first conductivity type. The drift region may be located below the base region in the semiconductor substrate. The doping concentration of the drift region may be lower than that of the emitter region. The semiconductor device may include a high-resistance region. The high-resistance region may be located between the emitter electrode and the base region in the depth direction of the semiconductor substrate. The high-resistance region may have a higher resistance than the emitter region. The emitter region and the contact region may be arranged alternately in the stretching direction.

[0005] The gate trench portion may have a gate conductive portion. The gate conductive portion may be located below the position where the high-resistance portion is provided in the depth direction of the semiconductor substrate.

[0006] The emitter region may have a first high-concentration emitter region. The high-resistance region is provided above the first high-concentration emitter region and may be a low-concentration emitter region with a lower doping concentration than the first high-concentration emitter region.

[0007] The emitter region may have a second high-concentration emitter region. The second high-concentration emitter region may be located above the low-concentration emitter region. The doping concentration in the second high-concentration emitter region may be higher than that in the low-concentration emitter region.

[0008] The doping concentration in the low-concentration emitter region may be greater than or equal to the doping concentration in the base region. The doping concentration in the low-concentration emitter region may be less than or equal to the doping concentration in the base region.

[0009] The doping concentration in the low-concentration emitter region adjacent to the gate trench may be higher than the doping concentration in the low-concentration emitter region in the center of the mesa region.

[0010] The base region may have a low-concentration base region. The base region may have a high-concentration base region. The high-concentration base region may be located below the low-concentration base region. The doping concentration in the high-concentration base region may be higher than that in the low-concentration base region.

[0011] A second aspect of the present invention provides a semiconductor device comprising a semiconductor substrate. The semiconductor device may include a plurality of gate trenches. The plurality of gate trenches may be provided on the upper surface of the semiconductor substrate and may extend along the stretching direction. The semiconductor device may include an emitter electrode. The emitter electrode may be provided above the semiconductor substrate. The semiconductor device may include a mesa. The mesa may be provided between adjacent gate trenches within the plurality of gate trenches. The semiconductor device may include an emitter region of a first conductivity type. The emitter region may be provided on the upper surface of the mesa and may be in contact with the gate trenches. The semiconductor device may include a contact region of a second conductivity type. The contact region may be provided on the upper surface of the mesa. The semiconductor device may include a base region of a second conductivity type. The base region may be provided below the emitter region and the contact region in the semiconductor substrate. The base region may be in contact with the gate trenches. The doping concentration of the base region may be lower than that of the contact region. The semiconductor device may include a drift region of a first conductivity type. The drift region may be located below the base region in the semiconductor substrate. The drift region may have a lower doping concentration than the emitter region. The semiconductor device may include a polysilicon resistor. The polysilicon resistor may be located between the emitter electrode and the base region in the depth direction of the semiconductor substrate. At least a portion of the polysilicon resistor may be located above the semiconductor substrate. The polysilicon resistor may have a higher resistance than the emitter region. The emitter region and the contact region may be arranged alternately in the stretching direction.

[0012] The polysilicon resistor may cover the emitter region when viewed from above.

[0013] The polysilicon resistor and emitter electrode may alternately contact the upper surface of the semiconductor substrate in the stretching direction.

[0014] The semiconductor device may include an interlayer insulating film. The interlayer insulating film may be provided above the gate trench portion. The polysilicon resistor portion may be formed in the interlayer insulating film.

[0015] The semiconductor device may include a metal plug. The metal plug may be provided above the contact region. The metal plug may be formed in the interlayer insulating film.

[0016] Note that the above summary of the invention does not enumerate all the features of the present invention. Also, sub-combinations of these feature groups can also be inventions.

Brief Description of the Drawings

[0017] [Figure 1] It is a top view showing an example of the semiconductor device 100. [Figure 2] It is a diagram showing a comparative example of the arrangement on the upper surface of the semiconductor substrate 10 in the region D of FIG. 1. [Figure 3] It is a diagram showing a comparative example of the arrangement on the upper surface of the interlayer insulating film 38 in the region D of FIG. 1. [Figure 4] It is a diagram showing an example of the a-a cross section in FIG. 2. [Figure 5] It is a diagram showing an example of the b-b cross section in FIG. 2. [Figure 6] It is a diagram showing an example of the doping concentration distribution along the c-c line in FIG. 4. [Figure 7] It is a diagram showing the semiconductor device 200 according to an embodiment. [Figure 8] It is a diagram showing the semiconductor device 200 according to an embodiment. [Figure 9] It is a diagram showing an example of the d-d cross section in FIG. 7. [Figure 10] It is a diagram showing an example of the e-e cross section in FIG. 7. [Figure 11] It is a diagram showing an example of the doping concentration distribution along the f-f line in FIG. 9. [Figure 12] It is a diagram for explaining the effect of the low-concentration N-type emitter region 13. [Figure 13] It is a diagram for explaining an example of the flowchart of the manufacturing method of the semiconductor device 200. [Figure 14] It is a diagram showing another example of the doping concentration distribution along the f-f line in FIG. 9. [Figure 15] Figure 9 shows an example of the doping concentration distribution along the gg line. [Figure 16] Figure 9 shows another example of the doping concentration distribution along the gg line. [Figure 17] This figure shows a semiconductor device 300 according to another embodiment. [Figure 18] This figure shows a semiconductor device 300 according to another embodiment. [Figure 19] Figure 17 shows an example of an hh cross-section. [Figure 20] This figure shows an example of cross-section ii in Figure 17. [Figure 21] Figure 19 shows an example of the doping concentration distribution along the jj line. [Figure 22] This figure shows a semiconductor device 400 according to another embodiment. [Figure 23] Figure 22 shows an example of a cross-section of the kk section. [Figure 24] Figure 22 shows an example of a cross-section. [Figure 25] This diagram illustrates the effect of the polysilicon resistor 66. [Figure 26] This figure shows a semiconductor device 500 according to another embodiment. [Figure 27] Figure 26 shows an example of a mm cross-section. [Figure 28] This figure shows a semiconductor device 600 according to another embodiment. [Figure 29] This figure shows a semiconductor device 600 according to another embodiment. [Figure 30] Figure 28 shows an example of a cross-section. [Figure 31] This figure shows a semiconductor device 700 according to another embodiment. [Figure 32] This figure shows a semiconductor device 700 according to another embodiment. [Figure 33] Figure 31 shows an example of a cross-section of qq. [Figure 34]This figure shows a semiconductor device 800 according to another embodiment. [Figure 35] This figure shows a semiconductor device 800 according to another embodiment. [Figure 36] Figure 34 shows an example of an SS cross-section. [Figure 37] This figure shows a semiconductor device 1100 according to another embodiment. [Figure 38] This figure shows a semiconductor device 1100 according to another embodiment. [Figure 39] This figure shows another example of the dd section in Figure 7. [Figure 40] Figure 39 shows an example of the doping concentration distribution along the uu line. [Figure 41] This figure shows the relationship between the impurity concentration in the low-concentration N-type emitter region 13 and the contact-emitter ratio. [Figure 42] This figure shows a semiconductor device 900 according to another embodiment. [Figure 43] This figure shows a semiconductor device 1000 according to another embodiment. [Figure 44] This figure shows the IV characteristics in the high-current region. [Figure 45] This figure shows the IV characteristics in the rated current range. [Modes for carrying out the invention]

[0018] The present invention will be described below through embodiments, but these embodiments are not intended to limit the scope of the claims. Furthermore, not all combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0019] In this specification, one side of a semiconductor substrate parallel to its depth direction is referred to as "top," and the other side as "bottom." Of the two main surfaces of a substrate, layer, or other component, one surface is referred to as the top surface, and the other surface as the bottom surface. The directions of "top" and "bottom" are not limited to the direction of gravity or the direction in which the semiconductor device is mounted.

[0020] In this specification, technical matters may be described using the Cartesian coordinate axes, the X, Y, and Z axes. The Cartesian coordinate axes merely specify the relative positions of components and do not limit any particular direction. For example, the Z axis does not limit the direction to height relative to the ground. Note that the +Z axis direction and the -Z axis direction are opposite directions. When the sign is not specified and only the Z axis direction is written, it means the direction parallel to the +Z and -Z axes.

[0021] In this specification, the orthogonal axes parallel to the top and bottom surfaces of the semiconductor substrate are defined as the X and Y axes. The axis perpendicular to the top and bottom surfaces of the semiconductor substrate is defined as the Z axis. In this specification, the direction of the Z axis may be referred to as the depth direction. In this specification, the direction parallel to the top and bottom surfaces of the semiconductor substrate, including the X and Y axes, may be referred to as the horizontal direction.

[0022] Furthermore, the region from the center of the semiconductor substrate in the depth direction to the top surface of the semiconductor substrate is sometimes referred to as the top surface. Similarly, the region from the center of the semiconductor substrate in the depth direction to the bottom surface of the semiconductor substrate is sometimes referred to as the bottom surface.

[0023] In this specification, the terms "identical" or "equal" may include cases where there are errors due to manufacturing variations, etc. Such errors are, for example, within 10%.

[0024] In this specification, the conductivity type of a doped region containing impurities is described as either P-type or N-type. In this specification, impurities may specifically refer to either N-type donors or P-type acceptors, and may be referred to as dopants. In this specification, doping means introducing donors or acceptors into a semiconductor substrate to make it a semiconductor exhibiting either an N-type conductivity or a P-type conductivity.

[0025] In this specification, doping concentration means the concentration of the donor or acceptor at thermal equilibrium. In this specification, net doping concentration means the net concentration obtained by adding up the charge polarity, with the donor concentration being the concentration of positive ions and the acceptor concentration being the concentration of negative ions. As an example, the donor concentration is N D , the acceptor concentration is N A Therefore, the net doping concentration at any given position is N D -N A In this specification, net doping concentration may be simply referred to as doping concentration.

[0026] Donors have the function of supplying electrons to a semiconductor. Acceptors have the function of receiving electrons from a semiconductor. Donors and acceptors are not limited to impurities themselves. For example, VOH defects, which are formed by the bonding of vacancies (V), oxygen (O), and hydrogen (H) in a semiconductor, function as electron donors. In this specification, VOH defects may be referred to as hydrogen donors.

[0027] In this specification, when P+ type or N+ type is mentioned, it means that the doping concentration is higher than that of P type or N type, and when P- type or N- type is mentioned, it means that the doping concentration is lower than that of P type or N type. Unless otherwise specified, the units used in this specification are the SI units. Although units of length may be expressed in cm, calculations may be performed after converting to meters (m).

[0028] In this specification, chemical concentration refers to the atomic density of impurities measured independently of the electrical activation state. Chemical concentration (atomic density) can be measured, for example, by secondary ion mass spectrometry (SIMS). The net doping concentration described above can be measured by voltage-capacitance (CV) spectroscopy. Alternatively, the carrier concentration measured by spheroidal resistance (SR) spectroscopy may be used as the net doping concentration. The carrier concentration measured by CV or SR spectroscopy may be the value at thermal equilibrium. Furthermore, in the N-type region, since the donor concentration is sufficiently larger than the acceptor concentration, the carrier concentration in that region may be used as the donor concentration. Similarly, in the P-type region, the carrier concentration in that region may be used as the acceptor concentration. In this specification, the doping concentration in the N-type region may be referred to as the donor concentration, and the doping concentration in the P-type region may be referred to as the acceptor concentration.

[0029] Furthermore, if the concentration distribution of the donor, acceptor, or net doping has a peak, the peak value may be used as the concentration of the donor, acceptor, or net doping in that region. In cases where the concentrations of the donor, acceptor, or net doping are nearly uniform, the average value of the concentrations of the donor, acceptor, or net doping in that region may be used as the concentration of the donor, acceptor, or net doping. In this specification, concentrations per unit volume are expressed as atoms / cm³. 3 , or / cm 3 This unit is used for donor or acceptor concentrations in semiconductor substrates, or for chemical concentrations. The atom notation may be omitted.

[0030] The carrier concentration measured by the SR method may be lower than the donor or acceptor concentration. When measuring spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value for the crystalline state in the range where current flows. The decrease in carrier mobility occurs because carriers are scattered due to disorder in the crystal structure caused by lattice defects, etc.

[0031] The donor or acceptor concentrations calculated from carrier concentrations measured by the CV method or SR method may be lower than the chemical concentrations of the elements that act as donors or acceptors. For example, in silicon semiconductors, the donor concentrations of phosphorus or arsenic, or the acceptor concentrations of boron, are approximately 99% of their respective chemical concentrations. On the other hand, the donor concentration of hydrogen, which acts as a donor in silicon semiconductors, is approximately 0.1% to 10% of the hydrogen chemical concentration. The concentrations used herein may be values ​​at room temperature. For example, values ​​at 300 K (Kelvin) (approximately 26.9°C) may be used.

[0032] Figure 1 is a top view showing an example of a semiconductor device 100. In Figure 1, the positions of each component projected onto the top surface of the semiconductor substrate 10 are shown. In Figure 1, only some components of the semiconductor device 100 are shown, and some components are omitted.

[0033] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed of a semiconductor material. For example, the semiconductor substrate 10 is a silicon substrate, but the material of the semiconductor substrate 10 is not limited to silicon.

[0034] The semiconductor substrate 10 has a first edge 161 and a second edge 162 when viewed from above. In this specification, when simply referred to as "viewed from above," it means viewed from the top side of the semiconductor substrate 10. In this example, the semiconductor substrate 10 faces each other when viewed from above. 1 The pair has a first end edge 161. In addition, the semiconductor substrates 10 in this example face each other when viewed from above. 1 The pair has a second end edge 162. In Figure 1, the first end edge 161 is parallel to the X-axis direction. The second end edge 162 is parallel to the Y-axis direction. The Z-axis is perpendicular to the upper surface of the semiconductor substrate 10. The first end edge 161 is perpendicular to the extension direction of the gate trench section, which will be described later. The second end edge 162 is parallel to the extension direction of the gate trench section, which will be described later.

[0035] The semiconductor substrate 10 is provided with an active section 160. The active section 160 is a region in which the main current flows in the depth direction between the upper and lower surfaces of the semiconductor substrate 100 when the semiconductor device 100 is operating. An emitter electrode is provided above the active section 160, but it is omitted in Figure 1.

[0036] In this example, the active section 160 is provided with a transistor section 70 including a transistor element such as an IGBT. In other examples, the transistor section 70 and the diode section including a diode element such as an FWD (Free Wheel Diode) may be arranged alternately along a predetermined arrangement direction on the upper surface of the semiconductor substrate 10. In this example, one transistor section 70 is provided, but multiple transistor sections 70 may be provided. P+ type well regions or gate runners may be provided between the transistor sections 70.

[0037] The transistor section 70 has a P+ type P-type collector region in the area in contact with the lower surface of the semiconductor substrate 10. Furthermore, the transistor section 70 has a surface MOS structure periodically arranged on the upper surface side of the semiconductor substrate 10, having an N+ type emitter region, a P- type base region, an N- type drift region, a gate conductor portion, and a gate insulating film.

[0038] The semiconductor device 100 may have one or more pads on the semiconductor substrate 10. In this example, the semiconductor device 100 has a gate pad 164. The semiconductor device 100 may also have pads such as an anode pad, a cathode pad, and a current sensing pad. Each pad is located near the first edge 161. The vicinity of the first edge 161 refers to the region between the first edge 161 and the emitter electrode in a top view. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via wiring such as wires.

[0039] A gate potential is applied to the gate pad 164. The gate pad 164 is electrically connected to the conductive part of the gate trench part of the active part 160. The semiconductor device 100 includes a gate wiring 130 that connects the gate pad 164 and the gate trench part. In FIG. 1, the gate wiring 130 is marked with slanted hatching.

[0040] The gate wiring 130 is disposed between the active part 160 and the first end side 161 or the second end side 162 in a top view. The gate wiring 130 of this example surrounds the active part 160 in a top view. The area surrounded by the gate wiring 130 in a top view may be regarded as the active part 160. Also, the gate wiring 130 is connected to the gate pad 164. The gate wiring 130 is disposed above the semiconductor substrate 10. The gate wiring 130 may be a metal wiring containing aluminum or the like. The gate wiring 130 may be provided separately from the emitter electrode.

[0041] The P-type peripheral well region 11 is provided overlapping the gate wiring 130. That is, similar to the gate wiring 130, the P-type peripheral well region 11 surrounds the active part 160 in a top view. The P-type peripheral well region 11 also extends with a predetermined width in a range where it does not overlap the gate wiring 130. The P-type peripheral well region 11 is a region of the second conductivity type. The P-type peripheral well region 11 of this example is P+. The impurity concentration of the P-type peripheral well region 11 may be 5.0×10 17 atoms / cm 3 or more and 5.0×10 19 atoms / cm 3 or less. The impurity concentration of the P-type peripheral well region 11 may be 2.0×10 18 atoms / cm 3 or more and 2.0×10 19 atoms / cm 3 or less.

[0042] Furthermore, the semiconductor device 100 may include a temperature sensing unit (not shown), which is a PN junction diode made of polysilicon or the like, and a current detection unit (not shown) that simulates the operation of the transistor unit 70 provided in the active unit 160. The temperature sensing unit may be connected to the anode pad and cathode pad via wiring. If a temperature sensing unit is provided, it is preferable that it be located in the center of the semiconductor substrate 10 in the X-axis and Y-axis directions.

[0043] In this example, the semiconductor device 100 includes an edge termination structure 90 between the active portion 160 and the first edge 161 or the second edge 162 when viewed from above. The edge termination structure 90 in this example is Gate wiring 130 It is positioned between the first edge 161 or the second edge 162. The edge termination structure 90 mitigates electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure 90 may include at least one of a guard ring, a field plate, and a resurf, which are provided in an annular shape surrounding the active part 160.

[0044] Figure 2 shows a comparative example of the arrangement on the upper surface of the semiconductor substrate 10 in region D of Figure 1. Region D is the region including the transistor portion 70 of the active portion 160. In Figure 2, the semiconductor device 100 includes a gate trench portion 40, an N-type emitter region 12, and a P-type contact region 15 provided inside the upper surface of the semiconductor substrate 10. Figure 2 shows the arrangement of the gate trench portion 40, the N-type emitter region 12, and the P-type contact region 15 on the upper surface of the semiconductor substrate 10.

[0045] The transistor section 70 has multiple gate trench sections 40 arranged in the arrangement direction. In this example, the gate trench sections 40 are provided on the active section 160 on the upper surface of the semiconductor substrate 10. The gate trench sections 40 may also be provided in the P-type outer peripheral well region 11. The gate trench sections 40 are provided in a stripe pattern in the transistor section 70 when viewed from above. In this example, only the gate trench sections 40 are arranged, but one gate trench section 40 and one dummy trench section may be provided alternately. The arrangement direction in Figure 2 is the X-axis direction. The gate trench sections 40 may be provided extending in the stretching direction (Y-axis direction).

[0046] In the arrangement direction, mesa portions 60 are provided between each gate trench portion 40. The mesa portion 60 refers to the region sandwiched between the trench portions within the semiconductor substrate 10. In other words, the mesa portion 60 may be provided between adjacent gate trench portions 40. For example, the upper end of the mesa portion 60 is the upper surface of the semiconductor substrate 10. The depth position of the lower end of the mesa portion 60 is the same as the depth position of the lower end of the trench portion. In this example, the mesa portion 60 is provided on the upper surface of the semiconductor substrate 10, extending along the gate trench portion 40 in the extension direction (Y-axis direction).

[0047] Each mesa portion 60 may be provided with at least one of a first conductivity type N-type emitter region 12 and a second conductivity type P-type contact region 15. In this example, the N-type emitter region 12 is N+ type, and the P-type contact region 15 is P+ type. The N-type emitter region 12 and the P-type contact region 15 may be provided in the depth direction between the P-type base region and the upper surface of the semiconductor substrate 10.

[0048] The mesa portion 60 of the transistor portion 70 has an N-type emitter region 12 exposed on the upper surface of the semiconductor substrate 10. The N-type emitter region 12 is provided in contact with the gate trench portion 40. The mesa portion 60 in contact with the gate trench portion 40 may have a P-type contact region 15 exposed on the upper surface of the semiconductor substrate 10.

[0049] Each of the P-type contact region 15 and N-type emitter region 12 in the mesa section 60 extends from one trench section to the other in the X-axis direction. As an example, the P-type contact region 15 and N-type emitter region 12 of the mesa section 60 are arranged alternately along the extension direction (Y-axis direction) of the trench section.

[0050] In Figure 2, the width of the N-type emitter region 12 in the Y-axis direction is defined as the emitter width L1. Also in Figure 2, the sum of the width of the N-type emitter region 12 in the Y-axis direction and the width of the P-type contact region 15 in the Y-axis direction is defined as the pitch width L2. For example, the emitter width L1 is 1.5 μm, and for example, the pitch width L2 is 5.0 μm.

[0051] In other examples, the P-type contact region 15 and N-type emitter region 12 of the mesa portion 60 may be arranged in a stripe pattern along the extension direction (Y-axis direction) of the trench portion. For example, the N-type emitter region 12 may be provided in the region in contact with the trench portion, and the P-type contact region 15 may be provided in the region sandwiched between the N-type emitter regions 12.

[0052] Figure 3 shows a comparative example of the arrangement of the interlayer insulating film 38 on the upper surface in region D of Figure 1. Figure 3 shows an arrangement in the XY plane different from that in Figure 2. In Figure 3, the semiconductor device 100 includes an interlayer insulating film 38 and a metal plug 62 provided inside the upper surface of the semiconductor substrate 10. Figure 3 shows the arrangement of the metal plug 62 on the upper surface of the interlayer insulating film 38. Also in Figure 3, the arrangement of the gate trench portion 40 and the mesa portion 60 is shown by dotted lines.

[0053] The interlayer insulating film 38 is provided above the semiconductor substrate 10. In this example, the interlayer insulating film 38 is provided on the upper surface of the semiconductor substrate 10. The interlayer insulating film 38 is a film that includes at least one layer of insulating film such as silicate glass with impurities such as boron or phosphorus added, a thermal oxide film, and other insulating films. The interlayer insulating film 38 is provided above the gate trench portion 40. In this example, the interlayer insulating film 38 covers the gate trench portion 40.

[0054] The metal plug 62 is formed in the interlayer insulating film 38. The metal plug 62 may be formed in a contact hole provided in the interlayer insulating film 38. The metal plug 62 electrically connects the semiconductor substrate 10 (mesa portion 60) and the emitter electrode. By providing the metal plug 62, the contact resistance between the semiconductor substrate 10 and the emitter electrode can be reduced. The metal plug 62 is formed of, for example, Ta, W, Mo, etc. The metal plug 62 is provided above the mesa portion 60.

[0055] Figure 4 shows an example of the aa cross-section in Figure 2. The aa cross-section is the XZ plane passing through the N-type emitter region 12. In this example, the semiconductor device 100 comprises a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, a collector electrode 24, and a metal plug 62 in this cross-section.

[0056] The emitter electrode 52 is positioned above the gate trench 40, the N-type emitter region 12, and the P-type contact region 15. The emitter electrode 52 contacts the N-type emitter region 12 and the P-type contact region 15 on the upper surface 21 of the semiconductor substrate 10 through the contact hole 54.

[0057] The emitter electrode 52 is formed from a material containing metal. For example, at least a portion of the emitter electrode 52 is formed from aluminum or an aluminum-silicon alloy, such as AlSi or AlSiCu. The emitter electrode 52 may have a barrier metal formed from titanium or a titanium compound in the layer below the region formed from aluminum or the like. The metal plug 62 may be in contact with the barrier metal and the aluminum or the like within the contact hole 54.

[0058] The interlayer insulating film 38 is provided on the upper surface 21 of the semiconductor substrate 10. The interlayer insulating film 38 is a film that includes at least one layer of insulating film such as silicate glass with impurities such as boron or phosphorus added, a thermal oxide film, and other insulating films. Contact holes 54 are provided in the interlayer insulating film 38. The interlayer insulating film 38 is optional. In this case, the emitter electrode 52 may be in contact with the upper surface 21 of the semiconductor substrate 10.

[0059] The emitter electrode 52 is provided above the semiconductor substrate 10. In this example, the emitter electrode 52 is provided above the interlayer insulating film 38. The emitter electrode 52 is in contact with the upper surface 21 of the semiconductor substrate 10 through the contact hole 54 of the interlayer insulating film 38. The emitter electrode 52 is provided above the P-type outer peripheral well region 11. Even if they're not there Good. Gate wiring 130 may be provided above the P-type outer periphery well region 11.

[0060] The collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10. The collector electrode 24 is made of a metallic material such as aluminum, similar to the emitter electrode 52. In this specification, the direction connecting the emitter electrode 52 and the collector electrode 24 (Z-axis direction) is referred to as the depth direction.

[0061] Each mesa portion 60 is provided with a second conductivity type P-type base region 14. The P-type base region 14 may be in contact with the gate trench portion 40. The N-type emitter region 12 and the P-type contact region 15 are provided between the upper surface 21 of the semiconductor substrate 10 and the P-type base region 14. In this example, the P-type base region 14 is P-type. That is, the doping concentration of the P-type base region 14 may be lower than that of the P-type contact region 15.

[0062] The semiconductor substrate 10 has an N-type drift region 18 of the first conductivity type. In this example, the N-type drift region 18 is N-type. That is, the doping concentration of the N-type drift region 18 may be lower than that of the N-type emitter region 12. The N-type drift region 18 may be located below the P-type base region 14.

[0063] In Figure 4, the mesa portion 60 is provided with an N+ type N-type emitter region 12 and a P- type P-type base region 14, in order from the upper surface 21 side of the semiconductor substrate 10. An N-type drift region 18 is provided below the P-type base region 14. An N+ type storage region (not shown) may also be provided in the mesa portion 60.

[0064] The N-type emitter region 12 is exposed on the upper surface 21 of the semiconductor substrate 10. The N-type emitter region 12 is also provided in contact with the gate trench portion 40. The N-type emitter region 12 may be in contact with the trench portions on both sides of the mesa portion 60. The doping concentration of the N-type emitter region 12 may be higher than that of the N-type drift region 18.

[0065] The P-type base region 14 is located below the N-type emitter region 12. In this example, the P-type base region 14 is located in contact with the N-type emitter region 12. The P-type base region 14 may be in contact with the gate trench regions 40 on both sides of the mesa region 60. The peak of the impurity concentration in the P-type base region 14 is, as an example, 2.5 × 10⁻⁶. 17 atoms / cm 3 Therefore, the impurity concentration in the P-type base region 14 is 5.0 × 10⁻⁶. 16 atoms / cm 3 The above and 1.0 × 10 18 atoms / cm 3 The following is acceptable:

[0066] An N+ type N-type buffer region 20 may be provided below the N-type drift region 18. The doping concentration in the N-type buffer region 20 is higher than the doping concentration in the N-type drift region 18. The N-type buffer region 20 may have a concentration peak with a higher doping concentration than the N-type drift region 18. The doping concentration at the concentration peak refers to the doping concentration at the peak of the concentration peak. Furthermore, the doping concentration in the N-type drift region 18 may be the average value of the doping concentration in a region where the doping concentration distribution is nearly flat.

[0067] The N-type buffer region 20 may be formed by ion implantation of an N-type dopant such as hydrogen (proton) or phosphorus. In this example, the N-type buffer region 20 is formed by ion implantation of hydrogen. The N-type buffer region 20 may function as a field stop layer that prevents the depletion layer extending from the lower end of the P-type base region 14 from reaching the P+-type P-type collector region 22.

[0068] Below the N-type buffer region 20, a P+-type P-type collector region 22 is provided. The acceptor concentration in the P-type collector region 22 is higher than that of the P-type base region 14. The P-type collector region 22 may contain the same acceptors as the P-type base region 14, or it may contain different acceptors. The acceptor in the P-type collector region 22 is, for example, boron. The elements that act as acceptors are not limited to the examples given above.

[0069] The P-type collector region 22 is exposed on the lower surface 23 of the semiconductor substrate 10 and is connected to the collector electrode 24. The collector electrode 24 may be in contact with the entire lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed from a metallic material such as aluminum.

[0070] One or more gate trenches 40 are provided on the upper surface 21 of the semiconductor substrate 10. In this example, multiple gate trenches 40 are provided on the upper surface 21 of the semiconductor substrate 10. In this example, each gate trench 40 extends from the upper surface 21 of the semiconductor substrate 10, through the P-type base region 14, and reaches the N-type drift region 18. In regions where at least one of the N-type emitter region 12 and the P-type contact region 15 is provided, each gate trench 40 also extends through these doping regions and reaches the N-type drift region 18. The statement that a trench penetrates a doping region is not limited to manufacturing in the order of forming the doping region before forming the trench. Even when doping regions are formed between the trenches after the trenches have been formed, the trenches are still included in the statement that a trench penetrates a doping region.

[0071] The gate trench portion 40 has a gate trench provided on the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate conductive portion 44 is formed of polysilicon, which is a conductive material. The gate conductive portion 44 may be formed of the same material as the gate runner. The gate insulating film 42 is provided covering the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor of the inner wall of the gate trench. In Figure 4, the gate conductive portion 44 is provided inside the gate trench, inside the gate insulating film 42. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10.

[0072] The gate conductive portion 44 within the gate trench portion 40 may be provided to be longer than the P-type base region 14 in the depth direction. The gate trench portion 40 in this cross-section is covered by an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to the gate wiring 130. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel formed by an electron inversion layer is formed on the surface layer of the interface of the P-type base region 14 that is in contact with the gate trench portion 40.

[0073] In this example, the gate trench portion 40 is covered by an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The bottom of the gate trench portion 40 may be a curved surface that is convex downwards (curved in cross-section).

[0074] A protective film (not shown) may be provided on the upper surface of the emitter electrode 52. By providing a protective film on the upper surface of the emitter electrode 52, the electrode can be protected. The protective film may be patterned. The protective film is, as an example, a polyimide film.

[0075] Figure 5 shows an example of the bb cross-section in Figure 2. The bb cross-section is the XZ plane passing through the P-type contact region 15. In this example, the semiconductor device 100 comprises a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, a collector electrode 24, and a metal plug 62 in this cross-section.

[0076] In this example, the P-type contact region 15 is exposed on the upper surface 21 of the semiconductor substrate 10. In this example, the mesa portion 60 is provided with a P+-type P-type contact region 15 and a P--type P-type base region 14, in order from the upper surface 21 of the semiconductor substrate 10. An N-type drift region 18 is provided below the P-type base region 14.

[0077] Figure 6 shows an example of the doping concentration distribution at the cc line in Figure 4. The cc line may be located at the center of the mesa region 60 in the X-axis direction. Figure 6 shows the doping concentration distribution in the N-type emitter region 12, the P-type base region 14, and the N-type drift region 18.

[0078] In the center of the mesa region 60, the doping concentration in the N-type emitter region 12 may be higher than the doping concentration in the P-type base region 14. The N-type emitter region 12 may have a concentration peak with a higher doping concentration than the P-type base region 14.

[0079] In the center of the mesa region 60, the doping concentration in the P-type base region 14 may be higher than the doping concentration in the N-type drift region 18. The P-type base region 14 may have a concentration peak with a higher doping concentration than the N-type drift region 18.

[0080] As explained above, the transistor section 70 of the semiconductor device 100 has surface MOS structures periodically arranged on the upper surface 21 side of the semiconductor substrate 10, each having an N+ type N-type emitter region 12, a P- type P-type base region 14, an N- type N-type drift region 18, a gate conductive portion 44, and a gate insulating film 42. Due to the current saturation function of the surface MOS structure, the IGBT has a current limiting function. Therefore, even in a short-circuit state where current and voltage are applied to the semiconductor device 100 simultaneously, it has short-circuit withstand characteristics that allow it to shut off non-destructively even after a certain period of time. In miniaturized IGBTs, if all cells are made of surface MOS structure, the saturation current becomes very large. Therefore, as shown in Figure 2, a decimated emitter structure (or repeating structure) is adopted in which the N+ type N-type emitter region 12 is decimated and replaced with a P+ type P-type contact region 15. By adopting a decimated emitter structure, the on-voltage and saturation current can be adjusted. of It is possible.

[0081] The current saturation characteristics of a surface MOS structure can generally be expressed by the following equation 1 using the parameters of the semiconductor device 100. Here, Isat is the saturation current, Z is the total emitter width of the N-type emitter region 12, μn is the electron mobility, Cox is the gate oxide capacitance, Lch is the channel length, Vge is the gate-emitter voltage, and Vth is the threshold voltage. The total emitter width Z may be the total number of emitter widths in the Y-axis direction.

number

[0082] Furthermore, the channel resistance Rch of a surface MOS structure is generally represented by Equation 2 below. Comparing Equation 1 and Equation 2, it can be seen that reducing the saturation current Isat increases the channel resistance Rch, and increasing the saturation current Isat decreases the channel resistance Rch. In other words, it can be seen that there is a trade-off correlation where reducing the saturation current to improve the short-circuit withstand capability of the semiconductor device 100 increases the on-voltage. In the decimated emitter structure, the N-type emitter region 12 is sparsely formed in the mesa region 60, so the supply of electron current to the N-type drift region 18 is also sparse, resulting in an uneven current flow and an increase in the on-voltage.

number

[0083] Figure 7 shows a semiconductor device 200 according to an embodiment. Figure 7 shows the arrangement on the upper surface 21 of the semiconductor substrate 10. Figure 7 differs from Figure 2 in that the width of the N-type emitter region 12 in the Y-axis direction is the emitter width L3, and the sum of the width of the N-type emitter region 12 in the Y-axis direction and the width of the P-type contact region 15 in the Y-axis direction is the pitch width L4. The other configurations of Figure 7 may be the same as those of Figure 2.

[0084] Figure 8 shows a semiconductor device 200 according to an embodiment. Figure 8 shows the arrangement on the upper surface of the interlayer insulating film 38. Figure 8 shows an arrangement in the XY plane different from that in Figure 7. The configuration in Figure 8 may be the same as that in Figure 3.

[0085] Figure 9 shows an example of the dd cross-section in Figure 7. The dd cross-section is the XZ plane passing through the N-type emitter region 12. Figure 9 differs from Figure 4 in that a low-concentration N-type emitter region 13 is provided. The other configurations of Figure 9 may be the same as those of Figure 4.

[0086] The low-concentration N-type emitter region 13 is provided between the emitter electrode 52 and the P-type base region 14 in the depth direction of the semiconductor substrate 10. In this example, the low-concentration N-type emitter region 13 is provided in the N-type emitter region 12. The N-type emitter region 12 below the low-concentration N-type emitter region 13 is designated as N-type emitter region 12-1, and the N-type emitter region 12 above the low-concentration N-type emitter region 13 is designated as N-type emitter region 12-2. N-type emitter region 12-1 is an example of a first high-concentration emitter region. N-type emitter region 12-2 is an example of a second high-concentration emitter region. Note that the N-type emitter region 12 may also have a low-concentration N-type emitter region 13. The N-type emitter region 12 may include an N-type emitter region 12-1, an N-type emitter region 12-2, and a low-concentration N-type emitter region 13.

[0087] In this example, the low-concentration N-type emitter region 13 has higher resistance than the N-type emitter regions 12-1 and 12-2. At the center of the mesa region 60, the doping concentration of the low-concentration N-type emitter region 13 is higher than the doping concentration of the N-type emitter regions 12-1 and 12-2. Low is fine The low-concentration N-type emitter region 13 in this example is N-type. The low-concentration N-type emitter region 13 may also be N-type. The low-concentration N-type emitter region 13 is an example of a high-resistance region.

[0088] Figure 10 shows an example of the ee cross-section in Figure 7. The ee cross-section is the XZ plane passing through the P-type contact region 15. The configuration of Figure 10 may be the same as that of Figure 5.

[0089] Figure 11 shows an example of the doping concentration distribution at the ff line in Figure 9. The ff line may be the central position of the mesa region 60 in the X-axis direction. Figure 11 shows the doping concentration distributions of the N-type emitter region 12-2, the low-concentration N-type emitter region 13, the N-type emitter region 12-1, the P-type base region 14, and the N-type drift region 18.

[0090] In the center of the mesa region 60, the doping concentration of the N-type emitter region 12-1 may be higher than the doping concentration of the low-concentration N-type emitter region 13. The N-type emitter region 12-1 may have a concentration peak with a higher doping concentration than the low-concentration N-type emitter region 13. In the center of the mesa region 60, the doping concentration of the N-type emitter region 12-2 may be higher than the doping concentration of the low-concentration N-type emitter region 13. The emitter region 12-2 may have a concentration peak with a higher doping concentration than the low-concentration N-type emitter region 13.

[0091] In this example, the doping concentration in the low-concentration N-type emitter region 13 at the center of the mesa region 60 is higher than the doping concentration in the P-type base region 14. The low-concentration N-type emitter region 13 may have a concentration peak with a higher doping concentration than the P-type base region 14.

[0092] Figure 12 illustrates the effect of the low-concentration N-type emitter region 13. In Figure 12, the small current I1 is set to a current smaller than the rated current, and the large current I2 is set to a large current approximately equal to the saturation current. The resistance of the low-concentration N-type emitter region 13 is denoted as R1. Note that the interlayer insulating film 38 and metal plug 62 are omitted in Figure 12.

[0093] When a low-concentration N-type emitter region 13 is provided, the current flowing through the low-concentration N-type emitter region 13 and the resistance R1 of the low-concentration N-type emitter region 13 change the potential of the N-type emitter region 12-1. When a large current I2 flows, the potential of the N-type emitter region 12-1 rises significantly. On the other hand, when a small current I1 flows, the potential of the N-type emitter region 12-1 rises only slightly. Since the gate voltage Vge that drives the surface MOS structure is constant, the potential difference Vge-eff across the gate insulating film 42 becomes small in the high-current region. On the other hand, in the low-current region, the potential difference Vge-eff across the gate insulating film 42 becomes relatively large. Therefore, the saturation current can be greatly suppressed.

[0094] As described above, in this example, the semiconductor device 200 includes a low-concentration N-type emitter region 13 that functions as a high-resistance section. Because the low-concentration N-type emitter region 13 is provided, the saturation current can be reduced, and the reduced limiting current value can be adjusted by increasing the total emitter width Z. Therefore, small In the current domain, it is driven by a large gate voltage / emitter voltage difference. Large current area This allows for driving with a small gate voltage / emitter voltage difference, enabling the semiconductor device 200 to exhibit characteristics of low on-voltage and low saturation voltage.

[0095] In this example, the emitter width L3 is 1.5 μm, and the pitch width L4 is 3.5 μm, for example. Therefore, the semiconductor device 200 can increase the total emitter width Z compared to the semiconductor device 100, and can achieve a lower on-voltage than shown in Equation 2.

[0096] The gate conductive portion 44 may be provided below the position where the low-concentration N-type emitter region 13 is provided in the depth direction of the semiconductor substrate 10. Providing the gate conductive portion 44 below the position where the low-concentration N-type emitter region 13 is provided in the depth direction of the semiconductor substrate 10 means, for example, that the position of the upper end 43 of the gate conductive portion 44 in the depth direction of the semiconductor substrate 10 is at the position where the N-type emitter region 12-1 is provided in the depth direction of the semiconductor substrate 10. Providing the gate conductive portion 44 below the position where the low-concentration N-type emitter region 13 is provided in the depth direction of the semiconductor substrate 10 means that the position of the upper end 43 of the gate conductive portion 44 in the depth direction of the semiconductor substrate 10 is at the position where the N-type emitter region 12-1 is provided in the depth direction of the semiconductor substrate 10. Since the gate conductive portion 44 is located below the position where the low-concentration N-type emitter region 13 is provided in the depth direction of the semiconductor substrate 10, the low-concentration N-type emitter region 13 is prevented from becoming a carrier accumulation layer, and the low-concentration N-type emitter region 13 is more likely to function as a high-resistance portion. In other figures as well, the gate conductive portion 44 may be located below the position where the low-concentration N-type emitter region 13 is provided in the depth direction of the semiconductor substrate 10.

[0097] Figure 13 is a diagram illustrating an example of a flowchart for the manufacturing method of the semiconductor device 200. The manufacturing method of the semiconductor device 200 comprises a gate trench formation step S101, a base region formation step S102, a contact region formation step S103, a first high-concentration emitter region formation step S104, a low-concentration emitter region formation step S105, and a second high-concentration emitter region formation step S106.

[0098] In the gate trench formation step S101, a gate trench 40 is formed on the upper surface 21 of the semiconductor substrate 10. to A gate trench is provided. The gate trench may be formed by known methods such as etching. Subsequently, a gate insulating film 42 and a gate conductive portion 44 are formed inside the gate trench. The gate insulating film 42 may be formed by oxidizing the semiconductor substrate 10 by known methods. The gate conductive portion 44 may be formed by depositing polysilicon or the like by known methods such as CVD. After the gate trench formation step S101, screening oxidation may be performed.

[0099] In the base region formation step S102, a P-type base region 14 is formed in the mesa portion 60. The P-type base region 14 is formed, for example, by ion implantation of boron. In this example, in order to lower the boron concentration near the surface, the P-type base region 14 is formed by ion implantation of boron at a high acceleration voltage. After ion implantation, heat treatment may be performed to activate the P-type base region 14.

[0100] In the contact region formation step S103, a P-type contact region 15 is selectively formed on the mesa portion 60. Therefore, photolithography is performed in the contact region formation step S103, and the resist is patterned. The P-type contact region 15 may be formed, for example, by ion implantation of boron. In this example, since the P-type base region 14 is connected to the upper surface 21 of the semiconductor substrate 10 with a high-concentration P-type layer, the P-type contact region 15 is formed by multi-stage ion implantation of boron at a high acceleration voltage.

[0101] In the first high-concentration emitter region formation step S104, an N-type emitter region 12-1 is selectively formed in the mesa portion 60. Therefore, photolithography may be performed in the first high-concentration emitter region formation step S104 to pattern the resist. The resist formed in the first high-concentration emitter region formation step S104 may remain until the second high-concentration emitter region formation step S106. The N-type emitter region 12-1 is formed, for example, by ion implantation of phosphorus.

[0102] In step S105, the low-concentration emitter region formation step, a low-concentration N-type emitter region 13 is selectively formed in the mesa portion 60. The low-concentration N-type emitter region 13 is formed, for example, by ion implantation of phosphorus.

[0103] In the second high-concentration emitter region formation step S106, an N-type emitter region 12-2 is selectively formed in the mesa portion 60. The N-type emitter region 12-2 is formed, for example, by ion implantation of arsenic. After ion implantation, the resist may be removed. After the second high-concentration emitter region formation step S106, heat treatment is performed to activate the P-type contact region 15, the N-type emitter region 12-1, the N-type emitter region 12-2, and the low-concentration N-type emitter region 13.

[0104] Figure 14 shows another example of the doping concentration distribution at the ff line in Figure 9. The ff line may be located at the center of the mesa region 60 in the X-axis direction. Figure 14 shows the doping concentration distributions for the N-type emitter region 12-2, the low-concentration N-type emitter region 13, the N-type emitter region 12-1, the P-type base region 14, and the N-type drift region 18.

[0105] In the center of the mesa region 60, the doping concentration of the N-type emitter region 12-1 may be higher than the doping concentration of the low-concentration N-type emitter region 13. The N-type emitter region 12-1 may have a concentration peak with a higher doping concentration than the low-concentration N-type emitter region 13. In the center of the mesa region 60, the doping concentration of the N-type emitter region 12-2 may be higher than the doping concentration of the low-concentration N-type emitter region 13. The N-type emitter region 12-2 may have a concentration peak with a higher doping concentration than the low-concentration N-type emitter region 13.

[0106] In this example, the doping concentration in the low-concentration N-type emitter region 13 at the center of the mesa region 60 is greater than the doping concentration in the P-type base region 14. low The low-concentration N-type emitter region 13 has a lower doping concentration than the P-type base region 14. low It may have a concentration peak.

[0107] The doping concentration of the low-concentration N-type emitter region 13 may be less than or equal to the doping concentration of the P-type base region 14. In this example, at the center of the mesa region 60, the doping concentration of the low-concentration N-type emitter region 13 is lower than the doping concentration of the P-type base region 14. The P-type base region 14 may have a concentration peak with a higher doping concentration than the low-concentration N-type emitter region 13. Even with such a configuration, it is possible to realize the characteristics of a semiconductor device 200 with a low on-voltage and low saturation voltage.

[0108] Figure 15 shows an example of the doping concentration distribution at the gg line in Figure 9. The gg line may be the center in the depth direction of the low-concentration N-type emitter region 13. The center C is defined as the center of the mesa portion 60 in the X-axis direction. Figure 15 shows the doping concentration distribution of the low-concentration N-type emitter region 13 from one gate insulating film 42 to the adjacent gate insulating film 42.

[0109] In this example, the doping concentration of the low-concentration N-type emitter region 13 at the position in contact with the gate trench portion 40 (gate insulating film 42) is lower than the doping concentration of the low-concentration N-type emitter region 13 at the center C of the mesa portion 60. The doping concentration distribution in the gg line may have a concentration peak at the center C.

[0110] Figure 16 shows another example of the doping concentration distribution along the gg line in Figure 9. Figure 16 shows the doping concentration distribution in the low-concentration N-type emitter region 13 from one gate insulating film 42 to the adjacent gate insulating film 42.

[0111] In this example, the doping concentration of the low-concentration N-type emitter region 13 at the position in contact with the gate trench portion 40 (gate insulating film 42) is higher than the doping concentration of the low-concentration N-type emitter region 13 at the center C of the mesa portion 60. The doping concentration distribution in the gg line may have a concentration peak at the position in contact with the gate trench portion 40. By increasing the doping concentration of the low-concentration N-type emitter region 13 at the position in contact with the gate trench portion 40, the resistance of the low-concentration N-type emitter region 13 can be increased. It is preferable to implant ions at an angle in order to increase the doping concentration of the low-concentration N-type emitter region 13 at the position in contact with the gate trench portion 40.

[0112] Figure 17 shows a semiconductor device 300 according to another embodiment. Figure 17 shows the arrangement on the upper surface 21 of the semiconductor substrate 10. The semiconductor device 300 in Figure 17 differs from the semiconductor device 200 in Figure 7 in that it includes a metal plug 64 and a P-type diffusion region 16. The other configurations of Figure 17 may be the same as those in Figure 7.

[0113] Figure 18 shows a semiconductor device 300 according to another embodiment. Figure 18 shows the arrangement on the upper surface of the interlayer insulating film 38. The semiconductor device 300 in Figure 18 differs from the semiconductor device 200 in Figure 8 in that it has a metal plug 64 instead of a metal plug 62. The other configurations of Figure 18 may be the same as those in Figure 8.

[0114] Figure 19 shows an example of the hh cross-section in Figure 17. The hh cross-section is the XZ plane passing through the N-type emitter region 12. The semiconductor device 300 in Figure 19 differs from the semiconductor device 200 in Figure 9 in that it includes a metal plug 64 and a P-type diffusion region 16. The other configurations of Figure 19 may be the same as those in Figure 9.

[0115] In this example, the metal plug 64 is provided inside the semiconductor substrate 10. The metal plug 64 may be provided inside a trench provided in the mesa portion 60 of the semiconductor substrate 10. Also, similar to the metal plug 62, the metal plug 64 is provided in the interlayer insulating film 38. The metal plug 64 may be formed in a contact hole 54 provided in the interlayer insulating film 38. By providing the metal plug 64, the contact resistance between the semiconductor substrate 10 and the emitter electrode 52 can be reduced. The metal plug 64 is formed of Ta, W, Mo, etc., as an example.

[0116] In this example, a P-type diffusion region 16 is provided below the metal plug 64. The P-type diffusion region 16 may be provided between the P-type base region 14 and the metal plug 64. The P-type diffusion region 16 may be provided on the upper surface 21 of the semiconductor substrate 10. The P-type diffusion region 16 may be provided so as not to be in contact with the gate trench portion 40. The P-type diffusion region 16 is, for example, of the P+ type. By providing the P-type diffusion region 16, when the semiconductor device 100 is turned off, holes heading from the lower surface 23 towards the N-type emitter region 12 can be flowed to the metal plug 64 via the P-type diffusion region 16. This reduces the resistance of the path through which the holes pass, and suppresses latch-up. In addition, the metal plug 64 and the emitter electrode 52 make contact, improving the breakdown resistance.

[0117] Figure 20 shows an example of cross-section ii in Figure 17. Cross-section ii is the XZ plane passing through the P-type contact region 15. The semiconductor device 300 in Figure 20 differs from the semiconductor device 200 in Figure 10 in that it includes a metal plug 64 and a P-type diffusion region 16. The other configurations of Figure 20 may be the same as those of Figure 10. The metal plug 64 and the P-type diffusion region 16 may also be provided in the cross-section passing through the P-type contact region 15.

[0118] Figure 21 shows an example of the doping concentration distribution along the jj line in Figure 19. Figure 21 shows the doping concentration distribution in the P-type diffusion region 16, the P-type base region 14, and the N-type drift region 18.

[0119] In this example, the doping concentration in the P-type diffusion region 16 is higher than that in the P-type base region 14. The P-type diffusion region 16 may have a concentration peak with a higher doping concentration than the P-type base region 14. To form the P-type diffusion region 16, it is preferable to implant ions at an oblique angle.

[0120] Figure 22 shows a semiconductor device 400 according to another embodiment. Figure 22 shows the arrangement on the upper surface 21 of the semiconductor substrate 10. Figure 22 differs from the semiconductor device 100 in Figure 2 in that the width of the N-type emitter region 12 in the Y-axis direction is the emitter width L3, and the sum of the width of the N-type emitter region 12 in the Y-axis direction and the width of the P-type contact region 15 in the Y-axis direction is the pitch width L4. Also, the semiconductor device 400 in Figure 22 differs from the semiconductor device 100 in Figure 2 in that it has a polysilicon resistor 66 instead of an interlayer insulating film 38 and a metal plug 62. The other configurations of Figure 22 may be the same as those in Figure 2. In Figure 22, the arrangement of the polysilicon resistor 66 on the upper surface 21 of the semiconductor substrate 10 is shown by a thick dotted line.

[0121] Figure 23 shows an example of the kk cross-section in Figure 22. The kk cross-section is the XZ plane passing through the N-type emitter region 12. The semiconductor device 400 in Figure 23 differs from Figure 4 in that it has a polysilicon resistor 66 instead of an interlayer insulating film 38 and a metal plug 62. The other configurations of Figure 23 may be the same as those in Figure 4.

[0122] The polysilicon resistor 66 is provided between the emitter electrode 52 and the P-type base region 14 in the depth direction of the semiconductor substrate 10. In this example, at least a portion of the polysilicon resistor 66 is provided above the semiconductor substrate 10. At least a portion of the polysilicon resistor 66 may be provided on the upper surface 21 of the semiconductor substrate 10. In Figure 23, the entire polysilicon resistor 66 is provided on the upper surface 21 of the semiconductor substrate 10. The polysilicon resistor 66 may be provided above the N-type emitter region 12. The polysilicon resistor 66 may cover the N-type emitter region 12.

[0123] In this example, the polysilicon resistor 66 has a higher resistance than the N-type emitter region 12. Therefore, the polysilicon resistor 66 is an example of a high-resistance region. The gate conductive portion 44 may be provided below the position where the polysilicon resistor 66 is provided in the depth direction of the semiconductor substrate 10. In this example, the polysilicon resistor 66 is provided above the gate conductive portion 44. It is preferable that arsenic be injected into the surface of the polysilicon resistor 66 in order to reduce the contact resistance with the emitter electrode 52.

[0124] Figure 24 shows an example of cross-section ll in Figure 22. Cross-section ll is the XZ plane passing through the P-type contact region 15. The configuration in Figure 10 may be the same as that in Figure 5. In other words, in this cross-section, the semiconductor device 300 does not have a polysilicon resistor 66.

[0125] Figure 25 illustrates the effect of the polysilicon resistor 66. In Figure 25, the small current I1 is set to a current smaller than the rated current, and the large current I2 is set to a large current approximately equal to the saturation current. The resistance of the polysilicon resistor 66 is set to R2.

[0126] When a polysilicon resistor 66 is provided, the potential of the N-type emitter region 12-1 changes depending on the current flowing through the polysilicon resistor 66 and the resistance R2 of the polysilicon resistor 66. When a large current I2 flows, the potential of the N-type emitter region 12-1 rises significantly. On the other hand, when a small current I1 flows, the potential of the N-type emitter region 12-1 rises only slightly. Since the gate voltage Vge that drives the surface MOS structure is constant, the potential difference Vge-eff across the gate insulating film 42 becomes small in the high-current region. On the other hand, in the low-current region, the potential difference Vge-eff across the gate insulating film 42 becomes relatively large. Therefore, the saturation current can be greatly suppressed.

[0127] Therefore, in this example, the semiconductor device 400 is equipped with a polysilicon resistor 66 that functions as a high-resistance section. Because the polysilicon resistor 66 is provided, the saturation current can be reduced, and the reduced limiting current value can be adjusted by increasing the total emitter width Z. Therefore, small In the current domain, it is driven by a large gate voltage / emitter voltage difference. Large current area This allows for driving with a small gate voltage / emitter voltage difference, enabling the semiconductor device 200 to exhibit characteristics of low on-voltage and low saturation voltage.

[0128] In this example, the emitter width L3 is 1.5 μm, and the pitch width L4 is 3.5 μm, for example. Therefore, the semiconductor device 200 can increase the total emitter width Z compared to the semiconductor device 100, and can achieve a lower on-voltage than shown in Equation 2.

[0129] In Figure 22, the polysilicon resistor 66 covers the N-type emitter region 12 in a top view. By covering the N-type emitter region 12, the polysilicon resistor 66 prevents direct connection between the polysilicon resistor 66 and the emitter electrode 52.

[0130] Furthermore, the polysilicon resistor 66 may cover at least a portion of the P-type contact region 15 when viewed from above. The polysilicon resistor 66 does not have to cover at least a portion of the P-type contact region 15 when viewed from above. The emitter electrode 52 may be in contact with the P-type contact region 15 that is not covered by the polysilicon resistor 66. Therefore, the polysilicon resistor 66 and the emitter electrode 52 alternately contact the upper surface 21 of the semiconductor substrate 10. In this example, the polysilicon resistor 66 and the emitter electrode 52 alternately contact the upper surface 21 of the semiconductor substrate 10 in the stretching direction. This configuration makes it possible to achieve a low on-voltage while realizing the function of the P-type contact region 15. The width L5 covering the edge of the P-type contact region 15 when viewed from above is, for example, 0.5 μm.

[0131] Figure 26 shows a semiconductor device 500 according to another embodiment. Figure 26 shows the arrangement on the upper surface 21 of the semiconductor substrate 10. The arrangement of the N-type emitter region 12 and the polysilicon resistor 66 in the semiconductor device 500 of Figure 26 differs from that of the semiconductor device 400 in Figure 22. The other configurations of Figure 26 may be the same as those of Figure 22. Note that the nn cross-section in Figure 26 may be the same as the ll cross-section of the semiconductor device 400 shown in Figure 24.

[0132] Figure 27 shows an example of a mm cross-section in Figure 26. The mm cross-section is the XZ plane passing through the N-type emitter region 12. The semiconductor device 500 in Figure 27 differs from the semiconductor device 400 in Figure 23 in the arrangement of the N-type emitter region 12 and the polysilicon resistor 66. The other configurations of Figure 27 may be the same as those in Figure 23.

[0133] In this example, the N-type emitter region 12 is not provided in one mesa portion 60 (mesa portion 60-1). Therefore, the polysilicon resistor 66 does not need to be provided above the mesa portion 60-1. The polysilicon resistor 66 may be provided above the two gate trench portions 40 (gate trench portions 40-1) that sandwich the mesa portion 60-1 in the arrangement direction. The polysilicon resistor 66 may be provided from the end of the gate trench portion 40-1 opposite to the mesa portion 60-1 in the arrangement direction to the center of the gate trench portion 40-1 in the arrangement direction. Emitter electrodes 52 may be placed where the polysilicon resistor 66 is not provided.

[0134] Figure 28 shows a semiconductor device 600 according to another embodiment. Figure 28 shows the arrangement on the upper surface 21 of the semiconductor substrate 10. Figure 28 differs from the semiconductor device 100 in Figure 2 in that the width of the N-type emitter region 12 in the Y-axis direction is the emitter width L3, and the sum of the width of the N-type emitter region 12 in the Y-axis direction and the width of the P-type contact region 15 in the Y-axis direction is the pitch width L4. Also, the semiconductor device 600 in Figure 28 differs from the semiconductor device 100 in Figure 2 in that it includes a polysilicon resistor 66. The other configurations of Figure 28 may be the same as those in Figure 2. In Figure 28, the arrangement of the polysilicon resistor 66 on the upper surface 21 of the semiconductor substrate 10 is shown by a thick dotted line. Note that the pp cross section in Figure 28 may be the same as the bb cross section of the semiconductor device 100 shown in Figure 5.

[0135] Figure 29 shows a semiconductor device 600 according to another embodiment. Figure 29 shows the arrangement on the upper surface of the interlayer insulating film 38. Figure 29 shows an arrangement in the XY plane, which is different from that of Figure 28. The semiconductor device 600 in Figure 29 differs from the semiconductor device 100 in Figure 3 in that it includes a polysilicon resistor 66. The other configurations of Figure 29 may be the same as those in Figure 3.

[0136] Figure 30 shows an example of the oo cross-section in Figure 28. The oo cross-section is the XZ plane passing through the N-type emitter region 12. The semiconductor device 600 in Figure 30 differs from the semiconductor device 100 in Figure 4 in that a polysilicon resistor 66 is provided instead of a metal plug 62. The other configurations of Figure 30 may be the same as those in Figure 4.

[0137] In this example, the polysilicon resistor 66 is provided in the interlayer insulating film 38. The polysilicon resistor 66 may be formed in a contact hole 54 provided in the interlayer insulating film 38. The polysilicon resistor 66 electrically connects the semiconductor substrate 10 (mesa portion 60) and the emitter electrode 52.

[0138] In Figure 28, the polysilicon resistor 66 covers at least a portion of the N-type emitter region 12 in a top view. In this example, since the semiconductor device 600 includes an interlayer insulating film 38, the polysilicon resistor 66 does not need to cover the entire N-type emitter region 12 in a top view.

[0139] Furthermore, the polysilicon resistor 66 may cover at least a portion of the P-type contact region 15 when viewed from above. The polysilicon resistor 66 does not have to cover at least a portion of the P-type contact region 15 when viewed from above. The P-type contact region 15 not covered by the polysilicon resistor 66 may be in contact with the metal plug 62 formed in the contact hole 54. The metal plug 62 may be provided above the P-type contact region 15. The metal plug 62 does not have to be provided above the N-type emitter region 12. Therefore, the polysilicon resistor 66 and the metal plug 62 alternately contact the upper surface 21 of the semiconductor substrate 10. In this example, the polysilicon resistor 66 and the metal plug 62 alternately contact the upper surface 21 of the semiconductor substrate 10 in the stretching direction. With this configuration, the function of the P-type contact region 15 can be realized while achieving a low on-voltage.

[0140] Figure 31 shows a semiconductor device 700 according to another embodiment. Figure 31 shows the arrangement on the upper surface 21 of the semiconductor substrate 10. The arrangement of the N-type emitter region 12 and the polysilicon resistor 66 in the semiconductor device 700 of Figure 31 differs from that of the semiconductor device 600 of Figure 28. The other configurations of Figure 31 may be the same as those of Figure 28. Note that the rr cross section in Figure 31 may be the same as the bb cross section of the semiconductor device 100 shown in Figure 5.

[0141] Figure 32 shows a semiconductor device 700 according to another embodiment. Figure 32 shows the arrangement on the upper surface of the interlayer insulating film 38. Figure 32 shows an arrangement in the XY plane, which is different from that of Figure 31. The arrangement of the polysilicon resistor 66 in the semiconductor device 700 of Figure 32 is different from that of the semiconductor device 600 of Figure 29. The other configurations of Figure 32 may be the same as those of Figure 29.

[0142] Figure 33 shows an example of the qq cross-section in Figure 31. The qq cross-section is the XZ plane passing through the N-type emitter region 12. The semiconductor device 700 in Figure 33 differs from the semiconductor device 600 in Figure 30 in the arrangement of the N-type emitter region 12 and the polysilicon resistor 66. The other configurations of Figure 33 may be the same as those in Figure 30.

[0143] In this example, the N-type emitter region 12 is not provided in one mesa portion 60 (mesa portion 60-1). Therefore, the polysilicon resistor portion 66 does not need to be provided above mesa portion 60-1. A metal plug 62 may be provided above mesa portion 60-1.

[0144] Figure 34 shows a semiconductor device 800 according to another embodiment. Figure 34 shows the arrangement on the upper surface 21 of the semiconductor substrate 10. The configuration of Figure 34 may be the same as that of Figure 28. Note that the tt cross section in Figure 34 may be the same as the bb cross section of the semiconductor device 100 shown in Figure 5. In Figure 34, the polysilicon resistor 66 formed in the contact hole 54 is referred to as the polysilicon resistor 66-1.

[0145] Figure 35 shows a semiconductor device 800 according to another embodiment. Figure 35 shows the arrangement on the upper surface of the interlayer insulating film 38. Figure 35 shows an arrangement in the XY plane, which is different from that of Figure 34. The semiconductor device 800 in Figure 35 differs from the semiconductor device 600 in Figure 29 in that the polysilicon resistor 66 is provided above the interlayer insulating film 38. The other configurations of Figure 35 may be the same as those of Figure 29. In Figure 35, the polysilicon resistor 66 provided above the interlayer insulating film 38 is referred to as the polysilicon resistor 66-2, and the arrangement of the polysilicon resistor 66-2 is shown by a thick dotted line. In this specification, "provided above" means being located at an upper position in the depth direction of the semiconductor substrate 10.

[0146] Figure 36 shows an example of the ss cross-section in Figure 34. The ss cross-section is the XZ plane passing through the N-type emitter region 12. The semiconductor device 800 in Figure 36 differs from the semiconductor device 600 in Figure 30 in that the polysilicon resistor 66-2 is located above the interlayer insulating film 38. The other configurations of Figure 36 may be the same as those of Figure 30. Also, in Figure 36, the boundary between the polysilicon resistor 66-1 and the polysilicon resistor 66-2 is shown by a dotted line.

[0147] In this example, the polysilicon resistor 66-2 is provided above the interlayer insulating film 38. By providing the polysilicon resistor 66-2, the resistance of the polysilicon resistor 66 can be adjusted without changing the depth of the contact hole 54 or the depth of the metal plug 62.

[0148] Figure 37 shows a semiconductor device 1100 according to another embodiment. Figure 37 shows the arrangement on the upper surface 21 of the semiconductor substrate 10. Figure 37 differs from the semiconductor device 600 in Figure 28 in that the polysilicon resistor 66 is provided only above the N-type emitter region 12. The other configurations of Figure 37 may be the same as those of Figure 28. Also, similar to Figure 28, in Figure 37 the metal plug 62 is provided only above the P-type contact region 15. In Figure 37, the arrangement of the polysilicon resistor 66 and the metal plug 62 on the upper surface 21 of the semiconductor substrate 10 is shown by thick dotted lines. Note that the uu cross-section in Figure 37 may be the same as the oo cross-section of the semiconductor device 600 shown in Figure 30. Note that the vv cross-section in Figure 37 may be the same as the bb cross-section of the semiconductor device 100 shown in Figure 5.

[0149] Figure 38 shows a semiconductor device 1100 according to another embodiment. Figure 38 shows the arrangement on the upper surface of the interlayer insulating film 38. Figure 38 shows an arrangement in the XY plane different from that in Figure 37. In this example, the interlayer insulating film 38 may be provided between the polysilicon resistor 66 and the metal plug 62 in the stretching direction (Y axis direction). Even with this configuration, the function of the P-type contact region 15 can be realized while achieving a low on-voltage.

[0150] Figure 39 shows another example of the dd cross-section in Figure 7. The dd cross-section is the XZ plane passing through the N-type emitter region 12. Figure 39 differs from Figure 9 in that a high-concentration P-type base region 17 is provided. The other configurations of Figure 39 may be the same as those of Figure 9. The high-concentration P-type base region 17 may be provided below the P-type base region 14. The P-type base region 14 is an example of a low-concentration base region.

[0151] Figure 40 shows an example of the doping concentration distribution along the uu line in Figure 39. The uu line may be located at the center of the mesa region 60 in the X-axis direction. Figure 40 shows the doping concentration distributions for the N-type emitter region 12-2, the low-concentration N-type emitter region 13, the N-type emitter region 12-1, the P-type base region 14, the high-concentration P-type base region 17, and the N-type drift region 18.

[0152] In this example, the doping concentration of the high-concentration P-type base region 17 in the center of the mesa region 60 is higher than the doping concentration of the P-type base region 14. The high-concentration P-type base region 17 in this example is P+ type. The high-concentration P-type base region 17 may have a concentration peak with a higher doping concentration than the P-type base region 14. Also, the doping concentration of the high-concentration P-type base region 17 in the center of the mesa region 60 may be higher than the doping concentration of the low-concentration N-type emitter region 13. The high-concentration P-type base region 17 may have a concentration peak with a higher doping concentration than the low-concentration N-type emitter region 13. Even with the provision of a high-concentration P-type base region 17, it is possible to realize the characteristics of a semiconductor device 200 with a low on-voltage and low saturation voltage. Note that there may be a peak at the boundary between the high-concentration P-type base region 17 and the P-type base region 14.

[0153] Figure 41 shows the relationship between the impurity concentration in the low-concentration N-type emitter region 13 and the contact-emitter ratio. The contact-emitter ratio is the ratio of the P-type contact region 15 to the N-type emitter region 12. In the example in Figure 7, the contact-emitter ratio is (L4-L3) / L3 = 2.0 μm / 1.5 μm ≈ 1.33. In Figure 41, the contact-emitter ratio at which the saturation current is equivalent was calculated when the impurity concentration in the low-concentration N-type emitter region 13 was changed.

[0154] In Figure 41, the impurity concentration in the low-concentration N-type emitter region 13 is 3.0 × 10⁻⁶. 18 cm -3 By reducing it to the following extent, the contact-emitter ratio can be reduced. Therefore, the total emitter width Z can be increased, and a lower on-voltage than that shown in equation 2 can be achieved. Note that the lowest concentration portion of the low-concentration N-type emitter region 13 is 3.0 × 10 18 cm -3 The following is preferable:

[0155] Figure 42 shows a semiconductor device 900 according to another embodiment. Figure 42 shows the XZ plane passing through the N-type emitter region 12-2. In Figure 42, only the vicinity of the mesa portion 60 and the gate trench portion 40 is shown. Note that in Figure 42, common reference numerals are omitted from explanation. In Figure 42, when a positive voltage is applied to the gate conductive portion 44, the N-type storage layer formed in the low-concentration N-type emitter region 13 is shown by a thick line. Also in Figure 42, when a positive voltage is applied to the gate conductive portion 44, the N-type inversion layer formed in the P-type base region 14 is shown by a thick dotted line. Also in Figure 42, when a positive voltage is applied to the gate conductive portion 44, the N-type storage layer formed in the N-type drift region 18 is shown by a thick line.

[0156] In this example, the low-concentration N-type emitter region 13 is in contact with the P-type base region 14. In other words, unlike in Figure 9, an N-type emitter region 12-1 is not provided in Figure 42. Even with this configuration, the saturation current can be reduced.

[0157] In the semiconductor device 900, the upper end 43 of the gate conductive portion 44 is located within a low-concentration N-type emitter region 13 in the depth direction of the semiconductor substrate 10. In this case, when a positive voltage is applied to the gate conductive portion 44, the N-type storage layer formed in the low-concentration N-type emitter region 13 becomes shorter, so the low-concentration N-type emitter region 13 has a greater function as a resistor.

[0158] Figure 43 shows a semiconductor device 1000 according to another embodiment. Figure 43 shows the XZ plane passing through the N-type emitter region 12-2. In Figure 43, only the vicinity of the mesa portion 60 and the gate trench portion 40 is shown. Note that in Figure 43, reference numerals common to Figure 42 are not explained.

[0159] In the semiconductor device 1000, the position of the upper end 43 of the gate conductive portion 44 in the depth direction of the semiconductor substrate 10 is located within the N-type emitter region 12-2. In this case, when a positive voltage is applied to the gate conductive portion 44, the N-type storage layer formed in the low-concentration N-type emitter region 13 becomes longer, thereby suppressing variations in the saturation current.

[0160] Figure 44 shows the IV characteristics in the high-current region. In Figure 44, semiconductor device 100 is shown by a solid line and semiconductor device 200 is shown by a dotted line. The semiconductor device 200 is adjusted to have a saturation current similar to that of semiconductor device 100 by adjusting the total emitter width Z.

[0161] Figure 45 shows the IV characteristics in the rated current region. In Figure 45, semiconductor device 100 is shown by a solid line and semiconductor device 200 is shown by a dotted line. Compared to semiconductor device 100, semiconductor device 200 has a larger total emitter width Z, resulting in a lower on-voltage.

[0162] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. It will be clear from the claims that such modified or improved forms may also be included in the technical scope of the present invention.

[0163] It should be noted that the execution order of operations, procedures, steps, and stages in the apparatus, systems, programs, and methods shown in the claims, specifications, and drawings is not explicitly stated as "before," "prior to," etc., and that these can be implemented in any order unless the output of a previous process is used in a later process. Even if the operation flow in the claims, specifications, and drawings is described using phrases such as "first," "next," etc. for convenience, it does not mean that it is essential to perform the operations in that order. [Explanation of Symbols]

[0164] 10...Semiconductor substrate, 11...P-type outer well region, 12...N-type emitter region, 13...Low-concentration N-type emitter region, 14...P-type base region, 15...P-type contact region, 16...P-type diffusion region, 17...High-concentration P-type base region, 18...N-type drift region, 19...Bottom edge, 20...N-type buffer region, 21...Top surface, 22...P-type collector region, 23...Bottom surface, 24...Collector electrode, 38...Interlayer insulating film, 40...Gate trench region, 42...Gate insulating film, 43...Top edge, 44...Gate conductive region, 52...Emitter electrode, 54...Contact Hole, 60...Mesa section, 62...Metal plug, 64...Metal plug, 66...Polysilicon resistor section, 70...Transistor section, 90...Edge termination structure section, 100...Semiconductor device, 130...Gate wiring, 160...Active section, 161...First edge, 162...Second edge, 164...Gate pad, 200...Semiconductor device, 300...Semiconductor device, 400...Semiconductor device, 500...Semiconductor device, 600...Semiconductor device, 700...Semiconductor device, 800...Semiconductor device, 900...Semiconductor device, 1000...Semiconductor device, 1100...Semiconductor device

Claims

1. A semiconductor substrate and The semiconductor substrate is provided on the upper surface and comprises a plurality of gate trench portions extending along the stretching direction, An emitter electrode provided above the semiconductor substrate, A mesa portion is provided between adjacent gate trench portions within the plurality of gate trench portions, A first conductivity type emitter region is provided on the upper surface of the mesa portion and is in contact with the gate trench portion, A second conductive contact region provided on the upper surface of the mesa portion, In the semiconductor substrate, a base region of a second conductivity type is provided below the emitter region and the contact region, in contact with the gate trench portion, and having a lower doping concentration than the contact region. In the semiconductor substrate, a drift region of a first conductivity type is provided below the base region, and the doping concentration is lower than that of the emitter region. A high-resistance portion is provided between the emitter electrode and the base region in the depth direction of the semiconductor substrate, and has a higher resistance than the emitter region. Prepare, The emitter region and the contact region are arranged alternately in the stretching direction. The emitter region has a first high-concentration emitter region, The high-resistance section is located above the first high-concentration emitter region and is a low-concentration emitter region with a lower doping concentration than the first high-concentration emitter region. The doping concentration in the low-concentration emitter region is equal to or greater than the doping concentration in the base region. Semiconductor equipment.

2. A semiconductor substrate and The semiconductor substrate is provided on the upper surface and comprises a plurality of gate trench portions extending along the stretching direction, An emitter electrode provided above the semiconductor substrate, A mesa portion is provided between adjacent gate trench portions within the plurality of gate trench portions, A first conductivity type emitter region is provided on the upper surface of the mesa portion and is in contact with the gate trench portion, A second conductive contact region provided on the upper surface of the mesa portion, In the semiconductor substrate, a base region of a second conductivity type is provided below the emitter region and the contact region, in contact with the gate trench portion, and having a lower doping concentration than the contact region. In the semiconductor substrate, a drift region of a first conductivity type is provided below the base region, and the doping concentration is lower than that of the emitter region. A high-resistance portion is provided between the emitter electrode and the base region in the depth direction of the semiconductor substrate, and has a higher resistance than the emitter region. Prepare, The emitter region and the contact region are arranged alternately in the stretching direction. The emitter region has a first high-concentration emitter region, The high-resistance section is located above the first high-concentration emitter region and is a low-concentration emitter region with a lower doping concentration than the first high-concentration emitter region. The doping concentration in the low-concentration emitter region at the position in contact with the gate trench is higher than the doping concentration in the low-concentration emitter region at the center of the mesa. Semiconductor equipment.

3. A semiconductor substrate and The semiconductor substrate is provided on the upper surface and comprises a plurality of gate trench portions extending along the stretching direction, An emitter electrode provided above the semiconductor substrate, A mesa portion is provided between adjacent gate trench portions within the plurality of gate trench portions, A first conductivity type emitter region is provided on the upper surface of the mesa portion and is in contact with the gate trench portion, A second conductive contact region provided on the upper surface of the mesa portion, In the semiconductor substrate, a base region of a second conductivity type is provided below the emitter region and the contact region, in contact with the gate trench portion, and having a lower doping concentration than the contact region. In the semiconductor substrate, a drift region of a first conductivity type is provided below the base region, and the doping concentration is lower than that of the emitter region. A high-resistance portion is provided between the emitter electrode and the base region in the depth direction of the semiconductor substrate, and has a higher resistance than the emitter region. Prepare, The emitter region and the contact region are arranged alternately in the stretching direction. The emitter region has a high-concentration emitter region. The high-resistance section is located below the high-concentration emitter region and is a low-concentration emitter region with a lower doping concentration than the high-concentration emitter region. The low-concentration emitter region is in contact with the gate trench and the base region. The gate trench portion has a gate conductive portion, The position of the upper end of the gate conductive portion in the depth direction is provided within the low-concentration emitter region or the high-concentration emitter region. The low-concentration emitter region is separated from the emitter electrode by the high-concentration emitter region. Semiconductor equipment.

4. The gate trench portion has a gate conductive portion, The gate conductive portion is provided below the position where the high-resistance portion is provided in the depth direction of the semiconductor substrate. The semiconductor device according to claim 1 or 2.

5. The emitter region is provided above the low-concentration emitter region and further comprises a second high-concentration emitter region having a higher doping concentration than the low-concentration emitter region. The semiconductor device according to any one of claims 1, 2, or 4.

6. The doping concentration in the low-concentration emitter region is less than or equal to the doping concentration in the base region. The semiconductor device according to claim 2 or 3.

7. The aforementioned base region is Low concentration base region, A high-concentration base region is provided below the low-concentration base region, and the doping concentration is higher than that of the low-concentration base region. has The semiconductor device according to any one of claims 1 to 6.

8. Semiconductor substrate and The semiconductor substrate is provided on the upper surface and comprises a plurality of gate trench portions extending along the stretching direction, An emitter electrode provided above the semiconductor substrate, A mesa portion is provided between adjacent gate trench portions within the plurality of gate trench portions, A first conductivity type emitter region is provided on the upper surface of the mesa portion and is in contact with the gate trench portion, A second conductive contact region provided on the upper surface of the mesa portion, In the semiconductor substrate, a base region of a second conductivity type is provided below the emitter region and the contact region, in contact with the gate trench portion, and having a lower doping concentration than the contact region. In the semiconductor substrate, a drift region of a first conductivity type is provided below the base region, and the doping concentration is lower than that of the emitter region. A polysilicon resistor is provided between the emitter electrode and the base region in the depth direction of the semiconductor substrate, with at least a portion of it provided above the semiconductor substrate and having a higher resistance than the emitter region. Prepare, The emitter region and the contact region are arranged alternately in the stretching direction in a semiconductor device.

9. The polysilicon resistor portion covers the emitter region when viewed from above. The semiconductor device according to claim 8.

10. The polysilicon resistor and the emitter electrode are alternately in contact with the upper surface of the semiconductor substrate in the stretching direction. The semiconductor device according to claim 9.

11. The gate trench portion is further provided with an interlayer insulating film, The polysilicon resistor is formed in the interlayer insulating film. The semiconductor device according to any one of claims 8 to 10.

12. The system further comprises a metal plug provided above the contact region and formed in the interlayer insulating film. The semiconductor device according to claim 11.

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