Differential amplifier circuit

Abstract

To provide a differential amplification circuit which can operate rapidly and generates less sampling errors.SOLUTION: A differential amplification circuit 100 including a sample holding function has: a main differential amplification unit A1 for differentially amplifying a differential input signal; a switch pair SW4 connected to two differential output ends of the main differential amplification unit A1; and an auxiliary differential amplification unit A2 in which two differential output ends are connected to the two differential output ends of the main differential amplification unit A1, two differential input ends are connected to two differential output ends of the main differential amplification unit A1 by a switch pair SW3, the auxiliary differential amplification unit negatively feeding back a differential voltage between the two differential output ends of the main differential amplification unit A1 to the two differential output ends by turning on the switch pair SW3.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] This invention relates to a differential amplifier circuit having a sample - hold function.

Background Art

[0002] In analog circuits such as flash - type AD conversion circuits, a differential amplifier circuit having a sample - hold function is used. FIG. 3 is a circuit diagram showing the configuration of a conventional differential amplifier circuit 100A, which is an example of this type of differential amplifier circuit. This differential amplifier circuit 100A has a sample - hold section 1, a main differential amplifier A1, and an output section 2.

[0003] The sample - hold section 1 has a first capacitor pair C1, a first switch pair SW1, and a first reference power supply VBIAS1. Here, the first capacitor pair C1 is connected between a first node pair N1 to which a differential input signal is applied and a second node pair N2 connected to two differential input terminals of the main differential amplifier A1, respectively. Also, the first switch pair SW1 is connected between the second node pair N2 and the first reference power supply VBIAS1, respectively.

[0004] The output section 2 has a second capacitor pair C2, a second switch pair SW2, and a second reference power supply VBIAS2. Here, the second capacitor pair C2 is connected between a third node pair N3 connected to two differential output terminals of the main differential amplifier A1 and a fourth node pair N4 which is the output terminal of the differential amplifier circuit 100A, respectively. Also, the second switch pair SW2 is connected between the fourth node pair N4 and the second reference power supply VBIAS2, respectively.

[0005] Figure 4 is a time chart showing an example of the operation of this differential amplifier circuit 100A. In Figure 4, S is an abbreviation for sampling period and H is an abbreviation for hold period. The same applies to Figures 2, 6, and 7. In this differential amplifier circuit 100A, the first switch pair SW1 and the second switch pair SW2 are turned ON during the sampling period. When the first switch pair SW1 is turned ON, the second node pair N2 is connected to the first reference power supply VBIAS, and the differential voltage of the second node pair N2 becomes 0V. As a result, the differential voltage of the voltage output from the main differential amplifier A1 to the third node pair N3 changes toward the output offset voltage of the main differential amplifier A1. Also, the first capacitor pair C1 is charged by the differential input signal from the first node pair N1. Furthermore, when the second switch pair SW2 is turned ON, the second capacitor pair C2 is charged by the differential signals output from the two differential output terminals of the main differential amplifier A1. The differential voltage between each voltage applied to this second capacitor pair C2 (i.e., each voltage in the third node pair N3) changes toward the output offset voltage of the main differential amplifier A1.

[0006] During the hold period, the first switch pair SW1 and the second switch pair SW2 are turned OFF. As a result, the fluctuations of each voltage in the first node pair N1 from the voltages held in the first capacitor pair C1 are supplied to the two differential input terminals of the main differential amplifier A1, and the main differential amplifier A1 outputs the difference between the differential signals to the two differential input terminals with a gain of gm1. Then, the voltage held in the second capacitor pair C2 is subtracted from the two differential output signals of the main differential amplifier A1 and output to the fourth node pair N4. Here, the difference between each voltage held in the second capacitor pair C2 coincides with the output offset voltage of the main differential amplifier A1. Therefore, the differential output signal with the output offset voltage removed is output to the fourth node pair N4.

[0007] Incidentally, when the differential input signal applied to the first node pair N1 is large in amplitude, during the hold period, the main differential amplifier A1 differentially amplifies this large-amplitude differential input signal with a gain of gm1 and outputs it to the third node pair N3. Then, when the sampling period begins, the first switch pair SW1 turns ON, causing the differential voltage of the second node pair N2 to become 0V, and the differential voltage of the third node pair N3 changes from a large voltage value toward 0V. Here, if the differential amplifier circuit 100A is operating at high speed and the sampling period is short, it is necessary to increase the output current of the main differential amplifier A1 in order to charge and discharge the second capacitor pair C2. However, if sufficient output current cannot be supplied to the main differential amplifier A1, as shown in Figure 4, the differential voltage of the third node pair will not converge within the sampling period, and an abnormality will occur in the operation of the differential amplifier circuit 100A.

[0008] Patent Document 1 proposes a differential amplifier circuit 100B shown in Figure 5 to solve this problem. This differential amplifier 100B is configured in which a third switch SW3, which is a reset switch, is connected to the third node pair N3 of the differential amplifier 100A shown in Figure 3.

[0009] Figure 6 is a time chart showing an example of the operation of the differential amplifier circuit 100B. As shown in Figure 6, in the differential amplifier circuit 100B, at the start of the sampling period, the third switch SW3 is turned ON for a period shorter than the sampling period, forcing the differential voltage between the third node and N3 to 0V. This operation is expected to improve the convergence of the differential voltage between the third node and N3. [Prior art documents] [Patent Documents]

[0010] [Patent Document 1] Japanese Patent Publication No. 2009-21667 [Overview of the Initiative] [Problems that the invention aims to solve]

[0011] However, in the differential amplifier circuit 100B shown in Figure 5, the main differential amplifier A1 has an output offset voltage Vofs. Therefore, after the third switch SW3 switches from ON to OFF, the differential voltage between the third node and N3 changes from 0V towards the output offset voltage Vofs, as shown in Figure 7. However, as shown in Figure 7, if the sampling period ends before the differential voltage between the third node and N3 converges to the output offset voltage Vofs, a residual voltage is generated, which is the difference between the differential voltage between the third node and N3 at that point and the output offset voltage Vofs. This residual voltage causes an error in the charging voltage of the second capacitor pair C2. This is the sampling error.

[0012] This invention has been made in view of the circumstances described above, and aims to provide a differential amplifier circuit that is capable of high-speed operation and has reduced sampling error. [Means for solving the problem]

[0013] This invention provides a differential amplifier circuit with a sample-and-hold function, comprising: a main differential amplifier that differentially amplifies a differential input signal; a reset switch connected between the two differential output terminals of the main differential amplifier; a pair of switches, each with one end connected to the two differential output terminals of the main differential amplifier; and an auxiliary differential amplifier, the auxiliary differential amplifier having two differential output terminals connected to the two differential output terminals of the main differential amplifier, and two differential input terminals connected to the two differential output terminals of the main differential amplifier via the pair of switches, which, when the pair of switches is turned ON, negatively feeds back the differential voltage between the two differential output terminals of the main differential amplifier to those two differential output terminals.

[0014] According to this invention, when the switch pair is turned ON, the differential voltage between the two differential output terminals of the main differential amplifier is negatively fed back to the two differential output terminals, thereby correcting the output offset voltage of the main differential amplifier. Specifically, when the gain of the auxiliary differential amplifier is gm2, the output offset voltage of the main differential amplifier is corrected to 1 / gm2. Therefore, after being reset by the reset switch, the differential voltage between the two differential output terminals of the main differential amplifier converges toward the output offset voltage corrected to 1 / gm2, and convergence is completed early. Thus, according to this invention, sampling errors can be reduced when the differential amplifier circuit is operating at high speed. [Brief explanation of the drawing]

[0015] [Figure 1] This is a circuit diagram showing the configuration of a differential amplifier circuit, which is one embodiment of this invention. [Figure 2] This is a time chart showing the operation of the differential amplifier circuit. [Figure 3] This is a circuit diagram showing an example of a conventional differential amplifier circuit configuration. [Figure 4] This is a time chart showing an example of the operation of the differential amplifier circuit. [Figure 5] This is a circuit diagram showing another example of a conventional differential amplifier circuit configuration. [Figure 6] This is a time chart showing an example of the operation of the differential amplifier circuit. [Figure 7] This is a timing chart showing other operating examples of the differential amplifier circuit. [Modes for carrying out the invention]

[0016] The embodiments of this invention will be described below with reference to the drawings.

[0017] FIG. 1 is a circuit diagram showing the configuration of a differential amplifier circuit 100 according to an embodiment of the present invention. This differential amplifier circuit 100 has a configuration in which a fourth switch pair SW4, an auxiliary differential amplifier A2, and a fourth capacitor C4 are added to the differential amplifier circuit 100B in FIG. 5. Here, one end of each switch of the fourth switch pair SW4 is connected to the third node pair N3, and it is ON during the sampling period and OFF during the hold period. The auxiliary differential amplifier A2 has two differential output terminals connected to the third node pair N3, and two differential input terminals connected to the third node pair SW3 via the fourth switch pair SW4. When the fourth switch pair SW4 is turned ON, this auxiliary differential amplifier A2 negatively feeds back the differential voltage of the third node pair N3 to the third node pair N3 to correct the output offset voltage Vofs of the main differential amplifier A1 generated in the third node pair N3. Specifically, when the gain of the auxiliary differential amplifier A2 is gm2, the output offset voltage Vofs is corrected to the output offset voltage Vofsa of 1 / gm2 thereof. The fourth capacitor C4 is connected between the two differential input terminals of the auxiliary differential amplifier A). This fourth capacitor C4 serves to hold the differential voltage generated in the third node pair N3 immediately before the transition from the sampling period to the hold period, that is, the corrected output offset voltage Vofsa, during the hold period.

[0018] FIG. 2 is a time chart showing an operation example of the differential amplifier circuit 100. At the start of the sampling period, when the third switch SW3, which is a reset switch, is turned ON for a period shorter than the sampling period, the differential voltage of the third node pair N3 is forcibly reset to 0V.

[0019] On the other hand, during the sampling period, the fourth switch pair SW4 is turned ON, and the differential voltage generated in the third node pair N3 is negatively fed back to the third node pair N3 via the auxiliary differential amplifier A2.

[0020] When the third switch SW3 is turned off, the differential voltage of the third node pair N3 changes from 0V towards the output offset voltage of the main differential amplifier A1. At this time, since the differential voltage generated in the third node pair N3 is negatively feedback to the third node pair N3 via the auxiliary differential amplifier A2, the output offset voltage Vofs of the main differential amplifier A1 is corrected to the output offset voltage Vofsa of 1 / gm2 thereof. Therefore, the differential voltage of the third node pair N3 attempts to converge to the output offset voltage Vofsa after this correction.

[0021] Here, the output offset voltage Vofsa after correction is smaller than the output offset voltage Vofs before correction. Therefore, even when the differential amplifier circuit 100 operates at high speed and the sampling period is short, the differential voltage of the third node pair N3 converges to the output offset voltage Vofsa after correction within the sampling period. Then, each voltage of the third node pair N3 with the output offset voltage Vofsa after this correction as the differential voltage is held by the second capacitor pair C2.

[0022] During the hold period, the main differential amplifier A1 differentially amplifies the differential input signal supplied via the first capacitor pair C1 and outputs it to the third node pair N3. At this time, the auxiliary amplifier A2 applies negative feedback based on the differential voltage held by the fourth capacitor C4, that is, the output offset voltage Vofsa after correction, to the two differential output terminals of the main differential amplifier A1. Therefore, the output offset voltage of the main differential amplifier A1 becomes the output offset voltage Vofsa after correction. Then, during the hold period, the output signals of the two differential output terminals of the main differential amplifier A1 are output via the second capacitor pair C2 that holds the output offset voltage Vofsa after correction as the differential voltage. Therefore, a differential output signal with the output offset voltage removed can be obtained.

[0023] As described above, according to this embodiment, a main differential amplifier A1 that differentially amplifies a differential input signal, a switch pair SW4 connected to the two differential output terminals of the main differential amplifier A1, and an auxiliary differential amplifier A2 whose two differential output terminals are connected to the two differential output terminals of the main differential amplifier A1, and whose two differential input terminals are connected to the two differential output terminals of the main differential amplifier A1 via a switch pair SW3, and which, when the switch pair SW3 is turned ON, negatively feeds back the differential voltage between the two differential output terminals of the main differential amplifier A1 to those two differential output terminals. As a result, a differential amplifier circuit that enables high-speed operation and reduces sampling error can be realized.

[0024] Furthermore, according to this embodiment, since it is not necessary to increase the current flowing through the main differential amplifier in order to achieve high-speed operation, it is possible to realize a differential amplifier circuit that can operate at high speed without increasing power consumption and has reduced sampling error. [Explanation of Symbols]

[0025] 100... Differential amplifier circuit, 1... Sample and hold section, 2... Output section, N1... First node pair, N2... Second node pair, SW1... First switch pair, VBIAS1... First reference power supply, A1... Main differential amplifier, N3... Third node pair, SW3... Third switch, SW4... Fourth switch, C4... Fourth capacitor, A2... Auxiliary differential amplifier, C2... Second capacitor pair, N4... Fourth node pair, SW2... Second switch pair, VBIAS2... Second reference power supply.

Claims

1. In a differential amplifier circuit with a sample-and-hold function, A main differential amplifier that differentially amplifies differential input signals, A reset switch connected between the two differential output terminals of the main differential amplifier, A pair of switches, each having one end connected to the two differential output terminals of the main differential amplifier, An auxiliary differential amplifier is provided, in which two differential output terminals are connected to the two differential output terminals of the main differential amplifier, and two differential input terminals are connected to the two differential output terminals of the main differential amplifier via the switch pair, and when the switch pair is turned ON, the differential voltage between the two differential output terminals of the main differential amplifier is negatively fed back to the two differential output terminals. A differential amplifier circuit having the following characteristics.

2. The differential amplifier circuit according to claim 1, wherein a capacitor is connected between the two differential input terminals of the auxiliary differential amplifier.

3. Main differential amplifier and A sample-and-hold unit having a first pair of capacitors connected between a first pair of nodes and a second pair of nodes connected to the two differential input terminals of the main differential amplifier, and a first pair of switches connected between the first pair of nodes and a first reference power supply, which are ON during the sampling period and OFF during the hold period, An output section having a third node pair connected to the two differential output terminals of the main differential amplifier, a second capacitor pair connected between the third node pair and the fourth node pair, and a second switch pair connected between the fourth node pair and the second reference power supply, which is ON during the sampling period and OFF during the hold period. A third switch connected between each node of the third node pair, which is turned ON for a period shorter than the sampling period at the start of the sampling period, A fourth pair of switches, each having one end connected to the third pair of nodes, which are ON during the sampling period and OFF during the hold period, An auxiliary differential amplifier having two differential output terminals connected to the third node pair, and two differential input terminals connected to the third node pair via the fourth switch pair, wherein when the fourth switch pair is turned ON, the differential voltage of the third node pair is negatively fed back to the third node pair; A fourth capacitor connected between the two differential input terminals of the auxiliary differential amplifier, A differential amplifier circuit having the following characteristics.

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