Method for manufacturing a semiconductor device having a diode

Abstract

To easily form a diode having a crystal defect in a cathode layer.SOLUTION: A manufacturing method for a semiconductor device includes a cathode layer forming step, and a laser irradiating step of irradiating a second surface of a semiconductor substrate with laser after the cathode layer forming step. In the cathode layer forming step, a first cathode layer of n type distributing in a range including the second surface, and a second cathode layer of n type in contact with the first cathode layer from a first surface side and having lower n-type impurity concentration than the first cathode layer are formed. In the laser irradiating step, a heating range of 950°C or more is formed in a surface layer part of the semiconductor substrate near the second surface. In the laser irradiating step, a border between the first cathode layer and the second cathode layer exists in the heating range, and an end part of the second cathode layer on the first surface side exists on the first surface side relative to the heating range.SELECTED DRAWING: Figure 7

Description

Technical Field

[0001] The technology disclosed in this specification relates to a method for manufacturing a semiconductor device having a diode.

[0002] Patent Document 1 discloses a method for manufacturing a semiconductor device having an insulated gate bipolar transistor (hereinafter sometimes referred to as IGBT) and a diode. In this manufacturing method, an n-type cathode layer is formed by ion implantation of n-type impurities. Next, by irradiating the semiconductor substrate with helium ions, crystal defects are formed at high density in the cathode layer. By forming crystal defects in the cathode layer, snapback can be suppressed when the IGBT is turned on.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] It has been found that when crystal defects are formed in the cathode layer of a diode, the recovery current of the diode can be rapidly attenuated. This effect can be obtained not only in a semiconductor device having an IGBT and a diode, but also in a semiconductor device of a single diode. When forming crystal defects in the cathode layer by irradiation with helium ions as in Patent Document 1, dedicated equipment for irradiating helium ions is required, resulting in high manufacturing costs. In this specification, a technique for easily forming a diode having crystal defects in the cathode layer is proposed.

Means for Solving the Problems

[0005] A semiconductor device manufacturing method disclosed herein is provided for manufacturing a semiconductor device having a diode having a p-type anode layer (42), an n-type cathode layer (48), and a drift layer (44) disposed between the anode layer and the cathode layer. This manufacturing method comprises a semiconductor substrate preparation step, an anode layer formation step, a cathode layer formation step, and a laser irradiation step. In the semiconductor substrate preparation step, a semiconductor substrate is prepared which is made of silicon and has a first surface (12a) and a second surface (12b) located on the opposite side of the first surface, and which has the drift layer. In the anode layer formation step, the anode layer is formed in the semiconductor substrate in a region including the first surface. In the cathode layer formation step, the cathode layer is formed in the semiconductor substrate in a region including the second surface by injecting n-type impurities into the second surface. In the laser irradiation step, after the cathode layer formation step is performed, the second surface is irradiated with a laser (92). In the cathode layer formation step, a cathode layer is formed having an n-type first cathode layer (48a) distributed in a range including the second surface, and an n-type second cathode layer (48b) that is in contact with the first cathode layer from the first surface side and has a lower n-type impurity concentration than the first cathode layer. In the laser irradiation step, a heating range (94) of 950°C or higher is formed in the surface layer of the semiconductor substrate near the second surface. In the laser irradiation step, the boundary between the first cathode layer and the second cathode layer is located within the heating range, and the end of the second cathode layer on the first surface side is located on the first surface side of the heating range.

[0006] The anode layer may be formed by either ion implantation or epitaxial growth. Furthermore, the anode layer formation process and the cathode layer formation process may be performed in either order. Also, in the cathode layer formation process, the first cathode layer and the second cathode layer may be formed in either order.

[0007] In this manufacturing method, when n-type impurities are injected into the first and second cathode layers, high-density crystal defects are formed inside the first and second cathode layers. Subsequently, a laser is irradiated onto the second surface during the laser irradiation process. During the laser irradiation process, a heating range of 950°C or higher is formed. Within this heating range, the silicon is exposed to temperatures of 950°C or higher, which activates the impurities and eliminates the crystal defects. Since the boundary between the first and second cathode layers is located within this heating range (i.e., the entire first cathode layer is included within this heating range), the entire first cathode layer is activated, and most of the crystal defects within the first cathode layer are eliminated. In this way, a first cathode layer with high crystallinity and a high concentration of n-type impurities is formed, enabling the realization of high on-characteristics for the diode. Furthermore, since the edge of the second cathode layer on the first surface side is located on the first surface side of the heating range (i.e., outside the heating range), crystal defects are difficult to eliminate at the edge of the second cathode layer on the first surface side. Therefore, a large number of crystal defects remain in the second cathode layer. As a result, the recovery current can be attenuated quickly in this diode. As described above, this manufacturing method makes it possible to manufacture a diode having crystal defects in the cathode layer. Moreover, in this manufacturing method, a cathode layer having crystal defects can be formed by the general process of injecting n-type impurities into the cathode layer and irradiating the second surface with a laser. Therefore, a diode having crystal defects in the cathode layer can be manufactured at low cost. [Brief explanation of the drawing]

[0008] [Figure 1] Cross-sectional view of semiconductor device 10. [Figure 2] Enlarged cross-sectional view of cathode layer 48. [Figure 3] Diagram illustrating the manufacturing method of the semiconductor device 10. [Figure 4] Diagram illustrating the manufacturing method of the semiconductor device 10. [Figure 5] Diagram illustrating the manufacturing method of the semiconductor device 10. [Figure 6] Diagram illustrating the manufacturing method of the semiconductor device 10. [Figure 7] Diagram illustrating the manufacturing method of the semiconductor device 10. [Figure 8] A graph showing recovery characteristics. [Modes for carrying out the invention]

[0009] In one embodiment disclosed herein, the process may further include a buffer layer formation step, prior to the laser irradiation step, in which an n-type buffer layer (46) is formed in the semiconductor substrate, which is in contact with the second cathode layer from the first surface side and has lower levels of n-type impurities than the second cathode layer.

[0010] In one embodiment disclosed herein, the semiconductor device may include an insulated-gate bipolar transistor adjacent to the diode. The insulated-gate bipolar transistor may have a p-type collector layer (30) located in the semiconductor substrate including the second surface and adjacent to the cathode layer. In the buffer layer formation step, the buffer layer may be formed such that it is distributed across the range of the insulated-gate bipolar transistor and the range of the diode.

[0011] In one example of the embodiments disclosed herein, the laser may be a green laser.

[0012] This configuration allows for the retention of high-density crystal defects within the cathode layer, even when the cathode layer is thin.

[0013] The semiconductor device 10 in the embodiment shown in Figure 1 has a semiconductor substrate 12, an upper electrode 14, and a lower electrode 16. The semiconductor substrate 12 is made of silicon. The upper electrode 14 is provided on the upper surface 12a of the semiconductor substrate 12. The lower electrode 16 is provided on the lower surface 12b of the semiconductor substrate 12.

[0014] The semiconductor substrate 12 has an IGBT region 20 where vertical IGBTs are provided and a diode region 40 where vertical diodes are provided. The upper electrode 14 serves as both the emitter electrode of the IGBT and the anode electrode of the diode. The lower electrode 16 serves as both the collector electrode of the IGBT and the cathode electrode of the diode.

[0015] A drift layer 44 is provided in the central portion of the semiconductor substrate 12 in the thickness direction. The drift layer 44 is a low-concentration n-type layer. The drift layer 44 extends across the IGBT region 20 and the diode region 40.

[0016] A buffer layer 46 is provided below the drift layer 44. The buffer layer 46 is an n-type layer having an n-type impurity concentration higher than that of the drift layer 44. The buffer layer 46 extends across the IGBT region 20 and the diode region 40. The buffer layer 46 contacts the drift layer 44 from below in the IGBT region 20 and the diode region 40.

[0017] An emitter layer 22, a body layer 24, and a collector layer 30 are provided in the semiconductor substrate 12 within the IGBT region 20.

[0018] The emitter layer 22 is a high-concentration n-type layer and is disposed in a range exposed to the upper surface 12a of the semiconductor substrate 12. The emitter layer 22 is ohmically connected to the upper electrode 14.

[0019] The body layer 24 is a p-type layer and is in contact with the emitter layer 22. The body layer 24 is disposed in a range exposed to the upper surface 12a of the semiconductor substrate 12. The body layer 24 extends from the side of the emitter layer 22 to the lower side of the emitter layer 22. The body layer 24 has a body contact layer 24a and a low-concentration body layer 24b. The body contact layer 24a has a high p-type impurity concentration. The body contact layer 24a is disposed in a range exposed to the upper surface 12a of the semiconductor substrate 12 and is ohmically connected to the upper electrode 14. The low-concentration body layer 24b has a lower p-type impurity concentration than the body contact layer 24a. The low-concentration body layer 24b is disposed below the emitter layer 22 and the body contact layer 24a. The low-concentration body layer 24b is in contact with the drift layer 44 from above.

[0020] The collector layer 30 is a high-concentration p-type layer and is disposed below the buffer layer 46. The collector layer 30 is in contact with the buffer layer 46 from below. The collector layer 30 is separated from the body layer 24 by the drift layer 44 and the buffer layer 46. The collector layer 30 is disposed in a range exposed to the lower surface 12b of the semiconductor substrate 12. The collector layer 30 is ohmically connected to the lower electrode 16.

[0021] A plurality of trenches are provided on the upper surface 12a of the semiconductor substrate 12 within the IGBT region 20. Each trench is disposed at a position adjacent to the emitter layer 22. Each trench extends to a depth reaching the drift layer 44. The inner surface of each trench within the IGBT region 20 is covered by a gate insulating film 32. Also, a gate electrode 34 is disposed within each trench. Each gate electrode 34 is insulated from the semiconductor substrate 12 by the gate insulating film 32. Each gate electrode 34 faces the emitter layer 22, the low-concentration body layer 24b, and the drift layer 44 through the gate insulating film 32. An interlayer insulating film 36 is provided above each gate electrode 34. Each gate electrode 34 is insulated from the upper electrode 14 by the interlayer insulating film 36.

[0022] An anode layer 42 and a cathode layer 48 are provided within the semiconductor substrate 12 in the diode region 40.

[0023] The anode layer 42 is located in an area exposed to the upper surface 12a of the semiconductor substrate 12. The anode layer 42 has an anode contact layer 42a and a low-concentration anode layer 42b. The anode contact layer 42a has a high p-type impurity concentration. The anode contact layer 42a is located in an area exposed to the upper surface 12a of the semiconductor substrate 12 and is ohmic connected to the upper electrode 14. The low-concentration anode layer 42b has a lower p-type impurity concentration than the anode contact layer 42a. The low-concentration anode layer 42b is distributed to the sides and below the anode contact layer 42a. The low-concentration anode layer 42b is in contact with the drift layer 44 from above.

[0024] The cathode layer 48 is an n-type layer having a higher n-type impurity concentration than the buffer layer 46. The cathode layer 48 is located below the buffer layer 46. The cathode layer 48 is in contact with the buffer layer 46 from below. The cathode layer 48 is located in a region exposed to the lower surface 12b of the semiconductor substrate 12. The cathode layer 48 is ohmic-connected to the lower electrode 16.

[0025] Multiple trenches are provided on the upper surface 12a of the semiconductor substrate 12 within the diode region 40. Each trench extends to a depth that reaches the drift layer 44. The inner surface of each trench within the diode region 40 is covered with an insulating film 52. A control electrode 54 is also placed within each trench. Each control electrode 54 is insulated from the semiconductor substrate 12 by the insulating film 52. Each control electrode 54 faces the anode layer 42 and the drift layer 44 via the insulating film 52. An interlayer insulating film 56 is placed above each control electrode 54. Each control electrode 54 is insulated from the upper electrode 14 by the interlayer insulating film 56. Each control electrode 54 may be electrically connected to the gate electrode 34, or it may have a potential different from that of the gate electrode 34.

[0026] Figure 2 is an enlarged cross-sectional view of the cathode layer 48. The cathode layer 48 has a first cathode layer 48a and a second cathode layer 48b. The second cathode layer 48b has a higher n-type impurity concentration than the buffer layer 46. The first cathode layer 48a has a higher n-type impurity concentration than the second cathode layer 48b. The first cathode layer 48a is located in a region exposed to the lower surface 12b of the semiconductor substrate 12. The first cathode layer 48a is ohmic connected to the lower electrode 16. The second cathode layer 48b is located between the first cathode layer 48a and the buffer layer 46. The second cathode layer 48b is in contact with the first cathode layer 48a from above and with the buffer layer 46 from below. The collector layer 30 is adjacent to the cathode layer 48 on the lower surface 12b of the semiconductor substrate 12.

[0027] Within the second cathode layer 48b, there is a high-density defect region 50 with a higher crystal defect density than the surrounding area. Crystal defects act as carrier recombination centers. Therefore, the carrier lifetime is shorter within the high-density defect region 50.

[0028] Next, the manufacturing method of the semiconductor device 10 will be described. The semiconductor device 10 is manufactured from the semiconductor substrate 12 before processing shown in Figure 3. The entire semiconductor substrate 12 before processing is composed of a drift layer 44.

[0029] First, an anode layer formation process is carried out. In the anode layer formation process, as shown in Figure 4, an anode layer 42 is formed on the semiconductor substrate 12 by ion implantation or epitaxial growth. Here, a body layer 24 is formed simultaneously with the anode layer 42. Next, as shown in Figure 4, an emitter layer 22 is formed. Then, as shown in Figure 5, a trench, gate insulating film 32, gate electrode 34, interlayer insulating film 36, insulating film 52, control electrode 54, interlayer insulating film 56, and upper electrode 14 are formed on the semiconductor substrate 12.

[0030] Next, a buffer layer formation process is carried out. In the buffer layer formation process, as shown in Figure 5, a buffer layer 46 is formed that extends across the IGBT region 20 and the diode region 40. Here, the buffer layer 46 is formed by ion implanting n-type impurities into the lower surface 12b of the semiconductor substrate 12. After the buffer layer 46 is formed, the n-type impurities in the buffer layer 46 are activated by annealing the buffer layer 46.

[0031] Next, as shown in Figure 5, a collector layer 30 is formed on the semiconductor substrate 12. Here, the collector layer 30 is formed by ion implanting p-type impurities into the lower surface 12b within the IGBT region 20. After the collector layer 30 is formed, the p-type impurities within the collector layer 30 are activated by annealing the collector layer 30.

[0032] Next, as shown in Figure 6, a cathode layer 48 is formed by injecting n-type impurities into the lower surface 12b within the diode region 40. That is, a first cathode layer 48a and a second cathode layer 48b are formed. In the first cathode layer formation step, n-type impurities are injected into the lower surface 12b with low energy and a high dose. Therefore, a first cathode layer 48a with a high n-type impurity concentration is formed in the surface layer including the lower surface 12b. In the second cathode layer formation step, n-type impurities are injected into the lower surface 12b with higher energy than in the first cathode layer formation step and with a lower dose than in the first cathode layer formation step. For example, the dose for the first cathode layer 48a is 7 × 10⁻⁶. 14 cm -2 The dose amount for the second cathode layer 48b is 6 × 10⁻⁶. 13 cm -2This can be done. Therefore, a second cathode layer 48b having a lower n-type impurity concentration than the first cathode layer 48a is formed above the first cathode layer 48a. The second cathode layer 48b is formed to have a higher n-type impurity concentration than the buffer layer 46. The first cathode layer formation step and the second cathode layer formation step may be performed in any order. Hereinafter, the thickness of the first cathode layer 48a (i.e., the distance from the bottom surface 12b to the top surface of the first cathode layer 48a) will be referred to as thickness A. Also below, the total thickness of the cathode layer 48 (i.e., the combined thickness of the first cathode layer 48a and the second cathode layer 48b) will be referred to as thickness B. Thickness B can also be said to be the distance from the bottom surface 12b to the top surface of the second cathode layer 48b. For example, thickness A can be 0.2 μm and thickness B can be 1.0 μm. Furthermore, the hatched areas in Figure 6 indicate high-density defect regions 50. In the ion implantation process, crystal defects are formed at high density in the areas where ions are implanted. Therefore, immediately after the first cathode layer formation process and the second cathode layer formation process, high-density defect regions 50 are distributed throughout the entire first cathode layer 48a and the second cathode layer 48b. Note that in the second cathode layer formation process, n-type impurities are ion-implanted at a lower density than in the first cathode layer process, so crystal defects are formed in the second cathode layer 48b at a lower density than in the first cathode layer 48a. That is, the crystal defect density in the high-density defect region 50 in the second cathode layer 48b is lower than the crystal defect density in the high-density defect region 50 in the first cathode layer 48a.

[0033] Next, a laser irradiation process is performed. In the laser irradiation process, as shown in FIG. 7, a green laser 92 is irradiated onto the lower surface 12b. Here, by moving the spot of the green laser 92, the entire lower surface 12b within the diode region 40 is irradiated with the green laser 92. In the laser irradiation process, the entire lower surface 12b including the diode region 40 and the IGBT region 20 may be irradiated with the green laser 92. When the lower surface 12b is irradiated with the green laser 92, the surface layer portion near the lower surface 12b of the semiconductor substrate 12 is heated to a temperature of 950° C. or higher. Hereinafter, the range heated to a temperature of 950° C. or higher by the irradiation of the green laser 92 is referred to as a heating range 94. Further, hereinafter, the depth of the heating range 94 is referred to as a depth D. Since the wavelength of the green laser 92 is short, in the laser irradiation process, only a very shallow range near the lower surface 12b is heated. For example, when the wavelength of the green laser 92 is 532 nm, the depth D of the heating range 94 can be controlled to be 50 to 230 nm. Also, when using a laser with a shorter wavelength, the depth D of the heating range 94 can be made smaller. Here, the depth D is controlled so that the thicknesses A, B, and the depth D satisfy the relationship A < D < B.

[0034] When silicon is heated to 950 °C or higher, impurities inside the silicon are activated. Also, when silicon is heated to 950 °C or higher, crystal defects inside the silicon disappear, reducing the crystal defect density. Therefore, in the laser irradiation process, within the heating range 94, n-type impurities are activated and the high-density defect region 50 disappears. Since A < D is satisfied, the boundary surface between the first cathode layer 48a and the second cathode layer 48b is located within the heating range 94. Therefore, the entire first cathode layer 48a is included within the heating range 94. That is, throughout the entire first cathode layer 48a, n-type impurities are activated and the high-density defect region 50 disappears. Also, since D < B is satisfied, the upper end portion of the second cathode layer 48b (that is, the boundary surface between the second cathode layer 48b and the buffer layer 46) is located above the heating range 94. Therefore, the lower portion of the second cathode layer 48b is included within the heating range 94 while the upper portion of the second cathode layer 48b is not included within the heating range 94. Therefore, the high-density defect region 50 disappears in the lower portion of the second cathode layer 48b and remains in the upper portion of the second cathode layer 48b. In this embodiment, since the depth D is slightly larger than the thickness A, the high-density defect region 50 remains in a region that is more than half of the thickness of the second cathode layer 48b.

[0035] Next, as shown in FIG. 1, a lower electrode 16 is formed over the entire lower surface 12b. The collector layer 30 and the first cathode layer 48a are ohmically connected to the lower electrode 16. Through the above steps, the semiconductor device 10 is completed.

[0036] Next, the operation of the diode within the diode region 40 will be described. When a higher potential is applied to the upper electrode 14 than to the lower electrode 16, a forward voltage is applied to the pn junction at the interface between the anode layer 42 and the drift layer 44. As a result, electrons flow from the lower electrode 16 into the drift layer 44 via the cathode layer 48 and the buffer layer 46. Simultaneously, holes flow from the anode layer 42 into the drift layer 44, reducing the resistance of the drift layer 44. Therefore, electrons can pass through the drift layer 44 with low loss. Electrons that have passed through the drift layer 44 flow to the upper electrode 14 via the anode layer 42. This flow of electrons from the lower electrode 16 to the upper electrode 14 turns on the diode. As described above, the n-type impurity concentration of the first cathode layer 48a is high, and the crystallinity of the first cathode layer 48a is high. Therefore, the contact resistance of the first cathode layer 48a to the lower electrode 16 is low. Therefore, the losses that occur when the diode is on (so-called steady-state losses) are small.

[0037] As described above, when the diode is ON, holes flow from the anode layer 42 to the drift layer 44. The holes that flow into the drift layer 44 flow to the lower electrode 16 via the buffer layer 46 and the cathode layer 48. Therefore, when the diode is ON, holes exist in the drift layer 44, the buffer layer 46, and the cathode layer 48. Subsequently, when the potential of the lower electrode 16 is raised to a potential higher than the potential of the upper electrode 14, the diode enters a recovery state, and the holes present in the drift layer 44, the buffer layer 46, and the cathode layer 48 are discharged to the upper electrode 14. As a result, a reverse current (so-called recovery current) temporarily flows through the diode.

[0038] Figure 8 shows a comparison of the recovery characteristics of the diode in the embodiment and the diode in the comparative example. The diode in the comparative example differs from the diode in the embodiment in that it does not have a high-density defect region 50. In Figure 8, the voltage Vak is the anode-cathode voltage of the diode, with the higher cathode voltage indicated as positive. The voltage Vak is common to both the embodiment and the comparative example. In Figure 8, the current I FThe value indicates the current flowing through the diode. A positive value indicates current flowing in the forward direction, and a negative value indicates current flowing in the reverse direction.

[0039] In Figure 8, current I F The recovery state is when the value is negative. In the recovery state, holes present in the drift layer 44, buffer layer 46, and cathode layer 48 are more easily discharged to the upper electrode 14 the closer they are to the anode layer 42. Therefore, it takes time for holes present in the cathode layer 48 to be discharged to the upper electrode 14. In the comparative example diode, the recovery current flows until the holes present in the cathode layer 48 are discharged to the upper electrode 14, so the recovery current does not decay easily. In contrast, in the embodiment diode, the crystal defects in the high-density defect region 50 function as recombination centers, so many holes in the second cathode layer 48b disappear by recombining with electrons. For this reason, the recovery current decays faster in the embodiment diode than in the comparative example diode. Therefore, recovery losses are less likely to occur in the embodiment diode.

[0040] As described above, the manufacturing method of this embodiment makes it possible to form a first cathode layer 48a with a high n-type impurity concentration and high crystallinity, as well as a second cathode layer 48b having a high-density defect region 50. Therefore, the steady-state loss and recovery loss of the diode can be reduced.

[0041] Furthermore, in the manufacturing method of this embodiment, n-type impurities are injected into the second cathode layer 48b at a lower density than in the first cathode layer 48a, so the crystal defect density in the second cathode layer 48b can be controlled independently of the n-type impurity concentration in the first cathode layer 48a. This prevents the crystal defect density in the second cathode layer 48b from becoming excessively high, and prevents the steady-state loss of the diode from becoming high.

[0042] Furthermore, in the manufacturing method of this embodiment, since the first cathode layer 48a is annealed with a short-wavelength green laser, it is possible to create a first cathode layer 48a in which high-density defect regions 50 do not exist and a second cathode layer 48b in which high-density defect regions 50 exist within the thin cathode layer 48.

[0043] Furthermore, in the manufacturing method of this embodiment, a first cathode layer 48a without high-density defect regions 50 and a second cathode layer 48b with high-density defect regions 50 can be formed by general processes of ion implantation of n-type impurities and laser irradiation. Since special processes such as helium irradiation are not required, semiconductor devices can be manufactured at low cost.

[0044] In the embodiment described above, a green laser was used in the laser irradiation process, but a laser with a shorter wavelength than a green laser or a laser with a longer wavelength than a green laser may be used instead. However, when the thickness of the cathode layer 48 is thin, using a green laser or a laser with a shorter wavelength than a green laser makes it easier to leave high-density defect regions 50 within the cathode layer 48.

[0045] Furthermore, although the embodiments described above describe a method for manufacturing a semiconductor device having a diode and an IGBT, the techniques disclosed herein may also be applied when manufacturing a semiconductor device having a diode alone, or a semiconductor device having elements other than a diode and an IGBT. In addition, a trench, an insulating film 52, a control electrode 54, and an interlayer insulating film 56 are not required to be provided within the diode region.

[0046] In the above embodiment, the upper surface 12a is an example of a first surface, and the lower surface 12b is an example of a second surface.

[0047] Although embodiments have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various modifications and changes to the specific examples illustrated above. The technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technologies illustrated in this specification or drawings achieve multiple objectives simultaneously, and achieving even one of these objectives constitutes technical usefulness. [Explanation of Symbols]

[0048] 10: Semiconductor device, 12: Semiconductor substrate, 40: Diode region, 42: Anode layer, 44: Drift layer, 46: Buffer layer, 48: Cathode layer, 48a: First cathode layer, 48b: Second cathode layer, 50: High-density defect region, 92: Green laser, 94: Heating area

Claims

1. A method for manufacturing a semiconductor device having a semiconductor substrate made of silicon and having a first surface (12a) and a second surface (12b) located on the opposite side of the first surface, The semiconductor substrate has a diode and an insulated gate bipolar transistor provided next to the diode. The diode has a p-type anode layer (42) arranged in a region including the first surface and an n-type cathode layer (48) arranged in a region including the second surface. The insulated gate bipolar transistor has a p-type collector layer (30) that is arranged in a region including the second surface and adjacent to the cathode layer. The aforementioned semiconductor device is The insulated gate bipolar transistor and the diode are distributed across the range of the diode, and within the diode, a drift layer (44) is located between the anode layer and the cathode layer, An n-type buffer layer (46) is distributed across the range of the insulated gate bipolar transistor and the range of the diode, is in contact with the cathode layer and the collector layer from the first surface side, and has n-type impurities that are lower than the cathode layer and higher than the drift layer, It has, The aforementioned manufacturing method is A step of preparing the semiconductor substrate having the drift layer, The anode layer formation step for forming the anode layer, A cathode layer formation step, in which the cathode layer is formed by injecting n-type impurities into the second surface, A buffer layer formation step for forming the buffer layer, After the cathode layer formation step and the buffer layer formation step are carried out, a laser irradiation step is performed in which a laser (92) is irradiated onto the second surface. It has, In the cathode layer formation step, the cathode layer is formed having an n-type first cathode layer (48a) distributed in a range including the second surface, and an n-type second cathode layer (48b) that is in contact with the first cathode layer from the first surface side and has a lower n-type impurity concentration than the first cathode layer. In the laser irradiation step, a heating range (94) of 950°C or higher is formed in the surface layer of the semiconductor substrate near the second surface. In the laser irradiation step, the boundary between the first cathode layer and the second cathode layer is located within the heating range, and the end of the second cathode layer on the first surface side is located on the first surface side of the heating range. Within the second cathode layer, the density of crystal defects is higher in the upper part of the second cathode layer than in the lower part of the second cathode layer. Manufacturing method.

2. The manufacturing method according to claim 1, wherein the laser is a green laser.

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