Manufacturing method of switching elements

Abstract

To provide a technique for manufacturing a switching element having a bottom part injection region, capable of suppressing an impurity implantation to a channel region as well as enabling a refining of the switching element.SOLUTION: A manufacturing method of a switching element, includes: a step of forming a trench (14) of which a thickness of a depth is a thickness of a first n type region onto a front surface of a semiconductor substrate within a range where the first n type region is exposed; a step of forming an impurity implantation region (38) into a second n type region by implanting p type or n type impurity to a bottom surface of the trench; and a step of increasing the depth of the trench so that the impurity implantation region is exposed to the bottom surface of the trench by etching the bottom surface of the trench.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The technology disclosed in this specification relates to a method for manufacturing a switching element.

[0002] Patent Document 1 discloses a method for manufacturing a switching element having a trench gate structure. In this manufacturing method, a semiconductor substrate having an n-type source region and a p-type body region is prepared. In this manufacturing method, a trench is formed on the surface of the semiconductor substrate that penetrates the source region and reaches the body region. Next, a sidewall insulating film covering the side surface of the trench is formed. Next, impurities are implanted into the bottom surface of the trench to form a bottom implantation region around the bottom surface of the trench. Next, the sidewall insulating film is removed, and a gate insulating film and a gate electrode are formed in the trench. In a switching element having a trench gate structure, the range of the body region among the side surfaces of the trench is a region where a channel is formed during the operation of the switching element (hereinafter referred to as the channel region). In the manufacturing method of Patent Document 1, in the implantation process for the bottom implantation region, the implantation of impurities into the channel region is suppressed by the sidewall insulating film. Therefore, according to the manufacturing method of Patent Document 1, variations in the characteristics of the switching element can be suppressed. Note that in Patent Document 1, n-type impurities are implanted into the bottom implantation region, but p-type impurities may also be implanted into the bottom implantation region. Even in this case, by suppressing the implantation of impurities into the channel region, variations in the characteristics of the switching element can be suppressed.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the technology described in Patent Document 1, the impurity injection range into the bottom surface of the trench is limited by the insulating film on the side walls. Therefore, in order to form a wide bottom injection region, it is necessary to form a wide trench in advance. Consequently, miniaturization of the switching element is difficult with this technology.

[0005] Another manufacturing method involves implanting impurities with high energy before forming trenches, creating a bottom implantation region at a deep location. After forming the bottom implantation region, trenches are formed on the surface of the semiconductor substrate, exposing the bottom implantation region at the bottom of the trenches. This manufacturing method also allows for the production of switching elements with bottom implantation regions around the bottom of the trenches. However, this method requires special ion implantation equipment to perform high-energy ion implantation. Furthermore, high-energy ion implantation has a low impurity rate per unit time, making the ion implantation process time-consuming. Consequently, this manufacturing method results in higher production costs for switching elements.

[0006] This specification proposes a technique for manufacturing a switching element having a bottom injection region, which enables miniaturization of the switching element and facilitates the suppression of impurity implantation into the channel region. [Means for solving the problem]

[0007] A method for manufacturing a switching element, comprising a semiconductor substrate preparation step, a trench formation step, an impurity implantation step, a trench depth increase step, a gate insulating film formation step, and a gate electrode formation step. In the semiconductor substrate preparation step, a semiconductor substrate is prepared having a first n-type region in the area exposed on the surface, a p-type body region below the first n-type region, and a second n-type region below the body region. In the trench formation step, a trench is formed on the surface within the area where the first n-type region is exposed, with a depth less than or equal to the thickness of the first n-type region. In the impurity implantation step, an impurity implantation region is formed in the second n-type region by implanting p-type or n-type impurities into the bottom surface of the trench. In the trench depth increase step, after forming the impurity implantation region, the depth of the trench is increased by etching the bottom surface of the trench so that the impurity implantation region is exposed on the bottom surface of the trench. In the gate insulating film formation step, after exposing the impurity implantation region on the bottom surface of the trench, a gate insulating film is formed to cover the inner surface of the trench. In the gate electrode formation step, the gate electrode is formed in the trench after the gate insulating film is formed.

[0008] In this manufacturing method, a trench with a depth less than or equal to the thickness of the first n-type region is formed, and then an impurity implantation region is formed within the second n-type region by injecting impurities into the bottom surface of the trench. Although the impurity implantation region is formed at a depth relative to the surface of the semiconductor substrate, because a trench is formed, the impurity implantation region can be formed with relatively low injection energy. Also, because the depth of the trench is less than or equal to the thickness of the first n-type region, the implantation of impurities into the channel region within the body region is suppressed. After the formation of the impurity implantation region, the depth of the trench is increased so that the impurity implantation region is exposed at the bottom surface of the trench. Then, by forming a gate insulating film and a gate electrode, a gate structure having an impurity implantation region at the bottom of the trench is completed. Thus, this manufacturing method can suppress the implantation of impurities into the channel region and suppress variations in the characteristics of the switching element. Also, this manufacturing method allows for the formation of an impurity implantation region with relatively low injection energy, making it easy to form a gate structure. Furthermore, this manufacturing method allows for the formation of an impurity implantation region even with a narrow trench width, enabling miniaturization of the switching element. [Brief explanation of the drawing]

[0009] [Figure 1] Cross-sectional view of the switching element 10. [Figure 2] Diagram illustrating the manufacturing method of the embodiment. [Figure 3] Diagram illustrating the manufacturing method of the embodiment. [Figure 4] Diagram illustrating the manufacturing method of the embodiment. [Figure 5] Diagram illustrating the manufacturing method of the embodiment. [Figure 6] Diagram illustrating the manufacturing method of the embodiment. [Figure 7] Diagram illustrating the manufacturing method of the embodiment. [Figure 8] Diagram illustrating the manufacturing method of the embodiment. [Figure 9] Diagram illustrating the manufacturing method for Comparative Example 1. [Figure 10] Diagram illustrating the manufacturing method for Comparative Example 2. [Modes for carrying out the invention]

[0010] The switching element 10 shown in Figure 1 is a MOSFET (metal oxide semiconductor field effect transistor). The switching element 10 has a semiconductor substrate 12 made of SiC (silicon carbide). The semiconductor substrate 12 may be made of other semiconductor materials such as silicon. Multiple trenches 14 are provided on the upper surface 12a of the semiconductor substrate 12. The inner surface of each trench 14 is covered with a gate insulating film 16. A gate electrode 18 is placed in each trench 14. Each gate electrode 18 is insulated from the semiconductor substrate 12 by the gate insulating film 16. An interlayer insulating film 20 and an upper electrode 22 are provided on the upper part of the semiconductor substrate 12. The interlayer insulating film 20 covers the upper surface of each gate electrode 18. The upper electrode 22 covers the upper surface 12a of the semiconductor substrate 12 and the interlayer insulating film 20. The upper electrode 22 is insulated from each gate electrode 18 by the interlayer insulating film 20. The upper electrode 22 is in contact with the upper surface 12a of the semiconductor substrate 12 at a location where the interlayer insulating film 20 is not present. A lower electrode 24 is provided at the bottom of the semiconductor substrate 12. The lower electrode 24 is in contact with the bottom surface 12b of the semiconductor substrate 12.

[0011] The semiconductor substrate 12 has a plurality of source regions 30, a plurality of contact regions 32, a body region 34, a drift region 36, a bottom region 38, a buffer region 39, and a drain region 40.

[0012] Each source region 30 is an n-type region with a high concentration of n-type impurities. A source region 30 is positioned in each of the regions sandwiched between the trenches 14 (hereinafter referred to as the inter-trench region). In each inter-trench region, the source region 30 is positioned to include the upper end and upper surface 12a of the side surface of the trench 14. Each source region 30 is in contact with the gate insulating film 16 on the side surface of the trench 14. Each source region 30 is in ohmic contact with the upper electrode 22.

[0013] Each contact region 32 is a p-type region with a high concentration of p-type impurities. A contact region 32 is located in each trench region. Each contact region 32 is positioned to include the upper surface 12a. Each contact region 32 is in ohmic contact with the upper electrode 22. Each contact region 32 is adjacent to the source region 30.

[0014] The body region 34 is a p-type region with a lower p-type impurity concentration than the contact region 32. The body region 34 is distributed across multiple inter-trench regions. The body region 34 is in contact with the source region 30 and the contact region 32 from below. The body region 34 is in contact with the gate insulating film 16 below the source region 30.

[0015] The drift region 36 is an n-type region with a lower n-type impurity concentration than the source region 30. The drift region 36 is distributed across the lower part of multiple inter-trench regions. The drift region 36 is in contact with the body region 34 from below. The drift region 36 is in contact with the gate insulating film 16 below the body region 34. The drift region 36 is separated from each source region 30 by the body region 34.

[0016] Each bottom region 38 is positioned to include the bottom surface of each trench 14. Each bottom region 38 is provided along the bottom surface of the corresponding trench 14. Each bottom region 38 is in contact with the gate insulating film 16 at the bottom surface of the corresponding trench 14. In the cross-section shown in Figure 1, each bottom region 38 is separated from the body region 34 by a drift region 36. Each bottom region 38 may be connected to the potential of the body region 34 or it may be floating. When each bottom region 38 is connected to the potential of the body region 34, each bottom region 38 is connected to the body region 34 at a position not shown. Each bottom region 38 is in contact with the drift region 36 on its sides and bottom surface.

[0017] The buffer region 39 is an n-type region with a higher n-type impurity concentration than the drift region 36. The buffer region 39 is in contact with the drift region 36 from below.

[0018] The drain region 40 is an n-type region having a higher n-type impurity concentration than the buffer region 39. The drain region 40 is in contact with the buffer region 39 from below. The drain region 40 is disposed at a position including the lower surface 12b. The drain region 40 makes an ohmic contact with the lower electrode 24.

[0019] When the switching element 10 is in use, a potential higher than that of the upper electrode 22 is applied to the lower electrode 24. When a potential equal to or higher than the gate threshold is applied to the gate electrode 18, a channel is formed in a portion of the body region 34 adjacent to the gate insulating film 16 (hereinafter referred to as the channel region). Through the channel, each source region 30 is connected to the drift region 36. For this reason, electrons flow from the source region 30 through the channel, the drift region 36, and the buffer region 39 to the drain region 40. That is, the switching element 10 is turned on. As described above, when the switching element 10 is turned on, electrons flow through the channel formed in the channel region. Therefore, the channel region greatly affects the characteristics of the switching element (particularly, channel resistance, gate threshold, etc.).

[0020] When the potential of the gate electrode 18 is lowered to a potential lower than the gate threshold, the channel disappears and the flow of electrons stops. That is, the switching element 10 is turned off. When the switching element 10 is turned off, depletion layers spread from the body region 34 and each bottom region 38 to the drift region 36. The depletion layers spreading from each bottom region 38 to the drift region 36 suppress the electric field concentration near the bottom surface of each trench 14. Therefore, the switching element 10 has a high breakdown voltage.

[0021] Next, a method for manufacturing the switching element 10 will be described. The switching element 10 is manufactured from a semiconductor substrate 12 entirely composed of a drift region 36 (that is, the semiconductor substrate 12 before processing).

[0022] First, epitaxial growth, ion implantation, etc., are performed on the semiconductor substrate 12 to form a source region 30, a contact region 32, and a body region 34, as shown in Figure 2. This results in a structure in which the source region 30 is provided in the area exposed on the upper surface 12a, the body region 34 is provided below the source region 30, and the drift region 36 is provided below the body region 34.

[0023] Next, as shown in Figure 3, a mask 50 having an opening 50a is formed on the upper part of the semiconductor substrate 12. Here, the mask 50 is formed so that the opening 50a is located above the central part of the source region 30. Next, anisotropic etching is performed on the upper surface 12a of the semiconductor substrate 12 through the mask 50. This forms trenches 14 in each area of ​​the upper surface 12a where the source region 30 is exposed. Here, the trenches 14 are formed so that the depth D1 of the trenches 14 is less than the thickness T1 of the source region 30. That is, the trenches 14 are formed so that they do not penetrate the source region 30.

[0024] Next, as shown in Figure 4, p-type impurities (e.g., aluminum ions) are implanted into the semiconductor substrate 12 via the mask 50. That is, p-type impurities are implanted into the bottom surface of each trench 14. Here, a bottom region 38 is formed inside the drift region 36 by implanting p-type impurities so that they penetrate the body region 34 and stop within the drift region 36. In Figure 4, the bottom region 38 is separated from the body region 34, but as shown in Figure 5, the bottom region 38 may be formed so that its upper end overlaps with the body region 34.

[0025] Next, as shown in Figure 6, the depth of the trench 14 is increased by performing anisotropic etching on the bottom surface of the trench 14 through the mask 50. Here, the depth of the trench 14 is increased so that the trench 14 penetrates the body region 34 and the bottom region 38 is exposed on the bottom surface of the trench 14. Note that in either state shown in Figures 4 and 5, the bottom region 38 can be exposed on the bottom surface of the trench 14 by deepening the trench 14 through etching, as shown in Figure 6. Since the trench 14 penetrates the body region 34, the body region 34 and the drift region 36 are exposed on the side surface of the trench 14. The body region 34 in the area exposed on the side surface of the trench 14 becomes the channel region described above. After deepening the trench 14, the mask 50 is removed.

[0026] Next, as shown in Figure 7, a gate insulating film 16 is formed to cover the inner surface of the trench 14. Next, as shown in Figure 8, a gate electrode 18 is formed inside the trench 14. Next, an interlayer insulating film 20 and an upper electrode 22 are formed on the upper part of the semiconductor substrate 12. Next, a buffer region 39 and a drain region 40 are formed by ion implanting n-type impurities into the lower surface 12b of the semiconductor substrate 12. Next, a lower electrode 24 is formed on the lower part of the semiconductor substrate 12. Through these steps, the switching element 10 shown in Figure 1 is completed.

[0027] Next, the advantages of the manufacturing method described above will be explained. Figure 9 shows the process of forming the bottom region 38 in Comparative Example 1. In Figure 9, the bottom region 38 is formed by injecting p-type impurities into the upper surface 12a of the semiconductor substrate 12 without forming the trench 14. In this case, since the injection distance of the p-type impurities (i.e., the distance from the upper surface 12a to the formation position of the bottom region 38) is long, it is necessary to inject the p-type impurities with high energy. In contrast, in the manufacturing method of the embodiment, as shown in Figures 4 and 5, the injection of p-type impurities is performed with the trench 14 already formed, so the injection distance of the impurities is shorter than in Figure 9. Therefore, the bottom region 38 can be formed with lower injection energy than in Figure 9. For this reason, the bottom region 38 can be formed at a low cost.

[0028] Figure 10 shows the process of forming the bottom region 38 in Comparative Example 2. In Figure 10, a trench 14 reaching the drift region 36 is formed, and the bottom region 38 is formed by injecting p-type impurities into the bottom surface of the trench 14. In this method, as shown by the dashed arrows in Figure 10, p-type impurities reflected and scattered from the mask 50, semiconductor substrate 12, etc., are injected into the side surface of the trench 14 within the range of the body region 34. That is, the reflected and scattered p-type impurities are directly injected into the channel region. As a result, in the manufacturing method of Figure 10, a large number of crystal defects are formed in the channel region, leading to problems such as an increase in channel resistance and variations in the gate threshold. In contrast, as shown in Figures 4 and 5, in the manufacturing method of the embodiment, the body region 34 is not exposed on the side surface of the trench 14 during the p-type impurity injection process. As a result, as shown by the dashed arrows in Figures 4 and 5, p-type impurities reflected and scattered from the mask 50, semiconductor substrate 12, etc., are not directly injected into the channel region. In this way, the injection of reflected and scattered p-type impurities into the channel region is suppressed. Therefore, according to the manufacturing method of the embodiment, problems such as an increase in channel resistance and variations in gate threshold can be prevented. In the manufacturing method of the embodiment, p-type impurities that are reflected and scattered during the formation process of the bottom region 38 are injected into the source region 30 that constitutes the side surface of the trench 14. However, since the concentration of n-type impurities in the source region 30 is high, the injection of p-type impurities into the source region 30 has almost no effect on the characteristics of the switching element 10.

[0029] Furthermore, as described above, in the manufacturing method of the embodiment, it is not necessary to form a protective film on the side surface of the trench 14 to prevent the injection of p-type impurities. Therefore, even if the width of the trench 14 is narrow, the p-type impurity injection process into the bottom region 38 can be suitably carried out. Since the width of the trench 14 can be narrowed, the switching element can be miniaturized. For this reason, a high-density integrated switching element can be formed according to this manufacturing method.

[0030] In the embodiment described above, the depth D1 of the trench 14 was smaller than the thickness T1 of the source region 30 before the formation of the bottom region 38. However, the depth D1 of the trench 14 may be equal to the thickness T1 of the source region 30 before the formation of the bottom region 38. In this configuration as well, since the body region 34 is not exposed on the side surface of the trench 14 when the bottom region 38 is formed, the injection of p-type impurities into the channel region can be suppressed.

[0031] Furthermore, although the switching element 10 was a MOSFET in the above-described embodiment, the switching element 10 may also be an IGBT (i.e., an insulated gate bipolar transistor). By replacing the n-type drain region 40 with a p-type collector region in Figure 1, the structure of an IGBT can be obtained. The same manufacturing method as in the above-described embodiment can also be used in the manufacturing process of the IGBT.

[0032] Furthermore, in the embodiment described above, the bottom region 38 was a p-type region, but the bottom region 38 may be an n-type region with a higher n-type impurity concentration than the drift region 36. In Figures 4 and 5, by injecting n-type impurities into the bottom surface of the trench 14, an n-type bottom region 38 can be formed. In this case, the injection of n-type impurities into the channel region is suppressed. In this case as well, changes in the characteristics of the switching element (i.e., an increase in channel resistance, an increase in gate threshold variation, etc.) can be suppressed.

[0033] The source region 30 in the example is an example of a first-type n region. The drift region 36 in the example is an example of a second-type n region. The bottom region 38 in the example is an example of an impurity injection region.

[0034] Although embodiments have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various modifications and changes to the specific examples illustrated above. The technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technologies illustrated in this specification or drawings achieve multiple objectives simultaneously, and achieving even one of these objectives constitutes technical usefulness. [Explanation of Symbols]

[0035] 12: Semiconductor substrate, 14: Trench, 16: Gate insulating film, 18: Gate electrode, 30: Source region, 34: Body region, 36: Drift region, 38: Bottom region

Claims

[Claim 1] A method for manufacturing a switching element, A semiconductor substrate is prepared, wherein a first n-type region (30) is provided in the area exposed on the surface, a p-type body region (34) is provided below the first n-type region, and a second n-type region (36) is provided below the body region. A step of forming a mask (50) having an opening (50a) on the upper part of the semiconductor substrate, After the step of forming the mask, the step of forming a trench (14) on the surface within the range where the first n-type region in the opening is exposed by anisotropic etching, the trench having a depth less than or equal to the thickness of the first n-type region. The process of forming an impurity implantation region (38) within the second n-type region by injecting p-type or n-type impurities into the bottom surface of the trench, After forming the impurity implantation region, the depth of the trench is increased by etching the bottom surface of the trench so that the impurity implantation region is exposed on the bottom surface of the trench. After exposing the impurity implantation region on the bottom surface of the trench, a step of forming a gate insulating film that covers the inner surface of the trench, After forming the gate insulating film, a step of forming a gate electrode in the trench, A manufacturing method having the following characteristics.

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