Information processing device

Abstract

To reduce power consumption involved in save processing.SOLUTION: An information processing device includes a CPU, a DRAM, an SRAM, and a hibernation circuit. The hibernation circuit executes, when a predetermined execution condition for hibernation is satisfied, save processing of reading specific data stored in the DRAM and storing it in the SRAM (S22, S23). The CPU interrupts, after the save processing is complete, power supply to the DRAM while maintaining power supply to the SRAM (S31). The CPU reads, if the specific data is stored in the SRAM at the time of startup, the specific data stored in the SRAM.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to an information processing apparatus.

Background Art

[0002] The information processing system of Patent Document 1 includes a processor, a RAM, and a NAND memory. The processor can execute various processes by executing a program. The RAM is a volatile memory. The NAND memory is a non-volatile memory.

[0003] The information processing system of Patent Document 1 executes hibernation. Specifically, when turning off the power of the information processing system, the information processing system stores the data in the RAM, which is a volatile memory, in the NAND memory, which is a non-volatile memory, and then turns off the power. And when turning on the power of the information processing system, the information processing system restores the stored data from the NAND memory, which is a non-volatile memory, to the RAM, which is a volatile memory.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In the information processing system of Patent Document 1, power is also consumed for the processor to execute various processes associated with hibernation. It is not preferable for the processor to consume a large amount of power along with hibernation.

Means for Solving the Problems

[0006] An information processing device for solving the above problems comprises a main processing circuit capable of performing various processes by executing a program, a DRAM which is a volatile memory and requires a refresh process for data retention, an SRAM which is a volatile memory and does not require a refresh process for data retention, and a sub-processing circuit capable of performing a save process that reads specific data stored in the DRAM and stores it in the SRAM. The processing speed of the sub-processing circuit is lower than that of the main processing circuit, and the sub-processing circuit is a circuit that consumes less power than the main processing circuit. When predetermined execution conditions for hibernation are met, the sub-processing circuit can perform the save operation; after the save operation is completed, the main processing circuit can cut off the power supply to the DRAM while maintaining the power supply to the SRAM; and when starting up, if the specific data is stored in the SRAM, the main processing circuit can read the specific data stored in the SRAM. [Effects of the Invention]

[0007] In the above configuration, instead of a main processing circuit capable of executing various processes, a sub-processing circuit performs a save operation that stores the DRAM data in the SRAM. This sub-processing circuit only needs to be able to perform the save operation. Therefore, a low-power circuit can be used as the sub-processing circuit, even if its processing speed is somewhat slower. Consequently, the above configuration can suppress the power consumed in conjunction with the execution of the save operation. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a schematic diagram of the vehicle's configuration. [Figure 2] Figure 2 is a schematic diagram of the main memory configuration. [Figure 3] Figure 3 is a sequence diagram showing the evacuation control. [Figure 4] Figure 4 is a sequence diagram showing the startup control. [Modes for carrying out the invention]

[0009] <Outline of the vehicle configuration> An embodiment of the present invention will be described below with reference to Figures 1 to 4. First, the general configuration of the vehicle 100 will be described.

[0010] As shown in Figure 1, the vehicle 100 is equipped with an engine ECU 10, a brake ECU 20, an advanced driver assistance ECU 30, and a multimedia ECU 50. "ECU" is an abbreviation for Electronic Control Unit. The vehicle 100 also includes an external bus 90 and a battery 95. The external bus 90 connects the engine ECU 10, brake ECU 20, advanced driver assistance ECU 30, and multimedia ECU 50 so that they can communicate with each other. The battery 95 supplies power to the engine ECU 10, brake ECU 20, advanced driver assistance ECU 30, and multimedia ECU 50.

[0011] The engine ECU 10 controls an engine (not shown). In this embodiment, the engine is the power source for the vehicle 100. The brake ECU 20 controls a braking system (not shown). The advanced driver assistance ECU 30 implements driver assistance corresponding to various application software by executing various application software. These various applications include application software for following a vehicle traveling ahead of the vehicle 100 while maintaining a constant distance between the two vehicles.

[0012] The multimedia ECU 50 controls a navigation system and audio system, etc. (not shown). The multimedia ECU 50 includes a CPU 60, main memory 70, and storage 80. The CPU 60, main memory 70, and storage 80 can communicate with each other via an internal bus (not shown) within the multimedia ECU 50. The storage 80 is a non-volatile memory. An example of the storage 80 is so-called flash memory. The storage 80 pre-stores various programs and various data. Here, an example of various programs is application software for operating the navigation system and audio system, etc. An example of various data is data related to the settings of the navigation system and audio system, etc. Specifically, the various data is data related to the volume set by the user of the vehicle 100. The storage 80 also includes peripheral circuits such as a power supply circuit and a data converter. The CPU 60 can perform various processes by executing programs stored in the storage 80, etc. In this embodiment, the CPU 60 is an example of a main processing circuit. The multimedia ECU 50 is an example of an information processing device.

[0013] As shown in Figure 2, the main memory 70 includes a DRAM 71, an SRAM 72, a hibernation circuit 73, and an interface 74. The main memory 70 also includes a decoder 75, a bridge 76, a first power line 77, a second power line 78, and a power switch 79.

[0014] DRAM 71 is a volatile memory. Furthermore, DRAM 71 requires a refresh process to retain data. The refresh process involves reading the data from each element and storing that data again. In this specification, "storing" means writing data. DRAM 71 is connected to interface 74 via decoder 75. Interface 74 is connected to CPU 60 via an internal bus (not shown) within the multimedia ECU 50. That is, interface 74 connects CPU 60 and DRAM 71 in a communicative manner. Decoder 75 converts the code input to it into a signal recognizable by DRAM 71, or into a signal recognizable by CPU 60.

[0015] SRAM72 is a volatile memory. Furthermore, SRAM72 does not require a refresh process for data retention. Therefore, the power consumed by SRAM72 for data retention is less than the power consumed by DRAM71 for data retention. In this embodiment, the storage capacity of SRAM72 is smaller than that of DRAM71. SRAM72 is connected to decoder75 via bridge76. That is, bridge76 is interposed between interface74 and SRAM72. Bridge76 converts the signal input to it into a signal recognizable by SRAM72, or a signal input to bridge76 into a signal recognizable by decoder75. In this embodiment, bridge76 is an interposed device between interface74 and SRAM72, and converts data between CPU60 and SRAM72 so that it can be communicated.

[0016] The hibernation circuit 73 is interposed between the DRAM 71 and the SRAM 72. The hibernation circuit 73 can perform a backup process that reads specific data DA, which is data stored in the DRAM 71, and stores it in the SRAM 72. Specifically, in the backup process, the hibernation circuit 73 stores data stored in a predetermined specific area as part of the storage area of ​​the DRAM 71 as specific data DA in the SRAM 72. The storage capacity of the specific area of ​​the DRAM 71 is less than or equal to the storage capacity of the SRAM 72. In this embodiment, the hibernation circuit 73 is a dedicated circuit for performing the backup process. The processing speed of the hibernation circuit 73 is lower than the processing speed of the CPU 60. Therefore, the power consumed when the hibernation circuit 73 performs the backup process is smaller than the power consumed when the CPU 60 performs the backup process. The hibernation circuit 73 is an example of a sub-processing circuit.

[0017] The hibernation circuit 73 may be configured as a circuit including one or more processors that execute various processes according to a computer program (software). The hibernation circuit 73 may also be configured as a circuit including one or more dedicated hardware circuits, such as application-specific integrated circuits (ASICs), or a combination thereof, that execute at least some of the various processes. The processor includes a CPU and memory such as RAM and ROM. The memory stores program code or instructions configured to cause the CPU to execute processes. Memory, or computer-readable media, includes any media that can be accessed by a general-purpose or dedicated computer.

[0018] The first end of the first power line 77 is connected to the SRAM 72. The second end of the first power line 77 is connected to the battery 95. Therefore, the first power line 77 can supply power from the battery 95 to the SRAM 72.

[0019] The first end of the second power line 78 is connected to the DRAM 71. Also, the second end of the second power line 78 is connected in the middle of the first power line 77. Therefore, the second power line 78 can supply power from the battery 95 to the DRAM 71. The power switch 79 is located in the middle of the second power line 78. When the power switch 79 is in the on state, the power switch 79 allows the supply of power from the battery 95 to the DRAM 71. On the other hand, when the power switch 79 is in the off state, the power switch 79 cuts off the supply of power from the battery 95 to the DRAM 71.

[0020] <Retreat control> Next, referring to FIG. 3, the retreat control executed by the multimedia ECU 50 will be described. This retreat control is for storing specific data DA stored in the DRAM 71 in the SRAM 72. In the present embodiment, the multimedia ECU 50 starts the retreat control at every predetermined control cycle on the condition that the system of the vehicle 100 is in the on state. Note that the on state of the system of the vehicle 100 means a state in which power is supplied from the battery 95 to all of the ECUs including the engine ECU 10, the brake ECU 20, the advanced driving support ECU 30, and the multimedia ECU 50. Therefore, the on state includes states such as a sleep state and a standby state in which each ECU can realize only some functions.

[0021] As shown in FIG. 3, when the CPU 60 of the multimedia ECU 50 starts the save control, it executes the process of step S11. In step S11, the CPU 60 determines whether a predetermined execution condition for hibernation is satisfied. In the present embodiment, an example of the execution condition is that a request to switch the system of the vehicle 100 to the off state occurs when a start switch (not shown) is operated by the user of the vehicle 100. Note that the start switch may be referred to as an ignition switch, a system-on switch, or the like. In step S11, if the CPU 60 determines that the execution condition is not satisfied (S11: NO), the CPU 60 ends the current save control. On the other hand, in step S11, if the CPU 60 determines that the execution condition is satisfied (S11: YES), the CPU 60 advances the process to step S21.

[0022] In step S21, the CPU 60 outputs an execution signal for executing the save process to the hibernation circuit 73. As a result, the hibernation circuit 73 acquires the execution signal. After step S21, the hibernation circuit 73 advances the process to step S22.

[0023] In step S22, the hibernation circuit 73 reads out specific data DA stored in the DRAM 71. In the present embodiment, an example of the specific data DA is data generated when the CPU 60 executes software. Specifically, the specific data DA is a random number table generated by the CPU 60, a clock setting calibrated when starting various communications, data indicating up to which step the application software has been executed, and the like. After step S22, the hibernation circuit 73 advances the process to step S23.

[0024] In step S23, the hibernation circuit 73 stores the specific data DA read in step S22 into the SRAM 72. In this embodiment, the processing in steps S22 and S23 corresponds to the save process. After step S23, the hibernation circuit 73 proceeds to step S24.

[0025] In step S24, the hibernation circuit 73 outputs a completion signal to the CPU 60 indicating that the save process is complete. As a result, the CPU 60 receives the completion signal. After step S24, the CPU 60 proceeds to step S31. In other words, the CPU 60 proceeds to step S31 after the save process is complete.

[0026] In step S31, the CPU 60 outputs a control signal to the power switch 79, thereby turning off the power switch 79. As a result, the power supply from the battery 95 to the DRAM 71 is cut off. In other words, the CPU 60 cuts off the power supply to the DRAM 71 while maintaining the power supply to the SRAM 72. Note that by cutting off the power supply to the DRAM 71, all data, including the specific data DA, stored in the DRAM 71 is erased. After step S31, the CPU 60 terminates this save control.

[0027] <Startup control> Next, with reference to Figure 4, the startup control performed by the multimedia ECU 50 will be described. This startup control is for reading specific data DA etc. stored in the SRAM 72. In this embodiment, the multimedia ECU 50 starts the startup control when a start switch (not shown) is operated by the user of the vehicle 100, thereby creating a request to switch the system of the vehicle 100 to the ON state. In other words, the multimedia ECU 50 starts the startup control when it starts up, specifically when it starts up all the functions of the multimedia ECU 50, including the DRAM 71.

[0028] As shown in Figure 4, when the CPU 60 of the multimedia ECU 50 starts startup control, it executes the process in step S61. In step S61, the CPU 60 turns on the power switch 79 by outputting a control signal to the power switch 79. As a result, power is supplied to the DRAM 71 from the battery 95. In other words, the CPU 60 resumes supplying power to the DRAM 71 while maintaining the power supply to the SRAM 72. Therefore, after step S61, the DRAM 71 is able to store data. After step S61, the CPU 60 proceeds to step S71. In other words, the CPU 60 proceeds to step S71 after resuming the power supply to the DRAM 71.

[0029] In step S71, the CPU 60 reads the default data DB, which is data stored in the storage 80. An example of the default data DB is data related to the settings of application software and peripheral devices. Peripheral devices include, for example, navigation devices and audio devices. After step S71, the CPU 60 proceeds to step S72.

[0030] In step S72, the CPU 60 stores the specified data DB read in step S71 into the DRAM 71. After step S72, the CPU 60 proceeds to step S81.

[0031] In step S81, the CPU 60 reads the specific data DA stored in the SRAM 72. If the specific data DA is not stored in the SRAM 72 due to the save control, the CPU 60 terminates the current startup control without executing the process in step S81 or the process in step S82 described later. After step S81, the CPU 60 proceeds to step S82.

[0032] In step S82, the CPU 60 stores the specific data DA read in step S81 into the DRAM 71. In other words, the specific data DA that was stored in the DRAM 71 immediately before the aforementioned save process is restored to the DRAM 71. After step S82, the CPU 60 terminates the current startup control. After the startup control, the CPU 60 can use the DRAM 71 as a working area and perform various processes by referring to the specific data DA restored in the DRAM 71 as needed.

[0033] <Operation of this embodiment> As shown in Figure 3, if the execution conditions for step S11 in the hibernation control are met, in step S21, the CPU 60 outputs an execution signal to the hibernation circuit 73 to execute the hibernation process. Then, in steps S22 and S23, the hibernation circuit 73 executes a hibernation process that reads specific data DA stored in the DRAM 71 and stores it in the SRAM 72. After the hibernation process is completed, in step S31, the CPU 60 cuts off the power supply to the DRAM 71 while maintaining the power supply to the SRAM 72.

[0034] <Effects of this embodiment> (1) According to this embodiment, the hibernation circuit 73 performs the saving process, rather than the CPU 60 which is capable of performing various processes. The hibernation circuit 73 only needs to be able to perform the saving process. Therefore, even if the processing speed is slower than that of the CPU 60, a circuit with lower power consumption than that of the CPU 60 can be used as the hibernation circuit 73. Consequently, the power consumed in conjunction with the execution of the saving process can be suppressed in the multimedia ECU 50.

[0035] (2) In step S23, the hibernation circuit 73 stores the specific data DA read in step S22 into the SRAM 72. Generally, the read / write speed to the SRAM 72 is higher than the read / write speed to the storage 80, which is a non-volatile memory. Therefore, according to this embodiment, the time required to store the specific data DA can be shortened compared to, for example, storing the specific data DA read in step S22 into the storage 80.

[0036] (3) Generally, the structure of SRAM 72 is more complex than that of DRAM 71. Therefore, when comparing the same storage capacity, the cost of SRAM 72 is higher than that of DRAM 71. In this regard, the hibernation circuit 73 stores data stored in a predetermined specific area as part of the storage area of ​​DRAM 71 as specific data DA in SRAM 72 during the save process. This reduces the storage capacity required in SRAM 72 compared to, for example, the case where the specific data DA is data stored in all the storage areas of DRAM 71. In other words, it reduces the storage capacity of the relatively expensive SRAM 72.

[0037] (4) In this embodiment, interface 74 connects the CPU 60 and DRAM 71 in a communicative manner. Bridge 76 is interposed between interface 74 and SRAM 72 and is a converter that converts data between the CPU 60 and SRAM 72 in a communicative manner. With this configuration, since the interface 74 of DRAM 71 and SRAM 72 is common, the CPU 60 can communicate with DRAM 71 and SRAM 72 by accessing the same interface 74. In other words, the CPU 60 can treat DRAM 71 and SRAM 72 as the same type of storage area. Furthermore, since the interface 74 of DRAM 71 and SRAM 72 is common, compared to, for example, a case with two interfaces, it is expected that interface 74 can be made more compact and its cost reduced.

[0038] (5) As shown in Figure 4, in steps S71 and S72 of the startup control, the CPU 60 stores the specified data DB, which is data stored in the storage 80, into the DRAM 71. After the power supply to the DRAM 71 is restored, in steps S81 and S82, the CPU 60 stores the specific data DA, which is stored in the SRAM 72, into the DRAM 71. This allows various types of data, including the specific data DA, to be aggregated in the DRAM 71, which generally has a larger storage capacity than the SRAM 72. Furthermore, by aggregating various types of data in this way, it is possible to expect faster processing by the CPU 60 compared to, for example, when various types of data are distributed between the DRAM 71 and SRAM 72.

[0039] (6) In this embodiment, the specific data DA is data generated by the CPU 60 when executing the software. Specifically, the specific data DA includes a random number table generated by the CPU 60, a clock setting calibrated when starting various communications, and data indicating how far the application software has been executed. With this configuration, when the multimedia ECU 50 starts up, the CPU 60 can read the specific data DA, which includes the data generated by the CPU 60 when executing the software, from the SRAM 72. This allows the CPU 60 to quickly grasp the data generated by the CPU 60 when executing the software, compared to, for example, reading the specific data DA from the storage 80. Furthermore, if the CPU 60 can quickly grasp the data generated when executing the software in this way, the execution of the application software can be quickly resumed after the multimedia ECU 50 starts up.

[0040] <Example of changes> This embodiment can be implemented with the following modifications. This embodiment and the following modifications can be combined with each other to the extent that they do not contradict each other technically.

[0041] • In the above embodiment, the retraction control may be modified. For example, the execution conditions for step S11 may be changed. Specifically, in step S11, the CPU 60 may determine that the execution conditions are met each time a predetermined period of time has elapsed that is assumed to have changed the external environment of the vehicle 100. An example of a predetermined period is several tens of days to several months. Also, specifically, in step S11, the CPU 60 may determine that the execution conditions are met when predetermined data is updated. An example of predetermined data is data related to the initial settings of the vehicle 100 that is updated when the user using the vehicle 100 changes. Furthermore, specifically, in step S11, the CPU 60 may determine that the execution conditions are met when the remaining charge of the battery 95 is below a predetermined specified charge. Note that if the execution conditions are determined to be met when there is no request to switch the system of the vehicle 100 to the off state as described above, the processing in step S31 may be omitted.

[0042] For example, the data size of the specific data DA in step S22 may be changed. Specifically, if the data size of the specific data DA is less than or equal to the storage capacity of SRAM 72, the specific data DA may be data stored in all storage areas of DRAM 71.

[0043] For example, the data included in the specific data DA in step S22 may be changed. That is, the specific data DA may include other data in addition to, or instead of, the random number table, clock settings, and data indicating how far the application software has been executed. It is preferable to use data as the specific data DA that has a small data size but takes a long time to generate, such as the random number table, or data that does not need to be changed each time the system starts up, such as the clock settings.

[0044] • In the above embodiment, the startup control may be modified. For example, the process in step S82 may be omitted. In other words, it is not necessary to consolidate the specific data DA stored in SRAM72 and the specified data DB, which is data stored in storage 80, into DRAM71.

[0045] • In the above embodiment, the configuration of the vehicle 100 may be changed. For example, the information processing device may be another ECU. Specifically, in addition to or instead of the multimedia ECU 50, the information processing device may be an ECU such as the engine ECU 10, brake ECU 20, or advanced driver assistance ECU 30.

[0046] For example, the main memory 70 may have interfaces for DRAM 71 and SRAM 72 instead of interface 74. In this case, DRAM 71 only needs to be connected to the interface for DRAM 71 via a decoder for DRAM 71. Similarly, SRAM 72 only needs to be connected to the interface for SRAM 72 via a decoder for SRAM 72. In this configuration, the bridge 76, i.e., the converter, can be omitted. [Explanation of Symbols]

[0047] 10…Engine ECU 20…Brake ECU 30…Advanced Driver Assistance ECU 50…Multimedia ECU 60…CPU 70…Main Memory 71…DRAM 72…SRAM 73…Hibernation Circuit 74…Interface 75…Decoder 76…Bridge 77…First Power Line 78…Second Power Line 79…Power Switch 80…Storage 90…External Bus 95…Battery 100…Vehicle

Claims

1. A main processing circuit capable of performing various processes by executing a program, DRAM is a volatile memory that requires a refresh process to retain data, SRAM is a volatile memory that does not require a refresh process to retain data, A sub-processing circuit capable of performing a save operation that reads specific data, which is data stored in the DRAM, and stores it in the SRAM. Equipped with, The processing speed of the sub-processing circuit is lower than that of the main processing circuit, and the sub-processing circuit is a circuit that consumes less power than the main processing circuit. When predetermined execution conditions for hibernation are met, the sub-processing circuit executes the saving process, After the aforementioned saving process is completed, the main processing circuit maintains power supply to the SRAM while shutting off power supply to the DRAM, When starting up, if the specific data is stored in the SRAM, the main processing circuit reads the specific data stored in the SRAM. It is possible to execute Information processing device.

2. An interface that enables communication between the main processing circuit and the DRAM, The system includes a converter interposed between the interface and the SRAM, which converts data between the main processing circuit and the SRAM in a way that enables communication. The information processing apparatus according to claim 1.

3. The sub-processing circuit, in the save operation, stores data stored in a predetermined specific area as part of the storage area of ​​the DRAM as the specific data in the SRAM. The information processing apparatus according to claim 1 or claim 2.

4. The main processing circuit is, When starting up, the power supply to the SRAM is maintained while the power supply to the DRAM is restarted. After resuming power supply to the DRAM, if the specific data is stored in the SRAM, the specific data stored in the SRAM is read and stored in the DRAM. It is possible to execute The information processing apparatus according to claim 1 or claim 2.

5. The aforementioned specific data includes data generated when the main processing circuit executes the software. The information processing apparatus according to claim 1 or claim 2.

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