Semiconductor equipment

Abstract

To improve the performance of a semiconductor device.SOLUTION: A semiconductor device includes a wiring substrate SUB1 having a plurality of wiring layers, and a semiconductor chip having a first analog circuit. To the first analog circuit, a power supply potential pattern LVD4 capable of supplying first power supply potential to the first analog circuit and a reference potential pattern LVS4 capable of supplying first reference potential to the first analog circuit are electrically connected, respectively. The power supply potential pattern LVD4 is provided on a wiring layer WL8 which is the layer nearest to undersurface of the wiring substrate SUB1 of the plurality of wiring layers. The reference potential pattern LVS4 is provided on a wiring layer WL7 which is a layer nearest to the undersurface after the wiring layer WL8. In a transparent plan view, the power supply potential pattern LVD4 and the reference potential pattern LVS4 are mutually extended in the same direction in a mutually overlapped state.SELECTED DRAWING: Figure 9

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] There is a semiconductor device in which a semiconductor chip is mounted on a wiring board having a plurality of wiring layers in a flip chip connection method. For example, in Japanese Patent Application Laid-Open No. 2005-340247 (Patent Document 1), as a countermeasure against crosstalk noise of digital signals on a wiring board, between a wiring layer where terminals for signal transmission are arranged and a wiring layer where signal transmission wirings are arranged, a ground plane and a power plane (the plane means a large-area conductor pattern) that function as a shield are arranged.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] With the increasing functionality of semiconductor devices, in order to stabilize the operation of the circuits included in the semiconductor device, in the path for supplying power to the circuits, a technique for reducing the influence of noise is required. For example, for the purpose of stabilizing the transmission quality of digital signals, an analog circuit such as a PLL (Phase Locked Loop) circuit may be provided in a semiconductor chip within the semiconductor device. Since an analog circuit is more easily affected by noise in circuit operation compared to a digital circuit, the path for supplying power to the analog circuit is preferably shorter in its path distance compared to other paths (for example, the path for supplying power to a digital circuit).

[0005] However, with the increasing sophistication of semiconductor devices, the number of external terminals on these devices is on the rise. Furthermore, in order to achieve miniaturization of semiconductor devices, the density of multiple external terminals is also on the rise. As a result, in some cases, the path distance from the semiconductor chip's electrodes to the external terminals becomes longer in some of the power supply paths to analog circuits. In power supply paths with long path distances from the semiconductor chip's electrodes to the external terminals, the inductance component of the power supply path is large. Therefore, the power supply potential and reference potential flowing through this path are easily affected by noise and prone to changes in potential.

[0006] Other challenges and novel features will become apparent from the description and accompanying drawings in this specification. [Means for solving the problem]

[0007] A semiconductor device according to one embodiment includes a wiring substrate having a plurality of wiring layers and a semiconductor chip having a first analog circuit. The first analog circuit is electrically connected to a first power supply potential pattern capable of supplying a first power supply potential to the first analog circuit, and to a first reference potential pattern capable of supplying a first reference potential to the first analog circuit. One of the first power supply potential pattern and the first reference potential pattern is provided on the first wiring layer, which is the layer closest to the bottom surface of the wiring substrate among the plurality of wiring layers. The other of the first power supply potential pattern and the first reference potential pattern is provided on the second wiring layer, which is the next closest layer to the bottom surface after the first wiring layer. The first power supply potential pattern and the first reference potential pattern overlap each other and extend in the same direction. [Effects of the Invention]

[0008] According to the above embodiment, the performance of the semiconductor device can be improved. [Brief explanation of the drawing]

[0009] [Figure 1] This is a top view of a semiconductor device according to one embodiment. [Figure 2] Figure 1 is a bottom view of the semiconductor device shown. [Figure 3] This is a plan view showing the internal structure of a semiconductor device on a wiring board with the cover member shown in Figure 1 removed. [Figure 4] This is a cross-sectional view along line AA in Figure 1. [Figure 5] Figure 4 is an explanatory diagram showing an example of the circuit configuration of the semiconductor device shown. [Figure 6] This is an explanatory diagram illustrating the power supply path to the analog circuit shown in Figure 5. [Figure 7] Figure 6 is an enlarged plan view showing an example of noise countermeasures for the power supply path and reference potential supply path. [Figure 8] This is an enlarged cross-sectional view along line BB in Figure 7. [Figure 9] Figure 6 is an enlarged plan view showing another example of noise countermeasures for the power supply path and reference potential supply path. [Figure 10] Figure 9 is an enlarged cross-sectional view along the CC line. [Figure 11] Figure 6 is an enlarged plan view showing another example of noise countermeasures for the power supply path and reference potential supply path. [Figure 12] This is an enlarged cross-sectional view along the DD line in Figure 11. [Figure 13] Figure 11 is an enlarged plan view showing only the power supply potential pattern and reference potential pattern. [Figure 14] Figure 6 is an enlarged plan view showing another example of noise countermeasures for the power supply path and reference potential supply path. [Figure 15] This is an enlarged plan view showing another variation of Figure 11. [Figure 16] This is an enlarged plan view showing another variation of Figure 11. [Figure 17] This is an enlarged plan view showing an example of the shape of a conductor pattern formed in the third wiring layer from the bottom layer shown in Figure 10. [Figure 18]It is an enlarged plan view showing an example of the shape of a conductor pattern formed on the third wiring layer counted from the lowermost layer shown in FIG. 12. [Figure 19] It is a plan view for comparing the difference in wiring width between a signal wiring for transmitting an electrical signal to the analog circuit shown in FIG. 5 and the reference potential pattern and power supply potential pattern shown in FIG. 9 or FIG. 11. [Figure 20] It is an enlarged cross-sectional view showing a modified example of FIG. 10 or FIG. 12.

Mode for Carrying Out the Invention

[0010] (Explanation of the description format, basic terms, and usage in this application) In this application, the description of the embodiments is divided into a plurality of sections, etc. for convenience as necessary. However, unless otherwise explicitly stated, these are not mutually independent and separate. Regardless of the order of description, each part of a single example, one is a detailed part, a partial or total modification, etc. of the other. Also, in principle, the description of similar parts is omitted. Further, each component in the embodiments is not essential unless otherwise explicitly stated, limited in number theoretically, or clearly not so from the context.

[0011] Similarly, in the description of the embodiments, etc., regarding materials, compositions, etc., even if it is stated as "X consisting of A", etc., unless otherwise explicitly stated or clearly not so from the context, it does not exclude those containing elements other than A. For example, in terms of components, it means "X containing A as the main component". For example, even if it is stated as "silicon member", etc., it is not limited to pure silicon, but also includes members containing SiGe (silicon-germanium) alloys, other multi-element alloys with silicon as the main component, and other additives. Also, even if it is stated as gold plating, Cu layer, nickel plating, etc., unless otherwise explicitly stated, it includes not only pure ones but also members with gold, Cu, nickel, etc. as the main components.

[0012] Furthermore, when referring to a specific number or quantity, unless explicitly stated otherwise, it may be a number greater than or less than that specific number, unless theoretically limited to that number or clearly otherwise indicated by the context.

[0013] Furthermore, in each figure of the embodiment, identical or similar parts are indicated by the same or similar symbols or reference numbers, and descriptions are generally not repeated.

[0014] Furthermore, in attached drawings, hatching or similar markings may be omitted even in cross-sections if it would make the drawing unnecessarily complicated or if the distinction from voids is clear. In connection with this, background contour lines may be omitted even for holes that are closed in plan view, if it is clear from the explanation, etc. Moreover, hatching or dot patterns may be added even to areas that are not voids or to indicate the boundaries of an area, even if they are not cross-sections.

[0015] Furthermore, in this specification, "semiconductor component" refers to a component that utilizes electrons within a semiconductor. Examples of such "semiconductor components" include semiconductor chips and semiconductor packages in which semiconductor chips are packaged. In addition, "electronic component" refers to any component that is incorporated into an electrical circuit and performs an electrical function, regardless of whether it contains a semiconductor or not. Electronic components include not only semiconductor components but also components such as resistors, capacitors, and inductors.

[0016] <Semiconductor device> Figure 1 is a top view of the semiconductor device of this embodiment. Figure 2 is a bottom view of the semiconductor device shown in Figure 1. Figure 3 is a plan view showing the internal structure of the semiconductor device on a wiring board with the cover member shown in Figure 1 removed. Figure 4 is a cross-sectional view along line AA in Figure 1.

[0017] The semiconductor device PKG1 of this embodiment includes a wiring board SUB1 and a semiconductor chip CHP1 (see Figure 3) mounted on the wiring board SUB1. The semiconductor device PKG1 also includes an adhesive layer BND1 disposed on the semiconductor chip CHP1 and a cover member LID that covers the entire semiconductor chip CHP1, the entire adhesive layer BND1, and a portion of the wiring board SUB1, and to which the adhesive layer BND1 is fixed.

[0018] As shown in Figure 4, the wiring board SUB1 has an upper surface (main surface, chip mounting surface, first main surface) 2t on which the semiconductor chip CHP1 is mounted, and a lower surface (main surface, mounting surface, second main surface) 2b opposite to the upper surface 2t. In addition, in a plan view, the wiring board SUB1 has multiple edges 2s (see Figures 1 to 3) that form the outer edges of the upper surface 2t and the lower surface 2b. In this embodiment, the upper surface 2t (see Figure 1) and the lower surface 2b (see Figure 2) of the wiring board SUB1 are each rectangular, and the wiring board SUB1 has four edges 2s in a plan view.

[0019] Furthermore, the wiring board SUB1 has multiple wiring layers (eight layers in the example shown in Figure 4) WL1, WL2, WL3, WL4, WL5, WL6, WL7, and WL8 provided between the upper surface 2t and the lower surface 2b. Of these multiple wiring layers, there is a wiring layer WL1 that is closest to the upper surface 2t of the wiring board SUB1 and has a terminal (terminal 2PD) provided on it. Also, there is a wiring layer WL8 that is closest to the lower surface 2b of the wiring board SUB1 and has a terminal (land 2LD) provided on it.

[0020] Each wiring layer has a conductor pattern, such as wiring, which is a path for supplying electrical signals or power. An insulating layer 2e is placed between each wiring layer. Each wiring layer is electrically connected to each other via vias 2v, which are interlayer conductive paths that penetrate the insulating layer 2e, or through-hole wiring 2THW. In this embodiment, a wiring board SUB1 with eight wiring layers is shown as an example, but the number of wiring layers in the wiring board SUB1 is not limited to eight. For example, a wiring board with seven or fewer wiring layers, or nine or more wiring layers, can be used as a modified example.

[0021] Furthermore, among the multiple wiring layers, the wiring layer WL1, which is the layer closest to the top surface 2t (the uppermost layer), is covered with an insulating film SR1. The insulating film SR1 has openings, and the multiple terminals 2PD provided on the wiring layer WL1 are exposed from the insulating film SR1 at these openings. Also, among the multiple wiring layers, the wiring layer WL8, which is the layer closest to the bottom surface 2b of the wiring substrate SUB1 (the lowest layer), has multiple lands. The wiring layer WL8 is also covered with an insulating film SR2. Both insulating films SR1 and SR2 are solder resist films. The multiple terminals 2PD provided on the wiring layer WL1 are electrically connected to the multiple lands (land patterns) 2LD provided on the wiring layer WL8, and to the conductor patterns (wiring 2d and large-area conductor patterns), vias 2v, and through-hole wiring 2THW formed on each wiring layer of the wiring substrate SUB1.

[0022] Furthermore, the wiring board SUB1 is formed by laminating multiple wiring layers on the upper surface 2Ct and lower surface 2Cb of the insulating layer (core material, core insulating layer) 2CR, which is made of a prepreg of glass fiber impregnated with resin, using a build-up method. In addition, the wiring layer WL4 on the upper surface 2Ct side of the insulating layer 2CR and the wiring layer WL5 on the lower surface 2Cb side are electrically connected via multiple through-hole wiring 2THW embedded in multiple through-holes that penetrate from one side of the upper surface 2Ct to the other.

[0023] In the example shown in Figure 4, the wiring board SUB1 is a wiring board in which multiple wiring layers are laminated on the upper surface 2Ct and lower surface 2Cb of the insulating layer 2CR, which is the core material. However, as a modification of Figure 4, a so-called coreless board may be used, which does not have an insulating layer 2CR made of a hard material such as prepreg, and is formed by sequentially laminating an insulating layer 2e and a conductor pattern such as wiring 2d. When a coreless board is used, through-hole wiring 2THW is not formed, and each wiring layer is electrically connected via 2v.

[0024] Furthermore, in the example shown in Figure 4, a solder ball (solder material, external terminal, electrode, external electrode) SB is connected to each of the multiple lands 2LD. The solder ball SB is a conductive component that electrically connects multiple terminals on the motherboard side (not shown) to multiple lands 2LD when mounting the semiconductor device PKG1 to a motherboard (not shown). The solder ball SB is made of solder material consisting of, for example, Sn-Pb solder material containing lead (Pb), or so-called lead-free solder that substantially does not contain Pb. Examples of lead-free solder include tin (Sn) only, tin-bismuth (Sn-Bi), tin-copper-silver (Sn-Cu-Ag), tin-copper (Sn-Cu), etc. Here, lead-free solder means that the lead (Pb) content is 0.1 wt% or less, and this content is defined as a standard in the RoHS (Restriction of Hazardous Substances) directive.

[0025] Furthermore, as shown in Figure 2, multiple solder balls SB are arranged in a matrix (array). Although not shown in Figure 2, multiple lands 2LD (see Figure 4) to which multiple solder balls SB are joined are also arranged in a matrix. A semiconductor device in which multiple external terminals (solder balls SB, lands 2LD) are arranged in a matrix on the mounting surface side of the wiring board SUB1 is called an area array type semiconductor device. Area array type semiconductor devices are preferable because they can effectively utilize the mounting surface (bottom surface 2b) side of the wiring board SUB1 as space for external terminals, thus suppressing an increase in the mounting area of ​​the semiconductor device even when the number of external terminals increases. In other words, semiconductor devices with an increasing number of external terminals due to increased functionality and integration can be mounted in a space-saving manner.

[0026] Furthermore, the semiconductor device PKG1 includes a semiconductor chip CHP1 mounted on a wiring board SUB1. As shown in Figure 4, each semiconductor chip CHP1 has a front surface (main surface, top surface) 3t and a back surface (main surface, bottom surface) 3b opposite to the front surface 3t. The semiconductor chip CHP1 also has multiple edges 3s that form the outer edges of the front surface 3t and back surface 3b in a plan view. As shown in Figure 3, the semiconductor chip CHP1 has a rectangular shape in a plan view with a smaller planar area than the wiring board SUB1. Therefore, the semiconductor chip CHP1 has four edges 3s in a plan view. In the example shown in Figure 3, the semiconductor chip CHP1 is mounted in the center of the top surface 2t of the wiring board SUB1, and each of the four edges 3s of the semiconductor chip CHP1 extends along each of the four edges 2s of the wiring board SUB1.

[0027] Furthermore, multiple electrodes (pads, electrode pads, bonding pads) 3PD are formed on the surface 3t side of the semiconductor chip CHP1. In the example shown in Figure 4, the semiconductor chip CHP1 is mounted on the wiring substrate SUB1 with its surface 3t facing the upper surface 2t of the wiring substrate SUB1. This mounting method is called the face-down mounting method or the flip-chip connection method.

[0028] Although not shown in the diagram, multiple semiconductor elements (circuit elements) are formed on the main surface of the semiconductor chip CHP1 (more specifically, the semiconductor element formation region provided on the element formation surface of the semiconductor substrate that is the base material of the semiconductor chip CHP1). Multiple electrodes 3PD are electrically connected to these multiple semiconductor elements via wiring (not shown) formed on a wiring layer located inside the semiconductor chip CHP1 (more specifically, between the surface 3t and the semiconductor element formation region, which is not shown).

[0029] The semiconductor substrate of the semiconductor chip CHP1 is made of, for example, silicon (Si). An insulating film is formed on the surface 3t of the semiconductor chip CHP1, covering the semiconductor substrate and wiring, and a portion of each of the multiple electrodes 3PD (see Figure 4) is exposed from the insulating film through an opening formed in the insulating film. Each of the multiple electrodes 3PD is made of a metal, and in this embodiment, it is made of, for example, aluminum (Al).

[0030] Furthermore, as shown in Figure 4, a protruding electrode 3BP is connected to each of the multiple electrodes 3PD, and the multiple electrodes 3PD of the semiconductor chip CHP1 and the multiple terminals 2PD of the wiring board SUB1 are electrically connected via the multiple protruding electrodes 3BP. The protruding electrode (bump electrode) 3BP is a metal member (conductive member) formed to protrude from the surface 3t of the semiconductor chip CHP1. In this embodiment, the protruding electrode 3BP is a so-called solder bump, in which solder material is laminated on the electrode 3PD via an underlay metal film (underbump metal). As for the solder material constituting the solder bump, leaded solder material or lead-free solder can be used, similar to the solder ball SB described above. When mounting the semiconductor chip CHP1 on the wiring board SUB1, solder bumps are formed in advance on both the multiple electrodes 3PD and the multiple terminals 2PD, and by applying a heat treatment (reflow treatment) with the solder bumps in contact with each other, the solder bumps are integrated and the protruding electrode 3BP is formed. Furthermore, as a modification of this embodiment, pillar bumps (columnar electrodes) formed by forming a solder film on the tip surface of a conductive column made of copper (Cu) or nickel (Ni) may be used as the protruding electrode 3BP.

[0031] Furthermore, as shown in Figure 4, an underfill resin (insulating resin) UF is placed between the semiconductor chip CHP1 and the wiring substrate SUB1. The underfill resin UF is positioned to fill the space between the surface 3t of the semiconductor chip CHP1 and the upper surface 2t of the wiring substrate SUB1. Each of the multiple protruding electrodes 3BP is sealed by the underfill resin UF. The underfill resin UF is made of an insulating (non-conductive) material (e.g., a resin material) and is positioned to seal the electrical connection portion (the junction of the multiple protruding electrodes 3BP) between the semiconductor chip CHP1 and the wiring substrate SUB1. In this way, by covering the junction between the multiple protruding electrodes 3BP and the multiple terminals 2PD with the underfill resin UF, the stress generated in the electrical connection portion between the semiconductor chip CHP1 and the wiring substrate SUB1 can be relieved. Furthermore, the stress generated in the junction between the multiple electrodes 3PD and the multiple protruding electrodes 3BP of the semiconductor chip CHP1 can also be relieved. In addition, the main surface on which the semiconductor elements (circuit elements) of the semiconductor chip CHP1 are formed can be protected.

[0032] Furthermore, a cover member (lid, heat spreader, heat dissipation member) LID is positioned on the back surface 3b of the semiconductor chip CHP1. The cover member LID is, for example, a metal plate with a higher thermal conductivity than the wiring board SUB1, and has the function of dissipating the heat generated by the semiconductor chip CHP1 to the outside. The cover member LID is also thermally connected to the semiconductor chip CHP1 via an adhesive layer BND1. The adhesive layer BND1 is in contact with both the semiconductor chip CHP1 and the cover member LID.

[0033] The adhesive layer BND1 consists of an adhesive obtained, for example, by curing a paste in which fillers are mixed into a resin paste. Examples of fillers include metal particles as well as metal oxide particles such as alumina. Since the adhesive layer BND1 contains fillers mixed in for the purpose of improving heat dissipation properties, it can improve the thermal conductivity between the semiconductor chip CHP1 and the cover member LID compared to a resin adhesive that does not contain fillers.

[0034] Furthermore, the peripheral region of the cover member LID is bonded and fixed to the upper surface 2t of the wiring board SUB1 via adhesive layer BND2. In the case of adhesive layer BND2, heat dissipation characteristics are not required as with adhesive layer BND1, so the material is not particularly limited and can be selected within a range that provides the necessary adhesive strength. For example, if the same material as adhesive layer BND1 is used, the manufacturing process can be simplified. Alternatively, a material with higher adhesive strength than adhesive layer BND1 may be used.

[0035] Furthermore, semiconductor devices equipped with a cover member LID as a heat dissipation component, such as semiconductor device PKG1, have high heat dissipation efficiency for the semiconductor chip CHP1, allowing for stable circuit operation even with enhanced functionality. However, as a modification of this embodiment, the structure of the wiring board SUB1 described later may be applied to a semiconductor device that does not have the cover member LID, adhesive layer BND1, and adhesive layer BND2 shown in Figure 4.

[0036] <Example Circuit Configuration> Next, we will describe an example of the circuit configuration of the semiconductor device PKG1 shown in Figure 4. Figure 5 is an explanatory diagram showing an example of the circuit configuration of the semiconductor device shown in Figure 4. In Figure 5, we will illustrate exemplify parts of the multiple circuits, multiple signal transmission paths, and multiple power supply paths that the semiconductor device PKG1 has.

[0037] As shown in Figure 5, the semiconductor chip CHP1 in the semiconductor device PKG1 of this embodiment has an analog circuit AC1. In the example shown in Figure 5, the semiconductor chip CHP1 has an analog circuit AC1 and a core circuit CC1 electrically connected to the analog circuit AC1. The analog circuit AC1 is, for example, a PLL circuit that generates a new signal synchronized with the phase of the input signal.

[0038] In the example shown in Figure 5, a signal (AC signal, high frequency signal) SG1 is input to the analog circuit AC1 from an external device of the semiconductor device PKG1. Signal SG1 is input to the analog circuit AC1 of the semiconductor chip CHP1 via the signal transmission path PSG1 of the wiring board SUB1. The analog circuit AC1 includes a phase comparison circuit, a filter circuit, and an oscillator circuit (not shown), and outputs a new signal (AC signal, high frequency signal) SG2 in which the phase of signal SG1 and the phase of an input signal for comparison (not shown) are synchronized. Signal SG2 is input to the core circuit CC1. The core circuit CC1 performs data processing (e.g., arithmetic processing) on ​​the input signal SG2 and outputs a signal (AC signal, high frequency signal) SG3. Signal SG3 is output from the core circuit CC1 of the semiconductor chip CHP1 to an external device (not shown) via the signal transmission path PSG3 of the wiring board SUB1. Signal SG2 input to the core circuit CC1 is synchronized by the analog circuit AC1, which is a PLL circuit. Therefore, the core circuit CC1 is supplied with a signal SG2 that has little phase fluctuation (jitter). Note that while the core circuit CC1 is typically a digital circuit, it can also be an analog circuit.

[0039] Furthermore, the semiconductor chip CHP1 includes a power supply circuit AC2 for supplying power to the analog circuit AC1, and a power supply circuit CC2 for supplying power to the core circuit CC1. The analog circuit AC1 is supplied with a power supply potential VD1 and a reference potential VS1 via the power supply circuit AC2. On the other hand, the core circuit CC1 is supplied with a power supply potential VD2 and a reference potential VS2 via the power supply circuit CC2.

[0040] The power supply potential VD1 is supplied to the power supply circuit AC2 of the semiconductor chip CHP1 via the power supply potential supply path PVD1 of the wiring board SUB1. The reference potential VS1 is supplied to the power supply circuit AC2 of the semiconductor chip CHP1 via the reference potential supply path PVS1 of the wiring board SUB1. The power supply potential VD2 is supplied to the power supply circuit CC2 of the semiconductor chip CHP1 via the power supply potential supply path PVD2 of the wiring board SUB1. The reference potential VS2 is supplied to the power supply circuit CC2 of the semiconductor chip CHP1 via the reference potential supply path PVS2 of the wiring board SUB1.

[0041] Note that the reference potential VS1 is a different potential from the power supply potential VD1, but it may also be a potential other than the ground potential. Similarly, the reference potential VS2 is a different potential from the power supply potential VD2, but it may also be a potential other than the ground potential. Furthermore, the reference potentials VS1 and VS2 may be the same potential, or they may be different. As will be described later, in this embodiment, even if the reference potentials VS1 and VS2 are the same potential, the reference potential supply path PVS1 and the reference potential supply path PVS2 are configured with wiring patterns that are separated from each other.

[0042] To ensure stable operation of the analog circuit AC1 shown in Figure 5, it is necessary to minimize the change in the potential difference between the power supply potential VD1 supplied to the analog circuit AC1 via the power supply circuit AC2 and the reference potential VS1. This is because a change in the potential difference between the power supply potential VD1 and the reference potential VS1 degrades the quality of the signal SG2 output from the analog circuit AC1. Examples of noise sources that can affect the change in the potential difference between the power supply potential VD1 and the reference potential VS1 include the following: For example, noise induced by high-frequency signals such as signals SG1 and SG3 can affect the potential difference between the power supply potential VD1 and the reference potential VS1. Also, for example, the power supply potential VD2 may change instantaneously due to the power demand of the core circuit CC1. In this case, if the power supply potential supply path PVD2 is located near the power supply potential supply path PVD1 and the reference potential supply path PVS1, noise generated in the power supply potential VD2 may affect the potential difference between the power supply potential VD1 and the reference potential VS1.

[0043] To reduce the influence of noise on the potential difference between the power supply potential VD1 and the reference potential VS1, it is preferable to shorten the path distance of the power supply potential supply path PVD1 and the reference potential supply path PVS1. By shortening the path distance, the inductance of the power supply potential supply path PVD1 and the reference potential supply path PVS1 can be reduced, thereby reducing the influence of noise.

[0044] However, with the increasing sophistication of semiconductor devices, the number of external terminals on these devices is on the rise. Furthermore, in order to achieve miniaturization of semiconductor devices, the density of multiple external terminals is increasing. In some cases, the path distance of the power supply potential path PVD1 and the reference potential supply path PVS1 must become longer. In other words, if the effects of noise can be reduced even when the path distance of the power supply potential supply path PVD1 and the reference potential supply path PVS1 is long, the degree of design flexibility can be improved. The next section describes a technique for reducing the effects of noise by devising the layout of the power supply potential supply path PVD1 and the reference potential supply path PVS1 on the wiring board SUB1.

[0045] <Layout of power supply path> Figure 6 is a schematic diagram illustrating the power supply path to the analog circuit shown in Figure 5. In Figure 6, the outline of region R1, which overlaps with the semiconductor chip CHP1, is shown by a dotted line.

[0046] As shown in Figure 6, the semiconductor device PKG1 has multiple pairs of power potential supply paths PVD1 and reference potential supply paths PVS1. The power potential supply paths PVD1 and reference potential supply paths PVS1 are arranged in pairs.

[0047] Here, each of the multiple protruding electrodes 3BP is located within region R1, which overlaps with the semiconductor chip CHP1. On the other hand, of the multiple lands 2LD, those included in either the power supply potential supply path PVD1 or the reference potential supply path PVS1 are located outside region R1 in a plan view. Region R1 (especially the region overlapping with the core circuit CC1 shown in Figure 5) mainly contains lands included in the power supply potential supply path PVD2 and the reference potential supply path PVS2, which supply power to the core circuit CC1 shown in Figure 5. Therefore, it is difficult to secure space in region R1 for lands 2LD included in either the power supply potential supply path PVD1 or the reference potential supply path PVS1. However, there are cases where some of the multiple lands 2LD included in either the power supply potential supply path PVD1 or the reference potential supply path PVS1 are located within region R1.

[0048] In a transmitted plan view, it is preferable that the electrically connected protruding electrode 3BP and land 2LD are located close to each other. However, depending on the design conditions, it may be difficult to place land 2LD near protruding electrode 3BP. In the example shown in Figure 6, a power potential supply path PVD1S and a reference potential supply path PVS1S have a relatively short path distance connecting the protruding electrode 3BP and land 2LD, while a power potential supply path PVD1L and a reference potential supply path PVS1L have a relatively long path distance connecting the protruding electrode 3BP and land 2LD. Also in Figure 6, a power potential supply path PVD1M and a reference potential supply path PVS1M have a relatively intermediate path distance connecting the protruding electrode 3BP and land 2LD.

[0049] The path distance of the power potential supply path PVD1S and the reference potential supply path PVS1S (path distance DVDS and path distance DVSS from the protruding electrode 3BP to the land 2LD) is, for example, 5 mm or less. The path distance of the power potential supply path PVD1M and the reference potential supply path PVS1M (path distance DVDM and path distance DVSM from the protruding electrode 3BP to the land 2LD) is, for example, greater than 5 mm and 7 mm or less. The path distance of the power potential supply path PVD1L and the reference potential supply path PVS1L (path distance DVDL and path distance DVSL from the protruding electrode 3BP to the land 2LD) is, for example, greater than 7 mm. The path distance of the power potential supply path PVD1L and the reference potential supply path PVS1L may be 10 mm or more.

[0050] The relationships between the path distances shown in Figure 6 can be expressed as follows: The path distance of the power potential supply path PVD1L, which includes the power potential pattern LVD1 (see Figure 11 described later), from the protruding electrode 3BP of the semiconductor chip CHP1 (see Figure 4) to the land 2LD of the wiring board SUB1, is defined as path distance DVDL. The path distance of the reference potential supply path PVS1L, which includes the reference potential pattern LVS1 (see Figure 11 described later), from the protruding electrode 3BP of the semiconductor chip CHP1 to the land 2LD of the wiring board SUB1, is defined as path distance DVSL. The path distance of the power potential supply path PVD1S, which includes the power potential pattern LVD3 (see Figure 7 described later), from the protruding electrode 3BP of the semiconductor chip CHP1 to the land 2LD of the wiring board SUB1, is defined as path distance DVDS. The path distance of the reference potential supply path PVS1S, which includes the reference potential pattern LVS3 (see Figure 7 described later), from the protruding electrode 3BP of the semiconductor chip CHP1 to the land 2LD of the wiring board SUB1, is defined as path distance DVSS. The path distance of the power potential supply path PVD1M from the protruding electrode 3BP of the semiconductor chip CHP1 (see Figure 4) to the land 2LD of the wiring board SUB1, including the power potential pattern LVD4 (see Figure 9 described later), is defined as path distance DVDM. The path distance of the reference potential supply path PVS1M from the protruding electrode 3BP of the semiconductor chip CHP1 to the land 2LD of the wiring board SUB1, including the reference potential pattern LVS4 (see Figure 9 described later), is defined as path distance DVSM. In this case, path distance DVDL is longer than each of path distances DVDM, DVDS, DVSM, and DVSS. Path distance DVSL is longer than each of path distances DVDM, DVDS, DVSM, and DVSS. Path distance DVDM is longer than each of path distances DVDS and DVSS. Path distance DVSM is longer than each of path distances DVDS and DVSS.

[0051] In the example shown in Figure 6, noise countermeasures should be given priority to the power supply potential path PVD1L and the reference potential supply path PVS1L. Furthermore, noise countermeasures should be given priority to the power supply potential path PVD1M and the reference potential supply path PVS1M over those to the power supply potential path PVD1S and the reference potential supply path PVS1S. The noise countermeasures will be explained in detail below.

[0052] <First noise reduction method> First, as the first noise countermeasure method, we will describe a noise countermeasure technique that is effective when applied to the power potential supply path PVD1S and the reference potential supply path PVS1S shown in Figure 6. Figure 7 is an enlarged plan view showing an example of noise countermeasures for the power potential supply path and the reference potential supply path shown in Figure 6. Figure 8 is an enlarged cross-sectional view along line BB in Figure 7. In Figures 7 and 8, symbols are used to schematically indicate the inductively coupled state of the power potential pattern LVD3 constituting the power potential supply path PVD1 and the reference potential pattern LVS3 constituting the reference potential supply path PVS1. Among the multiple wiring layers shown in Figure 4, the wiring layer shown in Figure 7 is, for example, wiring layer WL7. As shown in Figures 4 and 8, among the multiple wiring layers, wiring layer WL7 is the layer closest to the bottom surface 2b of the wiring board SUB1, after wiring layer WL8. Although not shown, as a modification, the same power potential pattern LVD3 and reference potential pattern LVS3 as in Figure 7 may be arranged on wiring layers other than wiring layer WL7.

[0053] As a method to reduce the noise influence on the power potential supply path PVD1 and the reference potential supply path PVS1 shown in Figure 6, inductive coupling of the power potential pattern LVD3 and the reference potential pattern LVS3 is effective. Inductive coupling refers to a state in which the mutual induction between the power potential supply path and the reference potential supply path becomes dominant. When the power potential supply path and the reference potential supply path are inductively coupled, the loop inductance between each path can be reduced by mutual induction. As a result, voltage fluctuations with respect to high-frequency current components can be suppressed (in other words, self-noise can be reduced). For example, if high-frequency noise or pulse noise is superimposed on the power potential pattern LVD3, which is supplied with a fixed potential, if the power potential pattern LVD3 and the reference potential pattern LVS3 are inductively coupled, the potential fluctuations with respect to high-frequency current components flowing through these loop paths can be suppressed.

[0054] As shown in Figure 7, the power supply potential pattern LVD3 and the reference potential pattern LVS3 are formed on the same wiring layer WL7. Also, in a plan view, the power supply potential pattern LVD3 and the reference potential pattern LVS3 are adjacent to each other and extend in the same direction. As schematically shown in Figures 7 and 8 using capacitor circuit symbols, the power supply potential pattern LVD3 and the reference potential pattern LVS3 are inductively coupled.

[0055] The noise suppression effect achieved by inductively coupling the power supply potential pattern LVD3 and the reference potential pattern LVS3 is proportional to the magnitude of the mutual inductance between the power supply potential pattern LVD3 and the reference potential pattern LVS3. Therefore, the wider the path width between the opposing power supply potential pattern LVD3 and the reference potential pattern LVS3 separated by the insulating layer 2e, and the smaller the distance between the opposing patterns, the better the noise suppression effect. The opposing path width refers to the width of the portion where the power supply potential supply path and the reference potential supply path face each other. In the example shown in Figure 8, the thickness of the power supply potential pattern LVD3 and the reference potential pattern LVS3 (length in the Z direction in Figure 8) corresponds to the opposing path width. Therefore, in the example shown in Figure 8, it is preferable that the thickness of the power supply potential pattern LVD3 and the reference potential pattern LVS3 running parallel to each other be thicker, and that the distance between the power supply potential pattern LVD3 and the reference potential pattern LVS3 be smaller.

[0056] In the plan view shown in Figure 7, conductor patterns 2CP are located next to the power supply potential pattern LVD3 and next to the reference potential pattern LVS3. These conductor patterns 2CP are paths through which any potential is supplied. For example, they constitute either the power supply potential supply path PVD2 or the reference potential supply path PVS2, as explained using Figure 5. Alternatively, the conductor patterns 2CP shown in Figure 7 may constitute supply paths for other potentials not shown.

[0057] Furthermore, the wiring board SUB1 has a reference potential pattern LVS2 (see Figure 8) that can supply a reference potential VS2 to circuits other than the analog circuit AC1 shown in Figure 5 (for example, the core circuit CC1 shown in Figure 5). The reference potential pattern LVS2 is a conductor pattern that constitutes part of the reference potential supply path PVS2 shown in Figure 5. As shown in Figure 8, the reference potential pattern LVS2 is formed on wiring layers WL6 and WL8 of the wiring board SUB1, which are adjacent to wiring layer WL7 on which the power supply potential pattern LVD3 and the reference potential pattern LVS3 are formed, and overlaps with the power supply potential pattern LVD3 and the reference potential pattern LVS3. Preferably, the reference potential pattern LVS2 of wiring layer WL6 and the reference potential pattern LVS2 of wiring layer WL8 each extend in the same direction while overlapping with the power supply potential pattern LVD3 and the reference potential pattern LVS3.

[0058] The reference potential pattern LVS2 functions as an electromagnetic shield to suppress noise generated in the surroundings from reaching the power supply potential pattern LVD3 and the reference potential pattern LVS3. As shown in Figure 8, by providing the reference potential pattern LVS2 which functions as an electromagnetic shield, the noise applied to the power supply potential pattern LVD3 and the reference potential pattern LVS3 can be reduced.

[0059] In the examples shown in Figures 7 and 8, an embodiment is illustrated in which the power supply potential pattern LVD3 and the reference potential pattern LVS3 are formed on the wiring layer WL7, and therefore, the reference potential pattern LVS2, which functions as an electromagnetic shield, is placed on both the wiring layer WL6 and the wiring layer WL8. However, as a modified example, the power supply potential pattern LVD3 and the reference potential pattern LVS3 may be formed on the wiring layer WL8. In this case, the structure of the wiring layer WL6 is not particularly limited as long as the reference potential pattern LVS2 is placed on the wiring layer WL7.

[0060] However, in the methods shown in Figures 7 and 8, it is difficult to make the thickness of the power supply potential pattern LVD3 and the reference potential pattern LVS3 extremely thick. For example, the thickness of the power supply potential pattern LVD3 and the reference potential pattern LVS3 shown in Figure 8 is about 10 to 20 μm. Therefore, the upper limit of mutual induction between the power supply potential pattern LVD3 and the reference potential pattern LVS3 is low. Consequently, the effectiveness of the methods shown in Figures 7 and 8 as noise countermeasures for paths with long path lengths and large path inductances, such as the power supply potential supply path PVD1M and power supply potential supply path PVD1L shown in Figure 6, is limited.

[0061] As described above, the power supply potential supply path PVD1S and the reference potential supply path PVS1S shown in Figure 6 have short path distances DVDS and DVSS, respectively, of 5 mm or less, and have low path inductance (for example, lower path inductance compared to power supply potential supply path PVD1M and power supply potential supply path PVD1L). Therefore, in the case of power supply potential pattern LVD3 and reference potential pattern LVS3, noise can be reduced even if the power supply potential pattern LVD3 and reference potential pattern LVS3 are formed on the same wiring layer WL7, as shown in Figure 7.

[0062] <Second noise reduction method> Next, as a second noise countermeasure method, we will describe a noise countermeasure technique that is effective for noise countermeasures against the power supply potential supply path PVD1M and power supply potential supply path PVD1L shown in Figure 6. In each of the second noise countermeasure method described below, and the third noise countermeasure method described later, we will assume that at least one of the power supply potential pattern LVD1 and the reference potential pattern LVS1 is placed in the bottommost wiring layer WL8. In addition to the wiring layers WL1 to WL8 shown in Figure 4, it is also conceivable to add a new wiring layer for noise countermeasures. However, increasing the number of wiring layers results in disadvantages such as an increase in the thickness of the semiconductor device, an increase in the manufacturing process of the wiring board, or an increase in manufacturing costs due to an increase in the constituent materials of the wiring board. Therefore, the inventors of this application have investigated a technique to reduce noise by utilizing the bottommost wiring layer WL8 without adding a wiring layer for noise countermeasures.

[0063] Figure 9 is an enlarged plan view showing another example of noise countermeasures for the power supply path and reference potential supply path shown in Figure 6. Figure 10 is an enlarged cross-sectional view along the CC line in Figure 9. In the noise countermeasures examples shown in Figures 9 and 10, the power potential pattern LVD1 and the reference potential pattern LVS1 are located on adjacent wiring layers. When wiring layers WL7 and WL8 shown in Figure 9 are superimposed, it is difficult to distinguish between the power potential pattern LVD4 and the reference potential pattern LVS4. Therefore, although Figure 9 should be a transparent plan view, it is shown with a portion of wiring layer WL7 and a portion of wiring layer WL8 that overlaps with the above portion, arranged vertically. Figure 9 clearly shows the positional relationship of the power potential pattern LVD4, the reference potential pattern LVS4, and the multiple lands 2LD in a transparent plan view of the wiring board SUB1 viewed from the bottom surface 2b (see Figure 10), so Figure 9 can be considered a transparent plan view. As will be described later, Figures 11, 14, 15, and 16, like Figure 9, are diagrams in which a portion of the wiring layer WL7 and a portion of the wiring layer WL8 that overlaps with the aforementioned portion are shown side by side vertically, and can be considered as transparent plan views. Furthermore, as will be described later, Figures 17 and 18 are diagrams in which a portion of the wiring layer WL6, a portion of the wiring layer WL7 that overlaps with the aforementioned portion, and a portion of the wiring layer WL8 that overlaps with the aforementioned portion are shown side by side vertically, and can be considered as transparent plan views.

[0064] Furthermore, Figures 9 and 10 show symbols schematically representing the inductively coupled state of the power supply potential pattern LVD4 and the reference potential pattern LVS4.

[0065] The analog circuit AC1 shown in Figure 5 is electrically connected to a power supply potential pattern LVD4 (see Figure 9) that can supply power supply potential VD1 to the analog circuit AC1, and a reference potential pattern LVS4 (see Figure 9) that can supply reference potential VS1 to the analog circuit AC1. The power supply potential pattern LVD4 shown in Figures 9 and 10 constitutes a part of the power supply potential supply path PVD1M shown in Figure 5. The reference potential pattern LVS4 also constitutes a part of the reference potential supply path PVS1M shown in Figure 5.

[0066] As shown in Figures 9 and 10, one of the power supply potential pattern LVD4 and the reference potential pattern LVS4 is provided in the wiring layer WL8, and the other of the power supply potential pattern LVD4 and the reference potential pattern LVS4 is provided in the wiring layer WL7. In the example shown in Figures 9 and 10, the power supply potential pattern LVD4 is provided in the wiring layer WL8 and the reference potential pattern LVS4 is provided in the wiring layer WL7. However, in a modified example, the reference potential pattern LVS4 may be provided in the wiring layer WL8 and the power supply potential pattern LVD4 may be provided in the wiring layer WL7.

[0067] Furthermore, in a transparent planar view, the power supply potential pattern LVD4 and the reference potential pattern LVS4 overlap each other and extend in the same direction. Of the power supply potential pattern LVD4 and the reference potential pattern LVS4, the pattern formed on the wiring layer WL8 (in Figure 10, the power supply potential pattern LVD4) is formed to extend with a width WV4. Similarly, the pattern placed on the wiring layer WL7 (in Figure 10, the reference potential pattern LVS4) is also formed to extend with a width WV4.

[0068] In the noise countermeasure shown in Figure 10, the power supply potential pattern LVD4 and the reference potential pattern LVS4 face each other in the thickness direction (Z direction in Figure 10) of the wiring board SUB1 via an insulating layer 2e that functions as a dielectric. Therefore, the area of ​​the portion where the power supply potential pattern LVD4 and the reference potential pattern LVS4 face each other can be made larger compared to the examples shown in Figures 7 and 8. In the example shown in Figure 9, the width WV4 is, for example, about 50 to 200 μm, which is larger than the thickness TV4 of the power supply potential pattern LVD4 and reference potential pattern LVS4 shown in Figure 10 (for example, about 10 to 20 μm). Therefore, the mutual induction between the power supply potential pattern LVD4 and the reference potential pattern LVS4 is greater than the mutual induction between the power supply potential pattern LVD3 and the reference potential pattern LVS3 shown in Figure 7. Furthermore, the thickness of the power supply potential pattern LVD1 and the reference potential pattern LVS1 shown in Figures 11-16, 18, and 19, which will be described later, is approximately 10-20 μm, similar to the thickness TV4 of the power supply potential pattern LVD4 and the reference potential pattern LVS4 shown in Figure 10.

[0069] Therefore, applying the structures shown in Figures 9 and 10 is particularly effective for power potential supply paths with long path distances, such as the power potential supply paths PVD1M and PVD1L shown in Figure 6. Furthermore, for the power potential supply path PVD1L shown in Figure 6, the structures shown in Figures 12 and 13, which will be discussed later, are even more effective.

[0070] In the example shown in Figure 9, in the wiring layer WL8, the power potential pattern LVD4 is positioned between two adjacent lands 2LDs in the Y direction that intersect (orthogonal to in Figure 9) with the extension direction of the power potential pattern LVD4 (X direction in Figure 9). The width WV4 is smaller than the distance PLD between the centers of adjacent lands 2LDs in the Y direction, and also smaller than the distance GLD between them.

[0071] <Third noise reduction method> Next, as a third noise countermeasure method, we will describe a noise countermeasure technique that is particularly effective for noise countermeasures against the power supply potential supply path PVD1L shown in Figure 6. Figure 11 is an enlarged plan view showing another example of noise countermeasures for the power supply path and reference potential supply path shown in Figure 6. Figure 12 is an enlarged cross-sectional view along the DD line in Figure 11. Figure 13 is an enlarged plan view showing only the power supply potential pattern and reference potential pattern shown in Figure 11. In the noise countermeasure examples shown in Figures 11 to 13, the power supply potential pattern LVD1 and the reference potential pattern LVS1 are located on adjacent wiring layers. Therefore, Figure 11, like Figure 9, shows a portion of wiring layer WL7 and a portion of wiring layer WL8 that overlaps with the above portion, arranged vertically. Also, in Figures 11 and 12, symbols are used to schematically indicate the inductively coupled state of the power supply potential pattern LVD1 and the reference potential pattern LVS1.

[0072] The analog circuit AC1 shown in Figure 5 is electrically connected to a power supply potential pattern LVD1 (see Figure 11) that can supply power supply potential VD1 to the analog circuit AC1, and a reference potential pattern LVS1 (see Figure 11) that can supply reference potential VS1 to the analog circuit AC1. The power supply potential pattern LVD1 shown in Figures 11 and 12 constitutes a part of the power supply potential supply path PVD1L shown in Figure 5. The reference potential pattern LVS1 also constitutes a part of the reference potential supply path PVS1L shown in Figure 5.

[0073] As shown in Figures 11 and 12, one of the power supply potential pattern LVD1 and the reference potential pattern LVS1 is provided in the wiring layer WL8, and the other of the power supply potential pattern LVD1 and the reference potential pattern LVS1 is provided in the wiring layer WL7. In the example shown in Figures 11 and 12, the power supply potential pattern LVD1 is provided in the wiring layer WL8 and the reference potential pattern LVS1 is provided in the wiring layer WL7. However, in a modified example, the reference potential pattern LVS1 may be provided in the wiring layer WL8 and the power supply potential pattern LVD1 may be provided in the wiring layer WL7.

[0074] As shown in Figure 11, among the power supply potential pattern LVD1 and the reference potential pattern LVS1, the pattern formed on the wiring layer WL8 (in the example shown in Figure 11, the power supply potential pattern LVD1) has a planar shape that follows the shape of the outer edge of one of the multiple lands 2LD, which is located next to the power supply potential pattern LVD1. The power supply potential pattern LVD1 has multiple wide sections LWD1 (see Figure 13) with a width WV1W in the Y direction that intersects (orthogonal in Figure 11) the extending direction of the power supply potential pattern LVD1 (X direction in Figure 11), and multiple narrow sections LND1 (see Figure 13) with a width WV1N that is narrower than the width WV1W in the Y direction.

[0075] As shown in Figure 13, the wide portion LWD1 and the narrow portion LND1 are arranged alternately in the extending direction (X direction) of the power supply potential pattern LVD1. As shown in Figure 11, the width WV1W is greater than the separation distance GLD between adjacent lands 2LD across the power supply potential pattern LVD1 in the Y direction.

[0076] Each of the multiple narrow sections LND1 (see Figure 13) and multiple wide sections LWD1 (see Figure 13) overlaps with the power supply potential pattern LVD1 and the reference potential pattern LVS1, specifically the pattern formed on the wiring layer WL7 (in the example in Figure 11, the reference potential pattern LVS1).

[0077] As shown in Figure 12, in the case of the third noise suppression method, the presence of the wide section LWD1 allows for an even larger opposing area between the power supply potential pattern LVD1 and the reference potential pattern LVS1 compared to the second noise suppression method shown in Figure 10. In the example shown in Figure 11, the width WV1W is, for example, about 200 to 800 μm, which is larger than the width WV4 of the power supply potential pattern LVD4 and reference potential pattern LVS4 shown in Figure 9. Therefore, the mutual induction between the power supply potential pattern LVD1 and the reference potential pattern LVS1 is even greater than the mutual induction between the power supply potential pattern LVD4 and the reference potential pattern LVS4 shown in Figures 9 and 10. Consequently, even when the third noise suppression method shown in Figures 11 to 13 is applied to a path where the path distance DVDL (or path distance DVSL) exceeds 7 mm, such as the power supply potential supply path PVD1L or the reference potential supply path PVS1L shown in Figure 6, the influence of noise in the power supply potential supply path PVD1L can be reduced.

[0078] As shown in Figure 13, which illustrates the ranges of the wide section LWD1 and the narrow section LND1, the wide section LWD1 is defined as the portion of the power supply potential pattern LVD1 that extends with a width WV1W that can be considered substantially constant. The width WV1W is wider (larger) than the separation distance GLD between adjacent lands 2LD. Thus, by providing a wide section LWD1 with a width WV1W wider than the separation distance GLD, the third noise reduction measure shown in Figures 11 and 12 achieves an even higher noise reduction effect than the second noise reduction measure shown in Figures 9 and 10.

[0079] In the example shown in Figure 11, the width WV1W is narrower (smaller) than the distance PLD between the centers of adjacent lands 2LD in the Y direction. However, as will be described later as a variation, there are also cases where the width WV1W is wider (larger) than the distance PLD between the centers of adjacent lands 2LD in the Y direction.

[0080] The narrow section LND1 is defined as a portion having a width narrower than the width WV1W. Therefore, the width of the narrow section LND1 is not constant, as shown in Figure 13. The narrowest width WV1N of the narrow section LND1 is narrower than the distance 2LD between adjacent lands, as shown in Figure 11. Also, as shown in Figure 11, the narrow section LND1 (see Figure 13) includes portions that are wider than the distance GLD between adjacent lands 2LD. The shape of the narrow section LND1 is determined by the shape of the conductor pattern, such as the land 2LD, that is placed next to the power supply potential pattern LVD1. Therefore, the shape of the narrow section LND1 shown in Figure 13 is just one example, and there are various variations. However, since the power supply potential pattern LVD1 is positioned to pass between adjacent lands 2LD in the Y direction, each of the multiple narrow sections LND1 includes a portion with a width WV1N that is at least narrower (smaller) than the distance GLD between adjacent lands 2LD.

[0081] Next, we will describe the shape of the reference potential pattern LVS1, which is located in the wiring layer WL7 opposite the power potential pattern LVD1 located in the wiring layer WL8. As shown in Figure 13, in this embodiment, the power potential pattern LVD1 and the reference potential pattern LVS1 have similar planar shapes.

[0082] More specifically, of the power supply potential pattern LVD1 and the reference potential pattern LVS1, the pattern formed on the wiring layer WL7 (reference potential pattern LVS1 in the example shown in Figure 11) is formed to conform to the shape of the pattern formed on the wiring layer WL8 (power supply potential pattern LVD1 in the example shown in Figure 11) in a transmitted plan view.

[0083] The reference potential pattern LVS1 has multiple wide sections LWS1 (see Figure 13) with a width WV1W in the Y direction, which intersects (orthogonal in Figure 11) the extending direction (X direction) of the reference potential pattern LVS1, and multiple narrow sections LNS1 (see Figure 13) with a width narrower than WV1W (for example, width WV1N). The wide sections LWS1 and narrow sections LNS1 are arranged alternately in the extending direction (X direction) of the reference potential pattern LVS1. In a transmitted plan view, multiple narrow sections LND1 and multiple narrow sections LNS1 overlap, and multiple wide sections LWD1 and multiple wide sections LWS1 overlap.

[0084] Furthermore, the definition of the wide section LWS1 can be applied by substituting the power supply potential pattern LVD1 with the reference potential pattern LVS1 in the definition of the wide section LWD1 described above. Similarly, the definition of the narrow section LNS1 can be applied by substituting the power supply potential pattern LVD1 with the reference potential pattern LVS1 in the definition of the narrow section LND1 described above.

[0085] In this way, by making the planar shape of the reference potential pattern LVS1 and the planar shape of the power supply potential pattern LVD1 the same, and by arranging the multiple narrow sections LND1 and multiple narrow sections LNS1 to overlap, and the multiple wide sections LWD1 and multiple wide sections LWS1 to overlap, the majority of the reference potential pattern LVS1 and the power supply potential pattern LVD1 face each other. This is particularly preferable because it can reduce the entry points for noise from other power supply paths and signal transmission paths.

[0086] "Formed to resemble" means that, in the example shown in Figure 11, the reference potential pattern LVS1 and the power supply potential pattern LVD1 are formed with the same shape. However, this does not mean that slight differences in shape due to manufacturing precision are excluded. Also, depending on the layout constraints of, for example, the wiring layer WL7 or wiring layer WL8, there may be parts in which the shape of the reference potential pattern LVS1 and the shape of the power supply potential pattern LVD1 do not match. In other words, "formed to resemble" is not limited to cases where the shape of the reference potential pattern LVS1 and the shape of the power supply potential pattern LVD1 perfectly match throughout the entire path. Even in this case, if there are parts in which the shape of the reference potential pattern LVS1 and the shape of the power supply potential pattern LVD1 match, the noise countermeasures described in this section can be obtained in those parts.

[0087] However, it is preferable that 80% or more of the entire path of the reference potential pattern LVS1 and 80% or more of the entire path of the power supply potential pattern LVD1 are formed in the same shape and are arranged to overlap each other. Here, the entire path of the reference potential pattern LVS1 is defined as the path from one end of the reference potential pattern LVS1 (a via land connected to via wiring not shown) to the other end (a via 2LD connected to the reference potential pattern LVS1). Similarly, the entire path of the power supply potential pattern LVD1 is defined as the path from one end of the power supply potential pattern LVD1 (a via land connected to via wiring not shown) to the other end (a via 2LD connected to the power supply potential pattern LVD1).

[0088] In the following explanation, the phrase "A is formed in imitation of B" is used in the same sense unless a different interpretation is specifically explained.

[0089] Although not shown in the illustrations, as a modification of Figures 11 and 13, the planar shape of the reference potential pattern LVS1 formed on the wiring layer WL7 may be a strip-shaped pattern with a width WV1W extending in the Y direction. Even in this case, since most of the power supply potential pattern LVD1 shown in Figures 11 and 13 faces the reference potential pattern LVS1, it is an effective measure to reduce noise components that have entered the power supply potential pattern LVD1. However, in this case, a portion of the reference potential pattern LVS1 will overlap with a conductor pattern other than the power supply potential pattern LVD1 (for example, land 2LD). From the viewpoint of suppressing the intrusion of noise components from land 2LD into the reference potential pattern LVS1 formed on the wiring layer WL7, it is particularly preferable that the reference potential pattern LVS1 is formed to conform to the shape of the power supply potential pattern LVD1, as shown in Figures 11 and 13.

[0090] Next, we will describe a modified version of the third noise suppression method explained using Figures 11 to 13. Figure 14 is an enlarged plan view showing another example of noise suppression for the power supply path and reference potential supply path shown in Figure 6. In Figure 14, symbols are used to schematically indicate the state in which the power supply potential pattern LVD1 and the reference potential pattern LVS1 are inductively coupled. In the following modified versions, only the enlarged plan corresponding to Figure 11 is shown, and the enlarged cross-sectional view corresponding to Figure 12 and the enlarged plan view corresponding to Figure 13 are omitted from the illustration, and Figures 12 and 13 will be referred to as necessary for explanation.

[0091] In the modified example shown in Figure 14, the width WV1W of the wide section LWD1 (see Figure 13) of the power supply potential pattern LVD1 and the width WV1W of the wide section LWS1 (see Figure 13) of the reference potential pattern LVS1 are both wider than in the example shown in Figure 11. In both the example shown in Figure 9 and the example shown in Figure 14, each of the multiple lands 2LD is arranged at equal intervals. In the example shown in Figure 14, the width WV1W is greater than the distance PLD between the centers of adjacent lands 2LD in the Y direction via the power supply potential pattern LVD1.

[0092] In the modified example shown in Figure 14, the opposing path width between the power supply potential pattern LVD1 and the reference potential pattern LVS1 can be further increased compared to the example shown in Figure 11. Therefore, the effect of reducing noise components that have entered the power supply potential pattern LVD1 or the reference potential pattern LVS1 is even greater than in the example shown in Figure 11.

[0093] On the other hand, in the example shown in Figure 14, the area of ​​the power potential pattern LVD1 placed between multiple lands 2LD is large. Therefore, from the viewpoint of increasing the design freedom of the lead wiring connected to the lands 2LD, in other words, the design freedom of the wiring layer WL8, the example shown in Figure 11 is preferable. That is, in the example shown in Figure 11, the width WV1W is smaller than the distance PLD between the centers of adjacent lands 2LD in the Y direction via the power potential pattern LVD1. In this case, the design freedom of the wiring layer WL8 can be increased compared to the modified example shown in Figure 14.

[0094] Figure 15 is an enlarged plan view showing another modification of Figure 11. In Figure 15 and Figure 16 (described later), the symbols schematically representing the inductive coupling of the power supply potential pattern LVD1 and the reference potential pattern LVS1 are omitted. In the modification shown in Figure 15, some of the multiple lands 2LD are positioned in a location surrounded by the power supply potential pattern LVD1, which differs from the example shown in Figure 11. In the modification shown in Figure 15, the opposing area between the power supply potential pattern LVD1 and the reference potential pattern LVS1 can be further increased compared to the modification shown in Figure 14. Therefore, the effect of reducing noise components that have entered the power supply potential pattern LVD1 or the reference potential pattern LVS1 is even greater than in the example shown in Figure 14.

[0095] In the modified example shown in Figure 15, there are multiple (two in Figure 15) adjacent narrow sections LND1 in the Y direction via land 2LD. Although not shown in the illustration, the width WV1W of the wide section LWD1 of the power supply potential pattern LVD1 can be further increased.

[0096] On the other hand, as mentioned above, the example shown in Figure 11 is preferable from the viewpoint of increasing the design flexibility of the wiring layer WL8. For example, in the example shown in Figure 15, in order to electrically connect land 2LD, which is surrounded by the power supply potential pattern LVD1, to other wiring layers, it is necessary to connect via wiring at a position that overlaps with land 2LD.

[0097] Figure 16 is an enlarged plan view showing another modification of Figure 11. In the modification shown in Figure 16, the arrangement pattern of the multiple lands 2LD differs from that in Figures 9, 11, 14, and 15. In the example shown in Figure 16, among the multiple lands 2LD, the distance between the centers of adjacent lands 2LDs via the power potential pattern LVD1 is longer than the distance between the centers of adjacent lands 2LDs along the direction of extension of the power potential pattern LVD1 (the X direction in Figure 16) PLD2. The minimum width of the narrow section LWD1 (i.e., width WV1N) is greater than the distance between the centers PLD2.

[0098] The modified example shown in Figure 16 is a structure in which the land 2LD surrounding the power supply potential pattern LVD1 is not placed, compared to the modified example shown in Figure 15. In this structure, the opposing path width between the power supply potential pattern LVD1 and the reference potential pattern LVS1 can be further increased compared to the modified example shown in Figure 15. Therefore, the effect of reducing noise components that have entered the power supply potential pattern LVD1 or the reference potential pattern LVS1 is even greater than in the example shown in Figure 15.

[0099] In the modified example shown in Figure 16, if a portion of the power supply potential pattern LVD1 is used as land 2LD (i.e., an opening is provided in the insulating film SR2 (see Figure 4) covering the power supply potential pattern LVD1, and a solder ball SB (see Figure 4) is connected to the power supply potential pattern LVD1 exposed at the opening), the reduction in the number of terminals that occurs when applying the modified example shown in Figure 16 can be suppressed.

[0100] In the modified examples shown in Figures 14, 15, and 16, the planar shape of the reference potential pattern LVS1 placed in wiring layer WL7 is the same as that of the power supply potential pattern LVD1 placed in wiring layer WL8. However, as mentioned above, in modified examples, the planar shape of the reference potential pattern LVS1 formed in wiring layer WL7 may be a strip-shaped pattern with a width WV1W extending in the Y direction. Furthermore, as a further modification of Figures 14, 15, and 16, the reference potential pattern LVS1 may be placed in wiring layer WL8 and the power supply potential pattern LVD1 may be placed in wiring layer WL7.

[0101] <Noise countermeasures using electromagnetic shielding> Next, as a more preferred embodiment of each noise countermeasure described using Figures 7 to 16, a modified example will be described in which a conductor pattern that functions as an electromagnetic shield is placed in a position superimposed on the power supply potential pattern LVD1 and the reference potential pattern LVS1. Figure 17 is an enlarged plan view showing an example of the shape of a conductor pattern formed in the third wiring layer from the bottom layer shown in Figure 10. Wiring layer WL6 is the layer closest to the bottom surface 2b (see Figure 4) after wiring layer WL7. The enlarged cross-sectional view along the CC line shown in Figure 17 is the same as in Figure 10, so the redundant illustration is omitted. In Figure 17, symbols are used to schematically indicate the state in which the power supply potential pattern LVD1 and the reference potential pattern LVS1 are inductively coupled.

[0102] The wiring board SUB1, as described using Figure 5, has a reference potential pattern LVS2 (see Figure 17) that can supply a reference potential VS2 to circuits other than the analog circuit AC1 (for example, the core circuit CC1). Also, as shown in Figure 10, the multiple wiring layers of the wiring board SUB1 include a wiring layer WL6 located near the bottom surface, next to the wiring layer WL7. As shown in Figure 17, the reference potential pattern LVS2 is provided on the wiring layer WL6 and overlaps with the power supply potential pattern LVD4 and the reference potential pattern LVS4. The reference potential pattern LVS2, which is positioned to overlap with the power supply potential pattern LVD4 and the reference potential pattern LVS4, functions as an electromagnetic shield and can suppress the intrusion of noise components from other conductor patterns into the power supply potential pattern LVD4 and the reference potential pattern LVS4.

[0103] Incidentally, instead of the reference potential pattern LVS2 shown in Figure 17, a power supply potential pattern (not shown) capable of supplying power supply potential VD2 to circuits other than the analog circuit AC1 (for example, the core circuit CC1) can also be used. However, the reference potential pattern LVS2 is a conductor pattern that constitutes part of the reference potential supply path PVS2 for supplying reference potential to many circuits other than the analog circuit AC1, and is the conductor pattern with the lowest self-noise among the multiple conductor patterns provided on the wiring board SUB1. Therefore, it is particularly preferable to use the reference potential pattern LVS2 as the conductor pattern to be used as an electromagnetic shield.

[0104] Furthermore, in the example shown in Figure 17, in a transmitted plan view, the power supply potential pattern LVD4, the reference potential pattern LVS4, and the reference potential pattern LVS2 each overlap each other and extend in the same direction. The width WV2 of the reference potential pattern LVS2 is the same as the width WV4 of the power supply potential pattern LVD4 and the width WV4 of the reference potential pattern LVS4. In other words, the reference potential pattern LVS2 has the same planar shape as the power supply potential pattern LVD4 and the reference potential pattern LVS4. As a modification of Figure 17, in addition to the reference potential pattern LVS4 located in the wiring layer WL7 of Figure 17, a large-area reference potential pattern LVS2 may be provided that also overlaps with the conductor patterns 2CP located on both sides of the reference potential pattern LVS4.

[0105] In the wiring layer WL6 shown in Figure 17, if the potential supplied to the conductor patterns 2CP located on either side of the reference potential pattern LVS2 is a potential (or signal) other than the reference potential VS2 shown in Figure 5, the degree of freedom in the layout of the wiring layer WL6 can be improved by minimizing the shape of the reference potential pattern LVS2 within the range that functions as an electromagnetic shield.

[0106] Figure 18 is an enlarged plan view showing an example of the shape of a conductor pattern formed in the third wiring layer from the bottom layer shown in Figure 12. Wiring layer WL6 is the layer closest to the bottom surface 2b (see Figure 4) after wiring layer WL7. The enlarged cross-sectional view along the DD line shown in Figure 18 is the same as in Figure 12, so the redundant illustration is omitted.

[0107] The electromagnetic shield described using Figure 17 can also be applied in combination with the structure described using Figures 11 to 13. As shown in Figure 18, the reference potential pattern LVS2 is provided in the wiring layer WL6 and overlaps with the power supply potential pattern LVD1 and the reference potential pattern LVS1. The reference potential pattern LVS2, which is positioned to overlap with the power supply potential pattern LVD1 and the reference potential pattern LVS1, functions as an electromagnetic shield and can suppress the intrusion of noise components from other conductor patterns into the power supply potential pattern LVD1 and the reference potential pattern LVS1.

[0108] In the example shown in Figure 18, each of the multiple wide sections LWD1 (see Figure 13), multiple narrow sections LND1 (see Figure 13) of the power supply potential pattern LVD1, and each of the multiple wide sections LWS1 (see Figure 13) and multiple narrow sections LNS1 (see Figure 13) of the reference potential pattern LVS1, overlaps with the reference potential pattern LVS2 formed on the wiring layer WL6.

[0109] As a modification of Figure 18, in addition to the reference potential pattern LVS1 located in the wiring layer WL7 of Figure 18, a large-area reference potential pattern LVS2 may be provided that overlaps with the conductor patterns 2CP located on both sides of the reference potential pattern LVS1. In the example shown in Figure 18, the planar shape of the reference potential pattern LVS2 located in the wiring layer WL6 is the same as the planar shape of the reference potential pattern LVS1 located in the wiring layer WL7, and the planar shape of the power supply potential pattern LVD1 located in the wiring layer WL8. In a transmitted planar view, the reference potential pattern LVS2, the reference potential pattern LVS1, and the power supply potential pattern LVD1 each extend in the same direction while overlapping each other.

[0110] More specifically, the reference potential pattern LVS2 formed on the wiring layer WL6 is formed in a transmitted plan view following the shape of the power supply potential pattern LVD1 formed on the wiring layer WL8. The reference potential pattern LVS2 has multiple wide sections LWS2 with a width WV1W in the Y direction, which intersects (orthogonal in Figure 18) the extending direction (X direction) of the reference potential pattern LVS2, and multiple narrow sections LNS2 with a width narrower than WV1W. In the extending direction (X direction) of the reference potential pattern LVS2, the wide sections LWS2 and narrow sections LNS2 are arranged alternately. In a transmitted plan view, multiple narrow sections LND1 and multiple narrow sections LNS2 overlap, and multiple wide sections LWD1 and multiple wide sections LWS2 overlap.

[0111] As shown in Figure 18, minimizing the shape of the reference potential pattern LVS2 within the range that functions as an electromagnetic shield improves the flexibility of the wiring layer WL6 layout.

[0112] While embodiments using the reference potential pattern LVS2 as an electromagnetic shield have been described using Figures 17 and 18 as representative examples, in each structure described using Figures 14, 15, and 16, the reference potential pattern LVS2 described using Figure 17 or 18 may be placed in the wiring layer WL6 (see Figure 4). In this case, it is possible to suppress the intrusion of noise components from other conductor patterns into the power supply potential pattern LVD1 and the reference potential pattern LVS1 shown in Figures 14, 15, and 16.

[0113] <Regarding pattern width> Next, we will explain the widths of the reference potential pattern LVS1, reference potential pattern LVS4, power supply potential pattern LVD1, and power supply potential pattern LVD4, which were explained using Figures 9 to 18. Figure 19 is a plan view for comparing the difference in wiring width between the signal wiring for transmitting electrical signals to the analog circuit shown in Figure 5 and the reference potential pattern and power supply potential pattern shown in Figure 9 or Figure 11.

[0114] The wiring board SUB1 shown in Figure 5 has wiring (signal wiring, signal wiring pattern) LSG (see Figure 19) that constitutes part of the signal transmission path PSG1 that transmits a signal (electrical signal) SG1 to the analog circuit AC1. In other words, the analog circuit AC1 is electrically connected to wiring (signal wiring, signal wiring pattern) LSG that is capable of transmitting an electrical signal to the analog circuit AC1. As shown in Figure 19, the width WV4 of the power supply potential pattern LVD4 and the width WV4 of the reference potential pattern LVS4, as explained using Figure 9, are both wider than the wiring width WSG of the wiring LSG. Similarly, the minimum width WV1N of the power supply potential pattern LVD1 and the minimum width WV1N of the reference potential pattern LVS1, as explained using Figure 11, are both wider than the wiring width WSG of the wiring LSG. Thus, even when the conductor pattern for supplying power to the analog circuit AC1 is formed to extend, its width is wider than the wiring width WSG of the wiring LSG. Therefore, as described above, by superimposing the power supply potential pattern LVD1 and the reference potential pattern LVS1 in the thickness direction, or by superimposing the power supply potential pattern LVD4 and the reference potential pattern LVS4 in the thickness direction, mutual induction can be increased, thereby greatly enhancing the effect of reducing intruded noise.

[0115] <Regarding the distance between patterns> Next, the spacing distance of the patterns shown in Figures 10 and 20 will be explained. Figure 20 is an enlarged cross-sectional view showing a modified version of Figure 10 or Figure 12. The noise countermeasures and their modified versions explained using Figures 7 to 16 are techniques that reduce noise components that have entered the path by inductively coupling the power supply potential supply path and the reference potential supply path connected to the analog circuit. However, from the viewpoint of stabilizing the power supply to the analog circuit, it is preferable to suppress the intrusion of noise into the power supply path.

[0116] In the example shown in Figure 20, the distance GWL8 between the power potential pattern LVD1 (or power potential pattern LVD4) located on wiring layer WL8 and land 2LD is greater than the interlayer distance G78 between wiring layer WL7 and wiring layer WL8. The interlayer distance G78 can be rephrased as the distance in the thickness direction between the conductor pattern located on wiring layer WL8 and the conductor pattern located on wiring layer WL7. By making the distance GWL8 greater than the interlayer distance G78, the intrusion of noise components can be suppressed and mutual induction can be increased.

[0117] Although the present invention has been specifically described above based on embodiments, it goes without saying that the present invention is not limited to the above embodiments and can be modified in various ways without departing from its essence. [Explanation of Symbols]

[0118] 2b Bottom surface (face, main surface, mounting surface, second main surface) 2Cb bottom surface 2CP conductor pattern 2CR insulating layer (core material, core insulating layer) 2Ct top surface 2D wiring 2e insulating layer 2LD Land (Land Pattern) 2PD terminal 2s, 3s side 2t Top surface (surface, main surface, chip mounting surface, first main surface) 2THW Through-hole wiring 2V via 3b Back side (front, main side, bottom side) 3BP (Bump Electrode) 3PD electrodes (pads, electrode pads, bonding pads) 3t surface (main surface, top surface) AC1 Analog Circuit AC2,CC2 power supply circuit BND1,BND2 Adhesive layer CC1 Core Circuit CHP1 semiconductor chip (semiconductor component, electronic component) DVDL,DVDM,DVDS,DVSL,DVSM,DVSS Route distance G78 Interlayer distance GLD,GWL8 Separation distance LID cover components (lid, heat spreader, heat dissipation component) LND1,LNS1,LNS2 Narrow part LSG wiring (signal wiring) LVD1, LVD3, LVD4 Power Supply Potential Patterns LVS1, LVS2, LVS3, LVS4 Reference Potential Patterns LWD1, LWS1, LWS2 Wide section PKG1 Semiconductor device PLD,PLD1,PLD2 center distance PSG1, PSG3 signal transmission path PVD1, PVD1L, PVD1M, PVD1S, PVD2 Power Potential Supply Path PVS1, PVS1L, PVS1M, PVS1S, PVS2 Reference Potential Supply Path SB Solder Balls (Solder material, external terminals, electrodes, external electrodes) SG1,SG2,SG3 signal SR1, SR2 insulating film SUB1 Wiring board UF Underfil resin (insulating resin) VD1,VD2 Power supply potential VS1, VS2 Reference Potentials WL1-WL8 wiring layer WSG Wiring Width WV1N, WV1W, WV2, WV4 width

Claims

1. A wiring board having an upper surface, a lower surface opposite to the upper surface, and a plurality of wiring layers provided between the upper surface and the lower surface, A semiconductor chip having a first surface, a plurality of protruding electrodes formed on the first surface, and a second surface opposite to the first surface, mounted on the upper surface of the wiring substrate via the plurality of protruding electrodes, Includes, The semiconductor chip has a first analog circuit, The plurality of wiring layers of the wiring board are Among the plurality of wiring layers, the first wiring layer is the layer closest to the lower surface and has a plurality of land patterns, A second wiring layer, which is the layer closest to the bottom surface after the first wiring layer, Includes, The first analog circuit is electrically connected to a first power supply potential pattern capable of supplying a first power supply potential to the first analog circuit, and to a first reference potential pattern capable of supplying a first reference potential to the first analog circuit. One of the first power supply potential pattern and the first reference potential pattern is provided in the first wiring layer, The other of the first power supply potential pattern and the first reference potential pattern is provided in the second wiring layer. A semiconductor device in which the first power supply potential pattern and the first reference potential pattern overlap each other and extend in the same direction.

2. In claim 1, Of the first power supply potential pattern and the first reference potential pattern, the first pattern formed on the first wiring layer is, The planar shape is such that it follows the outer edge shape of the land pattern located next to the first pattern among the plurality of land patterns. A plurality of first wide portions having a first width in a first direction intersecting the extending direction of the first pattern, and a plurality of first narrow portions having a width narrower than the first width in the first direction, It has, In the extending direction of the first pattern, the first wide portion and the first narrow portion are arranged alternately. The first width is greater than the distance between adjacent land patterns in the first direction via the first pattern. A semiconductor device in which each of the plurality of first narrow portions and the plurality of first wide portions overlaps with a second pattern formed on the second wiring layer, among the first power supply potential pattern and the first reference potential pattern.

3. In claim 2, Of the first power supply potential pattern and the first reference potential pattern, the second pattern formed on the second wiring layer is, In a transparent planar view, it is formed in accordance with the shape of the first pattern formed on the first wiring layer. In a second direction intersecting the extending direction of the second pattern, a plurality of second wide portions having the first width and a plurality of second narrow portions having a width narrower than the first width, It has, In the extending direction of the second pattern, the second wide portion and the second narrow portion are arranged alternately. A semiconductor device in which the plurality of first narrow portions and the plurality of second narrow portions overlap, and the plurality of first wide portions and the plurality of second wide portions overlap.

4. In claim 2, Each of the aforementioned land patterns is arranged at equal intervals, A semiconductor device wherein the first width is greater than the distance between the centers of adjacent land patterns in the first direction via the first pattern among the plurality of land patterns.

5. In claim 4, A semiconductor device in which a portion of the plurality of land patterns is located in a position surrounded by the first pattern.

6. In claim 2, Each of the aforementioned land patterns is arranged at equal intervals, A semiconductor device wherein the first width is smaller than the distance between the centers of adjacent land patterns in the first direction, across the first pattern, among the plurality of land patterns.

7. In claim 2, Among the plurality of land patterns, the first distance between the centers of adjacent land patterns via the first pattern is longer than the second distance between the centers of adjacent land patterns along the extension direction of the first pattern. A semiconductor device in which the minimum width of the first narrow portion is greater than the second center-to-center distance.

8. In claim 1, The wiring board has a second reference potential pattern capable of supplying a second reference potential to a first circuit other than the first analog circuit, The plurality of wiring layers of the wiring board further include a third wiring layer which is the layer closest to the bottom surface after the second wiring layer, A semiconductor device wherein the second reference potential pattern is provided on the third wiring layer and overlaps with the first power supply potential pattern and the first reference potential pattern.

9. In claim 8, A semiconductor device in which the first power supply potential pattern, the first reference potential pattern, and the second reference potential pattern each overlap each other and extend in the same direction.

10. In claim 9, Of the first power supply potential pattern and the first reference potential pattern, the first pattern formed on the first wiring layer is, The planar shape is such that it follows the outer edge shape of the land pattern located next to the first pattern among the plurality of land patterns. A plurality of first wide portions having a first width in a first direction intersecting the extending direction of the first pattern, and a plurality of first narrow portions having a width narrower than the first width in the first direction, It has, In the extending direction of the first pattern, the first wide portion and the first narrow portion are arranged alternately. The first width is wider than the distance between adjacent land patterns in the first direction via the first pattern. A semiconductor device wherein each of the plurality of first narrow portions and the plurality of first wide portions overlaps with the second pattern formed on the second wiring layer and the second reference potential pattern formed on the third wiring layer, among the first power supply potential pattern and the first reference potential pattern.

11. In claim 10, Of the first power supply potential pattern and the first reference potential pattern, the second pattern formed on the second wiring layer is: In a transparent planar view, it is formed in accordance with the shape of the first pattern formed on the first wiring layer. In a second direction intersecting the extending direction of the second pattern, a plurality of second wide portions having the first width and a plurality of second narrow portions having a width narrower than the first width, It has, In the extending direction of the second pattern, the second wide portion and the second narrow portion are arranged alternately. A semiconductor device wherein, in a transmitted plan view, the plurality of first narrow portions and the plurality of second narrow portions overlap, the plurality of first wide portions and the plurality of second wide portions overlap, and each of the plurality of first narrow portions, the plurality of second narrow portions, the plurality of first wide portions, and the plurality of second wide portions overlaps with the second reference potential pattern formed on the third wiring layer.

12. In claim 1, The first analog circuit is further electrically connected to a third power supply potential pattern capable of supplying the first power supply potential to the first analog circuit, and to a third reference potential pattern capable of supplying the first reference potential to the first analog circuit. Each of the third power supply potential pattern and the third reference potential pattern is formed on the same wiring layer among the plurality of wiring layers, In a plan view, the third power supply potential pattern and the third reference potential pattern are adjacent to each other and extend in the same direction. The first power supply potential supply path, which includes the first power supply potential pattern, is defined as the path distance of the first power supply potential supply path from the protruding electrode of the semiconductor chip to the land pattern of the wiring substrate, The first reference potential supply path, which includes the first reference potential pattern, is defined as the path distance of the first reference potential supply path from the protruding electrode of the semiconductor chip to the land pattern of the wiring substrate, and the path distance of the first reference potential supply path is defined as the second path distance. The third power supply potential supply path, which includes the third power supply potential pattern, is defined as the path distance of the third power supply potential supply path from the protruding electrode of the semiconductor chip to the land pattern of the wiring substrate. If the path distance of the third reference potential supply path, which includes the third reference potential pattern, from the protruding electrode of the semiconductor chip to the land pattern of the wiring substrate, is defined as the fourth path distance, A semiconductor device in which the first path distance is longer than each of the third and fourth path distances, and the second path distance is longer than each of the third and fourth path distances.

13. In claim 12, The wiring board has a second reference potential pattern capable of supplying a second reference potential to a first circuit other than the first analog circuit, A semiconductor device wherein the second reference potential pattern is formed in a wiring layer adjacent to the wiring layer on which the third power supply potential pattern and the third reference potential pattern are formed, among the plurality of wiring layers of the wiring board, and overlaps with the third power supply potential pattern and the third reference potential pattern.

14. In claim 2, The first analog circuit is electrically connected to a fourth power supply potential pattern capable of supplying the first power supply potential to the first analog circuit, and to a fourth reference potential pattern capable of supplying the first reference potential to the first analog circuit. One of the fourth power supply potential pattern and the fourth reference potential pattern is provided in the first wiring layer, The other of the fourth power supply potential pattern and the fourth reference potential pattern is provided in the second wiring layer. In a transmitted planar view, the fourth power supply potential pattern and the fourth reference potential pattern overlap each other and extend in the same direction. Of the fourth power supply potential pattern and the fourth reference potential pattern, the third pattern formed on the first wiring layer is formed to extend with a third width. The third width is narrower than the distance between adjacent land patterns across the third pattern in a third direction intersecting the extension direction of the third pattern. The first power supply potential supply path, which includes the first power supply potential pattern, is defined as the path distance of the first power supply potential supply path from the protruding electrode of the semiconductor chip to the land pattern of the wiring substrate, The first reference potential supply path, which includes the first reference potential pattern, is defined as the path distance of the first reference potential supply path from the protruding electrode of the semiconductor chip to the land pattern of the wiring substrate, and the path distance of the first reference potential supply path is defined as the second path distance. The fourth power supply potential path includes the fourth power supply potential pattern, and the path distance of the fourth power supply potential supply path from the protruding electrode of the semiconductor chip to the land pattern of the wiring substrate is defined as the fifth path distance. If the path distance of the fourth reference potential supply path, which includes the fourth reference potential pattern and extends from the protruding electrode of the semiconductor chip to the land pattern of the wiring substrate, is defined as the sixth path distance, A semiconductor device wherein the first path distance is longer than each of the fifth and sixth path distances, and the second path distance is longer than each of the fifth and sixth path distances.

15. In claim 2, A semiconductor device wherein the distance between the first pattern and the land pattern located next to the first pattern is greater than the interlayer distance between the first wiring layer and the second wiring layer.

16. In claim 1, The first analog circuit is further electrically connected to a first signal pattern capable of transmitting an electrical signal to the first analog circuit. A semiconductor device wherein the width of the first power supply potential pattern and the width of the first reference potential pattern are each wider than the width of the first signal pattern.

17. In claim 1, A semiconductor device wherein the width of the first power supply potential pattern and the first reference potential pattern is greater than the thickness of the first power supply potential pattern and the first reference potential pattern, respectively.

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