Semiconductor equipment

Abstract

To provide a semiconductor device that realizes inhibition of the leakage current during operation under a high-temperature environment.SOLUTION: A semiconductor device 10 comprises a substrate 100, a semiconductor stack structure 200, a source electrode 600S, a gate electrode 600G, a drain electrode 600D, and a gate insulating film 700. The semiconductor stack structure includes: a first semiconductor layer 300 comprising a first nitride semiconductor formed on the substrate; and a second semiconductor layer 400 formed on the first semiconductor layer and comprising a second nitride semiconductor having a larger band gap than the first nitride semiconductor. The gate leakage current at an operating temperature of 400 K is 2×10-5 A / mm or less when a reverse bias of 100 V is applied to between the gate electrode and the drain electrode.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] Nitride semiconductors have characteristics such as high saturated electron velocity and wide bandgap. Therefore, various studies have been conducted on applying nitride semiconductors to high-voltage and high-output semiconductor devices by utilizing these characteristics. In recent years, for device applications for high frequencies from several tens of GHz to several hundreds of GHz, the development of GaN-based high electron mobility transistors (HEMTs) (hereinafter sometimes referred to as "GaN-HEMTs") has been actively carried out. For example, Al , , , ,

[0003] , , , , , , , , ,

[0004] , , , Ga 1-x N (0 < x < 1) is used as an electron supply layer, and a two-dimensional electron gas (hereinafter sometimes referred to as "2DEG") is generated at the Al x Ga 1-x N (0 < x < 1) / GaN heterointerface, and a sheet carrier concentration of 1 × 10 13 cm -2 or more can be obtained without doping anything. As a result, high-frequency operation is realized (Patent Documents 1 and 2).

Prior Art Documents

Patent Documents

[0003] b>

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] When a semiconductor device is in the off state, the unintended current flowing between its electrodes is called leakage current. Specifically, the leakage current between the source electrode and the drain electrode is called drain leakage current, and the leakage current between the source electrode and the gate electrode is called gate leakage current. Large leakage currents in semiconductor devices are not only disadvantageous in terms of energy efficiency, but also pose a major safety problem. Therefore, suppressing leakage current is an important issue.

[0005] On the other hand, the need for HEMT devices to be used in high-temperature environments is increasing year by year. For example, high frequencies are required for communication in the space environment, but the ambient temperature is extremely high. Taking the lunar surface as an example, the surface temperature during the day can reach over 100°C. For this reason, the development of HEMT devices that can withstand high-temperature operation is urgently needed.

[0006] Even if gate and drain leakage currents are not problematic at room temperature, both increase when the operating temperature is raised. In conventional HEMT devices, this is thought to be because doped layers in the carrier compensation layer, such as the GaN:Fe layer or AlN buffer layer, are the source of leakage, but the details are still unclear. As described above, no semiconductor device has been obtained that can suppress leakage current during operation in high-temperature environments.

[0007] Therefore, the object of the present invention is to provide a semiconductor device that suppresses leakage current during operation in a high-temperature environment. [Means for solving the problem]

[0008] In response to the above problems, the inventors of this invention conducted diligent research and found that the above problems can be solved by a semiconductor device in which the gate leakage current value or drain leakage current value during high-temperature operation is below a certain value, thus completing the present invention.

[0009] In other words, the gist of the present invention is as follows: [1] A semiconductor device including a substrate, a semiconductor stacked structure, a source electrode, a gate electrode, and a drain electrode, wherein the semiconductor stacked structure includes a first semiconductor layer made of a first nitride semiconductor formed on the substrate, and a second semiconductor layer made of a second nitride semiconductor formed on the first semiconductor layer and having a larger bandgap than the first nitride semiconductor, wherein a gate leakage current value at an operating temperature of 400 K when a reverse bias of 100 V is applied between the gate electrode and the drain electrode is 2×10 -5 A / mm or less. [2] The semiconductor device according to [1], wherein a gate leakage current value at an operating temperature of 500 K when a reverse bias of 100 V is applied between the gate electrode and the drain electrode is less than 1×10 -4 A / mm. ?

[0010] [3] A semiconductor device including a substrate, a semiconductor stacked structure, a source electrode, a gate electrode, and a drain electrode, wherein the semiconductor stacked structure includes a first semiconductor layer made of a first nitride semiconductor formed on the substrate, and a second semiconductor layer made of a second nitride semiconductor formed on the first semiconductor layer and having a larger bandgap than the first nitride semiconductor, wherein a gate leakage current value at an operating temperature of 400 K when a reverse bias of 20 V is applied between the gate electrode and the drain electrode is 1×10 -5 A / mm or less. [4] The semiconductor device according to [3], wherein a gate leakage current value at an operating temperature of 500 K when a reverse bias of 20 V is applied between the gate electrode and the drain electrode is 4×10 -5 A / mm or less. [5] The semiconductor device according to [3] or [4], wherein a gate leakage current value at an operating temperature of 600 K when a reverse bias of 20 V is applied between the gate electrode and the drain electrode is less than 1×10 -4 A / mm.

[0011] [6] A semiconductor device comprising a substrate, a semiconductor stacked structure, a source electrode, a gate electrode and a drain electrode, The semiconductor stacked structure includes a first semiconductor layer made of a first nitride semiconductor formed on the substrate, and a second semiconductor layer formed on the first semiconductor layer and made of a second nitride semiconductor having a larger band gap than the first nitride semiconductor. When a reverse bias of 10V is applied between the gate electrode and the source electrode, and a forward bias of 100V is applied between the source electrode and the drain electrode, the drain leakage current value at an operating temperature of 400K is 5 × 10⁻¹⁰ -5 Semiconductor equipment with an A / mm ratio of less than 1 / mm. [7] When a reverse bias of 10V is applied between the gate electrode and the source electrode, and a forward bias of 100V is applied between the source electrode and the drain electrode, the drain leakage current value at an operating temperature of 500K is 5 × 10 -4 The semiconductor device described in [6] above, wherein the A / mm is less than A / mm. [8] When a reverse bias of 10V is applied between the gate electrode and the source electrode, and a forward bias of 100V is applied between the source electrode and the drain electrode, the drain leakage current value at an operating temperature of 600K is 1 × 10⁻¹⁰ -3 The semiconductor device according to [6] or [7], wherein the A / mm is less than A / mm.

[0012] [9] A semiconductor device comprising a substrate, a semiconductor stacked structure, a source electrode, a gate electrode and a drain electrode, The semiconductor stacked structure includes a first semiconductor layer made of a first nitride semiconductor formed on the substrate, and a second semiconductor layer formed on the first semiconductor layer and made of a second nitride semiconductor having a larger band gap than the first nitride semiconductor. When a reverse bias of 10V is applied between the gate electrode and the source electrode, and a forward bias of 20V is applied between the source electrode and the drain electrode, the drain leakage current value at an operating temperature of 400K is 3 × 10⁻¹⁰. -5 Semiconductor equipment with an A / mm ratio of less than 1 / mm.

[10] When a reverse bias of 10 V is applied between the gate electrode and the source electrode and a forward bias of 20 V is applied between the source electrode and the drain electrode, the drain leakage current value at an operating temperature of 500 K is 1.5×10 -4 A / mm or less, the semiconductor device according to [9] above.

[11] When a reverse bias of 10 V is applied between the gate electrode and the source electrode and a forward bias of 20 V is applied between the source electrode and the drain electrode, the drain leakage current value at an operating temperature of 600 K is 1×10 -3 A / mm or less, the semiconductor device according to [9] or

[10] above.

[0013]

[12] The first nitride semiconductor contains GaN, The second nitride semiconductor is Al[[ID=一三]] x Ga 1-x N (0 <x <1), the semiconductor device according to any one of [1] to

[11] above.

[13] The substrate is a GaN substrate, the semiconductor device according to any one of [1] to

[12] above.

[14] The resistivity of the GaN substrate at 400 K is 1×10 7 Ωcm or more, the semiconductor device according to

[13] above.

[15] The resistivity of the GaN substrate at 500 K is 1×10 6 Ωcm or more, the semiconductor device according to

[13] or

[14] above.

[16] The resistivity of the GaN substrate at 600 K is 1×10 5 Ωcm or more, the semiconductor device according to any one of

[13] to

[15] above.

[17] The GaN substrate is a Mn-doped GaN substrate, the semiconductor device according to any one of

[13] to

[16] above.

Advantages of the Invention

[0014] The semiconductor device according to this embodiment effectively suppresses leakage current during operation in high-temperature environments. Therefore, it is highly suitable for application in environments requiring high-speed operation under high-temperature conditions. [Brief explanation of the drawing]

[0015] [Figure 1] Figure 1 is a schematic cross-sectional view showing an example of a semiconductor device according to this embodiment. [Figure 2] Figure 2 is a graph showing the resistivity measurement results for the GaN substrates used in Example 1 and Comparative Example 1. [Figure 3] Figure 3 is a graph showing the results of two-terminal measurements in the semiconductor device according to Example 1. [Figure 4] Figure 4 is a graph showing the results of a 3-terminal measurement in the semiconductor device according to Example 1. [Figure 5] Figure 5 is a graph showing the results of two-terminal measurements in the semiconductor device according to Comparative Example 1. [Figure 6] Figure 6 is a graph showing the results of 3-terminal measurements in the semiconductor device according to Comparative Example 1. [Modes for carrying out the invention]

[0016] The present invention will be described in detail below, but the present invention is not limited to the embodiments described below and can be implemented with various modifications within the scope of its gist. In this specification, the crystal axis parallel to the

[0001] axis is called the c-axis, the crystal axis parallel to the <10-10> axis is called the m-axis, and the crystal axis parallel to the <11-20> axis is called the a-axis. The crystal plane perpendicular to the c-axis is called the c-plane. The Miller indices (hkil) of a hexagonal crystal are sometimes written with three digits, (hkl), because the relationship h+k=-i holds. For example, (0004) is written with three digits as (004). In this specification, when crystal axes, crystal planes, crystal orientations, etc. are referred to, unless otherwise specified, they refer to the crystal axes, crystal planes, crystal orientations, etc., in the substrate or semiconductor layer, respectively. In this specification, the Mn concentration and Fe concentration at a specific location are both values ​​determined by the respective detection levels using secondary ion mass spectrometry (SIMS). In this specification, when the expression "~" is used, it is used to include the numerical value or physical property value before and after it. That is, "A~B" means that it is greater than or equal to A and less than or equal to B. In this specification, the gate electrode and the semiconductor are Schottky junctions. Therefore, applying a voltage so that the gate electrode becomes the positive electrode is defined as "forward bias," and applying a voltage so that the gate electrode becomes the negative electrode is defined as "reverse bias." Between the source electrode and the drain electrode, following the common academic notation, applying a voltage so that the drain electrode becomes the positive electrode is defined as "forward bias."

[0017] [Semiconductor device] The semiconductor device according to the first embodiment comprises a substrate, a semiconductor stacked structure, a source electrode, a gate electrode, and a drain electrode. The semiconductor stacked structure includes a first semiconductor layer made of a first nitride semiconductor formed on the substrate, and a second semiconductor layer formed on the first semiconductor layer and made of a second nitride semiconductor having a larger band gap than the first nitride semiconductor. The semiconductor device has a gate leakage current of 2 × 10⁻¹⁰ at an operating temperature of 400K when a reverse bias of 100V is applied between the gate electrode and the drain electrode. -5 It is less than or equal to A / mm.

[0018] The gate leakage current value at an operating temperature of 400K is 2 × 10⁻¹⁰ when a reverse bias of 100V is applied between the gate electrode and the drain electrode. -5 A value of A / mm or less means that the gate leakage current in high-temperature environments is effectively suppressed when the semiconductor device is in the off state. This prevents large gate leakage currents from flowing and causing device failure when the semiconductor device is operated in a high-temperature environment. In this specification, a high-temperature environment refers to an environment of 50°C or higher, and may be, for example, 100°C or higher, or 150°C or higher. There is no particular upper limit, but it is usually 500°C or lower.

[0019] The gate leakage current value at an operating temperature of 400K when a reverse bias of 100V is applied between the gate electrode and the drain electrode is 2 × 10⁻⁶. -5 While a value of A / mm or less is acceptable, from the perspective of reducing the risk of equipment failure due to gate leakage current, 1.5 × 10⁻⁶ is preferable. -5 A / mm or less is preferred, and 1 × 10 -5 A / mm or less is more preferable. A smaller gate leakage current value is preferable, but typically 1.0 × 10⁻⁶ is preferable. -8 The value will be A / mm or higher.

[0020] Furthermore, it is desirable that the gate leakage current of the semiconductor device be suppressed even in higher operating environments. From this perspective, the gate leakage current value at an operating temperature of 500K when a reverse bias of 100V is applied between the gate electrode and the drain electrode should be 1 × 10⁻¹⁰ -4 Preferably less than A / mm, 8 × 10 -5 A / mm or less is preferred, and 5 × 10 -5 A / mm or less is more preferable, 3 × 10 -5 A value of A / mm or less is even more preferable. When the gate leakage current at an operating temperature of 500K is within the above range, the risk of equipment failure due to gate leakage current can be further reduced. A smaller gate leakage current value is preferable, but typically 1.0 × 10⁻⁶ is preferable. -8 The value will be A / mm or higher.

[0021] The semiconductor device according to the second embodiment comprises a substrate, a semiconductor stacked structure, a source electrode, a gate electrode, and a drain electrode. The semiconductor stacked structure includes a first semiconductor layer formed on the substrate and made of a first nitride semiconductor, and a second semiconductor layer formed on the first semiconductor layer and made of a second nitride semiconductor having a larger band gap than the first nitride semiconductor. The semiconductor device has a gate leakage current of 1 × 10⁻¹⁰ at an operating temperature of 400K when a reverse bias of 20V is applied between the gate electrode and the drain electrode. -5 It is less than or equal to A / mm.

[0022] The gate leakage current at an operating temperature of 400K is 1 × 10⁻¹⁰ when a reverse bias of 20V is applied between the gate electrode and the drain electrode. -5 A value of A / mm or less means that the gate leakage current in high-temperature environments is effectively suppressed when the semiconductor device is in the off state. This prevents large gate leakage currents from flowing and causing device failure when the semiconductor device is operated in a high-temperature environment.

[0023] The gate leakage current value at an operating temperature of 400K when a reverse bias of 20V is applied between the gate electrode and the drain electrode is 1 × 10⁻⁶ -5 While a value of A / mm or less is acceptable, from the perspective of reducing the risk of equipment failure due to gate leakage current, 8 × 10 -6 A / mm or less is preferred, and 5 × 10 -6 A / mm or less is more preferable, 2 × 10 -6 A value of A / mm or less is particularly preferred. A smaller gate leakage current value is preferable, but typically 1.0 × 10⁻⁶ is preferable. -8 The value will be A / mm or higher.

[0024] Furthermore, it is desirable that the gate leakage current of the semiconductor device be suppressed even in higher operating environments. From this perspective, the gate leakage current value at an operating temperature of 500K when a reverse bias of 20V is applied between the gate electrode and the drain electrode should be 4 × 10⁻¹⁰ -5 Preferably A / mm or less, 2 × 10 -5 A / mm or less is preferred, and 1 × 10 -5 A / mm or less is more preferable, 8×10 -6 A / mm or less is even more preferable, 5 × 10 -6A value of A / mm or less is particularly preferred. When the gate leakage current at an operating temperature of 500K is within the above range, the risk of equipment failure due to gate leakage current can be further reduced. A smaller gate leakage current value is preferable, but typically 1.0 × 10⁻⁶ is preferable. -8 The value will be A / mm or higher.

[0025] From a similar perspective, it is desirable that semiconductor devices suppress gate leakage current even in higher operating environments. From this viewpoint, the gate leakage current value at an operating temperature of 600K when a reverse bias of 20V is applied between the gate electrode and the drain electrode should be 1 × 10⁻¹⁰ -4 It is preferable that the A / mm is less than 9 × 10 -5 A / mm or less is preferred, and 8 × 10 -5 A / mm or less is more preferable. When the gate leakage current at an operating temperature of 600K is within the above range, the risk of equipment failure due to gate leakage current can be further reduced. A smaller gate leakage current value is preferable, but typically 1.0 × 10⁻⁶ is preferable. -8 The value will be A / mm or higher.

[0026] The semiconductor device according to the third embodiment comprises a substrate, a semiconductor stacked structure, a source electrode, a gate electrode, and a drain electrode. The semiconductor stacked structure includes a first semiconductor layer made of a first nitride semiconductor formed on the substrate, and a second semiconductor layer formed on the first semiconductor layer and made of a second nitride semiconductor having a larger band gap than the first nitride semiconductor. The semiconductor device, with a reverse bias of 10V applied between the gate electrode and source electrode, and a forward bias of 100V applied between the source electrode and drain electrode, exhibits a drain leakage current of 5 × 10¹⁰ at an operating temperature of 400K. -5 It is less than A / mm.

[0027] When a reverse bias of 10V is applied between the gate electrode and the source electrode, and a forward bias of 100V is applied between the source electrode and the drain electrode, the drain leakage current value at an operating temperature of 400K is 5 × 10⁻¹⁰. -5A value of less than A / mm means that the drain leakage current in high-temperature environments is effectively suppressed when the semiconductor device is in the off state. This prevents large drain leakage currents from flowing and causing device failure when the semiconductor device is operated in a high-temperature environment.

[0028] When a reverse bias of 10V is applied between the gate electrode and the source electrode, and a forward bias of 100V is applied between the source electrode and the drain electrode, the drain leakage current value at an operating temperature of 400K is 5 × 10⁻¹⁰ -5 While a value of less than A / mm is acceptable, from the perspective of reducing the risk of equipment failure due to drain leakage current, 4 × 10 -5 A / mm or less is preferred, and 3 × 10 -5 A / mm or less is more preferable, 2 × 10 -5 A value of A / mm or less is even more preferable. A smaller drain leakage current value is preferable, but typically 1.0 × 10⁻⁶ is preferable. -8 The value will be A / mm or higher.

[0029] Furthermore, it is desirable that the drain leakage current of the semiconductor device be suppressed even in higher operating environments. From this perspective, when a reverse bias of 10V is applied between the gate electrode and the source electrode, and a forward bias of 100V is applied between the source electrode and the drain electrode, the drain leakage current value at an operating temperature of 500K should be 5 × 10⁻⁶. -4 Preferably less than A / mm, 2 × 10 -4 A / mm or less is preferred, and 1 × 10 -4 A / mm or less is more preferable, 8×10 -5 A / mm or less is even more preferable, 6 × 10 -5 A value of A / mm or less is particularly preferred. When the drain leakage current at an operating temperature of 500K is within the above range, the risk of equipment failure due to drain leakage current can be further reduced. A smaller drain leakage current value is preferable, but typically 1.0 × 10⁻⁶ is preferable. -8 The value will be A / mm or higher.

[0030] From a similar perspective, it is desirable that semiconductor devices suppress drain leakage current even in higher operating environments. From this perspective, when a reverse bias of 10V is applied between the gate electrode and the source electrode, and a forward bias of 100V is applied between the source electrode and the drain electrode, the drain leakage current value at an operating temperature of 600K should be 1 × 10⁻¹⁰ -3 It is preferable that the A / mm is less than 9 × 10 -4 A / mm or less is preferred, and 8 × 10 -4 A / mm or less is more preferable. When the drain leakage current at an operating temperature of 600K is within the above range, the risk of equipment failure due to drain leakage current can be further reduced. A smaller drain leakage current value is preferable, but typically 1.0 × 10⁻⁶ is preferable. -8 The value will be A / mm or higher.

[0031] The semiconductor device according to the fourth embodiment comprises a substrate, a semiconductor stacked structure, a source electrode, a gate electrode, and a drain electrode. The semiconductor stacked structure includes a first semiconductor layer made of a first nitride semiconductor formed on the substrate, and a second semiconductor layer formed on the first semiconductor layer and made of a second nitride semiconductor having a larger band gap than the first nitride semiconductor. The semiconductor device, with a reverse bias of 10V applied between the gate electrode and source electrode, and a forward bias of 20V applied between the source electrode and drain electrode, exhibits a drain leakage current of 3 × 10⁻¹⁰ at an operating temperature of 400K. -5 It is less than A / mm.

[0032] When a reverse bias of 10V is applied between the gate electrode and the source electrode, and a forward bias of 20V is applied between the source electrode and the drain electrode, the drain leakage current value at an operating temperature of 400K is 3 × 10⁻¹⁰. -5 A value of less than A / mm means that the drain leakage current in high-temperature environments is effectively suppressed when the semiconductor device is in the off state. This prevents large drain leakage currents from flowing and causing device failure when the semiconductor device is operated in a high-temperature environment.

[0033] When a reverse bias of 10V is applied between the gate electrode and the source electrode, and a forward bias of 20V is applied between the source electrode and the drain electrode, the drain leakage current value at an operating temperature of 400K is 3 × 10⁻¹⁰ -5 While a value of less than A / mm is acceptable, from the perspective of reducing the risk of equipment failure due to drain leakage current, 1 × 10 -5 A / mm or less is preferred, and 8 × 10 -6 A / mm or less is more preferable, 6 × 10 -6 A value of A / mm or less is even more preferable. A smaller drain leakage current value is preferable, but typically 1.0 × 10⁻⁶ is preferable. -8 The value will be A / mm or higher.

[0034] Furthermore, it is desirable that the drain leakage current of the semiconductor device be suppressed even in higher operating environments. From this perspective, when a reverse bias of 10V is applied between the gate electrode and the source electrode, and a forward bias of 20V is applied between the source electrode and the drain electrode, the drain leakage current value at an operating temperature of 500K should be 1.5 × 10⁻¹⁰. -4 Preferably A / mm or less, 1 × 10 -4 A / mm or less is preferred, and 8 × 10 -5 A / mm or less is more preferable, 5 × 10 -5 A / mm or less is even more preferable, 3 × 10 -5 A value of A / mm or less is particularly preferred. When the drain leakage current at an operating temperature of 500K is within the above range, the risk of equipment failure due to drain leakage current can be further reduced. A smaller drain leakage current value is preferable, but typically 1.0 × 10⁻⁶ is preferable. -8 The value will be A / mm or higher.

[0035] From a similar perspective, it is desirable that semiconductor devices suppress drain leakage current even in higher operating environments. From this perspective, when a reverse bias of 10V is applied between the gate electrode and source electrode, and a forward bias of 20V is applied between the source electrode and drain electrode, the drain leakage current value at an operating temperature of 600K should be 1 × 10⁻¹⁰ -3 Preferably less than A / mm, 8 × 10 -4A / mm or less is preferred, and 5 × 10 -4 A / mm or less is more preferable, 3 × 10 -4 A value of A / mm or less is particularly preferred. When the drain leakage current at an operating temperature of 600K is within the above range, the risk of equipment failure due to drain leakage current can be further reduced. A smaller drain leakage current value is preferable, but typically 1.0 × 10⁻⁶ is preferable. -8 The value will be A / mm or higher.

[0036] ·composition Figure 1 is a schematic cross-sectional view showing an example of a semiconductor device according to this embodiment. In the semiconductor device 10, a semiconductor stacked structure 200 is formed on a substrate 100. The semiconductor stacked structure 200 includes a first semiconductor layer 300 and a second semiconductor layer 400 in order, and optionally also includes a cap layer 500. A source electrode 600S, a drain electrode 600D, and a gate electrode 600G are formed on a semiconductor stacked structure 200. A gate insulating film 700 is optionally formed between the source electrode 600S and the gate electrode 600G, and between the drain electrode 600D and the gate electrode 600G. The first semiconductor layer 300 is a layer made of a first nitride semiconductor, and for example, it consists of a C-containing GaN layer 301 and an i-GaN layer 302. The C-containing GaN layer 301 is preferably formed on the substrate 100, and the i-GaN layer 302 is preferably formed on the C-containing GaN layer 301. The second semiconductor layer 400 is a layer made of a second nitride semiconductor, and is preferably formed on, for example, the i-GaN layer 302 that constitutes the first semiconductor layer 300. When the semiconductor stacked structure 200 includes a cap layer 500, it is preferable that the cap layer 500 is formed on the second semiconductor layer 400. The source electrode 600S, drain electrode 600D, and gate electrode 600G are each formed on the cap layer 500.

[0037] ·substrate In any of the first to fourth embodiments of the present invention (which may be collectively referred to as "this embodiment"), the semiconductor device includes a substrate. The substrate is not particularly limited, but may be a silicon substrate, sapphire substrate, SiC substrate, or GaN substrate. Among these, a GaN substrate is preferred from the viewpoint of having high crystal quality in the nitride semiconductor layer epitaxially grown on the substrate and excellent device performance.

[0038] If the substrate is a GaN substrate, the resistivity at 400K is 1 × 10⁻¹⁶. 7 A value of Ωcm or greater is even more preferable. The inventors have found that the resistivity of the GaN substrate at 400K is 1 × 10⁻⁶. 7 We found that when the current is greater than Ωcm, the drain leakage current during high-temperature operation of semiconductor devices is significantly suppressed. The reason for this is still unclear, but we believe it is as follows. In other words, within the HEMT structure, the expansion of the depletion layer inhibits drain leakage current, but under high-temperature conditions, the resistivity of the substrate decreases, which is thought to allow drain leakage current to flow through the substrate. Based on this finding, it is thought that using a GaN substrate that has high resistivity even under high-temperature conditions for semiconductor devices will effectively suppress drain leakage current during high-temperature operation of semiconductor devices.

[0039] Furthermore, the resistivity of the GaN substrate at 400K is 1 × 10⁻¹⁶. 7 We found that when the current is greater than Ωcm, the gate leakage current during high-temperature operation of semiconductor devices is also significantly suppressed. The causes of gate leakage current are said to be surface current between the source electrode and gate electrode, defects in the channel layer, etc., but the detailed mechanism is unknown. The mechanism of gate leakage current generation in this embodiment is also unknown, but since the change in the resistivity of the substrate leads to a change in the gate leakage current, it is thought that the resistivity of the substrate affects the potential near the channel layer, and as a result the depletion layer distribution changes, causing a change in the gate leakage current.

[0040] From the above perspective, the resistivity of the GaN substrate at 400K is 1 × 10⁻¹⁶. 7 Preferably, it is Ωcm or more, 1 × 1010 More preferably, it is 1×10 12 Ωcm or more, still more preferably 1×10 15 Ωcm or more, and particularly preferably 1×10

[0041] From the same perspective, the GaN substrate preferably has a resistivity of 1×10 6 Ωcm or more at 500K, more preferably 1×10 9 Ωcm or more, still more preferably 1×10 11 Ωcm or more, and particularly preferably 1×10 12 Ωcm or more at 500K. Since the higher the resistivity at 500K, the better, the upper limit is not particularly limited.

[0042] From the same perspective, the GaN substrate preferably has a resistivity of 1×10 5 Ωcm or more at 600K, more preferably 1×10 7 Ωcm or more, still more preferably 1×10 8 Ωcm or more, and particularly preferably 1×10 9 Ωcm or more at 600K. Since the higher the resistivity at 600K, the better, the upper limit is not particularly limited.

[0043] The substrate is preferably a substrate doped with Mn, that is, a GaN substrate having a Mn-doped layer. In this case, the thickness of the Mn-doped layer in the c-axis direction does not necessarily have to match the thickness of the GaN substrate in the c-axis direction.

[0044] For example, when the thickness of the entire GaN substrate is 400μm, the thickness of the Mn-doped layer being 100μm in the surface layer of the GaN substrate is sufficient. Of course, the thickness of the Mn-doped layer is not limited to the above, and cases where it is thicker or thinner are not excluded at all, and a GaN substrate in which the entire thickness direction of the GaN substrate is composed of a Mn-doped layer may also be acceptable.

[0045] The Mn concentration in the Mn-doped layer of the GaN substrate is 1.0×10 16 atoms / cm 3The above 1.0 × 10 20 atoms / cm 3 The following is preferable: Since Mn, a compensating impurity, contributes to increased resistance, the Mn concentration should be 1.0 × 10⁻⁶. 16 atoms / cm 3 The above is preferable from the viewpoint of increasing the resistance of the GaN crystal, and also 1.0 × 10 20 atoms / cm 3 The following is preferable from the viewpoint of maintaining good crystal quality of the GaN crystal.

[0046] The Mn concentration in the Mn-doped layer of the GaN substrate is increased in the following steps, with an upper limit of 6.0 × 10⁻⁶ 19 atoms / cm 3 Below, 5.0 × 10 19 atoms / cm 3 Below, 3.0 × 10 19 atoms / cm 3 Below, 1.0 × 10 19 atoms / cm 3 Below, 5.0 × 10 18 atoms / cm 3 Preferably, the values ​​are as follows, with a lower limit of 1.0 × 10⁻⁶. 16 atoms / cm 3 The above is 3.0 × 10 16 atoms / cm 3 The above is 5.0 x 10 16 atoms / cm 3 The above is 1.0 × 10 17 atoms / cm 3 The above is 3.0 × 10 17 atoms / cm 3 The above is 5.0 x 10 17 atoms / cm 3 The above is preferable. The preferred combination of upper and lower limits for the Mn concentration is arbitrary.

[0047] • Semiconductor stacked structure The semiconductor device according to this embodiment comprises a semiconductor stacked structure including a first semiconductor layer made of a first nitride semiconductor formed on a substrate, and a second semiconductor layer formed on the first semiconductor layer and made of a second nitride semiconductor having a larger band gap than the first nitride semiconductor.

[0048] ··First semiconductor layer The first semiconductor layer is a nitride semiconductor crystal layer formed on a substrate, consisting of a first nitride semiconductor. A preferred example of the first nitride semiconductor is GaN. When the first nitride semiconductor is GaN, the first semiconductor layer preferably includes a carbon (C)-containing GaN layer and an i-GaN layer. The first semiconductor layer may consist of one layer or two or more layers, and may further include a crystalline phase made of GaN other than the C-containing GaN layer and the i-GaN layer.

[0049] ...C-containing GaN layer The first semiconductor layer has a carbon (C) concentration of 1 × 10⁻¹⁶ 16 atoms / cm 3 It is preferable to include a C-containing GaN layer as described above. The C-containing GaN layer is a crystalline layer made of epitaxially grown GaN that contains carbon (C) as an impurity. The presence of a carbon-containing GaN layer inhibits the movement of compensating impurities between different regions demarcated by the carbon-containing GaN layer. For example, if the substrate is Mn-doped, the Mn in the substrate may move through the HEMT structure as a compensating impurity through thermal diffusion and reach the 2DEG region. When compensating impurities such as Mn diffuse into the 2DEG region, electron movement in the 2DEG region is inhibited, which may degrade the performance of the semiconductor device. On the other hand, if a C-containing GaN layer is present, the movement of compensating impurities is inhibited, thus suppressing the degradation of the semiconductor device's performance.

[0050] The carbon concentration in the carbon-containing GaN layer is 1 × 10⁻¹⁶ 16 atoms / cm 3 The above is preferable, and from the viewpoint of more effectively inhibiting the movement of compensating impurities, 5 × 10 16 atoms / cm 3 The above is more preferable, 1 × 10 17 atoms / cm 3 The above is even more preferable. Furthermore, the C concentration in the C-containing GaN layer should be 1 × 10⁻¹⁶, from the viewpoint of preventing the occurrence of defects such as through-dislocations.19 atoms / cm 3 Less than 1 × 10 is preferable. 18 atoms / cm 3 Less than 5 × 10 17 atoms / cm 3 Less than is even preferable.

[0051] From the viewpoint of fabricating a normal device, the thickness of the C-containing GaN layer in the c-axis direction is preferably 50 nm or more, more preferably 100 nm or more, and even more preferably 200 nm or more. Furthermore, from the viewpoint of reducing leakage current, the thickness of the C-containing GaN layer is preferably 900 nm or less, more preferably 600 nm or less, and even more preferably 500 nm or less.

[0052] From the viewpoint of successful device fabrication, the thickness of the C-containing GaN layer in the c-axis direction is preferably 5% or more, more preferably 10% or more, and even more preferably 20% or more of the total thickness of the first semiconductor layer. Similarly, from the same viewpoint, the above thickness is preferably 90% or less, more preferably 80% or less, and even more preferably 70% or less of the total thickness of the first semiconductor layer. The total thickness of the first semiconductor layer refers to the total thickness in the c-axis direction, including the i-GaN layer and other layers described later, if the first semiconductor layer contains the C-containing GaN layer.

[0053] ...i-GaN layer In this embodiment, when the first semiconductor layer includes the above-mentioned C-containing GaN layer, it is preferable that the first semiconductor layer has an i-GaN layer in the

[0001] axial direction relative to the C-containing GaN layer. It is even more preferable that the i-GaN layer is directly disposed on the C-containing GaN layer. Having an i-GaN layer in the

[0001] axis direction relative to the C-containing GaN layer means that the i-GaN layer exists in the +c axis direction relative to the C-containing GaN layer, i.e., in the direction of the Ga polarity plane of the crystal.

[0054] The i-GaN layer is a crystalline layer made of GaN that is epitaxially grown without intentional impurity doping, and is distinguished from the C-containing GaN layer by its C concentration. Specifically, the C concentration of the i-GaN layer is 1 × 10⁻¹⁶. 16atoms / cm 3 is less than. The i-GaN layer functions as a so-called channel layer.

[0055] The thickness of the first semiconductor layer in the c-axis direction is preferably as thin as possible in order to reduce the drain leakage current during HEMT operation. From the perspective of normal device fabrication, the thickness of the i-GaN layer in the first semiconductor layer is preferably 50 nm or more, more preferably 100 nm or more, and even more preferably 200 nm or more. Also, from the perspective of reducing the leakage current, the thickness of the i-GaN layer is preferably 900 nm or less, more preferably 600 nm or less, and even more preferably 500 nm or less. The upper end surface of the i-GaN layer in the first semiconductor layer preferably coincides with the upper end surface of the first semiconductor layer.

[0056] ···Second semiconductor layer The second semiconductor layer is formed on the first semiconductor layer and is composed of a second nitride semiconductor having a larger bandgap than the first nitride semiconductor. The second nitride semiconductor is not particularly limited as long as its bandgap is larger than that of the first nitride semiconductor. For example, when the first nitride semiconductor is GaN, the second nitride semiconductor is preferably Al x Ga 1-x N(0 < x < 1) or AlInGaN. The second semiconductor layer may consist of one layer or two or more layers.

[0057] A two-dimensional electron gas (2DEG) is formed at the heterointerface between the first semiconductor layer and the second semiconductor layer. Specifically, when the first semiconductor layer has the above-mentioned i-GaN layer, a 2DEG is generated in the region sandwiched between the i-GaN layer and the second semiconductor layer. The second semiconductor layer functions as a so-called barrier layer or electron supply layer.

[0058] As a typical example, GaN (first semiconductor layer) / Al x Ga 1-xIn the hetero-structure of N(0 < x < 1) (the second semiconductor layer), a 2DEG is generated at the hetero-interface due to spontaneous polarization and piezoelectric polarization, and a sheet carrier concentration of 1×10 13 cm -2 or more can be obtained without doping anything, so high-frequency operation is realized.

[0059] From the perspective of normal device fabrication, the thickness of the second semiconductor layer in the c-axis direction is preferably 1 nm or more, more preferably 5 nm or more, and even more preferably 10 nm or more. Also, from the perspective of reducing leakage current, the thickness of the second semiconductor layer is preferably 50 nm or less, more preferably 40 nm or less, and even more preferably 30 nm or less. When the second semiconductor layer is composed of layers of two or more second nitride semiconductors, the above thickness is the total film thickness of the second semiconductor layer.

[0060] ··Cap layer The semiconductor stack structure includes a first semiconductor layer and a second semiconductor layer, but a cap layer may further be formed on the second semiconductor layer. The cap layer is preferably made of a nitride semiconductor different from the second nitride semiconductor. For example, when the second nitride semiconductor is Al x Ga 1-x N(0 < x < 1) or AlInGaN, it is preferably a cap layer made of GaN. The cap layer may consist of one layer or two or more layers.

[0061] From the perspective of normal device fabrication, the thickness of the cap layer in the c-axis direction is preferably 0.1 nm or more, more preferably 0.5 nm or more, and even more preferably 1 nm or more. Also, from the perspective of reducing leakage current, the thickness of the cap layer is preferably 10 nm or less, more preferably 8 nm or less, and even more preferably 5 nm or less. When the cap layer is composed of two or more layers, the above thickness is the total film thickness of the cap layer.

[0062] ·Electrode The semiconductor device according to this embodiment comprises a source electrode, a gate electrode, and a drain electrode. Preferably, the source electrode, gate electrode, and drain electrode are formed above the semiconductor stacked structure described above.

[0063] The source electrode is, for example, a metal electrode, specifically a multilayer structure containing titanium (Ti) and aluminum (Al), a multilayer structure containing molybdenum (Mo) and aluminum (Al), and so on.

[0064] The drain electrode is, for example, a metal electrode, specifically a multilayer structure containing titanium (Ti) and aluminum (Al), a multilayer structure containing molybdenum (Mo) and aluminum (Al), and so on.

[0065] It is preferable that the source electrode and drain electrode and the semiconductor stacked structure are ohmic-junctioned. The distance between the source electrode and the drain electrode is, for example, 5 μm to 30 μm.

[0066] The gate electrode is, for example, a metal electrode, specifically a multilayer structure containing nickel (Ni) and gold (Au), or a multilayer structure containing platinum (Pt) and gold (Au). The gate length is, for example, 1 μm to 15 μm. The gate electrode is preferably formed between the source electrode and the drain electrode. The distance between the gate electrode and the source electrode is, for example, 1 μm to 15 μm.

[0067] A gate insulating film may be present between the gate electrode and the semiconductor stacked structure. That is, the gate electrode may be formed above the semiconductor stacked structure via the gate insulating film. Furthermore, gate insulating films may be provided between the gate electrode and the source electrode, and between the gate electrode and the drain electrode.

[0068] The gate insulating film is, for example, an oxide or oxynitride. The gate insulating film is, for example, silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, or aluminum oxynitride.

[0069] In one preferred embodiment, a source electrode, a gate electrode, and a drain electrode are formed on a cap layer, and more preferably, a gate insulating film is provided between the source electrode and the gate electrode, and between the gate electrode and the drain electrode. In another preferred embodiment, a source electrode and a drain electrode are formed on the second semiconductor layer, and a gate electrode is formed on the cap layer. In another preferred embodiment, source electrodes and drain electrodes are formed on the cap layer, and a gate electrode is formed on the gate insulating film.

[0070] ·Applications The semiconductor device according to this embodiment can suppress leakage current when high-speed operation in high-temperature environments is required, and therefore can be suitably used for communication and other applications in high-temperature environments such as deserts and space.

[0071] [Manufacturing method for semiconductor devices] The method for manufacturing the semiconductor device according to this embodiment is not particularly limited, but one example embodiment is described below. Furthermore, preferred embodiments of the semiconductor device obtained by this manufacturing method are the same as the preferred embodiments described above in [Semiconductor Device]. The above embodiment of the method for manufacturing a semiconductor device includes at least the steps of: preparing a substrate; forming a semiconductor stacked structure on the substrate; and generating electrodes above the semiconductor stacked structure.

[0072] • How to prepare a circuit board The substrate used in the semiconductor device according to this embodiment is not particularly limited, as described above under [Semiconductor Device], but is preferably a GaN substrate, with a resistivity of 1 × 10 at 400K. 7A GaN substrate with a density of Ωcm or greater is more preferable. Alternatively, a GaN substrate having a Mn-doped layer may also be used.

[0073] The above-mentioned substrate may be manufactured and used by known methods, or it may be a commercially available product. When manufacturing a GaN substrate, the process of preparing the above-mentioned substrate is the process of manufacturing the GaN substrate. The resistivity at 400K is 1 × 10⁻⁶. 7 GaN substrates with a density of Ωcm or greater can be obtained, for example, by growing bulk GaN crystals on a seed using the HVPE (Hydride Vapor Phase Epitaxy) method while doping with compensating impurities such as Mn, and then performing processing such as slicing, grinding, and polishing. Mn-doped GaN substrates can be obtained, for example, by growing Mn-doped bulk GaN crystals on a seed using the HVPE method, and then performing processing such as slicing, grinding, and polishing.

[0074] • Method for forming a semiconductor stacked structure The semiconductor stacked structure includes a first semiconductor layer made of a first nitride semiconductor formed on a substrate, and a second semiconductor layer made of a second nitride semiconductor having a larger band gap than the first nitride semiconductor, formed on the first semiconductor layer. Therefore, the method for forming the semiconductor stacked structure includes the steps of forming the first semiconductor layer on a substrate and forming the second semiconductor layer on the first semiconductor layer.

[0075] The method for forming the first semiconductor layer on the substrate is not particularly limited, and various known methods can be employed. However, preferred examples include the use of MOCVD (metal-organic chemical vapor deposition) or molecular beam epitaxy (MBE). The following describes in detail a method for forming a first semiconductor layer made of GaN.

[0076] When using the MOCVD method, the raw material gas is not particularly limited as long as it contains a Ga source and an N source for forming GaN, and any known raw material gas can be used.

[0077] When forming a carbon-containing GaN layer by doping the first semiconductor layer with carbon, the carbon concentration is 1 × 10⁻⁶. 16 atoms / cm 3 As described above, the thickness in the c-axis direction (height in the thickness direction) of the C-containing GaN layer is preferably 50 nm or more from the viewpoint of normal device fabrication, and preferably 900 nm or less from the viewpoint of reducing leakage current.

[0078] The concentration of carbon in the carbon-containing GaN layer is 1 × 10⁻⁶. 16 atoms / cm 3 The above is acceptable, but the concentration is 5 × 10 16 atoms / cm 3 The above, or 1 x 10 17 atoms / cm 3 That's all.

[0079] The concentration of carbon in the carbon-containing GaN layer is set to 1 × 10⁻¹⁶ to avoid a significant decrease in crystal quality due to excessive doping. 19 atoms / cm 3 Less than 1 × 10 is preferable. 18 atoms / cm 3 Less than, or 5 x 10 17 atoms / cm 3 "Less than" is also acceptable.

[0080] C doping can be performed using conventionally known methods. For example, MOCVD or MBE methods are preferred.

[0081] When using the MOCVD method, hydrocarbon gases such as CH4 (methane) can be used as the raw material gas. However, from the viewpoint of simplification, it is preferable to use a raw material gas that also includes a Ga source and an N source for forming GaN. From this viewpoint, it is preferable to use trimethylgallium (TMG) or triethylgallium (TEG) as the C raw material gas, with TMG being more preferable. Furthermore, it is even more preferable to use a mixed gas of TMG and ammonia (NH3) or a mixed gas of TEG and NH3.

[0082] When using a mixed gas of trimethylgallium (TMG) and ammonia (NH3), the TMG supply rate is preferably 100 μmol / min or higher, and more preferably 200 μmol / min or higher, from the viewpoint of reducing the concentration of impurities such as Si. Furthermore, from the viewpoint of film thickness controllability, the TMG supply rate is preferably 500 μmol / min or lower, and more preferably 300 μmol / min or lower. Furthermore, the ratio of the supply rate expressed as TMG:NH3 is preferably 1:100 to 1:4000, more preferably 1:500 to 1:4000 or 1:100 to 1:2000, and even more preferably 1:500 to 1:2000, from the viewpoint of controllability of the C concentration.

[0083] As described above, a C-containing GaN layer may be formed as the first semiconductor layer, followed by the formation of an i-GaN layer. The method for forming the i-GaN layer is the same as the method for forming the C-containing GaN layer, except that it is done without intentional impurity doping. Suitable examples include the MOCVD method and the MBE method.

[0084] When using the MOCVD method to form the i-GaN layer, hydrocarbon gases such as CH4 (methane) can be used as the raw material gas. However, from the viewpoint of simplification, it is preferable to use a raw material gas that also includes a Ga source and an N source for forming GaN.

[0085] When using a mixed gas of trimethylgallium (TMG) and ammonia (NH3), the supply rate of TMG is preferably 50 μmol / min or more, more preferably 100 μmol / min or more, from the viewpoint of reducing the concentration of impurities such as Si. Also, the supply rate of TMG is preferably 250 μmol / min or less, more preferably 150 μmol / min or less, from the viewpoint of film thickness controllability. Also, the ratio of the supply rates represented by TMG:NH3 is preferably 1:400 to 1:16000, more preferably 1:400 to 1:1800 or 1:2000 to 1:16000, and even more preferably 1:2000 to 1:8000, from the viewpoint of reducing the C concentration.

[0086] The thickness of the i-GaN layer in the c-axis direction in the first semiconductor layer is the same as that described in "[Semiconductor layer device] · Semiconductor laminate structure \ · First semiconductor layer \ ·· i-GaN layer", and it is preferably 50 nm or more from the viewpoint of normal device fabrication, and preferably 900 nm or less from the viewpoint of reducing leakage current.

[0087] · Method for forming the second semiconductor layer After forming the above-described first semiconductor layer, a second semiconductor layer is formed on the first semiconductor layer. The second nitride semiconductor constituting the second semiconductor layer is not particularly limited as long as its bandgap is larger than that of the first nitride semiconductor. For example, when the first nitride semiconductor is GaN, the second nitride semiconductor is preferably Al x Ga 1-x N (0 <x <1) or AlInGaN. A 2DEG is generated in the region sandwiched between the first semiconductor layer and the second semiconductor layer.

[0088] The method for forming the second semiconductor layer is not particularly limited, and a conventionally known method may be employed. Suitable examples include using the MOCVD method or the MBE method. The preferred thickness of the second semiconductor layer in the c-axis direction on the first semiconductor layer is the same as that described in "[Semiconductor layer device] · Semiconductor laminate structure \ · Second semiconductor layer".

[0089] When the above-mentioned second semiconductor layer is formed, conventionally known layers such as a cap layer can be formed by conventionally known methods as needed.

[0090] • Method for forming electrodes The electrode formation method includes the step of forming a source electrode, a gate electrode, and a drain electrode on top of a semiconductor stacked structure. The method for forming the electrodes is not particularly limited, and any conventionally known method may be used, but a preferred example is the use of photolithography.

[0091] The source electrode is, for example, a metal electrode, specifically a multilayer structure containing titanium (Ti) and aluminum (Al), a multilayer structure containing molybdenum (Mo) and aluminum (Al), and so on. The drain electrode is, for example, a metal electrode, specifically a multilayer structure containing titanium (Ti) and aluminum (Al), a multilayer structure containing molybdenum (Mo) and aluminum (Al), and so on. It is preferable that the source electrode and drain electrode and the semiconductor stacked structure are ohmic-junctioned.

[0092] The gate electrode is, for example, a metal electrode, specifically a multilayer structure containing nickel (Ni) and gold (Au), or a multilayer structure containing platinum (Pt) and gold (Au). The gate electrode is preferably formed between the source electrode and the drain electrode. Alternatively, a gate insulating film may be present between the gate electrode and the semiconductor stacked structure. That is, the gate electrode may be formed above the semiconductor stacked structure via the gate insulating film. Furthermore, gate insulating films may be present between the gate electrode and the source electrode, and between the gate electrode and the drain electrode.

[0093] The gate insulating film is, for example, an oxide or oxynitride. The gate insulating film is, for example, silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, or aluminum oxynitride. The method for forming the gate insulating film is not particularly limited, and any conventionally known method may be used. However, a preferred example is the use of PECVD (plasma-enhanced chemical vapor deposition) method. [Examples]

[0094] The present invention will be specifically described below with reference to examples, but the present invention is not limited to these examples.

[0095] [Example 1] A GaN epitaxial substrate with a HEMT structure was obtained by depositing a semiconductor stacked structure on a c-plane GaN substrate having a Mn-doped layer obtained by the HVPE method using the MOCVD method. The total thickness of the c-plane GaN substrate in the c-axis direction was 400 μm, of which the Mn-doped layer was approximately 100 μm thick on the Ga polar plane side. The Mn concentration of the Mn-doped layer was 8 × 10⁻¹⁶. 17 atoms / cm 3 That was the case. The resistivity of a c-plane GaN substrate with a Mn-doped layer at 400K is 1.0 × 10⁻⁶. 12 The resistivity at 500K for values ​​above Ωcm is 1.0 × 10⁻¹⁰. 12 The resistivity at Ωcm and 600K is 1.4 × 10⁻⁶. 10 The resistance was Ωcm. The resistivity was measured using the method described later.

[0096] Specifically, for the formation of the first semiconductor layer, a c-plane GaN substrate was placed in an MOCVD apparatus and heated to 1090°C in a hydrogen / nitrogen mixed gas atmosphere and at atmospheric pressure, while trimethylgallium (TMG) and NH3 gas were supplied. The gas supply rates were 410 μmol / min for TMG and 5 slm for NH3 gas. By growing crystals under these conditions for 2.7 minutes, a C concentration of 1 × 10⁻¹⁶ was formed in the first semiconductor layer. 17 atoms / cm 3 A C-containing GaN layer was formed. The thickness of the C-containing GaN layer was 300 nm. Next, an i-GaN layer with a thickness of 200 nm was grown on the obtained C-containing GaN layer by changing the supply rates of TMG and NH3 gases, the growth time, i.e., the gas supply amount.

[0097] As the formation of the second semiconductor layer, an Al x Ga 1-x N (0 < x < 1) layer was formed with a thickness of 18 nm on the i-GaN layer formed above. Next, a GaN cap layer was grown to a thickness of 2 nm to form a semiconductor laminated structure. As described above, a GaN epitaxial substrate having a HEMT structure including a substrate and a semiconductor layer laminated structure was obtained.

[0098] By means of photolithography, electrodes were formed on the GaN epitaxial substrate obtained above. The source electrode and the drain electrode were each deposited by electron beam with Mo(7 nm) / Al(75 nm) / Mo(50 nm) / Au(120 nm), and the gate electrode was deposited with Ni(36 nm) / Au(370 nm). The values in parentheses indicate the respective thicknesses. The gate length, the distance between the gate electrode and the source electrode, and the distance between the gate electrode and the drain electrode were 2 μm, 2 μm, and 5 μm, respectively. SiNx was formed as a gate insulating film with a thickness of 60 nm by PECVD method between the gate electrode and the source electrode, and between the gate electrode and the drain electrode, respectively. As described above, a semiconductor device having a HEMT structure (also referred to as a HEMT element) was obtained.

[0099] [Comparative Example 1] A semiconductor device having a HEMT structure (HEMT element) was obtained in the same manner as in Example 1, except that Fe was used instead of Mn as a compensation impurity to form a c-plane GaN substrate having an Fe-doped layer. The Fe-doped layer exists on the Ga-polarity plane side with a thickness of about 100 μm, and the Fe concentration in the Fe-doped layer was 3×10 18 atoms / cm 3 . The resistivity of the c-plane GaN substrate having an Fe-doped layer at 400 K was 3.2×10 6The resistivity at Ωcm and 500K is 1.2 × 10⁻¹⁰. 5 The resistivity at Ωcm and 600K is 1.5 × 10⁻⁶ 4 The resistance was Ωcm. The resistivity was measured using the method described later.

[0100] [Measurement of resistivity of the circuit board] Ti30nm and Au100nm were continuously vacuum-deposited onto the surface of a c-plane GaN substrate, and Hall measurements were performed. The four-terminal Van der Pauw method was used for Hall measurements, and resistivity (specific resistivity) was measured while varying the measurement temperature. The resistivity measurement results for Example 1 are shown as "●" in Figure 2, and the resistivity measurement results for Comparative Example 1 are shown as "▲" in Figure 2. The carrier type determined by each Hall measurement across all temperature ranges was p-type.

[0101] [Evaluation of semiconductor equipment] • 2-terminal measurement In a HEMT semiconductor device, the two-terminal reverse breakdown voltage characteristics were evaluated by applying a reverse bias between the gate electrode and the drain electrode. The HEMT element was attached to a temperature-variable stage by vacuum adsorption. The temperature of the temperature-variable stage was changed to 300K, 400K, 500K, or 600K, and the two-terminal reverse breakdown voltage characteristics were evaluated at each temperature. The results for Example 1 are shown in Figure 3, and the results for Comparative Example 1 are shown in Figure 5. Vgd represents the bias value between the gate electrode and the drain electrode, and -Ig represents the gate leakage current. In the measurement, 1 × 10 -4 The cutoff current was defined as A / mm. The cutoff current is the threshold value used to determine whether the leakage current is good or bad, and is 1 × 10⁻⁶. -4 Values ​​of A / mm or higher indicate leakage. From the results in Figures 3 and 5, the -Ig values ​​at Vgd = 100V are shown in Table 1, and the -Ig values ​​at Vgd = 20V are shown in Table 2. In Tables 1 and 2, "leak" refers to a gate leakage current value of 1 × 10⁻⁶. -4 This means it was A / mm or higher.

[0102] • 3-terminal measurement In a HEMT semiconductor device, the three-terminal breakdown voltage characteristics were evaluated by applying a reverse bias of 10V between the gate electrode and the source electrode, and a forward bias between the source electrode and the drain electrode. The HEMT element was attached to a temperature-variable stage by vacuum adsorption. The temperature of the temperature-variable stage was changed to 300K, 400K, 500K, or 600K, and the three-terminal breakdown voltage characteristics were evaluated at each temperature. The results for Example 1 are shown in Figure 4, and the results for Comparative Example 1 are shown in Figure 6. Vds represents the bias value between the source electrode and the drain electrode, and Id represents the drain leakage current. In the measurement, 1 × 10 -3 The cutoff current was defined as A / mm. The cutoff current is the threshold value used to determine whether the leakage current is good or bad, and is 1 × 10⁻⁶. -3 Values ​​of A / mm or higher indicate leakage. From the results in Figures 4 and 6, the values ​​of Id at Vds = 100V are shown in Table 3, and the values ​​of Id at Vds = 20V are shown in Table 4. In Tables 3 and 4, "leak" refers to a drain leakage current value of 1 × 10⁻⁶. -3 This means it was A / mm or higher.

[0103] From the results in Table 1, when Vgd is 100V, at an operating temperature of 400K, the HEMT element of Comparative Example 1 has a gate leakage current of 2 × 10⁻¹⁰ -5 While the A / mm value was above average, the HEMT element in Example 1 had a gate leakage current value of 2 × 10⁻⁶. -5 The value was less than A / mm, which is considerably smaller than that of Comparative Example 1. Furthermore, at operating temperatures of 500K and 600K, the gate leakage current value of the HEMT element in Comparative Example 1 exceeded the cutoff current value and was determined to be leaking, whereas at an operating temperature of 500K, the gate leakage current value of the HEMT element in Example 1 was 1 × 10⁻⁶. -4 The value was small, less than A / mm.

[0104] From the results in Table 2, when Vgd is 20V, at an operating temperature of 400K, the HEMT element of Comparative Example 1 has a gate leakage current of 1 × 10⁻¹⁰ -5 While the A / mm value was above average, the HEMT element in Example 1 had a gate leakage current value of 1 × 10⁻⁶.-5 The A / mm was less than or equal to 500K. Furthermore, at an operating temperature of 500K, the gate leakage current of the HEMT element in Comparative Example 1 was 4 × 10⁻¹⁰. -5 While the A / mm was above average, the HEMT element in Example 1 had a gate leakage current of 4 × 10⁻⁶. -5 The value was less than A / mm. At both operating temperatures of 400K and 500K, the gate leakage current value of the HEMT element in Example 1 was considerably larger than that of Comparative Example 1. Furthermore, at an operating temperature of 600K, the gate leakage current value of the HEMT element in Comparative Example 1 exceeded the cutoff current value and was judged to be a leak, whereas the HEMT element in Example 1 was 1 × 10⁻⁶ -4 The value was small, less than A / mm.

[0105] From the results in Table 3, when Vds is 100V, at an operating temperature of 400K, the HEMT element of Comparative Example 1 has a drain leakage current of 5 × 10⁻¹⁰ -5 While the value was A / mm, the HEMT element of Example 1 had a drain leakage current of 5 × 10⁻⁶. -5 The value was less than A / mm, which is smaller than that of Comparative Example 1. Also, at an operating temperature of 500K, the drain leakage current of the HEMT element in Comparative Example 1 was 5 × 10⁻⁶. -4 While the value exceeded A / mm, the HEMT element in Example 1 had a drain leakage current value of 5 × 10⁻⁶. -4 The value was less than A / mm, which was considerably smaller than that of Comparative Example 1. Furthermore, at an operating temperature of 600K, the drain leakage current value of the HEMT element in Comparative Example 1 exceeded the cutoff current value and was determined to be leaking, whereas the drain leakage current value of the HEMT element in Example 1 was 1 × 10⁻⁶. -3 The value was small, less than A / mm.

[0106] From the results in Table 4, when Vds is 20V, the drain leakage current value of Comparative Example 1 at an operating temperature of 400K is 3 × 10⁻¹⁰. -5 While the value was A / mm, the HEMT element of Example 1 had a drain leakage current of 3 × 10⁻⁶. -5The value was less than A / mm, which was smaller than that of Comparative Example 1. Furthermore, at an operating temperature of 500K, the drain leakage current of the HEMT element in Comparative Example 1 was 1.5 × 10⁻⁶. -4 While the A / mm value was higher, the HEMT element in Example 1 had a drain leakage current value of 1.5 × 10⁻⁶. -4 The value was less than A / mm, which was considerably smaller than that of Comparative Example 1. Furthermore, at an operating temperature of 600K, the drain leakage current value of the HEMT element in Comparative Example 1 exceeded the cutoff current value and was determined to be leaking, whereas the drain leakage current value of the HEMT element in Example 1 was 1 × 10⁻⁶. -3 The value was small, less than A / mm.

[0107] [Table 1]

[0108] [Table 2]

[0109] [Table 3]

[0110] [Table 4]

Claims

1. A semiconductor device comprising a substrate, a semiconductor stacked structure, a source electrode, a gate electrode, and a drain electrode, The substrate is a Mn-doped GaN substrate. The semiconductor stacked structure includes a first semiconductor layer made of a first nitride semiconductor formed on the substrate, and a second semiconductor layer formed on the first semiconductor layer and made of a second nitride semiconductor having a larger band gap than the first nitride semiconductor. When a reverse bias of 100V is applied between the gate electrode and the drain electrode, the gate leakage current value at an operating temperature of 400K is 2 × 10⁻¹⁰ －５ A semiconductor device with an A / mm or less.

2. When a reverse bias of 100V is applied between the gate electrode and the drain electrode, the gate leakage current value at an operating temperature of 500K is 1 × 10⁻¹⁰ －４ The semiconductor device according to claim 1, wherein the A / mm is less than A.

3. A semiconductor device comprising a substrate, a semiconductor stacked structure, a source electrode, a gate electrode, and a drain electrode, The substrate is a Mn-doped GaN substrate. The semiconductor stacked structure includes a first semiconductor layer made of a first nitride semiconductor formed on the substrate, and a second semiconductor layer formed on the first semiconductor layer and made of a second nitride semiconductor having a larger band gap than the first nitride semiconductor. When a reverse bias of 20V is applied between the gate electrode and the drain electrode, the gate leakage current value at an operating temperature of 400K is 1 × 10⁻¹⁰. －５ A semiconductor device with an A / mm or less.

4. When a reverse bias of 20V is applied between the gate electrode and the drain electrode, the gate leakage current value at an operating temperature of 500K is 4 × 10⁻¹⁰ －５ The semiconductor device according to claim 3, wherein the A / mm is less than or equal to A / mm.

5. When a reverse bias of 20V is applied between the gate electrode and the drain electrode, the gate leakage current value at an operating temperature of 600K is 1 × 10⁻¹⁰ －４ The semiconductor device according to claim 3 or 4, wherein the A / mm is less than A.

6. A semiconductor device comprising a substrate, a semiconductor stacked structure, a source electrode, a gate electrode, and a drain electrode, The substrate is a Mn-doped GaN substrate. The semiconductor stacked structure includes a first semiconductor layer made of a first nitride semiconductor formed on the substrate, and a second semiconductor layer formed on the first semiconductor layer and made of a second nitride semiconductor having a larger band gap than the first nitride semiconductor. When a reverse bias of 10V is applied between the gate electrode and the source electrode, and a forward bias of 100V is applied between the source electrode and the drain electrode, the drain leakage current value at an operating temperature of 400K is 5 × 10⁻¹⁰ －５ A semiconductor device with a capacitance of less than A / mm.

7. When a reverse bias of 10V is applied between the gate electrode and the source electrode, and a forward bias of 100V is applied between the source electrode and the drain electrode, the drain leakage current value at an operating temperature of 500K is 5 × 10⁻¹⁰ －４ The semiconductor device according to claim 6, wherein the A / mm is less than A.

8. When a reverse bias of 10V is applied between the gate electrode and the source electrode, and a forward bias of 100V is applied between the source electrode and the drain electrode, the drain leakage current value at an operating temperature of 600K is 1 × 10⁻¹⁰ －３ The semiconductor device according to claim 6 or 7, wherein the A / mm is less than A.

9. A semiconductor device comprising a substrate, a semiconductor stacked structure, a source electrode, a gate electrode, and a drain electrode, The substrate is a Mn-doped GaN substrate. The semiconductor stacked structure includes a first semiconductor layer made of a first nitride semiconductor formed on the substrate, and a second semiconductor layer formed on the first semiconductor layer and made of a second nitride semiconductor having a larger band gap than the first nitride semiconductor. When a reverse bias of 10 V is applied between the gate electrode and the source electrode, and a forward bias of 20 V is applied between the source electrode and the drain electrode, the drain leakage current value at an operating temperature of 400 K is less than 3×10 －５ A / mm, semiconductor device.

10. When a reverse bias of 10V is applied between the gate electrode and the source electrode, and a forward bias of 20V is applied between the source electrode and the drain electrode, the drain leakage current value at an operating temperature of 500K is 1.5 × 10⁻¹⁰. －４ The semiconductor device according to claim 9, wherein the A / mm is less than or equal to A / mm.

11. When a reverse bias of 10V is applied between the gate electrode and the source electrode, and a forward bias of 20V is applied between the source electrode and the drain electrode, the drain leakage current value at an operating temperature of 600K is 1 × 10⁻¹⁰ －３ The semiconductor device according to claim 9 or 10, wherein the A / mm is less than A.

12. The first nitride semiconductor comprises GaN, The second nitride semiconductor is Al ｘ Ga １－ｘ A semiconductor device according to claim 1, 3, 6, or 9, including N (0 < x < 1).

13. The resistivity of the GaN substrate at 400K is 1 × 10⁻¹⁰ ７ A semiconductor device according to claim 1, 3, 6, or 9, wherein the capacitance is Ωcm or greater.

14. The resistivity of the GaN substrate at 500K is 1 × 10⁻¹⁰ ６ A semiconductor device according to claim 1, 3, 6, or 9, wherein the capacitance is Ωcm or greater.

15. The resistivity of the GaN substrate at 600K is 1 × 10⁻¹⁰ ５ A semiconductor device according to claim 1, 3, 6, or 9, wherein the capacitance is Ωcm or greater.

Images