Plasma etching chemicals for high aspect ratio features in dielectrics

Abstract

To provide a method for etching a feature to a lower stack of a patterned mask in an etching chamber.SOLUTION: A method of forming a semiconductor device onto a semiconductor wafer, contains steps of: arranging a stack in a chamber to a lower direction of a patterned mask; cooling the stack with a cooling agent with a cooling agent temperature that is less than -20°C; flowing an etching gas in an etching chamber and exposing the stack to a plasma after the realization of the plasma; supplying a bias toward the stack from the plasma in order to accelerate an ion; selectively etching the stack to the patterned mask by the etching plasma; and forming a semiconductor feature.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Cross-references to related applications This application claims the benefit of U.S. Provisional Patent Application No. 62 / 644,095, filed Mar. 16, 2018, which is hereby incorporated by reference in its entirety for all purposes.

[0002] This disclosure relates to a method of forming semiconductor devices on a semiconductor wafer.

Background Art

[0003] For example, in the formation of semiconductor devices, an etching layer can be etched to form memory holes or lines or other semiconductor features. Some semiconductor devices can be formed, for example, by etching a single silicon dioxide (SiO) stack to form capacitors within a dynamic access random memory (DRAM). Other semiconductor devices can be formed by etching stacks of alternating silicon dioxide (oxide) and silicon nitride (nitride) bilayers (ONON) or alternating silicon dioxide and polysilicon bilayers. Such stacks can be used in memory applications and three-dimensional “not and” gates (3D NAND). The description of the background art provided herein is for the purpose of generally presenting the background of the present disclosure. These stacks tend to require etching of dielectrics with a relatively high aspect ratio (HAR). For high aspect ratio etching, examples of desirable etching characteristics are high etching selectivity to a mask (such as an amorphous carbon mask), low sidewall etching with a straight profile, and high etching rate at the etch front. The achievements of the inventors named herein are not, in the context of the background art described, considered as prior art to the present disclosure, either explicitly or implicitly, including aspects of the description that cannot be normally considered as prior art at the time of filing.

Summary of the Invention

[0004] To achieve the above, a method is provided for etching features into a stack beneath a patterned mask in an etching chamber, in accordance with the purposes of this disclosure. The stack is cooled with a coolant having a coolant temperature of less than -20°C. An etching gas is flowed into the etching chamber. Plasma is generated from the etching gas. Features are selectively etched into the stack relative to the patterned mask.

[0005] The above-mentioned and other features of this disclosure will be described in detail in a detailed description with reference to the attached drawings. [Brief explanation of the drawing]

[0006] The attached drawings illustrate this disclosure for illustrative purposes only, not for limitation. In these attached drawings, similar components are denoted by the same reference numerals.

[0007] [Figure 1] A high-level flowchart of one embodiment.

[0008] [Figure 2] A schematic diagram showing an etching chamber that can be used in one embodiment.

[0009] [Figure 3] A schematic diagram showing a computer system that can be used to implement one embodiment.

[0010] [Figure 4A] A schematic cross-sectional view showing a stack processed according to one embodiment. [Figure 4B] A schematic cross-sectional view showing a stack processed according to one embodiment. [Modes for carrying out the invention]

[0011] The following description provides a detailed explanation of the disclosure with reference to several preferred embodiments illustrated in the accompanying drawings. The following description includes numerous specific details to facilitate a full understanding of the disclosure. However, as will be apparent to those skilled in the art, the disclosure can be implemented without some or all of these specific details. Furthermore, to avoid unnecessarily obscuring the disclosure, detailed descriptions of well-known processing steps and / or structures have been omitted.

[0012] Figure 1 is a high-level flowchart of one embodiment. In this embodiment, the stack is placed in the etching chamber (step 104). The stack is placed below the patterned mask. The stack has at least one dielectric layer. The stack is cooled by a coolant, which is a cryogenic coolant (step 108). Etching gas is supplied by flowing etching gas into the etching chamber (step 112). The etching gas is etched into an etching plasma (step 116). The stack is exposed to the plasma (step 120). A bias is supplied to accelerate ions from the plasma toward the stack (step 124). The stack is selectively etched by the etching plasma toward the patterned mask (step 128). The stack is removed from the etching chamber (step 132).

[0013] To manufacture semiconductor devices, etching of high aspect ratio structures through semiconductor materials such as silicon dioxide is generally required. High aspect ratio etching requires directional (anisotropic) etching, which differs from isotropic etching. Directional etching is typically achieved using ions in a plasma accelerated perpendicular to the wafer surface. For example, by applying a bias of 10 to 5000 electron volts (eV), ions present in the plasma are accelerated toward the wafer surface. These ions provide plasma etching.

[0014] In this specification and in the claims, the term cryogenic refers to a “cold” substrate temperature. In conventional etching, “cold” means below -20°C. The history of cryogenic etching dates back to 1988, with silicon materials being the most extensively studied. In high aspect ratio silicon etching, it is crucial to control the tendency of sidewalls to chemically etch in order to maintain directionality. Chemical etching is the process by which chemicals chemically adsorb onto a surface and spontaneously form new species with the surface as they desorb at the thermal surface temperature. For example, fluorine spontaneously reacts with silicon surfaces to form silicon tetrafluoride (SiF4) at room temperature. This is problematic in directional etching because chemical etching is isotropic. In other words, chemicals in the plasma are isotropic and land on the surface based on their line of sight. This chemical etching can cause lateral etching, thus compromising the directionality of high aspect ratio etching. In high aspect ratio silicon etching, this has been controlled using the Bosch process or cryogenic etching, which suppresses chemical etching. The most common approach to etching high aspect ratio structures and silicon is the Bosch process, which involves alternating between etching chemicals and vapor deposition chemicals to protect the sidewalls. This type of etching is typically performed at moderate temperatures (typically between -20°C and 100°C). The purpose of the vapor deposition chemicals is to protect the sidewalls.

[0015] The reason for using cryogenic temperatures is that natural chemical etching of the sidewalls is suppressed, eliminating the need for the deposition chemicals used in the Bosch process. Such cryogenic processes have generally not been pursued because it is difficult to maintain the substrate surface at cryogenic temperatures during processing.

[0016] In the literature on high aspect ratio etching of silicon, the typical chemicals used are sulfur hexafluoride (SF6) and oxygen (O2), where fluorine is the reactant for removing silicon as SiF4 or silicon difluoride (SiF2), and sulfur and oxygen provide some protection to the sidewalls, which evaporate when the wafer returns to room temperature. Ion etching is the primary etching process in cryogenic etching. While carbon fluoride is used in the deposition step of the Bosch process, carbon fluoride is typically not used for silicon at cryogenic temperatures because silicon and carbon form a very hard silicon carbide that hinders etching. At the etch front, the silicon carbide hinders etching but is eventually broken down by ionic bombardment. Another advantage of cryogenic etching of silicon (Si) is that strong sidewall protection is not required. Cryogenic etching of silicon can help increase etching rates by reducing the amount of deposition required to protect the sidewalls.

[0017] Etching of dielectrics can differ from etching of silicon. For example, silicon tends to be chemically etched, meaning that a chemical reaction occurs spontaneously to desorb silicon byproducts (such as SiF4 or SiCl2). Silicon nitride (SiN) can also be chemically etched with nitrogen trifluoride (NF3), but in contrast, silicon dioxide is not typically etched spontaneously. Instead, etching of silicon dioxide is ion-induced, with reactants to accelerate desorption. Furthermore, dielectrics such as oxides and nitrides contain silicon and other elements (such as oxygen or nitrogen) in their lattice. Silicon is spontaneously etched with halogens (such as fluorine, chlorine, or bromine), but oxygen does not readily form stable volatile species with halogens alone. At room temperature, the removal of oxygen from oxides results in carbon forming carbon monoxide (CO) or carbon dioxide (CO2) volatile compounds, or hydrogen (H) forming water (H2O), or volatile B x Cl z O yThe etching process is facilitated by the presence of boron chloride (BCl3) to form compounds, or sulfur oxide (SO) to form sulfur dioxide (SO2). In the case of nitrogen (N), fluorine can remove N as NF3, or together with H as ammonia (NH3). More specifically: For etching of silicon components at cryogenic temperatures, halogens (fluorine (F), chlorine (Cl), bromine (Br), and iodine (I), etc.) can be used to etch the silicon components. For etching of oxygen components in silicon oxide at cryogenic temperatures, carbon (C), boron (B), hydrogen (H), sulfur (S), and nitrogen are effective in etching the oxygen components. For etching of nitrogen components in silicon nitride at cryogenic temperatures, H and F can be used to etch the nitrogen components. It is also known that C, H, oxygen (O), silicon (Si), F, and S can be used as passivators at cryogenic temperatures. Therefore, the chemicals required to etch the dielectric layer at extremely low temperatures may differ from those used for silicon.

[0018] Typical examples of chemicals used to etch dielectrics at room temperature include carbon fluoride (such as octafluorocyclobutane (C4F8) and / or hexafluoride-2-butyne (C4F6)). C4F8 and / or C4F6 fragment in the plasma to form carbon fluoride polymers that can passivate the sidewalls and protect the mask. Meanwhile, at the etch front, as long as the polymer is not too dense, the ions incident on the etch front utilize the carbon and fluorine to etch the oxide. For example, carbon combines with oxygen to form CO and CO2. Fluorine combines with silicon to form SiF4 and SiF2 volatile compounds. The sidewalls do not receive incident ions, and the polymer still protects the sidewalls. Typical plasma treatment chemicals in 3D NAND applications for etching stacks of oxide and nitride layers are C4F8, C4F6, O2, and fluoromethane (CH3F). C4F8 and C4F6 gases fragment within the plasma to produce polymerized carbon fluoride. The carbon and fluorine present at the etch front are reactants. O2 is added as an effective knob to adjust and control the polymer to maintain the top of the feature opening. CH3F assists in the etching of the nitride by supplying a hydrogen source and carbon fluoride. Thus, compared to etching silicon at room temperature, etching dielectrics typically require not only halogen sources utilized as reactants, but also carbon and hydrogen sources.

[0019] However, etching at room temperature requires a trade-off between etching rate and selectivity ratio and / or sidewall profile. If the etching rate is high due to lean carbon fluoride polymer deposition, the sidewalls and mask may not be adequately protected, resulting in bowing (bending) on ​​the sidewalls. On the other hand, if the carbon fluoride polymer deposition is increased to protect the sidewalls and mask, the etching rate is hindered and slowed down. Pinch-off of the deposition at the top of the feature may also occur. Cryogenic etching offers an opportunity to overcome some of this trade-off in dielectric etching.

[0020] Despite extensive research on high aspect ratio etching of silicon at cryogenic temperatures, relatively little research has been done on high aspect ratio etching of dielectrics. As the surface temperature decreases, there are four main principles that provide various embodiments with different chemicals for etching dielectrics at cryogenic temperatures.

[0021] First principle: Similar to etching of high-aspect-ratio silicon, spontaneous chemical etching of dielectrics can also be suppressed. However, this principle differs for oxide etching compared to silicon etching. This difference is because oxide etching does not tend to be chemically etched. Instead, oxide etching is known to be an ion-induced process, as it requires ionic energy for desorption to proceed. Etching using ionic energy can provide vertical etching by deflecting ions that reach the sidewalls. However, nitrogen is rather similar to silicon and can be chemically etched. Cryogenic temperatures are preferable as they help reduce lateral etching of SiN. Therefore, cryogenic temperatures can help reduce chemical etching in high-aspect-ratio dielectric etching. However, unlike in the case of silicon, the reduction of chemical etching is not the most important principle of cryogenic etching. The degree to which cryogenic temperatures are important for high-aspect-ratio dielectric etching is due to the following: for polymer sidewall passivation, the reduction in the amount of passivation required allows for leaner carbon fluoride or fluorinated hydrocarbon (or a combination of carbon fluoride and hydrogen) etching chemicals. Lean etching chemicals have a low proportion of polymer components such as carbon. For example, in non-cryogenic etching processes, C4F6 and C4F8 may be used as passivators in the etching gas. At cryogenic temperatures, carbon tetrafluoride (CF4) is used as a passivator. Other examples of lean chemicals include fluoromethane (CHF3), CH3F, carbon tetrachloride (CCl4), trifluoroiodomethane (CF3I), dibromodifluoromethane (CBr2F2), pentafluoroethane (C2HF5), and C2F5Br. These chemicals may be combined with each other, or one or more of hydrogen (H2) or O2, or H2O, or hydrogen peroxide (H2O2) may be added. In addition to carbon-containing chemicals that etch dielectrics, other non-carbon-containing chemicals are also known to passivate and can be effective at cryogenic temperatures because strong passivation is not required. BCl3 can be included because it has passivating properties and can be effective at extremely low temperatures.BCl3 is not a conventional etchant for oxides at room temperature because boron trioxide (B2O3) blocks etching. At very low temperatures, the blockage may be reduced, so BCl3 is thought to function as an etchant component at very low temperatures. Other passivating components may be chromyl chloride (CrO2Cl2), silicon tetrachloride (SiCl4), thionyl chloride (SOCl2), titanium dichloride (TiCl2), titanium trichloride (TiCl3), and phosgene (CoCl2). The lean chemical substances in this example have a low carbon-to-fluorine ratio.

[0022] Second principle: When the surface temperature is lowered, the sticking coefficient increases. The sticking coefficient is a measure of how long a molecule physically adsorbs to the surface before it re-enters the gas phase. In other words, at lower temperatures, molecules adhere to the surface for a longer time according to Arrhenius' law, such that the adhesion time is inversely proportional to the surface temperature. This temperature dependence will have an even more pronounced effect at very low temperatures. The result of this temperature dependence of the sticking coefficient is very important in determining where and how much reactants and inhibitors (i.e., deposits) occur at various locations on the feature. Specifically, the deposition rate of the fluorocarbon polymer strongly depends on the sticking coefficient. Fluorocarbon polymer deposition is promoted by C x F y species in the plasma that tend to crosslink. Generally speaking, the larger the species and the higher the carbon content in the species, the higher the likelihood that they will form a polymer. Among the fragments formed by C4F6 gas in the plasma, C4F6, C4F5, trifluoroallene (C3F4), 1,2,3,3,3-pentafluoroprop-1-ene (C3F5), trifluorovinyl (C2F3), and C3F2 tend to crosslink and form a polymer. The lower the temperature, the longer these molecules adhere to the surface and the higher the deposition rate. Also, low temperature means that adhesion occurs mostly at the top of the feature. The polymer accumulates in the openings and cannot descend along the sidewalls at very low temperatures.

[0023] One consequence of the second principle is that the gas for cryogenic etching of dielectrics is selected to avoid excessive polymerization. In one embodiment, the gas mixture contains carbon. For carbon-containing gases, this principle presents CF4 as an example. CF4 is not a typical gas for dielectric etching at high aspect ratios. However, at cryogenic temperatures, CF4 can work well because it has a leaner C:F ratio and is less likely to clog the top of features. At the same time, the use of CF4 is preferable as it provides some protection to the sidewalls. Another example of a leaner chemical is the use of CHF3 for oxide etching or CHF3 and N2 for nitride etching. Another example may include CF4 and N2 for nitride etching. Also, CH2F2, CH3F, CCl4, carbonyl sulfide (COS), CO, CO2, methylene chloride (CH2Cl2), methane (CH4), CF3I, and chloroform (CHCl3) may be used as etchants. To facilitate etching at nitrides, other gases may be added to or combined with these gas mixtures, such as nitrogen-containing gases (e.g., NH3), hydrogen sulfide (H2S), silane (SiH4), disilane (SiH6), propene (C3H6), nitrogen oxide (N2O), H2O2, nitric acid (HNO3), or O2 may be added or combined to adjust the resulting deposition. Therefore, for example, some possible gas mixture recipes may be a mixture of CF4, O2, and N2; or a mixture of CF4, CHF3, and O2; or a mixture of CF4, COS, and N2; or a mixture of CF4 and CO; or a mixture of CF4 and CH4; and all other substitutions. Thus, since both oxygen and nitrogen may be desired, it may also be possible to use unconventional reactants for etching dielectrics, such as H2O in a combination of CF4 and H2O. Since H2O is not normally a gas at room temperature, some hardware modifications may be required to accommodate an H2O input. None of the above combinations polymerize sufficiently at room temperature and are therefore not typically used to etch high aspect ratio dielectric structures.However, at extremely low temperatures, these lean chemicals are likely to condense on the surface, thus providing some degree of protection to the sidewalls. Therefore, even chemicals that are normally considered etchants may deposit or passivate the sidewalls at extremely low temperatures.

[0024] Furthermore, regarding the second principle: the previous paragraph focused on leaner chemicals containing carbon. However, even if the gas does not contain carbon as passivation, at cryogenic temperatures, there is another group of chemicals that are not typically used at room temperature but can be used for sidewall passivation, as the gas is likely to protect the sidewalls. Since not much deposition is required, silicon with oxygen and / or nitrogen may be etched using the following halogen-containing chemical mixtures: a mixture of BCl3 with chlorine (Cl2) or HBr, or a mixture of Cl2 with N2 or CF4 or Br2 or COS or SiH4 as an H source for silicon nitride etching. In some embodiments, iodine may be used as the halogen. BCl3 does not readily etch oxides at room temperature because it forms a surface film of SiOBCl that blocks etching, and therefore is not typically used to etch dielectrics at room temperature. However, at low temperatures, it has been found that BCl3 deposition actually decreases. In this case, BCl3 etching occurs not due to an increase in the adhesion coefficient, but due to a slower reaction. As a result, BCl3 is normally deposited at room temperature, but volatile B is etched at extremely low temperatures. x Cl y O z It generates seeds. This is another example of a chemical that may be suitable for etching at extremely low temperatures but not at room temperature. Other chemicals of the same type as BCl3 may include MgCl2, PdCl2, and TiCl3.

[0025] The second principle provides a different result. We have discussed the increase in adhesion coefficient at low temperatures. This means that molecules tend to adhere to the top of the feature, or to the etch front of the feature, before descending the sidewalls. However, if the molecules are small enough or do not deposit, they can reach the bottom of the feature. Specifically, for carbon fluoride deposition, it is known that the etching species (ions or molecules) tend to be F, carbon fluoride (CF), and difluoromethane (CF2). These species are small enough not to polymerize, and instead are likely to etch if they reach the surface. In the reverse reactive ion etching (RIE) lag phenomenon, where high aspect ratio features etch faster than low aspect ratio features, the high aspect ratio is known to act as a kind of filter for small particles. Reverse RIE is caused by only small particles reaching the bottom of the feature. Reverse RIE can serve a choice between increasing the etching rate at the bottom due to less deposition and protecting the mask at the top where larger species deposit and form a deposited film.

[0026] The implication of the second principle is that utilizing gases with high fluorine sources is advantageous for high aspect ratio dielectric etching. C4F6 and C4F8, typically used at room temperature, are not good fluorine sources because at very low concentrations, these gases are fragmented into small particles of fluorine, CF, or CF2. Instead, at cryogenic temperatures, larger species in C4F6 and C4F8 are likely to adhere to the top of the feature, blocking etching without allowing any reactant to reach the bottom. Types of gases that fragment into fluorine (radical) sources include those readily available in the laboratory: CF4, SF6, NF3, XeF2, tungsten hexafluoride (WF6), SiF4, tantalum pentafluoride (TaF5), iodine heptafluoride (IF7), and hydrogen fluoride (HF) (indirectly produced in vapor or plasma). More generally, metals charged above +5 (such as metal halides) are more volatile and can be supplied to the surface via the plasma. Therefore, many pentafluorides tend to be gaseous and can be good candidates for fluorine-producing plasmas. This type of pentafluoride gas further includes chlorine pentafluoride (ClF5), bromine pentafluoride (BrF5), arsenic pentafluoride (AsF5), nitrogen pentafluoride (NF5), phosphorus pentafluoride (PF5), niobium pentafluoride (NbF5), bismuth pentafluoride (BiF5), and uranium (UF5). An advantage of some of these (BiF5) is that they also form polymers that can protect the sidewalls. This approach may also work with chlorine-containing species for the same reasons. Other options include SiCl2, CrO2Cl2, SiCl4, tantalum tetrachloride (TaCl4), hafnium tetrachloride (HfCl4), titanium chloride (TiCl3(l)), titanium tetrachloride (TiCl4(l)), and cobalt chloride (CoCl2(l)).

[0027] While some of these gases mentioned above are readily available, they are rarely used in dielectrics or any etching platforms because they are more commonly found in deposition platforms, such as WF6, TiCl3, and TiCl2. In fact, some of these are known in etching not as etching species, but as by-products. For example, WF6 is a by-product of etching tungsten (W) in SF6 or CF4 plasmas. TiCl4, TaCl4, and HfCl4 are by-products of etching titanium (Ti), tantalum (Ta), titanium nitride (TiN), and tantalum nitride (TaN) or hafnium (Hf) in Cl2 or BCl3 plasmas. Various embodiments use such gases as CF4, SF6, NF3, XeF2, WF6, SiF4, TaF5, IF7, HF, ClF5, BrF5, AsF5, NF5, PF5, NbF5, BiF5, UF5, WF6, TiCl3, and TiCl2 to supply high F or Cl species for dielectric etching. Cl species may not be very effective. Specifically, WF6, TaCl4, and HfCl4 may offer further advantages because W, Ta, Hf, niobium (Nb), and rhenium (Re) are high-melting-point metals known to be very hard. As mentioned above, the mask tends to be C. If a hard species is doped into C, the mask can be strengthened. Thus, for example, W-doped C is harder than amorphous C. Therefore, when etching is performed using WF6, TaCl4, or HfCl4, W, Ta, or Hf is injected into the mask. Injection is preferable as it has the additional advantage of hardening the mask and increasing the selectivity, since F may be more effective than Cl or Br. Preferred etching gases are WF6 or TaF5. Both WF6 and TaF are gases at room temperature and are easily injected into the plasma. In addition to high melting point metals, both B and C are also very hard and can harden or retard amorphous carbon masks. Therefore, CF4, boron trifluoride (BF3), and boron tribromide (BBr3) may be used as etchant component gases in various embodiments.Regarding fluoride-forming etching gases, preferred etching gases are those that supply F radicals and have fairly large molecules. Therefore, hexafluorine is preferred over tetrafluorine. For example, WF6 and TaF5 are preferred over SiCl2. These gases can be combined with C or H-containing gases if they can remove O.

[0028] As mentioned above, some of these gases are used in deposition processes. These gases can be deposited on the top of the feature rather than on the etch front at the bottom of the feature. In one embodiment, etching may be further enhanced by intentionally depositing on the top of the feature. For example, using etching gases such as WF6, TiCl4, or TaF5, metal can be deposited (rather than injected / doped) onto the mask on top of the feature, as done in ALD, using, for example, WF6 and H2 chemicals or WF6 and SiH4 chemicals. It is thought that only F and H reach and etch the bottom of the feature, while the deposited material adheres to and deposits on top of the feature. This is also a way to supply H as H2O or NH3, which can be useful for etching O and N. In another example, Ta is deposited using TaF5. Ta is a very hard material and can be used to harden the mask. Ti may be deposited using TiCl4 with a suitable precursor.

[0029] The third principle is as follows: While etching SiO2 at room temperature usually does not work with F alone and requires C, B, or H, one embodiment etches SiO2 at cryogenic temperatures using only F, without the need for C, B, or H. The reason why F requires C, B, or H to etch SiO2 at room temperature is that fluoronium diolate (FO2) is volatile at room temperature (boiling point -144°C). Oxygen difluoride (OF2) decomposes into oxygen and fluorine via a radical mechanism. In a plasma, this can occur even more rapidly. Therefore, OF2 is not stable. One embodiment uses cryogenic temperatures to supply a stable OF2 vapor. Then, at cryogenic temperatures, SiO2 is etched with an F-containing gas without the addition of C, B, or H additives. It is also known that insufficient exposure of plasma O2 results in preferential sputtering. Thus, the surface becomes more metallic. Therefore, one embodiment involves etching SiO2 at cryogenic temperatures with a component containing a fluorine-containing etching gas (such as SF6), but such gases are typically designed only for silicon and cannot etch SiO2.

[0030] The fourth principle is as follows: In other approaches, it has been found that etchants at non-cryogenic temperatures unexpectedly act as passivators at cryogenic temperatures. For example, SF6 is used as an etchant in non-cryogenic processes. However, it has been found that SF6 functions like a passivator rather than an etchant at cryogenic temperatures. Other molecules that do not provide passivation at non-cryogenic temperatures provide passivation at cryogenic temperatures. For example, as mentioned above, water can be a passivating component at cryogenic temperatures. Amines and SO2 can also be used as passivators at cryogenic temperatures. CO2 has been found to be usable as a passivator at cryogenic temperatures. CO2 can be a desirable passivator because it is less likely to form crystals and instead tends to take the form of a slurry. Other passivators at cryogenic temperatures may be COS, CO, S derived from SF6, or SiF4.

[0031] Another embodiment provides cryogenic atomic layer etching (ALE) or atomic layer deposition (ALD). In one embodiment of cryogenic ALE, a chemical reactant is supplied as an atomic layer etching gas in step A, where step B supplies thermal or ionic energy or another type of energy to desorb byproducts. Specifically, since any etching that occurs in step A is non-ideal and undesirable, cryogenic temperatures are used in step A of ALE to suppress any etching. At that time, many reactants can be adsorbed but do not etch at room temperature. There are a fair number of reactants that etch spontaneously at room temperature. The best known case of this is silicon spontaneously forming SiF4 at room temperature in the presence of fluorine. By using cryogenic temperatures, this reaction is suppressed. Various embodiments extend this approach. In one embodiment, tin oxide (SnO) spontaneously etches with H2 at room temperature, making it very difficult to convert it into an ALE process at room temperature. However, by using cryogenic temperatures estimated to be -70°C, this reaction is suppressed, and the ALE process can be successfully carried out.

[0032] ALE may be advantageous for HAR. In one embodiment of ALE, the second step involves supplying argon only. It is known that argon alone can indeed strengthen amorphous carbon films into a more diamond-like state. Therefore, intermittent use of argon-only plasma to strengthen masks can be used in high aspect ratio etching processes. Such a process may be used in ALD in one embodiment.

[0033] Furthermore, it has been found that harder materials are etched more easily using ALE. By performing ALE at cryogenic temperatures, the cryogenic temperature makes the material to be etched more hard without changing the surface bonding energy of the material. This provides easier ALE on the material. In one embodiment, chemical reaction step A is performed at a cryogenic temperature to provide a modified layer, and the utilization of ionic energy for activation in step B is also done at a cryogenic temperature to activate the modified layer. In another embodiment, chemical reaction step A is performed at a cryogenic temperature, and activation step B is performed at a higher temperature (with ions) or even thermally, where heat is used as the energy source. In one embodiment, the substrate is moved between two different chambers for each step, so that step A is performed in a cryogenic chamber and step B is performed in a non-cryogenic chamber. In another embodiment, step A is performed at a cryogenic temperature, and activation step B is performed under a heating lamp, where the heating lamp provides thermal energy to a small space where thermal energy is required.

[0034] In embodiments where cryogenic temperatures are used in ALD, a first precursor may be supplied as an atomic layer deposition gas and deposited at cryogenic temperatures during step A, and a second precursor may be deposited at cryogenic temperatures during step B. Normally, this is not done at cryogenic temperatures because the adsorption of precursors typically requires heating. However, when plasma is used to increase the reactivity of the precursors, cryogenic temperatures can be used to avoid other thermally activated surface reactions. Potential condensation of the precursors on the substrate becomes a concern. Condensation is not self-limiting. Therefore, the temperature range may or may not be suitable for cryogenic temperatures. The likelihood of the range being suitable for cryogenic temperatures increases when plasma is used.

[0035] example Figure 2 is a schematic diagram showing an etching reactor 200 available in one embodiment. In one or more embodiments, the etching reactor 200 comprises a gas distribution plate 206 providing a gas inlet and an electrostatic chuck (ESC) 208, located within an etching chamber 209 surrounded by chamber walls 252. Within the etching chamber 209, a stack 204 is positioned on the ESC 208. The ESC 208 may be supplied with bias from an ESC source 248. An etching gas source 210 is connected to the etching chamber 209 through the gas distribution plate 206. An ESC temperature controller 250 is connected to a cooler 214 that cools a coolant 215. In this embodiment, the cooler 214 supplies the coolant 215 to a channel 217 in or near the ESC 208. A radio frequency (RF) source 230 supplies RF power to the lower electrode and / or upper electrode, which in this embodiment are the ESC 208 and the gas distribution plate 206, respectively. In an exemplary embodiment, 400 kHz, 60 MHz, and optionally 2 MHz and 27 MHz power supplies constitute the RF source 230 and ESC source 248. In this embodiment, the upper electrode is grounded. In this embodiment, one generator is provided for each frequency. In another embodiment, multiple generators may be located in separate RF sources, or separate RF generators may be connected to different electrodes. For example, the upper electrode may have inner and outer electrodes connected to different RF sources. Other configurations of the RF sources and electrodes may be used in other embodiments. A controller 235 is controllably connected to the RF source 230, ESC source 248, exhaust pump 220, and etching gas source 210. An example of such an etching chamber is the Flex® etching system from Lam Research, Inc., Fremont, California. The processing chamber may be a CCP (capacitance-coupled plasma) reactor or an ICP (inductively coupled plasma) reactor.

[0036] Figure 3 is a high-level block diagram showing a computer system 300 suitable for implementing the controller 235 used in the embodiment. The computer system 300 may have many physical forms, ranging from integrated circuits, printed circuit boards, and small portable devices to large supercomputers. The computer system 300 comprises one or more processors 302 and may further include an electronic display device 304 (for displaying images, text, and other data), main memory 306 (e.g., random access memory (RAM)), a storage device 308 (e.g., a hard disk drive), a removable storage device 310 (e.g., an optical disk drive), a user interface device 312 (e.g., a keyboard, touchscreen, keypad, mouse, or other pointing device), and a communication interface 314 (e.g., a wireless network interface). The communication interface 314 enables the transfer of software and data between the computer system 300 and external devices via a link. The system may further include a communication infrastructure 316 (e.g., a communication bus, crossover bar, or network) to which the aforementioned devices / modules are connected.

[0037] The information transmitted via the communication interface 314 may be in the form of a signal, such as an electronic signal, an electromagnetic signal, an optical signal, or any other signal that can be received by the communication interface 314 via a communication link that carries the signal, and may be carried out using wires, i.e., cables, optical fibers, telephone lines, mobile phone links, radio frequency links, and / or communication channels. It is assumed that one or more processors 302 can receive information from or output information to the network using such a communication interface 314 when performing the steps of the method described above. Furthermore, embodiments of the method may be performed by a single processor or in cooperation with a remote processor that shares part of the processing via a network such as the Internet.

[0038] The term "non-temporary computer-readable medium" is generally used to refer to media such as main memory, secondary memory, removable storage, and storage devices (such as hard disks, flash memory, disk drive memory, CD-ROMs, and other forms of persistent memory), and should not be interpreted to encompass temporary objects such as carrier waves or signals. Examples of computer code include machine code, such as code generated by a compiler, and files containing high-level language code executed by a computer using an interpreter. A computer-readable medium may also be computer code, which represents a set of instructions that are transmitted by computer data signals embodied in a carrier wave and that can be executed by a processor.

[0039] In an exemplary embodiment, the stack is placed in the etching chamber (step 104). Figure 4A is a schematic cross-sectional view of the stack 204. In this embodiment, the stack 204 comprises a substrate 408 beneath a plurality of bilayers 412 placed beneath a patterned mask 416. In this example, one or more layers may be placed between the substrate 408 and the plurality of bilayers 412, or between the plurality of bilayers 412 and the patterned mask 416. In this example, the patterned mask 416 is a carbon-containing patterned mask, such as amorphous carbon. This embodiment does not have a silicon-containing mask above the plurality of bilayers 412 or above the patterned mask 416. In this example, the pattern of the patterned mask provides mask features 420 for high aspect ratio contacts. In some embodiments, the mask features 420 are formed before the stack 204 is placed in the etching chamber 209. In another embodiment, the mask features 420 are formed while the stack 204 is in the etching chamber 209. In this embodiment, each bilayer 412 is a bilayer of a silicon oxide layer 424 and a silicon nitride layer 428.

[0040] After the stack 204 is placed in the etching chamber 209, the stack 204 is cooled with a coolant at a coolant temperature of less than -20°C (step 108). The etching gas is flowed into the etching chamber 209 (step 112). In this example, the etching gas is CF4. In this example, a pressure of 5 to 60 mTorr is provided. The etching gas is etched into an etching plasma (step 116). This may be achieved by providing an excitation RF at a frequency of 60 MHz with 200 to 8000 watts. The stack 204 is exposed to the plasma (step 120). A bias of at least about 400 volts is supplied (step 124). In this embodiment, a high bias is supplied by supplying an RF with a frequency of 400 kHz at 2 kW to 18 kW to the ESC 208 by the ESC source 248. The bias accelerates ions toward the stack 204, causing selective etching of high aspect ratio etching features in multiple bilayers 412 against the carbon-containing patterned mask 416 (step 128). The plasma is maintained for 180–3600 seconds. Etching can etch both the silicon oxide layer 424 and the silicon nitride layer 428. After etching is complete, another process may be performed on the stack 204. The stack 204 is then removed from the etching chamber 209 (step 132).

[0041] Figure 4B is a cross-sectional view of the stack 204 after the contact 432 has been etched. The contact 432 is a high aspect ratio contact. Preferably, the high aspect ratio contact 432 has a height-to-critical dimension (CD) width aspect ratio greater than 20:1, where in this embodiment, the CD is measured at the top of the feature. In another embodiment, the height-to-width aspect ratio may be greater than 50:1. The etching process allows for selective etching of the silicon oxide layer 424 and silicon nitride layer 428 to amorphous carbon with a selectivity ratio greater than 5:1 when etching high aspect ratio features. The resulting features also exhibit reduced bowing, striations, distortion, capping, and tapering. Furthermore, this embodiment enables the use of carbon-containing patterned masks, such as amorphous carbon, without the need for silicon-containing masks, such as polysilicon. Eliminating the need for silicon-containing masks reduces costs and defects.

[0042] Prior to etching, the stack was processed at temperatures above -20°C and relied on fluorocarbon chemicals to etch and provide sidewall protection. In such processes, the resulting etching selectivity ratio of the mask to silicon oxide and silicon nitride was less than 5:1. Sidewall protection for previous processes was provided by polymer deposition. Polymer deposition was controlled by carbon concentration, where higher carbon concentrations increased sidewall deposition, and by oxygen, where higher oxygen concentrations consumed the deposited polymer. Higher oxygen concentrations also increased mask consumption. Some previous processes utilized silicon-containing masks. The above embodiments increase etching rates and improve contact shape / striation compared to conventional approaches.

[0043] In some embodiments, the coolant 215 is cooled to a coolant temperature of less than -60°C in order to provide the stack 204 with a coolant temperature of less than -20°C. In another embodiment, the coolant 215 is cooled to a coolant temperature between -30°C and -200°C. In yet another embodiment, the coolant 215 is cooled to a coolant temperature between approximately -40°C and approximately -200°C. In some embodiments, the stack is cooled to a temperature between -30°C and -200°C. In the specification and claims, performing etching at cryogenic temperatures is defined as performing etching using a coolant with a temperature of less than -20°C. More preferably, cryogenics utilize a coolant with a temperature between -20°C and -150°C. More preferably, cryogenics utilize a coolant with a temperature of less than -60°C. Generally, performing etching at cryogenic temperatures involves one coolant within the above range. In some embodiments, cryogenic operation cools the stack 204 to a temperature of less than -20°C at some point during the operation. In another embodiment, cryogenic operation maintains the stack 204 at a temperature below -20°C throughout the entire operation.

[0044] In some embodiments, the etching gas further comprises one or more of the following: a free fluorine-supplying component, a hydrogen-containing component, a hydrocarbon-containing component, a carbon fluoride-containing component, and an iodine-containing component. The free fluorine-supplying component is defined as a component that typically decomposes in the plasma to supply free fluorine, such as NF3 and sulfur hexafluoride (SF6). The hydrogen-containing component is preferably H2, CH3F, and difluoromethane (CH2F2).

[0045] The ONON stack may be etched to form features (such as contact holes, lines, or trenches) in the manufacturing of 3D NAND memory devices. In another embodiment, contact holes used in M0C and M0A may be etched, such contact holes being first metal contacts used to control the 3D NAND junction. Another embodiment may be used for etching dynamic random access memory (DRAM) capacitors. Another embodiment may be used to etch silicon oxide and polysilicon bilayers (OPOPs). The embodiment provides an etching depth greater than 20 microns. In another embodiment, the etching depth is greater than 3 microns. Such embodiments enable etching of at least 48 silicon oxide and silicon nitride bilayers in a single etching step using a single amorphous carbon mask with a thickness of less than 1 micron. Furthermore, the contacts preferably have an etching depth to neck aspect ratio greater than 30:1.

[0046] In some embodiments, the stack may be a single layer of silicon oxide or silicon nitride. In other embodiments, the stack may be a single or multiple layers of other silicon-containing materials.

[0047] The above embodiments utilize a bias of at least 400 volts. A bias of at least 1000 volts has been shown to improve etching. A bias of at least 2000 volts is thought to further improve etching. Without being bound by theory, higher biases are thought to enable etching of higher aspect ratios while utilizing other features, allowing for the use of amorphous carbon masks and reducing striations and boeing.

[0048] In some embodiments, liquid nitrogen is used as a coolant, which is flowed through the chuck or lower electrode to provide cooling. In another embodiment, Vertel Sinera™ manufactured by DuPont, Wilmington, Delaware, may be used as a coolant.

[0049] Boeing is typically a challenge in etching contacts, where the feature is cylindrical and may have a circular cross-section. Therefore, in various embodiments, the feature is a contact with a circular cross-section. In another embodiment, the feature may have other cross-sections, such as elliptical, quadrilateral, and other polygonal shapes. By reducing boeing, the etched feature becomes more cylindrical in shape. In another embodiment, the feature may be a line, step, or other shape. Another embodiment may have one or more silicon-containing masks or metal-containing masks. The halogen in various embodiments is preferably fluorine, bromine, or iodine.

[0050] While the present disclosure has been described above with reference to several preferred embodiments, various substitutes, modifications, replacements, and equivalents exist within the scope of this disclosure. It should also be noted that there are numerous other ways of carrying out the methods and apparatus of this disclosure. Therefore, the attached claims should be interpreted as encompassing all substitutes, modifications, replacements, and equivalents that fall within the true spirit and scope of this disclosure. [Application Example 1] A method for etching features onto a stack below a patterned mask in an etching chamber, a) Cool the stack with a coolant so that the coolant temperature is below -20°C. b) Flow etching gas into the etching chamber, c) A plasma is generated from the etching gas, d) Selectively etching the features in the stack against the patterned mask, A method that includes [a certain feature]. [Application Example 2] A method according to Application Example 1, further comprising supplying a bias of at least 400 volts. [Application Example 3] A method according to Application Example 1, wherein the etching gas does not contain oxygen. [Application Example 4] The method according to Application Example 1, wherein the etching gas comprises an etchant component, and the etchant component is CF 4 ,SCIENCE FICTION 6 NF 3 XeF 2 WF 6 SiF 4 TaF 5 , IF 7 HF, ClF 5 , BrF 5 AsF 5 NF 5 , PF 5 , NbF 5 BiF 5 UF 5 , SiCl 2 , CrO 2 Cl 2 , SiCl 4 TaCl 4 , HfCl 4 TiCl 3 (l), TiCl 4 (l), CoCl 2 (l), TiCl 3 , and TiCl 2 A method that includes at least one of the following. [Example 5] The method according to Example 1, wherein the etching gas includes a passivation component, and the passivation component is CF 4 CHF 3 CH 3 F, CCl 4 , CF 3 I, CBr 2 F 2 、C 2 HF 5 、C 2 F 5 Br, H 2 、O 2 、H 2 O, H 2 O 2 BCl 3 NH 3 , COS, CO, SF 6 , and SiF 4 A method that includes at least one of the following. [Application Example 6] The method according to Application Example 1, wherein the etching gas includes a passivation component, and the passivation component is CrO 2 Cl 2 , SiCl 4 SOCl 2 TiCl 2 TiCl 3 , and CoCl 2 A method that includes at least one of the following. [Example 7] A method according to Example 1, wherein the stack is cooled to a temperature below -20°C. [Example 8] A method according to Example 1, wherein the stack is cooled to a temperature below -60°C. [Application Example 9] The method according to Application Example 1, wherein the etching gas is an atomic layer etching gas or an atomic layer deposition gas, and the plasma from the etching gas modifies the layers of the stack to provide a modified layer. The above method further, e) Stop the generation of the plasma, f) After stopping the generation of the plasma, activate the modified layer of the stack. A method that includes [a certain feature]. [Example 10] A method relating to Example 9, wherein b) to f) are repeated multiple times. [Application Example 11] A method according to Application Example 10, wherein activating the modified layer of the stack comprises at least one of heating the modified layer, irradiating the modified layer, or flowing a gas to chemically react with the modified layer. [Example 12] A method according to Example 1, further comprising supplying a bias of at least 1000 volts. [Example 13] A method according to Example 1, wherein the etching gas comprises at least one of a fluorine-supplying component, a hydrogen-containing component, a hydrocarbon-containing component, a fluorinated carbon-containing component, and an iodine-containing component. [Example 14] A method according to Example 1, wherein the feature has a height-to-width aspect ratio greater than 20:1. [Application Example 15] A method according to Application Example 1, wherein the etching gas includes a metal halide gas. [Application Example 16] A method relating to Application Example 1, wherein the stack includes a dielectric layer. [Example 17] A method according to Example 1, wherein the stack comprises at least one layer of silicon nitride, silicon carbide, or silicon oxide.

Claims

1. A method for etching, a) A substrate is supported on a chuck in the chamber of a plasma processing system, the substrate includes a silicon-containing stack, and the chuck has a lower electrode. b) Cool the substrate to a temperature between -20°C and -150°C. c) Supply a halogen-containing gas, d) Supply phosphorus-containing gas, e) A method comprising generating a plasma from the halogen-containing gas and the phosphorus-containing gas, wherein the plasma etches features onto the silicon-containing stack and deposits a sidewall passivation on the sidewalls of the features.

2. The method according to claim 1, further, A method that provides a bias.

3. The method according to claim 1, A method comprising supplying RF power to generate the plasma from the halogen-containing gas and the phosphorus-containing gas.

4. The method according to claim 1, The aforementioned phosphorus-containing gas is phosphorus pentafluoride (PF 5 Methods including )

5. The method according to claim 1, The halogen-containing gas comprises a free fluorine supply component, and the method is as described above.

6. The method according to claim 1, further, A method comprising supplying one or more of the following: a hydrogen-containing component, a hydrocarbon-containing component, a fluorinated carbon-containing component, and an iodine-containing component.

7. The method according to claim 1, further, A method comprising supplying an oxygen-containing component.

8. The method according to claim 1, further, A method comprising supplying oxygen gas.

9. The method according to claim 1, further, A method comprising supplying a bias of at least 400 volts.

10. The method according to claim 1, The method wherein the substrate comprises at least two different silicon-containing layers.

11. The method according to claim 10, The method wherein the at least two different silicon-containing layers include a silicon oxide layer and a silicon nitride layer.

12. The method according to claim 10, The method wherein the at least two different silicon-containing layers include a silicon oxide layer and a polysilicon layer.

13. The method according to claim 10, The method further comprises a mask on the substrate, which is located on the at least two different silicon-containing layers.

14. A method for etching, a) A substrate is supported on a chuck in the chamber of a plasma processing system, the substrate includes a silicon-containing stack, and the chuck has a lower electrode. b) Supply a halogen-containing gas, c) Phosphorus pentafluoride (PF 5 ) Supply the gas containing, d) A method comprising supplying RF power to generate a plasma from the halogen-containing gas and the phosphorus pentafluoride (PF5)-containing gas, wherein the plasma etches features into the silicon-containing stack and deposits a sidewall passivation on the sidewalls of the features.

15. The method according to claim 14, further, A method that provides a bias.

16. The method according to claim 14, further, A method comprising cooling the substrate to a temperature below -20°C.

17. The method according to claim 14, The halogen-containing gas comprises a free fluorine supply component, and the method is as described above.

18. The method according to claim 14, further, A method comprising supplying one or more of the following: a hydrogen-containing component, a hydrocarbon-containing component, a fluorinated carbon-containing component, and an iodine-containing component.

19. The method according to claim 14, further, A method comprising supplying an oxygen-containing component.

20. The method according to claim 14, further, A method comprising supplying oxygen gas.

21. The method according to claim 14, further, A method comprising supplying a bias of at least 400 volts.

22. The method according to claim 14, The method wherein the substrate comprises at least two different silicon-containing layers.

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