Semiconductor equipment

Abstract

To provide a semiconductor device capable of suppressing increase of a chip area.SOLUTION: A semiconductor device comprises: an inter-layer insulation film; and a plurality of resistance films arranged onto the inter-layer insulation film. Each of the plurality of resistance films is extended to a first direction along an upper surface of the plurality of resistance films in a plan view. The plurality of resistance films is along the upper surface of the plurality of resistance films in the plan view, and is arranged with an interval to a second direction orthogonal to a first direction. The plurality of resistance films is divided into a first group; a second group; and a third group. The first group is positioned between the second group and the third group to a second direction. Each second width modulation amount of the plurality of second resistance films belongs to the second group and each third width modulation amount of the plurality of third resistance films belong to the third group are larger than each first width modulation amount of the plurality of first resistance films belonged to the first group.SELECTED DRAWING: Figure 2

Description

Technical Field

[0004] , ,

[0005] , ,

[0001] The present disclosure relates to a semiconductor device.

Background Art

[0002] The semiconductor device described in Japanese Patent Application Laid-Open No. 2011-155192 (Patent Document 1) has an interlayer insulating film and a plurality of resistance films. The plurality of resistance films are disposed on the interlayer insulating film. Each of the plurality of resistance films extends along a first direction. The plurality of resistance films are arranged at intervals along a second direction orthogonal to the first direction.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

[0006] The semiconductor device described herein makes it possible to suppress an increase in chip area. [Brief explanation of the drawing]

[0007] [Figure 1] This is a cross-sectional view of semiconductor device DEV1. [Figure 2] This is a planar layout diagram of multiple resistive RFs in semiconductor device DEV1. [Figure 3] This is a schematic block diagram of semiconductor device DEV1. [Figure 4] This is a manufacturing process diagram for semiconductor device DEV1. [Figure 5] This is a cross-sectional view illustrating the first wiring formation process S1. [Figure 6] This is a cross-sectional view illustrating the first interlayer insulating film formation process S2. [Figure 7]It is a cross-sectional view for explaining the first via hole forming step S3. [Figure 8] It is a cross-sectional view for explaining the first via plug forming step S4. [Figure 9] It is a cross-sectional view for explaining the resistive film forming step S5. [Figure 10] It is a cross-sectional view for explaining the second interlayer insulating film forming step S6. [Figure 11] It is a cross-sectional view for explaining the second via hole forming step S7. [Figure 12] It is a cross-sectional view for explaining the second via plug forming step S8. [Figure 13] It is a cross-sectional view for explaining the second wiring forming step S9. [Figure 14] It is a plan layout view of the resistive film RF in the semiconductor device DEV2. [Figure 15] It is a plan layout view of the resistive film RF in the semiconductor device DEV3. [Figure 16] It is a plan layout view of the resistive film RF in the semiconductor device DEV4. [Figure 17] ] It is a plan layout view of the resistive film RF in the semiconductor device DEV5. [Figure 18] It is a plan layout view of the resistive film RF in a modified example of the semiconductor device DEV5.

Embodiments for Carrying Out the Invention

[0008] Details of embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and redundant descriptions will not be repeated.

[0009] (First Embodiment) A semiconductor device according to the first embodiment will be described. The semiconductor device according to the first embodiment is referred to as semiconductor device DEV1.

[0010] [[ID= 50]] <Configuration of Semiconductor Device DEV1> Hereinafter, the configuration of the semiconductor device DEV1 will be described.

[0011] Figure 1 is a cross-sectional view of the semiconductor device DEV1. Figure 2 is a plan layout view of the resistive film RF in the semiconductor device DEV1. As shown in FIGS. 1 and 2, the semiconductor device DEV1 has a semiconductor substrate SUB and a plurality of interlayer insulating films ILD. The semiconductor substrate SUB is formed of, for example, single crystal silicon (Si). The plurality of interlayer insulating films ILD are disposed on the semiconductor substrate SUB. Each of the plurality of interlayer insulating films ILD is formed of, for example, silicon oxide (SiO2). One of the plurality of interlayer insulating films ILD is defined as the interlayer insulating film ILD1.

[0012] The semiconductor device DEV1 has a wiring WL1 and a wiring WL2. The wiring WL1 and the wiring WL2 are disposed on the interlayer insulating film ILD1. The wiring WL1 and the wiring WL2 are formed of, for example, aluminum (Al) or an aluminum alloy. A barrier metal BM1 is disposed between the wiring WL1 and the interlayer insulating film ILD1 and between the wiring WL2 and the interlayer insulating film ILD1. A barrier metal BM2 is disposed on the wiring WL1 and on the wiring WL2. The barrier metal BM1 and the barrier metal BM2 each consist of, for example, a laminated film of a titanium nitride (TiN) film and a titanium (Ti) film.

[0013] Another one of the plurality of interlayer insulating films ILD is defined as the interlayer insulating film ILD2. The interlayer insulating film ILD2 is disposed on the interlayer insulating film ILD1 so as to cover the wiring WL1 and the wiring WL2. Via holes VH1 and VH2 are formed in the interlayer insulating film ILD2. The via holes VH1 and VH2 penetrate the interlayer insulating film ILD2 in the thickness direction. At the bottom of the via hole VH1 and at the bottom of the via hole VH2, a part of the wiring WL1 and a part of the wiring WL2 are respectively exposed.

[0014] The semiconductor device DEV1 has via plugs VP1 and VP2. Via plugs VP1 and VP2 are embedded in via holes VH1 and VH2, respectively. Via plugs VP1 and VP2 are made of, for example, tungsten (W). The lower end of via plug VP1 is electrically connected to wiring WL1. The lower end of via plug VP2 is electrically connected to wiring WL2.

[0015] The semiconductor device DEV1 has multiple resistive film RFs. The resistive film RFs are arranged on an interlayer insulating film ILD2. The resistive film RFs are formed of a conductive material. Preferably, the resistive film RFs are formed of a material containing at least one selected from the group consisting of silicon chromium (SiCr), silicon chromium with carbon (C) introduced, nickel chromium (NiCr), titanium nitride, and tantalum nitride (TaN). However, the resistive film RFs may be formed of other conductive materials (e.g., polycrystalline silicon).

[0016] The resistive film RF is electrically connected to the upper ends of via plug VP1 and via plug VP2. This connects the resistive film RF to wiring WL1 and wiring WL2. The semiconductor device DEV1 may have multiple insulating films IF. The insulating films IF are arranged on the resistive film RF. As will be described later, the insulating films IF are masks (hard masks) for patterning the resistive film RF. The insulating films IF are formed from, for example, silicon oxide or silicon oxynitride (SiON).

[0017] Let ILD3 be one of the multiple interlayer insulating films (ILDs). ILD3 is positioned on ILD2 so as to cover multiple resistive films (RF) and multiple insulating films (IF).

[0018] Via holes VH3 and VH4 are formed in the interlayer insulating films ILD2 and ILD3. Via holes VH3 and VH4 penetrate the interlayer insulating films ILD2 and ILD3 along the thickness direction. At the bottom of via hole VH3 and the bottom of via hole VH4, a portion of wiring WL1 and a portion of wiring WL2 are exposed, respectively.

[0019] The semiconductor device DEV1 has via plugs VP3 and VP4. Via plugs VP3 and VP4 are embedded in via holes VH3 and VH4, respectively. Via plugs VP3 and VP4 are made of, for example, tungsten. The lower end of via plug VP3 is electrically connected to wiring WL1, and the lower end of via plug VP4 is electrically connected to wiring WL2.

[0020] The semiconductor device DEV1 has wiring WL3 and wiring WL4. Wiring WL3 and wiring WL4 are arranged on an interlayer insulating film ILD3. Wiring WL3 and wiring WL4 are formed of, for example, aluminum or an aluminum alloy. Barrier metal BM3 is placed between wiring WL3 and the interlayer insulating film ILD3 and between wiring WL4 and the interlayer insulating film ILD3. Barrier metal BM4 is placed on wiring WL3 and on wiring WL4. Barrier metal BM3 and barrier metal BM4 are made of, for example, a laminated film of titanium nitride and titanium. Wiring WL3 and wiring WL4 are electrically connected to the upper end of via plug VP3 and the upper end of via plug VP4, respectively. As a result, wiring WL3 is electrically connected to wiring WL1 and wiring WL4 is electrically connected to wiring WL2.

[0021] Let ILD4 be one of the multiple interlayer insulating films (ILDs). ILD4 is placed on ILD3 so as to cover wiring WL3 and wiring WL4. Although not shown in the figure, other wirings and other interlayer insulating films may be sequentially laminated on ILD4.

[0022] Each of the multiple resistive film RFs extends in a first direction D1 along the upper surface of the interlayer insulating film ILD2 in a plan view. The multiple resistive film RFs are spaced apart in a second direction D2 along the upper surface of the interlayer insulating film ILD2. The second direction D2 is perpendicular to the first direction D1.

[0023] Multiple resistive film RFs are divided into three groups: Group 1, Group 2, and Group 3. Multiple resistive film RFs belonging to Group 1 are designated as Multiple Resistive Film RF1, multiple resistive film RFs belonging to Group 2 are designated as Multiple Resistive Film RF2, and multiple resistive film RFs belonging to Group 3 are designated as Multiple Resistive Film RF3. Group 2 is located on one side of Group 1 in the second direction D2 (the left side in the example in Figure 2). That is, Group 1 is located between Group 2 and Group 3 in the second direction D2. Group 3 is located on the other side of Group 1 in the second direction D2 (the right side in the example in Figure 2). The number of Multiple Resistive Film RF1s is greater than the number of Multiple Resistive Film RF2s and Multiple Resistive Film RF3s. The lengths of each of the Multiple Resistive Film RFs are, for example, equal to each other. Here, the length of the resistive film RF is the length of the resistive film RF in the first direction D1. Note that even if the lengths of each of the Multiple Resistive Film RFs differ due to manufacturing variations, they are included if the lengths of each of the Multiple Resistive Film RFs are equal to each other.

[0024] The amount of width variation of each of the multiple resistive film RF2 (second width variation) and the amount of width variation of each of the multiple resistive film RF3 (third width variation) are greater than the amount of width variation of each of the multiple resistive film RF1 (first width variation). The first width variation is the difference between the width of each of the multiple resistive film RF1 and the reference width. The second width variation is the difference between the width of each of the multiple resistive film RF2 and the reference width. The third width variation is the difference between the width of each of the multiple resistive film RF3 and the reference width. The reference width is the width of the resistive film RF located in the center in the second direction D2. If the number of multiple resistive film RFs is even, the reference width is set to the width of one of the two resistive film RFs located in the center in the second direction D2. The first width variation of each of the multiple resistive film RF1 is, for example, within 0.5 percent of the reference width. The second width variation of each of the multiple resistive film RF2 and the third width variation of each of the multiple resistive film RF3 are, for example, greater than 0.5 percent of the reference width. In the example in Figure 2, the width of each of the multiple resistive films RF2 and the width of each of the multiple resistive films RF3 are smaller than the width of each of the multiple resistive films RF1. Here, the width of the resistive film RF is the width of the resistive film RF in the second direction D2.

[0025] Figure 3 is a schematic block diagram of the semiconductor device DEV1. As shown in Figure 3, the semiconductor device DEV1 has a plurality of circuits CIR1 and a plurality of circuits CIR2. The plurality of circuits CIR1 constitute a first circuit group. The plurality of circuits CIR2 constitute a second circuit group. The plurality of resistive films RF1 are electrically connected to the first circuit group. The plurality of resistive films RF2 and the plurality of resistive films RF3 are electrically connected to the second circuit group. The second circuit group is different from the first circuit group. Alternatively, the plurality of resistive films RF2 may be electrically connected to the second circuit group, and the plurality of resistive films RF3 may be electrically connected to a third circuit group different from the first and second circuit groups.

[0026] Each of the multiple circuits CIR1 is preferably at least one of an analog-to-digital converter circuit, a digital-to-analog converter circuit, a bandgap reference circuit, a high-frequency circuit, and an amplification circuit. Each of the multiple circuits CIR2 is preferably at least one of a circuit on which calibration is performed and a circuit that generates a voltage from the power supply voltage. In other words, the second group of circuits is preferably a group of circuits that require lower accuracy in electrical resistance values ​​than the first group of circuits.

[0027] <Manufacturing method for semiconductor device DEV1> The manufacturing method for the semiconductor device DEV1 is described below.

[0028] Figure 4 is a manufacturing process diagram for semiconductor device DEV1. As shown in Figure 4, the manufacturing method for semiconductor device DEV1 includes a first wiring formation step S1, a first interlayer insulating film formation step S2, a first via hole formation step S3, a first via plug formation step S4, a resistive film formation step S5, a second interlayer insulating film formation step S6, a second via hole formation step S7, a second via plug formation step S8, a second wiring formation step S9, and a third interlayer insulating film formation step S10.

[0029] Before the first wiring formation process S1 is performed, the interlayer insulating film ILD1 and the structures below it are formed. Since these structures can be formed by conventionally known methods, their description is omitted here.

[0030] Figure 5 is a cross-sectional view illustrating the first wiring formation process S1. As shown in Figure 5, in the first wiring formation process S1, wiring WL1, wiring WL2, barrier metal BM1, and barrier metal BM2 are formed on the interlayer insulating film ILD1. In the first wiring formation process S1, firstly, the constituent materials of barrier metal BM1, wiring WL1 (wiring WL2), and barrier metal BM2 are sequentially deposited, for example, by a sputtering method. Secondly, a resist pattern is formed on the constituent material of the deposited barrier metal BM2. The resist pattern is formed by exposing and developing a photoresist.

[0031] Thirdly, the constituent materials of the deposited barrier metal BM1, wiring WL1 (wiring WL2), and barrier metal BM2 are etched using the above resist pattern as a mask. As a result, wiring WL1, wiring WL2, barrier metal BM1, and barrier metal BM2 are formed. After the formation of wiring WL1, wiring WL2, barrier metal BM1, and barrier metal BM2, the above resist pattern is removed.

[0032] Figure 6 is a cross-sectional view illustrating the first interlayer insulating film formation step S2. In the first interlayer insulating film formation step S2, as shown in Figure 6, an interlayer insulating film ILD2 is formed on the interlayer insulating film ILD1 so as to cover the wiring WL1, wiring WL2, barrier metal BM1, and barrier metal BM2. In the first interlayer insulating film formation step S2, firstly, the constituent material of the interlayer insulating film ILD2 is deposited on the interlayer insulating film ILD1 so as to cover the wiring WL1, wiring WL2, barrier metal BM1, and barrier metal BM2, for example by the CVD (Chemical Vapor Deposition) method. Secondly, the upper surface of the constituent material of the deposited interlayer insulating film ILD2 is planarized, for example by the CMP (Chemical Mechanical Polishing) method. Through these steps, the interlayer insulating film ILD2 is formed.

[0033] Figure 7 is a cross-sectional view illustrating the first via hole formation step S3. In the first via hole formation step S3, via holes VH1 and VH2 are formed in the interlayer insulating film ILD2, as shown in Figure 7. In the first via hole formation step S3, firstly, a resist pattern is formed on the interlayer insulating film ILD2. The resist pattern is formed by exposing and developing a photoresist. Secondly, the interlayer insulating film ILD2 is etched using the resist pattern as a mask. As a result, via holes VH1 and VH2 are formed. After the formation of via holes VH1 and VH2, the resist pattern is removed.

[0034] Figure 8 is a cross-sectional view illustrating the first via plug formation step S4. In the first via plug formation step S4, as shown in Figure 8, via plugs VP1 and VP2 are formed in via holes VH1 and VH2. In the first via plug formation step S4, firstly, via holes VH1 and VH2 are filled with the constituent material of via plug VP1 (via plug VP2), for example by CVD. Secondly, the constituent material of via plug VP1 (via plug VP2) that has protruded from via holes VH1 and VH2 is removed, for example by CMP. As a result, via plugs VP1 and VP2 are formed.

[0035] Figure 9 is a cross-sectional view illustrating the resistive film formation process S5. As shown in Figure 9, in the resistive film formation process S5, a resistive film RF and an insulating film IF are formed on the interlayer insulating film ILD2. In the resistive film formation process S5, firstly, the constituent material of the resistive film RF is deposited on the interlayer insulating film ILD2, for example, by sputtering. Secondly, the constituent material of the insulating film IF is deposited on the deposited constituent material of the resistive film RF. Thirdly, a resist pattern is formed on the deposited constituent material of the insulating film IF. The resist pattern is formed by exposing and developing a photoresist.

[0036] Fourth, the constituent material of the deposited insulating film IF is etched using the above resist pattern as a mask. This forms the insulating film IF. After the formation of the insulating film IF, the above resist pattern is removed. Fifth, the constituent material of the deposited resistive film RF is etched using the insulating film IF as a mask (hard mask). This forms the resistive film RF. Note that the insulating film IF is not removed after the formation of the resistive film RF.

[0037] Figure 10 is a cross-sectional view illustrating the second interlayer insulating film formation step S6. In the second interlayer insulating film formation step S6, as shown in Figure 10, an interlayer insulating film ILD3 is formed on the interlayer insulating film ILD2 so as to cover the resistive film RF. In the second interlayer insulating film formation step S6, firstly, the constituent material of the interlayer insulating film ILD3 is deposited on the interlayer insulating film ILD2, for example by CVD, so as to cover the resistive film RF. Secondly, the upper surface of the constituent material of the deposited interlayer insulating film ILD3 is planarized, for example by CMP. Through these steps, the interlayer insulating film ILD3 is formed.

[0038] Figure 11 is a cross-sectional view illustrating the second via hole formation process S7. In the second via hole formation process S7, as shown in Figure 11, via holes VH3 and VH4 are formed in the interlayer insulating film ILD2 and ILD3.

[0039] In the second via hole formation step S7, firstly, a resist pattern is formed on the interlayer insulating film ILD3. The resist pattern is formed by exposing and developing a photoresist. Secondly, the interlayer insulating films ILD2 and ILD3 are etched using the above resist pattern as a mask. As a result, via holes VH3 and VH4 are formed. After the formation of via holes VH3 and VH4, the above resist pattern is removed.

[0040] Figure 12 is a cross-sectional view illustrating the second via plug formation step S8. In the second via plug formation step S8, as shown in Figure 12, via plugs VP3 and VP4 are formed in via holes VH3 and VH4, respectively.

[0041] In the second via plug formation step S8, firstly, via holes VH3 and VH4 are filled with the constituent material of via plug VP3 (via plug VP4) by, for example, CVD. Secondly, the constituent material of via plug VP3 (via plug VP4) that has protruded from via holes VH3 and VH4 is removed by, for example, CMP. As a result, via plugs VP3 and VP4 are formed.

[0042] Figure 13 is a cross-sectional view illustrating the second wiring formation process S9. As shown in Figure 13, in the second wiring formation process S9, wiring WL3, wiring WL4, barrier metal BM3, and barrier metal BM4 are formed on the interlayer insulating film ILD3. In the second wiring formation process S9, firstly, the constituent materials of barrier metal BM3, wiring WL3 (wiring WL4), and barrier metal BM4 are sequentially deposited, for example, by a sputtering method. Secondly, a resist pattern is formed on the constituent material of the deposited barrier metal BM4. The resist pattern is formed by exposing and developing a photoresist.

[0043] Thirdly, the constituent materials of the deposited barrier metal BM3, wiring WL3 (wiring WL4), and barrier metal BM4 are etched using the above resist pattern as a mask. As a result, wiring WL3, wiring WL4, barrier metal BM3, and barrier metal BM4 are formed. The above resist pattern is removed after the formation of wiring WL3, wiring WL4, barrier metal BM3, and barrier metal BM4.

[0044] In the third interlayer insulating film formation step S10, an interlayer insulating film ILD4 is formed on the interlayer insulating film ILD3 so as to cover the wiring WL3, wiring WL4, barrier metal BM3, and barrier metal BM4. In the third interlayer insulating film formation step S10, firstly, the constituent material of the interlayer insulating film ILD4 is deposited on the interlayer insulating film ILD3, for example by CVD, so as to cover the wiring WL3, wiring WL4, barrier metal BM3, and barrier metal BM4. Secondly, the upper surface of the constituent material of the deposited interlayer insulating film ILD4 is planarized, for example by CMP. As a result, the semiconductor device DEV1 with the structure shown in Figure 1 is formed. After the third interlayer insulating film formation step S10 is performed, other wiring and other interlayer insulating films are sequentially laminated on the interlayer insulating film ILD4. These structures can be formed by conventionally known methods, so their explanation is omitted here.

[0045] <Effects of Semiconductor Device DEV1> The effects of semiconductor device DEV1 are explained below.

[0046] In semiconductor device DEV1, due to the microloading effect during etching in the resistive film formation process S5, even if the design ensures that the width of each of the multiple resistive films RF is constant, the widths of each of the multiple resistive films RF2 and each of the multiple resistive films RF3 may end up being smaller than the designed width.

[0047] If multiple resistive films RF2 and RF3 are electrically connected to a first circuit group where resistance accuracy is required, the accuracy of the circuits included in the first circuit group will decrease. On the other hand, in some cases, multiple resistive films RF2 and RF3 can be made into dummy resistive films that are not electrically connected to the circuit, and other resistive films that are electrically connected to a second circuit group can be formed. In this case, although the decrease in accuracy of the circuits included in the first circuit group can be suppressed, the chip area increases because additional resistive films that are electrically connected to the second circuit group are formed.

[0048] In semiconductor device DEV1, multiple resistive RF1s are electrically connected to a first circuit group, and multiple resistive RF2s and multiple resistive RF3s are electrically connected to a second circuit group. This suppresses the reduction in accuracy of the circuits included in the first circuit group while suppressing an increase in chip area. This embodiment is not limited to the case where multiple resistive RFs are electrically connected to a first circuit group and a second circuit group. Multiple resistive RFs may be electrically connected to three or more circuit groups. For example, multiple resistive RF1s may be electrically connected to a first circuit group, multiple resistive RF2s may be electrically connected to a second circuit group, and multiple resistive RF3s may be electrically connected to a third circuit group. In this case, multiple resistive RFs can be used in more circuits while suppressing an increase in chip size.

[0049] (Second Embodiment) A semiconductor device according to the second embodiment will be described. The semiconductor device according to the second embodiment will be referred to as semiconductor device DEV2. Here, the differences from semiconductor device DEV1 will be mainly explained, and redundant explanations will not be repeated.

[0050] The semiconductor device DEV2 comprises a semiconductor substrate SUB, interlayer insulating films ILD1, ILD2, ILD3, and ILD4, wiring WL1, WL2, WL3, and WL4, multiple resistive films RF1, RF2, and RF3, and via plugs VP1, VP2, VP3, and VP4. In semiconductor device DEV2, multiple resistive films RF1 are electrically connected to a first circuit group, and multiple resistive films RF2 and RF3 are electrically connected to a second circuit group. In these respects, the configuration of semiconductor device DEV2 is the same as that of semiconductor device DEV1.

[0051] Figure 14 is a planar layout diagram of the resistive RF in semiconductor device DEV2. As shown in Figure 14, in semiconductor device DEV2, the width of each of the multiple resistive RF2s and the width of each of the multiple resistive RF3s are greater than the width of each of the multiple resistive RF1s. In this respect, the configuration of semiconductor device DEV2 differs from the configuration of semiconductor device DEV1.

[0052] In semiconductor device DEV2, multiple resistive films RF1 are electrically connected to the first circuit group, and multiple resistive films RF2 and multiple resistive films RF3 are electrically connected to the second circuit group. Therefore, similar to semiconductor device DEV1, it is possible to suppress the increase in chip area while suppressing the degradation of accuracy of the circuits included in the first circuit group.

[0053] (Third embodiment) A semiconductor device according to the third embodiment will be described. The semiconductor device according to the third embodiment will be referred to as semiconductor device DEV3. Here, the differences from semiconductor device DEV1 will be mainly explained, and redundant explanations will not be repeated.

[0054] The semiconductor device DEV3 comprises a semiconductor substrate SUB, interlayer insulating films ILD1, ILD2, ILD3, and ILD4, wiring WL1, WL2, WL3, and WL4, multiple resistive films RF1, RF2, and RF3, and via plugs VP1, VP2, VP3, and VP4. In semiconductor device DEV3, multiple resistive films RF1 are electrically connected to a first circuit group, and multiple resistive films RF2 and RF3 are electrically connected to a second circuit group. In these respects, the configuration of semiconductor device DEV3 is the same as that of semiconductor device DEV1.

[0055] Figure 15 is a planar layout diagram of resistive RFs in semiconductor device DEV3. As shown in Figure 15, in semiconductor device DEV3, each of the multiple resistive RFs 2 decreases in width the further they are on one side in the second direction D2 (the left side in the example of Figure 15). That is, the width of each of the multiple resistive RFs 2 decreases as the distance from the first group (multiple resistive RFs 1) increases in the second direction D2. Also, in semiconductor device DEV3, the difference in width between two adjacent resistive RFs 2 increases as you move toward one side in the second direction D2. That is, the difference in width between two adjacent resistive RFs 2 increases as the distance from the first group increases in the second direction D2. Similarly, each of the multiple resistive RFs 3 decreases in width the further they are on the other side in the second direction D2 (the right side in the example of Figure 15), and the difference in width between two adjacent resistive RFs 3 increases as you move toward the other side in the second direction D2. In other words, the width of each of the multiple resistive films RF3 decreases as the distance from the first group increases in the second direction D2, and the difference in width between two adjacent resistive films RF3 increases as the distance from the first group increases. From another perspective, the width of each of the multiple resistive films RF2 changes exponentially as the distance from the first group increases in the second direction D2, and the width of each of the multiple resistive films RF3 changes exponentially as the distance from the first group increases in the second direction D2.

[0056] In semiconductor device DEV3, the second circuit group includes an image processing circuit, and multiple resistive films RF2 and multiple resistive films RF3 are electrically connected to the image processing circuit. In the image processing circuit, it is possible to suitably use multiple resistive films RF2 and multiple resistive films RF3 with varying widths as described above.

[0057] In semiconductor device DEV3, multiple resistive films RF1 are electrically connected to the first circuit group, and multiple resistive films RF2 and multiple resistive films RF3 are electrically connected to the second circuit group. Therefore, similar to semiconductor device DEV1, it is possible to suppress the reduction in accuracy of the circuits included in the first circuit group while suppressing the increase in chip area.

[0058] (Fourth Embodiment) A semiconductor device according to the fourth embodiment will be described. The semiconductor device according to the fourth embodiment will be referred to as semiconductor device DEV4. Here, the differences from semiconductor device DEV1 will be mainly explained, and redundant explanations will not be repeated.

[0059] The semiconductor device DEV4 comprises a semiconductor substrate SUB, interlayer insulating films ILD1, ILD2, ILD3, and ILD4, wiring WL1, WL2, WL3, and WL4, multiple resistive films RF1, RF2, and RF3, and via plugs VP1, VP2, VP3, and VP4. In semiconductor device DEV4, multiple resistive films RF1 are electrically connected to the first circuit group. In these respects, the configuration of semiconductor device DEV4 is the same as that of semiconductor device DEV1.

[0060] Figure 16 is a planar layout diagram of resistive RFs in semiconductor device DEV4. As shown in Figure 16, in semiconductor device DEV4, a portion of the multiple resistive RFs 2 form a fourth group, and the remainder of the multiple resistive RFs 2 form a fifth group. The multiple resistive RFs 2 belonging to the fourth group are called the multiple resistive RFs 2a. The resistive RFs 2 belonging to the fifth group are called resistive RFs 2b. The resistive RFs 2b are located on one side of the multiple resistive RFs 2a in the second direction D2 (the left side in the example of Figure 16). That is, the multiple resistive RFs 2a are located between the multiple resistive RFs 1 and 2b in the second direction D2. The width of the resistive RFs 2b is greater than the width of each of the multiple resistive RFs 2a.

[0061] Furthermore, in semiconductor device DEV4, a portion of the multiple resistive films RF3 form group 6, and the remainder of the multiple resistive films RF3 form group 7. The multiple resistive films RF3 belonging to group 6 are referred to as the multiple resistive films RF3a. The resistive films RF3 belonging to group 7 are referred to as resistive films RF3b. The resistive films RF3b are located on the other side of the second direction D2 (to the right in the example of Figure 16) than the multiple resistive films RF3a. That is, the multiple resistive films RF3a are located between the multiple resistive films RF1 and the resistive films RF3b in the second direction D2. The width of the resistive films RF3b is greater than the width of each of the multiple resistive films RF3a.

[0062] In semiconductor device DEV4, multiple resistive films RF2a and multiple resistive films RF3a are electrically connected to the second circuit group. However, resistive films RF2b and RF3b are not electrically connected to the second circuit group or other circuits. In other words, in semiconductor device DEV4, some of the multiple resistive films RF2 and some of the multiple resistive films RF3 are electrically connected to the second circuit group, but the remaining parts of the multiple resistive films RF2 and the remaining parts of the multiple resistive films RF3 are dummy resistive films. In these respects, the configuration of semiconductor device DEV4 differs from the configuration of semiconductor device DEV1.

[0063] In the example above, there was one resistive RF2 in group 5 and one resistive RF3 in group 7, but there may be multiple resistive RF2s in group 5 and multiple resistive RF3s in group 7.

[0064] In semiconductor device DEV4, multiple resistive films RF1 are electrically connected to the first circuit group, while some of the multiple resistive films RF2 and some of the multiple resistive films RF3 are electrically connected to the second circuit group. Therefore, similar to semiconductor device DEV1, it is possible to suppress the increase in chip area while suppressing the degradation of accuracy of the circuits included in the first circuit group. Furthermore, in semiconductor device DEV4, the remaining portions of the multiple resistive films RF2 and the multiple resistive films RF3, which have increased width, are not electrically connected to the second circuit group, thus suppressing the degradation of accuracy of the circuits included in the second circuit group.

[0065] (Fifth embodiment) A semiconductor device according to the fifth embodiment will be described. The semiconductor device according to the fifth embodiment will be referred to as semiconductor device DEV5. Here, the differences from semiconductor device DEV1 will be mainly explained, and redundant explanations will not be repeated.

[0066] The semiconductor device DEV5 comprises a semiconductor substrate SUB, interlayer insulating films ILD1, ILD2, ILD3, and ILD4, wiring WL1, WL2, WL3, and WL4, multiple resistive films RF1, RF2, and RF3, and via plugs VP1, VP2, VP3, and VP4. In semiconductor device DEV5, multiple resistive films RF1 are electrically connected to a first circuit group, and multiple resistive films RF2 and RF3 are electrically connected to a second circuit group. In these respects, the configuration of semiconductor device DEV5 is the same as that of semiconductor device DEV1.

[0067] Figure 17 is a planar layout diagram of the resistive RF in semiconductor device DEV5. As shown in Figure 17, in semiconductor device DEV5, the length of each of the multiple resistive RF2 is shorter than the length of each of the multiple resistive RF1. In this respect, the configuration of semiconductor device DEV5 differs from the configuration of semiconductor device DEV1.

[0068] In semiconductor device DEV5, multiple resistive films RF1 are electrically connected to the first circuit group, and multiple resistive films RF2 and multiple resistive films RF3 are electrically connected to the second circuit group. Therefore, similar to semiconductor device DEV1, it is possible to suppress the reduction in accuracy of the circuits included in the first circuit group while suppressing the increase in chip area. In addition, in semiconductor device DEV5, the length of each of the multiple resistive films RF2 can be adjusted according to the type of circuit to which they are connected, thus improving the flexibility of the layout.

[0069] <Variation> In the example above, the resistance value of each of the multiple resistive films RF2 is adjusted by adjusting the length of each of the multiple resistive films RF2. Figure 18 is a planar layout diagram of resistive films RF in a modified example of semiconductor device DEV5. As shown in Figure 18, the resistance value of each of the multiple resistive films RF2 may be adjusted by adjusting the spacing between via plugs VP1 and VP2. More specifically, the spacing in the first direction D1 between via plugs VP1 and VP2 electrically connected to resistive film RF2 may be shorter than the spacing in the first direction D1 between via plugs VP1 and VP2 electrically connected to resistive film RF1.

[0070] Although the present invention has been specifically described above based on embodiments, it goes without saying that the present invention is not limited to the above embodiments and can be modified in various ways without departing from its essence. [Explanation of symbols]

[0071] BM1, BM2, BM3, BM4 Barrier metal, CIR1, CIR2 Circuit, D1 First direction, D2 Second direction, DEV1, DEV2, DEV3, DEV4, DEV5 Semiconductor device, IF Insulating film, ILD Interlayer insulating film, ILD1, ILD2, ILD3, ILD4 Interlayer insulating film, RF, RF1, RF2, RF2a, RF2b, RF3, RF3a, RF3b Resistive film, S1 First wiring formation process, S2 First interlayer insulating film formation process, S3 First via hole formation process, S4 First via plug formation process, S5 Resistive film formation process, S6 Second interlayer insulating film formation process, S7 Second via hole formation process, S8 Second via plug formation process, S9 Second wiring formation process, S10 Third interlayer insulating film formation process, VH1, VH2, VH3, VH4 Via hole, VP1, VP2, VP3, VP4 Via plugs, WL1, WL2, WL3, WL4 wiring, SUB semiconductor substrate.

Claims

1. Interlayer insulating film and The system comprises a plurality of resistive films disposed on the interlayer insulating film, Each of the plurality of resistive films extends in a first direction along the upper surface of the interlayer insulating film in a plan view, The plurality of resistive films are arranged in a plan view along the upper surface of the interlayer insulating film and spaced apart in a second direction perpendicular to the first direction. The aforementioned plurality of resistive films are divided into a first group, a second group, and a third group. The first group is located between the second group and the third group in the second direction. The second width variation of each of the multiple second resistive films belonging to the second group and the third width variation of each of the multiple third resistive films belonging to the third group are greater than the first width variation of each of the multiple first resistive films belonging to the first group. The first width variation is the difference between the reference width and the width of each of the plurality of first resistive films. The second width variation is the difference between the reference width and the width of each of the plurality of second resistive films. The third width variation is the difference between the reference width and the width of each of the plurality of third resistive films. The aforementioned reference width is the width of one of the plurality of resistive films located in the center in the second direction. The plurality of first resistive films are electrically connected to the first circuit group. At least a portion of the plurality of second resistive films and / or at least a portion of the plurality of third resistive films are electrically connected to a second circuit group different from the first circuit group. The first group of circuits includes at least one of an analog-to-digital converter circuit, a digital-to-analog converter circuit, a bandgap reference circuit, a high-frequency circuit, and an amplification circuit. The second group of circuits includes at least one of a circuit on which calibration is performed and a circuit on which a voltage is generated from a power supply voltage, wherein the semiconductor device.

2. The semiconductor device according to claim 1, wherein the plurality of second resistive films and the plurality of third resistive films are electrically connected to the second circuit group.

3. The semiconductor device according to claim 2, wherein the width of each of the plurality of second resistive films and the width of each of the plurality of third resistive films are smaller than the reference width.

4. The semiconductor device according to claim 3, wherein, in the first direction, the length of each of the plurality of second resistive films is shorter than the length of each of the plurality of first resistive films.

5. The semiconductor device according to claim 2, wherein the width of each of the plurality of second resistive films and the width of each of the plurality of third resistive films are greater than the reference width.

6. The width of each of the plurality of second resistive films decreases as the distance from the first group increases in the second direction. The difference in width between two adjacent second resistive films in the plurality of second resistive films increases as the distance from the first group increases in the second direction. The width of each of the plurality of third resistive films decreases as the distance from the first group increases in the second direction. The semiconductor device according to claim 2, wherein the difference in width between two adjacent third resistive films among the plurality of third resistive films increases as the distance from the first group increases in the second direction.

7. A portion of the plurality of second resistive films and a portion of the plurality of third resistive films are electrically connected to the second circuit group. The semiconductor device according to claim 1, wherein the remainder of the plurality of second resistive films and the remainder of the plurality of third resistive films are dummy resistive films.

8. The semiconductor device according to claim 1, wherein each of the plurality of resistive films is formed of a material comprising at least one selected from the group consisting of silicon chromium, silicon chromium with carbon introduced, nickel chromium, titanium nitride, and tantalum nitride.

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