Indication device

Abstract

To provide a display device capable of improving display quality.SOLUTION: A display device comprises: a substrate; a pixel circuit arranged above the substrate; an insulating layer that covers the pixel circuit and has a contact hole; a lower electrode arranged above the insulating layer, and connected with the pixel circuit via the contact hole; an upper electrode opposed to the lower electrode; an organic layer located between the lower electrode and the upper electrode, emitting light depending on a potential difference between the lower electrode and the upper electrode; a rib formed of an inorganic material, having an opening overlapping with the lower electrode; a barrier arranged above the rib; and a filler arranged inside the contact hole. The organic layer includes: a first organic layer in contact with the lower electrode via the opening; and a second organic layer located on the barrier and separated from the first organic layer. The barrier and the rib overlap with at least a part of the contact hole and at least a part of the filler in plan view.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] Embodiments of the present invention relate to a display device.

Background Art

[0002] In recent years, display devices applying organic light-emitting diodes (OLEDs) as display elements have been put into practical use. This display element includes a pixel circuit including a thin-film transistor, a lower electrode connected to the pixel circuit, an organic layer covering the lower electrode, and an upper electrode covering the organic layer.

[0003] Generally, the pixel circuit is covered with an insulating layer formed of an organic material, and the lower electrode is connected to the pixel circuit through a contact hole provided in this insulating layer. If an element disposed on the insulating layer is deformed by the contact hole, display defects may occur.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Summary of the Invention

Problems to be Solved by the Invention

[0005] An object of the present invention is to provide a display device capable of improving display quality.

Means for Solving the Problems

[0006] A display device according to one embodiment includes a substrate, a pixel circuit disposed above the substrate, an insulating layer covering the pixel circuit and having contact holes, a lower electrode disposed above the insulating layer and connected to the pixel circuit through the contact holes, an upper electrode facing the lower electrode, an organic layer located between the lower electrode and the upper electrode and emitting light in accordance with the potential difference between the lower electrode and the upper electrode, a rib made of an inorganic material and having an opening that overlaps with the lower electrode, a partition wall disposed above the rib, and a filler disposed inside the contact hole. The organic layer includes a first organic layer that contacts the lower electrode through the opening, and a second organic layer located above the partition wall and spaced apart from the first organic layer. The partition wall and the rib overlap at least a portion of the contact hole and the filler in a plan view. [Brief explanation of the drawing]

[0007] [Figure 1] Figure 1 shows an example of the configuration of a display device according to the first embodiment. [Figure 2] Figure 2 shows an example of the sub-pixel layout according to the first embodiment. [Figure 3] Figure 3 is a schematic cross-sectional view of the display device along the line III-III in Figure 2. [Figure 4] Figure 4 is a schematic plan view, an enlarged portion of Figure 2. [Figure 5] Figure 5 is a schematic cross-sectional view of the display device along the VV line in Figure 4. [Figure 6] Figure 6 is a schematic cross-sectional view showing a part of the manufacturing process of the display device according to the first embodiment. [Figure 7] Figure 7 is a schematic cross-sectional view of a comparative example of a display device. [Figure 8] Figure 8 is a schematic cross-sectional view of the display device according to the second embodiment. [Figure 9] Figure 9 is a schematic cross-sectional view of the display device according to the third embodiment. [Figure 10]Figure 10 is a schematic cross-sectional view of the display device according to the fourth embodiment. [Modes for carrying out the invention]

[0008] Several embodiments will be described with reference to the drawings. The disclosure is merely an example, and any modifications that a person skilled in the art could easily conceive of while maintaining the spirit of the invention are naturally included within the scope of the present invention. Furthermore, the drawings may schematically represent the width, thickness, shape, etc., of each part in order to clarify the explanation, but these are merely examples and do not limit the interpretation of the present invention. In addition, in this specification and each drawing, the same reference numerals are used for components that perform the same or similar functions as those described above with respect to previously shown drawings, and redundant detailed explanations may be omitted as appropriate.

[0009] Furthermore, the drawings will include mutually orthogonal X, Y, and Z axes as needed to facilitate understanding. The direction along the X axis will be referred to as the first direction, the direction along the Y axis as the second direction, and the direction along the Z axis as the third direction. Viewing the various elements parallel to the third direction Z is called a plan view.

[0010] Each embodiment of the display device is an organic electroluminescent display device equipped with an organic light-emitting diode (OLED) as a display element, and can be mounted in televisions, personal computers, in-vehicle equipment, tablet terminals, smartphones, mobile phone terminals, and the like.

[0011] [First Embodiment] Figure 1 shows an example configuration of a display device DSP according to the first embodiment. The display device DSP has a display area DA for displaying an image and a peripheral area SA around the display area DA, on an insulating substrate 10. The substrate 10 may be glass or a flexible resin film.

[0012] In this embodiment, the shape of the substrate 10 in plan view is rectangular. However, the shape of the substrate 10 in plan view is not limited to a rectangle, and may be other shapes such as a square, a circle, or an ellipse.

[0013] The display area DA includes a plurality of pixels PX arranged in a matrix in the first direction X and the second direction Y. The pixel PX includes a plurality of sub-pixels SP. In one example, the pixel PX includes a red sub-pixel SP1 (first sub-pixel), a green sub-pixel SP2 (second sub-pixel), and a blue sub-pixel SP3 (third sub-pixel). Note that the pixel PX may include sub-pixels SP of other colors such as white, either together with the sub-pixels SP1, SP2, SP3 or in place of any of the sub-pixels SP1, SP2, SP3.

[0014] The sub-pixel SP includes a pixel circuit 1 and a display element 20 driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a driving transistor 3, and a capacitor 4. The pixel switch 2 and the driving transistor 3 are switching elements constituted by, for example, thin film transistors.

[0015] The gate electrode of the pixel switch 2 is connected to the scanning line GL. One of the source electrode and the drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the driving transistor 3 and the capacitor 4. In the driving transistor 3, one of the source electrode and the drain electrode is connected to the power supply line PL and the capacitor 4, and the other is connected to the display element 20.

[0016] Note that the configuration of the pixel circuit 1 is not limited to the illustrated example. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0017] The display element 20 is an organic light emitting diode (OLED) as a light emitting element. For example, the sub-pixel SP1 includes a display element 20 that emits light in a red wavelength range, the sub-pixel SP2 includes a display element 20 that emits light in a green wavelength range, and the sub-pixel SP3 includes a display element 20 that emits light in a blue wavelength range.

[0018] Figure 2 shows an example of the layout of sub-pixels SP1, SP2, and SP3. In the example in Figure 2, sub-pixels SP1 and SP2 are aligned in the second direction Y. Furthermore, sub-pixels SP1 and SP2 are aligned with sub-pixel SP3 in the first direction X.

[0019] When sub-pixels SP1, SP2, and SP3 are arranged in this manner, the display area DA forms columns in which sub-pixels SP1 and SP2 are alternately arranged in the second direction Y, and columns in which multiple sub-pixels SP3 are repeatedly arranged in the second direction Y. These columns are arranged alternately in the first direction X.

[0020] Note that the layout of sub-pixels SP1, SP2, and SP3 is not limited to the example in Figure 2. Another example is that the sub-pixels SP1, SP2, and SP3 in each pixel PX may be arranged sequentially in the first direction X.

[0021] The display area DA has ribs 5 and partition walls 6. Ribs 5 have apertures AP1, AP2, and AP3 in sub-pixels SP1, SP2, and SP3, respectively. In the example in Figure 2, aperture AP2 is larger than aperture AP1, and aperture AP3 is larger than aperture AP2.

[0022] The partition wall 6 overlaps with the rib 5 in a plan view. The partition wall 6 has a plurality of first partition walls 6x extending in the first direction X and a plurality of second partition walls 6y extending in the second direction Y. The plurality of first partition walls 6x are arranged between adjacent openings AP1 and AP2 in the second direction Y, and between two adjacent openings AP3 in the second direction Y. The second partition walls 6y are arranged between adjacent openings AP1 and AP3 in the first direction X, and between adjacent openings AP2 and AP3 in the first direction X.

[0023] In the example shown in Figure 2, the first partition wall 6x and the second partition wall 6y are connected to each other. As a result, the partition wall 6 as a whole forms a grid that surrounds the openings AP1, AP2, and AP3. It can also be said that the partition wall 6, like the rib 5, has openings in the sub-pixels SP1, SP2, and SP3.

[0024] Sub-pixel SP1 comprises a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, which overlap with aperture AP1. Sub-pixel SP2 comprises a lower electrode LE2, an upper electrode UE2, and an organic layer OR2, which overlap with aperture AP2. Sub-pixel SP3 comprises a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, which overlap with aperture AP3. In the example in Figure 2, the outer shapes of upper electrode UE1 and organic layer OR1 match, upper electrode UE2 and organic layer OR2 match, and upper electrode UE3 and organic layer OR3 match.

[0025] The lower electrode LE1, upper electrode UE1, and organic layer OR1 constitute the display element 20 of the sub-pixel SP1. The lower electrode LE2, upper electrode UE2, and organic layer OR2 constitute the display element 20 of the sub-pixel SP2. The lower electrode LE3, upper electrode UE3, and organic layer OR3 constitute the display element 20 of the sub-pixel SP3.

[0026] The lower electrode LE1 is connected to the pixel circuit 1 of the sub-pixel SP1 (see Figure 1) through the contact hole CH1. The lower electrode LE2 is connected to the pixel circuit 1 of the sub-pixel SP2 through the contact hole CH2. The lower electrode LE3 is connected to the pixel circuit 1 of the sub-pixel SP3 through the contact hole CH3.

[0027] The contact holes CH1, CH2, and CH3 overlap with rib 5 overall. At least a portion of contact holes CH1 and CH2 overlaps with the first partition wall 6x between adjacent openings AP1 and AP2 in the second direction Y. At least a portion of contact hole CH3 overlaps with the first partition wall 6x between two adjacent openings AP3 in the second direction Y.

[0028] In the example shown in Figure 2, the lower electrode LE1 has a protrusion PR1 projecting toward the lower electrode LE2, and the lower electrode LE2 has a protrusion PR2 projecting toward the lower electrode LE1. The contact holes CH1 and CH2 overlap with the protrusions PR1 and PR2, respectively.

[0029] Figure 3 is a schematic cross-sectional view of the display device DSP along the line III-III in Figure 2. A circuit layer 11 is arranged on the substrate 10 described above. The circuit layer 11 includes various circuits and wiring, such as the pixel circuit 1, scan line GL, signal line SL, and power line PL shown in Figure 1. The circuit layer 11 is covered by an insulating layer 12. The insulating layer 12 functions as a planarizing film that flattens the irregularities caused by the circuit layer 11. Although not shown in the cross-section of Figure 3, the contact holes CH1, CH2, and CH3 described above are provided in the insulating layer 12.

[0030] The lower electrodes LE1, LE2, and LE3 are positioned on the insulating layer 12. The rib 5 is positioned on the insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by the rib 5.

[0031] The bulkhead 6 includes a lower section 61 positioned on the rib 5 and an upper section 62 covering the upper surface of the lower section 61. The upper section 62 has a greater width than the lower section 61. As a result, in Figure 3, both ends of the upper section 62 protrude beyond the sides of the lower section 61. This shape of the bulkhead 6 can also be described as overhanging.

[0032] The organic layer OR1 shown in Figure 2 includes a first organic layer OR1a and a second organic layer OR1b, which are spaced apart from each other. Similarly, the upper electrode UE1 shown in Figure 2 also includes a first upper electrode UE1a and a second upper electrode UE1b, which are spaced apart from each other. As shown in Figure 3, the first organic layer OR1a contacts the lower electrode LE1 through the opening AP1 and covers a portion of the rib 5. The second organic layer OR1b is located above the upper part 62. The first upper electrode UE1a faces the lower electrode LE1 and covers the first organic layer OR1a. Furthermore, the first upper electrode UE1a contacts the side surface of the lower part 61. The second upper electrode UE1b is located above the partition wall 6 and covers the second organic layer OR1b.

[0033] The organic layer OR2 shown in Figure 2 includes a first organic layer OR2a and a second organic layer OR2b, which are spaced apart from each other. Similarly, the upper electrode UE2 shown in Figure 2 also includes a first upper electrode UE2a and a second upper electrode UE2b, which are spaced apart from each other. As shown in Figure 3, the first organic layer OR2a contacts the lower electrode LE2 through the opening AP2 and covers a portion of the rib 5. The second organic layer OR2b is located above the upper part 62. The first upper electrode UE2a faces the lower electrode LE2 and covers the first organic layer OR2a. Furthermore, the first upper electrode UE2a contacts the side surface of the lower part 61. The second upper electrode UE2b is located above the partition wall 6 and covers the second organic layer OR2b.

[0034] The organic layer OR3 shown in Figure 2 includes a first organic layer OR3a and a second organic layer OR3b, which are spaced apart from each other. Similarly, the upper electrode UE3 shown in Figure 2 also includes a first upper electrode UE3a and a second upper electrode UE3b, which are spaced apart from each other. As shown in Figure 3, the first organic layer OR3a contacts the lower electrode LE3 through the opening AP3 and covers a portion of the rib 5. The second organic layer OR3b is located above the upper part 62. The first upper electrode UE3a faces the lower electrode LE3 and covers the first organic layer OR3a. Furthermore, the first upper electrode UE3a contacts the side surface of the lower part 61. The second upper electrode UE3b is located above the partition wall 6 and covers the second organic layer OR3b.

[0035] Sub-pixels SP1, SP2, and SP3 are each provided with sealing layers 71, 72, and 73. Sealing layer 71 continuously covers the first upper electrode UE1a, the side of the lower part 61, and the second upper electrode UE1b. Sealing layer 72 continuously covers the first upper electrode UE2a, the side of the lower part 61, and the second upper electrode UE2b. Sealing layer 73 continuously covers the first upper electrode UE3a, the side of the lower part 61, and the second upper electrode UE3b.

[0036] In the example shown in Figure 3, the second organic layer OR1b, the second upper electrode UE1b, and the sealing layer 71 on the partition wall 6 between sub-pixels SP1 and SP3 are separated from the second organic layer OR3b, the second upper electrode UE3b, and the sealing layer 73 on the same partition wall 6. Similarly, the second organic layer OR2b, the second upper electrode UE2b, and the sealing layer 72 on the partition wall 6 between sub-pixels SP2 and SP3 are separated from the second organic layer OR3b, the second upper electrode UE3b, and the sealing layer 73 on the same partition wall 6.

[0037] The sealing layers 71, 72, and 73 are covered by the resin layer 13. The resin layer 13 is covered by the sealing layer 14. Furthermore, the sealing layer 14 is covered by the resin layer 15.

[0038] The insulating layer 12 and resin layers 13 and 15 are made of organic materials. The ribs 5 and sealing layers 14, 71, 72, and 73 are made of inorganic materials, such as silicon nitride (SiNx). The thickness of the ribs 5, which are made of inorganic material, is sufficiently small compared to the thickness of the partition wall 6 and the insulating layer 12. In one example, the thickness of the ribs 5 is between 200 nm and 400 nm.

[0039] The lower part 61 of the partition wall 6 is conductive. The upper part 62 of the partition wall 6 may also be conductive. The lower electrodes LE1, LE2, and LE3 may be formed of a transparent conductive material such as ITO, or they may have a laminated structure of a metallic material such as silver (Ag) and a transparent conductive material. The upper electrodes UE1, UE2, and UE3 are formed of a metallic material such as a magnesium-silver alloy (MgAg). The upper electrodes UE1, UE2, and UE3 may also be formed of a transparent conductive material such as ITO.

[0040] When the potentials of the lower electrodes LE1, LE2, and LE3 are relatively higher than the potentials of the upper electrodes UE1, UE2, and UE3, the lower electrodes LE1, LE2, and LE3 correspond to the anodes, and the upper electrodes UE1, UE2, and UE3 correspond to the cathodes. Also, when the potentials of the upper electrodes UE1, UE2, and UE3 are relatively higher than the potentials of the lower electrodes LE1, LE2, and LE3, the upper electrodes UE1, UE2, and UE3 correspond to the anodes, and the lower electrodes LE1, LE2, and LE3 correspond to the cathodes.

[0041] The organic layers OR1, OR2, and OR3 include a pair of functional layers and an emissive layer disposed between these functional layers. As an example, the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, an emissive layer, a hole blocking layer, an electron transport layer, and an electron injection layer are stacked in that order.

[0042] The sub-pixels SP1, SP2, and SP3 may further include cap layers to adjust the optical properties of the light emitted by the light-emitting layers of the organic layers OR1, OR2, and OR3. Such cap layers may be provided between the upper electrode UE1 and the sealing layer 71, between the upper electrode UE2 and the sealing layer 72, and between the upper electrode UE3 and the sealing layer 73, respectively.

[0043] A common voltage is supplied to the partition wall 6. This common voltage is supplied to the first upper electrodes UE1a, UE2a, and UE3a, which are in contact with the sides of the lower part 61. Pixel voltages are supplied to the lower electrodes LE1, LE2, and LE3 through the pixel circuits 1 of the sub-pixels SP1, SP2, and SP3, respectively.

[0044] When a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of the first organic layer OR1a emits light in the red wavelength range. When a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of the first organic layer OR2a emits light in the green wavelength range. When a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of the first organic layer OR3a emits light in the blue wavelength range.

[0045] As another example, the light-emitting layers of organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include a color filter that converts the light emitted by the light-emitting layers into light of the color corresponding to the sub-pixels SP1, SP2, and SP3. Alternatively, the display device DSP may include a layer containing quantum dots that are excited by the light emitted by the light-emitting layers to generate light of the color corresponding to the sub-pixels SP1, SP2, and SP3.

[0046] Figure 4 is a schematic plan view showing an enlarged view of the vicinity of the sub-pixel SP1 in Figure 2. Of the region enclosed by the dashed line that shows the outline of the upper electrode UE1 and the organic layer OR1, the portion that overlaps with the partition wall 6 corresponds to the second upper electrode UE1b and the second organic layer OR1b described above. Furthermore, of the region enclosed by the dashed line, the portion located inside the second upper electrode UE1b and the second organic layer OR1b corresponds to the first upper electrode UE1a and the first organic layer OR1a described above.

[0047] The second upper electrode UE1b and the second organic layer OR1b surround the first upper electrode UE1a, the first organic layer OR1a, and the aperture AP1. Similarly, the second upper electrode UE2b and the second organic layer OR2b shown in Figure 3 surround the first upper electrode UE2a, the first organic layer OR2a, and the aperture AP2. Furthermore, the second upper electrode UE3b and the second organic layer OR3b shown in Figure 3 surround the first upper electrode UE3a, the first organic layer OR3a, and the aperture AP3.

[0048] As will be explained in detail with reference to Figure 5, the contact holes CH1 and CH2 are filled with filler material 8. The first partition wall 6x located between the openings AP1 and AP2 overlaps with a portion of the contact hole CH1 and a portion of the filler material 8. Furthermore, the rib 5 overlaps with the entire contact hole CH1 and the filler material 8. The first partition wall 6x may also overlap with the entire contact hole CH1 and the filler material 8. In the example in Figure 4, the contact hole CH1 also overlaps with the first organic layer OR1a, the second organic layer OR1b, the first upper electrode UE1a, and the second upper electrode UE1b.

[0049] The first partition wall 6x that overlaps with the contact hole CH1 has a width Wx1 in the second direction Y. The first partition wall 6x that does not overlap with the contact hole CH1 (the upper first partition wall 6x in the figure) has a width Wx2. Each second partition wall 6y has a width Wy in the first direction X. In the example in Figure 4, width Wx1 is greater than widths Wx2 and Wy (Wx1 > Wx2, Wy). For example, width Wy is the same as width Wx2.

[0050] The lower electrode LE1 has a first side S11 and a second side S12 parallel to the first direction X, and a third side S13 and a fourth side S14 parallel to the second direction Y. In the example in Figure 4, each side S11, S12, S13, and S14 does not overlap with the partition wall 6. The first side S11 is located between the contact hole CH1 and the opening AP1 in the second direction Y. The protrusion PR1 projects from the first side S11 toward the lower electrode LE2 and overlaps with the contact hole CH1.

[0051] The first partition wall 6x, which overlaps with a portion of contact hole CH1, also overlaps with a portion of contact hole CH2. Contact holes CH1 and CH2 are aligned in the first direction X. The lower electrode LE2 has a first side S21 near this first partition wall 6x. The first side S21 and the other sides of the lower electrode LE2, like the sides S12, S13, and S14 of the lower electrode LE1, do not overlap with partition wall 6. The protrusion PR2 projects from the first side S21 toward the lower electrode LE1 and overlaps with contact hole CH2. Although not shown in Figure 4, for the lower electrode LE3, one side adjacent to contact hole CH3 overlaps with the first partition wall 6x, while most of the other sides do not overlap with partition wall 6 (see Figure 2).

[0052] Rib 5 overlaps with the entire contact hole CH2 and the filler material 8 placed in contact hole CH2. Part of contact hole CH2 overlaps with the organic layer OR2 and the upper electrode UE2. In the example in Figure 4, contact hole CH1 does not overlap with the organic layer OR2 and the upper electrode UE2. Also, contact hole CH2 does not overlap with the organic layer OR1 and the upper electrode UE1.

[0053] Figure 5 is a schematic cross-sectional view of the display device DSP along the VV line in Figure 4. In this figure, the substrate 10, resin layers 13 and 15, and sealing layer 14 shown in Figure 3 are omitted.

[0054] The contact hole CH1 penetrates the insulating layer 12. The protrusion PR1 of the lower electrode LE1 is in contact with the conductive layer CL included in the circuit layer 11 through the contact hole CH1. The conductive layer CL corresponds to, for example, the source electrode or drain electrode of the drive transistor 3 shown in Figure 1.

[0055] A filler material 8 is placed inside the contact hole CH1. The filler material 8 can be made of an insulating organic material such as polyimide. The filler material 8 may also be made of the same material as the insulating layer 12. The thickness of the filler material 8 is greater than the thickness of the rib 5.

[0056] The filler material 8 covers the recessed portion (part of the protruding portion PR1) of the lower electrode LE1 due to the contact hole CH1. In the example in Figure 5, the upper surface 8a of the filler material 8 and the upper surface of the portion of the lower electrode LE1 located around the contact hole CH1 are approximately coincident. However, the upper surface 8a may protrude slightly from the upper surface of the portion of the lower electrode LE1 located around the contact hole CH1, or it may be located slightly below that upper surface.

[0057] In this embodiment, the upper surface 8a is covered by the rib 5. That is, at least a portion of the filler material 8 is located between the lower electrode LE1 and the rib 5 in the third direction Z (the thickness direction of the insulating layer 12 and the rib 5).

[0058] The lower part 61 of the first partition wall 6x (partition wall 6) has sides 61a and 61b. The first upper electrode UE1a is in contact with a portion of side 61a. The other portion of side 61a is covered with a sealing layer 71. Similarly, the first upper electrode UE2a is in contact with a portion of side 61b. The other portion of side 61b is covered with a sealing layer 72.

[0059] The upper part 62 of the first partition wall 6x has an end portion 62a protruding from the side surface 61a and an end portion 62b protruding from the side surface 61b. In the example of Figure 5, the sealing layer 71 covers the lower surface of the end portion 62a, and the sealing layer 72 covers the lower surface of the end portion 62b.

[0060] The second organic layers OR1b and OR2b, located above the first partition wall 6x, are spaced apart in the second direction Y. The second upper electrodes UE1b and UE2b, located above the first partition wall 6x, are spaced apart in the second direction Y. Furthermore, the end 71a of the sealing layer 71 and the end 72a of the sealing layer 72 are located above the first partition wall 6x and are spaced apart in the second direction Y.

[0061] In the example shown in Figure 5, side 61a is located above the contact hole CH1 and the filler material 8. Although not shown in the cross-section of Figure 5, side 61b is located above the contact hole CH2. That is, in a plan view, side 61a overlaps with the contact hole CH1, and side 61b overlaps with the contact hole CH2 in a plan view.

[0062] The cross-sectional structure near contact holes CH2 and CH3 is the same as the cross-sectional structure near contact hole CH1 shown in Figure 5. Specifically, a filler material 8 covering the lower electrode LE2 is placed inside contact hole CH2, and the upper surface 8a of this filler material 8 is covered by a rib 5. Similarly, a filler material 8 covering the lower electrode LE3 is placed inside contact hole CH3, and the upper surface 8a of this filler material 8 is covered by a rib 5.

[0063] Here, an example of the effects achieved by this embodiment will be explained using Figures 6 and 7. Figure 6 is a schematic cross-sectional view showing part of the manufacturing process of a display device DSP. When forming the organic layer OR1, first the base material is deposited over the entire display area DA. At this time, the material is divided into a first organic layer OR1a and a second organic layer OR1b by the partition wall 6. Subsequently, the base material for the upper electrode UE1 is deposited over the entire display area DA. At this time, the material is divided into a first upper electrode UE1a and a second upper electrode UE1b by the partition wall 6.

[0064] Furthermore, a sealing layer 71 is formed on the first upper electrode UE1a and the second upper electrode UE1b, and finally, a resist R is formed on the sealing layer 71 in the regions where the first organic layer OR1a, the second organic layer OR1b, the first upper electrode UE1a, and the second upper electrode UE1b should remain. Subsequent etching removes the portions of the first organic layer OR1a, the second organic layer OR1b, the first upper electrode UE1a, the second upper electrode UE1b, and the sealing layer 71 that are not covered by the resist R.

[0065] Figure 7 is a schematic cross-sectional view of a comparative example display device, showing the same manufacturing process as in Figure 6. In this comparative example, no filler material 8 is provided in the contact hole CH1. Since the rib 5, which is made of inorganic material, is sufficiently thinner than the insulating layer 12, which is made of organic material, the rib 5 is recessed above the contact hole CH1, forming a recess RS. Furthermore, the side surface 61a of the lower part 61 is located inside the recess RS.

[0066] In the comparative example structure, the end portion 62a of the upper part 62 faces upward compared to the structure in Figure 6, which means that the organic layer OR1 and the upper electrode UE1 may not be separated by the first partition wall 6x. In this case, when the resist R is formed and etching is performed, the end portion of the organic layer OR1 constituting the display element will be exposed from the upper electrode UE1 and the sealing layer 71. Generally, the organic layer OR1 has low resistance to moisture. Therefore, if moisture penetrates the organic layer OR1 through the exposed end portion, it may cause display defects.

[0067] In contrast, in this embodiment, since the filler material 8 is placed inside the contact hole CH1, the formation of the recess RS is suppressed. Therefore, a first partition wall 6x with a good shape is formed even in the vicinity of the contact hole CH1, and it is possible to divide the organic layer OR1 into a first organic layer OR1a and a second organic layer OR1b. In this case, the end of the first organic layer OR1a is well covered by the first upper electrode UE1a and the sealing layer 71, and the intrusion of moisture into the first organic layer OR1a is suppressed. As a result, display defects are suppressed and the display quality of the display device DSP is improved.

[0068] Although Figures 5 and 6 describe the effects of this embodiment focusing on the organic layer OR1, similar effects can be obtained for the organic layers OR2 and OR3 by arranging the filler material 8 inside the contact holes CH2 and CH3.

[0069] In this embodiment, the filler material 8 is positioned between the lower electrodes LE1, LE2, LE3 and the rib 5. Therefore, the organic layers OR1, OR2, OR3 do not come into contact with the filler material 8. In this case, even if the filler material 8 contains moisture, it is possible to prevent this moisture from reaching the organic layers OR1, OR2, OR3.

[0070] In this embodiment, the lower electrodes LE1 and LE2 have protrusions PR1 and PR2. In this case, as shown in Figures 2 and 4, the contact holes CH1 and CH2 can be aligned in the first direction X. This makes it possible to improve the efficiency of the pixel PX layout.

[0071] The second to fourth embodiments of the display device DSP are disclosed below. These embodiments mainly focus on the differences from the first embodiment, and the same configurations as the first embodiment are omitted from the description.

[0072] [Second Embodiment] Figure 8 is a schematic cross-sectional view of a display device DSP according to the second embodiment. In this figure, the circuit layer 11, insulating layer 12, partition wall 6 (first partition wall 6x), rib 5, and lower electrodes LE1, LE2 are shown, while other elements are omitted.

[0073] In the example shown in Figure 8, the rib 5 covers the lower electrode LE1 inside the contact hole CH1. As a result, the rib 5 is recessed above the contact hole CH1, forming a recess RS. The filler material 8 fills the recess RS. At least a portion of the upper surface 8a of the filler material 8 is covered by the lower part 61.

[0074] Thus, in the example shown in Figure 8, at least a portion of the filler 8 is located between the rib 5 and the partition wall 6 in the third direction Z. Even in this case, a first partition wall 6x with a good shape is formed near the contact hole CH1, so the same effects as in the first embodiment can be obtained.

[0075] For example, when manufacturing a display device DSP with the structure disclosed in Figure 5 in the first embodiment, it is necessary to form the filler material 8 between the process of forming the lower electrode LE1 and the process of forming the rib 5. In this case, the end of the lower electrode LE1 is exposed to the atmosphere for a longer period of time compared to a structure without the filler material 8. If the end of the lower electrode LE1 is exposed for a longer period of time, the lower electrode LE1 may deteriorate through that end.

[0076] In contrast, when manufacturing the DSP display device with the structure shown in Figure 8, the process of forming the rib 5 can be carried out immediately after the process of forming the lower electrode LE1, thus shortening the exposure time of the end of the lower electrode LE1. This suppresses the deterioration of the lower electrode LE1.

[0077] The same structure as in Figure 8 can be applied to the vicinity of contact holes CH2 and CH3. This allows the aforementioned effects to be obtained even in the vicinity of contact holes CH2 and CH3.

[0078] [Third Embodiment] Figure 9 is a schematic cross-sectional view of a display device DSP according to the third embodiment. In this figure, the circuit layer 11, insulating layer 12, partition wall 6 (first partition wall 6x), rib 5, and lower electrodes LE1, LE2 are shown, while other elements are omitted.

[0079] In the example shown in Figure 9, the lower electrode LE1 includes a first transparent conductive layer TL1, a metal layer ML, a second transparent conductive layer TL2, and a base layer UL. All of these layers are conductive. Lower electrodes LE2 and LE3 have the same configuration as lower electrode LE1.

[0080] The first transparent conductive layer TL1 and the second transparent conductive layer TL2 are formed of a transparent conductive material such as ITO. The metal layer ML is formed of a highly reflective metallic material such as silver. The base layer UL may be formed of a transparent conductive material or a metallic material.

[0081] The base layer UL covers the insulating layer 12 and is in contact with the conductive layer CL through the contact hole CH1. The filler 8 covers the portion of the base layer UL located inside the contact hole CH1. The first transparent conductive layer TL1 covers the upper surface 8a of the base layer UL and the filler 8. The metal layer ML covers the first transparent conductive layer TL1. The second transparent conductive layer TL2 covers the metal layer ML.

[0082] Thus, in the example shown in Figure 9, at least a portion of the filler 8 is located between the underlayer UL and the first transparent conductive layer TL1 in the third direction Z. Even in this case, a first partition wall 6x with a good shape is formed near the contact hole CH1, so the same effects as in the first embodiment can be obtained.

[0083] Furthermore, when manufacturing the DSP display device with the structure shown in Figure 9, the process of forming the rib 5 can be carried out immediately after the process of forming the first transparent conductive layer TL1, the metal layer ML, and the second transparent conductive layer TL2. This shortens the exposure time of the edges ED of the first transparent conductive layer TL1, the metal layer ML, and the second transparent conductive layer TL2, thereby suppressing the degradation of these layers.

[0084] In the example shown in Figure 9, the edges ED of the first transparent conductive layer TL1, the metal layer ML, and the second transparent conductive layer TL2 are located above the upper surface 8a. That is, a portion of the upper surface 8a is not covered by the first transparent conductive layer TL1. In another example, the edges ED may be entirely covered by the first transparent conductive layer TL1.

[0085] The same structure as in Figure 9 can be applied to the vicinity of contact holes CH2 and CH3. This allows the aforementioned effects to be obtained even in the vicinity of contact holes CH2 and CH3.

[0086] [Fourth Embodiment] Figure 10 is a schematic cross-sectional view of a display device DSP according to the fourth embodiment. In this figure, the circuit layer 11, insulating layer 12, partition wall 6 (first partition wall 6x), rib 5, and lower electrodes LE1, LE2 are shown, while other elements are omitted.

[0087] In the example shown in Figure 10, the lower electrode LE1 includes a first transparent conductive layer TL1, a metal layer ML, and a second transparent conductive layer TL2. All of these layers are conductive and can be formed from the materials exemplified in the third embodiment. The lower electrodes LE2 and LE3 have the same configuration as the lower electrode LE1.

[0088] In the example shown in Figure 10, the first transparent conductive layer TL1 covers the insulating layer 12 and is in contact with the conductive layer CL through the contact hole CH1. The filler 8 covers the portion of the first transparent conductive layer TL1 located inside the contact hole CH1. The metal layer ML covers the upper surface 8a of the first transparent conductive layer TL1 and the filler 8. The second transparent conductive layer TL2 covers the metal layer ML.

[0089] Thus, in the example shown in Figure 10, the filler 8 is located between the first transparent conductive layer TL1 and the metal layer ML in the third direction Z. Even in this case, a first partition wall 6x with a good shape is formed near the contact hole CH1, so the same effects as in the first embodiment can be obtained.

[0090] In the example shown in Figure 10, the edges ED of the first transparent conductive layer TL1, the metal layer ML, and the second transparent conductive layer TL2 are located outside the contact hole CH1. That is, the entire filler material 8 is surrounded by the first transparent conductive layer TL1 and the metal layer ML. In another example, the edges of the first transparent conductive layer TL1 may be covered by the filler material 8. Alternatively, the edges of the metal layer ML and the second transparent conductive layer TL2 may be located on the upper surface 8a.

[0091] The same structure as in Figure 10 can be applied to the vicinity of contact holes CH2 and CH3. This allows the aforementioned effects to be obtained even in the vicinity of contact holes CH2 and CH3.

[0092] All display devices that a person skilled in the art can implement by appropriately modifying the design based on the display devices described above as embodiments of the present invention also fall within the scope of the present invention insofar as they encompass the gist of the present invention.

[0093] Within the scope of the concept of the present invention, a person skilled in the art can conceive of various modifications, and such modifications are also understood to fall within the scope of the present invention. For example, any modifications made by a person skilled in the art to add, delete, or change the design of any of the above-described embodiments, or to add, omit, or change the conditions of any process, are also included within the scope of the present invention, as long as they retain the essence of the present invention.

[0094] Furthermore, any other effects and advantages brought about by the embodiments described above that are obvious from the description herein or that can be appropriately conceived by those skilled in the art are naturally considered to be brought about by the present invention. [Explanation of symbols]

[0095] DSP...Display device, PX...Pixel, SP1, SP2, SP3...Sub-pixel, LE1, LE2, LE3...Lower electrode, UE1, UE2, UE3...Upper electrode, OR1, OR2, OR3...Organic layer, CH1, CH2, CH3...Contact hole, 1...Pixel circuit, 5...Rib, 6...Partition, 10...Substrate, 61...Bottom, 62...Top, 71, 72, 73...Sealing layer.

Claims

1. circuit board and A pixel circuit arranged above the aforementioned substrate, An insulating layer covering the aforementioned pixel circuit and having contact holes, A lower electrode is positioned above the insulating layer and connected to the pixel circuit through the contact hole, An upper electrode facing the lower electrode, An organic layer located between the lower electrode and the upper electrode, which emits light in accordance with the potential difference between the lower electrode and the upper electrode, A rib made of an inorganic material, having an opening that overlaps with the lower electrode, A partition wall positioned above the rib, The system comprises a filler material disposed inside the contact hole, The organic layer includes a first organic layer that contacts the lower electrode through the opening, and a second organic layer located above the partition wall and spaced apart from the first organic layer. The partition wall and the rib overlap with at least a portion of the contact hole and the filler in a plan view. The aforementioned lower electrode is A conductive underlayer covering the insulating layer, A first transparent conductive layer formed of a transparent conductive material and covering the underlying layer, A metal layer formed of a metal material and covering the first transparent conductive layer, A second transparent conductive layer, formed of a transparent conductive material and covering the metal layer, Includes, The aforementioned underlayer is connected to the pixel circuit through the contact hole, At least a portion of the filler is located between the base layer and the first transparent conductive layer. The lower electrode has a first side located between the contact hole and the opening in a plan view, and a protrusion that extends from the first side and overlaps with the contact hole in a plan view. Display device.

2. circuit board and A pixel circuit arranged above the aforementioned substrate, An insulating layer covering the aforementioned pixel circuit and having contact holes, A lower electrode is positioned above the insulating layer and connected to the pixel circuit through the contact hole, An upper electrode facing the lower electrode, An organic layer located between the lower electrode and the upper electrode, which emits light in accordance with the potential difference between the lower electrode and the upper electrode, A rib made of an inorganic material, having an opening that overlaps with the lower electrode, A partition wall positioned above the rib, The system comprises a filler material disposed inside the contact hole, The organic layer includes a first organic layer that contacts the lower electrode through the opening, and a second organic layer located above the partition wall and spaced apart from the first organic layer. The partition wall and the rib overlap with at least a portion of the contact hole and the filler in a plan view. The aforementioned lower electrode is A first transparent conductive layer formed of a transparent conductive material and covering the insulating layer, A metal layer formed of a metal material and covering the first transparent conductive layer, A second transparent conductive layer, formed of a transparent conductive material and covering the metal layer, Includes, The first transparent conductive layer is connected to the pixel circuit through the contact hole, At least a portion of the filler is located between the first transparent conductive layer and the metal layer. Display device.

3. circuit board and A pixel circuit arranged above the aforementioned substrate, An insulating layer covering the aforementioned pixel circuit and having contact holes, A lower electrode is positioned above the insulating layer and connected to the pixel circuit through the contact hole, An upper electrode facing the lower electrode, An organic layer located between the lower electrode and the upper electrode, which emits light in accordance with the potential difference between the lower electrode and the upper electrode, A rib made of an inorganic material, having an opening that overlaps with the lower electrode, A partition wall positioned above the rib, The system comprises a filler material disposed inside the contact hole, The organic layer includes a first organic layer that contacts the lower electrode through the opening, and a second organic layer located above the partition wall and spaced apart from the first organic layer. The partition wall and the rib overlap with at least a portion of the contact hole and the filler in a plan view. The partition wall includes a lower portion positioned on the rib and an upper portion positioned on the lower portion and having an end portion that protrudes from the side surface of the lower portion. The second organic layer is positioned on top of the upper part, The upper electrode includes a first upper electrode covering the first organic layer and a second upper electrode covering the second organic layer and spaced apart from the first upper electrode. The first upper electrode is in contact with the side surface, The lower part is conductive. Display device.

4. The aforementioned lower side surface overlaps with the contact hole in a plan view. The display device according to claim 3.

5. It is formed of an inorganic material and further comprises a sealing layer that covers the first upper electrode, the side surface, and the second upper electrode. The display device according to claim 3 or 4.

6. The lower electrode has a first side located between the contact hole and the opening in a plan view, and a protrusion that extends from the first side and overlaps with the contact hole in a plan view. The display device according to any one of claims 2 to 5.

7. The aforementioned partition wall surrounds the opening in a plan view. The display device according to any one of claims 1 to 6.

8. The second organic layer surrounds the opening in a plan view. The display device according to any one of claims 1 to 7.

9. The second organic layer overlaps the contact hole in a plan view. The display device according to any one of claims 1 to 8.

10. The thickness of the rib is smaller than the thickness of the partition wall. The display device according to any one of claims 1 to 9.

11. circuit board and A pixel circuit arranged above the aforementioned substrate, An insulating layer covering the aforementioned pixel circuit and having contact holes, A lower electrode is positioned above the insulating layer and connected to the pixel circuit through the contact hole, An upper electrode facing the lower electrode, An organic layer located between the lower electrode and the upper electrode, which emits light in accordance with the potential difference between the lower electrode and the upper electrode, A rib made of an inorganic material, having an opening that overlaps with the lower electrode, A partition wall positioned above the rib, The system comprises a filler material disposed inside the contact hole, The organic layer includes a first organic layer that contacts the lower electrode through the opening, and a second organic layer located above the partition wall and spaced apart from the first organic layer. The partition wall and the rib overlap with at least a portion of the contact hole and the filler in a plan view. The device comprises a first sub-pixel, a second sub-pixel, and a third sub-pixel, each including the pixel circuit, the contact hole, the lower electrode, the upper electrode, the organic layer, and the aperture, respectively. The first subpixel and the third subpixel are aligned in the first direction. The first subpixel and the second subpixel are aligned in a second direction intersecting the first direction. The partition wall comprises a first partition wall positioned between the opening of the first sub-pixel and the opening of the second sub-pixel, and a second partition wall positioned between the opening of the first sub-pixel and the opening of the third sub-pixel. Display device.

12. The width of the first partition in the second direction is greater than the width of the second partition in the first direction. The display device according to claim 11.

13. The contact hole of the first subpixel overlaps with the first partition in a plan view. The display device according to claim 11 or 12.

14. The contact hole of the second subpixel overlaps with the first partition in a plan view and is aligned with the contact hole of the first subpixel in the first direction. The display device according to claim 13.

15. The second organic layer of the first subpixel and the second organic layer of the second subpixel are located on the first partition and are spaced apart in the second direction. The display device according to any one of claims 11 to 14.

16. At least a portion of the filler is located between the lower electrode and the rib in the thickness direction of the insulating layer. The display device according to claim 3 or 11.

17. At least a portion of the filler is located between the rib and the partition wall in the thickness direction of the insulating layer. The display device according to claim 3 or 11.

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