Method for manufacturing semiconductor memory devices

Abstract

To provide a semiconductor storage device, a method of manufacturing a semiconductor storage device, and a semiconductor wafer.SOLUTION: A semiconductor storage device of an embodiment has a plurality of memory cell array layers each having a first surface and a second surface opposite to the first surface and not including a substrate. Each memory cell array layer has a plurality of memory cells arranged three-dimensionally in a memory cell array region, and a surface wiring layer embedded in the first and second surfaces. Each memory cell has a laminate obtained by laminating a plurality of electrode layers via a plurality of insulating layers. The laminate has a staircase structure part obtained by shifting end positions of the plurality of electrode layers for each lamination position. The plurality of memory cell array layers are laminated while connecting the surface wiring layers formed on the first or second surface. The memory cell array layers adjacent in the lamination direction of the laminate are laminated so that the mutual staircase structure parts are directed toward a lamination boundary surface.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor memory device Manufacturing method .

Background Art

[0002] There is known a NAND flash memory having a bonded structure in which memory cells are three-dimensionally stacked

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The problem to be solved by the embodiments is to provide a stacked semiconductor memory device with a simplified bonding process Manufacturing method .<​​​​​​The semiconductor memory device of the embodiment has a first surface and a second surface opposite to the first surface, and is a memory cell array layer that does not include a substrate, and has a plurality of memory cells arranged three-dimensionally in the memory cell array region. It has a plurality of memory cell array layers, each having a surface wiring layer embedded in the first surface and the second surface. The memory cell is a memory cell having a laminate formed by stacking a plurality of electrode layers via a plurality of insulating layers, and the laminate is a laminate having a stepped structure in which the end positions of the plurality of electrode layers are shifted at each stacking position. The plurality of memory cell array layers are stacked by connecting the surface wiring layers formed on the first surface or the second surface, and the memory cell array layers adjacent to each other in the stacking direction of the laminate are stacked with the inclined portions of their stepped structures toward the stacking interface between adjacent memory cell array layers in the stacking direction, thereby forming a semiconductor memory device. [Brief explanation of the drawing]

[0006] [Figure 1] A schematic cross-sectional view of a semiconductor memory device according to the first embodiment. [Figure 2] A schematic perspective view of a semiconductor memory device according to the first embodiment. [Figure 3] A schematic partial cross-sectional view of a semiconductor memory device according to the first embodiment. [Figure 4] A schematic partial cross-sectional view showing an enlarged portion of a semiconductor memory device according to the first embodiment. [Figure 5] A plan view showing an example of a semiconductor wafer used when manufacturing a semiconductor memory device according to the first embodiment. [Figure 6] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 7] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 8] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 9] This is a schematic cross-sectional view showing an example of a semiconductor memory device manufacturing method according to the first embodiment, and is a schematic cross-sectional view partially enlarged from the state shown in Figure 6. [Figure 10]This is a schematic cross-sectional view showing an example of a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 11] This is a schematic cross-sectional view showing an example of a method for manufacturing a semiconductor memory device according to the first embodiment, and is a schematic cross-sectional view partially enlarged from the state shown in Figure 9. [Figure 12] A schematic cross-sectional view showing an example of a semiconductor memory device manufacturing method for comparative examples. [Figure 13] A schematic cross-sectional view showing an example of a semiconductor memory device manufacturing method for comparative examples. [Figure 14] A schematic cross-sectional view showing an example of a semiconductor memory device manufacturing method for comparative examples. [Figure 15] This is a schematic cross-sectional view showing an example of a semiconductor memory device manufacturing method for a comparative example, and is a partially enlarged schematic cross-sectional view of a state preceding the state shown in Figure 12. [Figure 16] This is a schematic cross-sectional view showing an example of a semiconductor memory device manufacturing method for a comparative example, and is a partially enlarged schematic cross-sectional view of the state one step further from the state shown in Figure 12. [Figure 17] This is a schematic cross-sectional view showing an example of a semiconductor memory device manufacturing method for a comparative example, and is a partially enlarged schematic cross-sectional view of the state one step further from the state shown in Figure 14. [Modes for carrying out the invention]

[0007] "First Embodiment" The semiconductor memory device according to the first embodiment will be described below with reference to the drawings. In the following description, components having the same or similar function are denoted by the same reference numeral. Duplication of these components may be omitted. In this specification, “connection” includes not only physical connections but also electrical connections. In this specification, “provided on a substrate” includes cases where at least a portion of the object is formed inside the substrate or where at least a portion of the object is formed on the substrate.

[0008] (First Embodiment) FIG. 1 is a schematic cross-sectional view of a semiconductor memory device according to the first embodiment. The semiconductor memory device SMD of the first embodiment includes a control circuit layer 100 provided on a substrate 1 with a control circuit for controlling writing, erasing, and reading of data to and from memory cells, and a first memory cell array layer 200 including a plurality of three-dimensionally arranged first memory cells, which are joined and laminated so as to face each other and have a bonded structure. Further, the first memory cell array layer 200 and a second memory cell array layer 300 including a plurality of three-dimensionally arranged second memory cells are joined and laminated so as to face each other and have a bonded structure. More specifically, the semiconductor memory device SMD has a structure in which the control circuit layer 100, the first memory cell array layer 200, and the second memory cell array layer 300 are laminated in the thickness direction of the substrate 1 on the substrate 1.

[0009] First, the first memory cell array layer 200 will be described. The first memory cell array layer 200 has a first surface (lower surface) Sa1 and a second surface (upper surface) Sa2 opposite to the first surface in FIG. 1, and has a first memory cell array 10a having a three-dimensional structure. FIG. 2 is a schematic perspective view showing a part of the semiconductor memory device SMD according to the first embodiment, and is a schematic perspective view of the first memory cell array 10a. In FIG. 2, illustration of some insulating layers such as an inter-electrode insulating layer is omitted. The lower side in FIG. 2 indicates the first surface Sa1 side, and the upper side indicates the second surface Sa2 side. In FIG. 2, two directions orthogonal to each other are defined as the X direction and the Y direction, and the X direction and the Y direction are parallel to the upper surface of the substrate 1 shown in FIG. 1. A direction orthogonal to these X and Y directions (XY plane) and in which a plurality of electrode layers WL are laminated is defined as the Z direction (lamination direction: thickness direction of the substrate 1). Also, when indicating a direction, directions 180° different may be distinguished and described with plus and minus signs such as the +X direction and the -X direction. The +X direction and the -X direction indicate directions 180° different, the +Y direction and the -Y direction indicate directions 180° different, and the +Z direction and the -Z direction indicate directions 180° different. When there is no need to distinguish between positive and negative directions, the + sign is omitted, and it is simply denoted as the X direction, the Y direction, the Z direction, etc.

[0010] The first memory cell array 10a has a first stacked body 12a in which a plurality of electrode layers WL and insulating layers 11 shown in FIG. 2 are alternately stacked one layer each. A plurality of first columnar portions 13a extending in the Z direction are provided in the first stacked body 12a. The first columnar portions 13a are provided, for example, in a cylindrical or elliptical column shape. The plurality of first columnar portions 13a are arranged, for example, in a staggered lattice or a square lattice in the XY plane. The electrode layer WL is separated into a plurality of blocks in the Y direction and extends in the X direction.

[0011] The electrode layer WL is, for example, a layer mainly containing silicon. Further, the electrode layer WL contains boron as an impurity for imparting conductivity to the silicon layer. The electrode layer WL may also contain a metal silicide. The insulating layer 11 mainly contains, for example, silicon and oxygen, and is a silicon oxide film (SiO), a silicon oxynitride film (SiON), a carbon-containing silicon oxide film (SiOC), or the like.

[0012] A drain-side select gate SGD is provided above the upper part on the second surface Sa2 side of the first columnar portion 13a, and a source-side select gate SGS is provided below the lower part on the first surface Sa1 side. The drain-side select gate SGD is provided on the uppermost electrode layer WL via the insulating layer 11. The source-side select gate SGS is provided under the lowermost electrode layer WL via the insulating layer 11. Here, for example, the drain-side select gate SGD and the source-side select gate SGS can be formed thicker than a single electrode layer WL.

[0013] A first bit line 16a (BL) is connected to the upper end portion on the second surface Sa2 side of the first columnar portion 13a. A plurality of first bit lines 16a are provided and are made of, for example, metal. The plurality of first bit lines 16a are spaced apart in the X direction and extend in the Y direction. The first bit line 16a is provided on the drain-side select gate SGD via the insulating layer 11 and the interlayer insulating layer 14 (see FIG. 3).

[0014] In Figure 2, the first source wire 17a (SL) is connected to the lower end of the first columnar portion 13a, which is on the first surface Sa1 side. The first source wire 17a is provided below the source-side selection gate SGS via an interlayer insulating layer 15. Furthermore, at the lower end of the first columnar portion 13a, further below the first source wire 17a, the first source-side wiring layer 19a is provided within the interlayer insulating layer 18. The interlayer insulating layer 18 may be a laminated layer.

[0015] Figure 3 is a schematic partial cross-sectional view of a semiconductor memory device (SMD) according to the first embodiment, and is a schematic partial cross-sectional view of the vicinity of the first columnar portion. Figure 4 is an enlarged schematic partial cross-sectional view of portion A, which is a part of the vicinity of the first columnar portion in Figure 3. Figures 3 and 4 represent partial cross-sections parallel to the YZ plane in Figure 2. As shown in Figure 3, the first columnar portion 13a is formed within an I-shaped memory hole formed in a first laminate 12a which includes a plurality of electrode layers WL and a plurality of insulating layers 11. A channel body 20, which serves as a semiconductor channel, is provided within the memory hole. The channel body 20 is, for example, a silicon film. The impurity concentration of the channel body 20 is lower than that of the electrode layers WL.

[0016] As shown in Figure 4, in the memory cell MC, a memory film 21 is provided between the inner wall of the memory hole and the channel body 20. The memory film 21 includes, for example, a block insulating film 22, a charge storage film 23, and a tunnel insulating film 24. Between the electrode layer WL and the channel body 20, the block insulating film 22, the charge storage film 23, and the tunnel insulating film 24 are provided in order from the electrode layer WL side.

[0017] The channel body 20 is provided in a cylindrical shape extending in the Z direction, and the memory film 21 is provided in a cylindrical shape extending in the Z direction so as to surround the outer surface of the channel body 20. The electrode layer WL surrounds the channel body 20 via the memory film 21. In addition, a core insulating film 25 is provided inside the channel body 20. The core insulating film 25 is, for example, a silicon oxide film. The block insulating film 22 is in contact with the electrode layer WL, the tunnel insulating film 24 is in contact with the channel body 20, and a charge storage film 23 is provided between the block insulating film 22 and the tunnel insulating film 24.

[0018] The channel body 20 functions as a channel in the memory cell MC, and the electrode layer WL functions as a control gate in the memory cell MC. The charge storage film 23 functions as a data storage layer that stores the charge injected from the channel body 20. In other words, a memory cell with a structure in which the channel is surrounded by a control gate is formed at the intersection of the channel body 20 and each electrode layer WL.

[0019] The semiconductor memory device SMD of the first embodiment is a non-volatile semiconductor memory device that allows for electrical erasure and writing of data and retains its stored contents even when the power is turned off. The memory cell MC in the above configuration is, for example, a charge trap type memory cell. The charge storage film 23 has many trap sites for capturing charge and is, for example, a silicon nitride film. The memory cell MC may also be a floating gate type memory cell.

[0020] The tunnel insulating film 24 acts as a potential barrier when charge is injected into the charge storage film 23 from the channel body 20, or when charge stored in the charge storage film 23 diffuses to the channel body 20. The tunnel insulating film 24 is, for example, a silicon oxide film. Alternatively, a multilayer film (ONO film) with a silicon nitride film sandwiched between a pair of silicon oxide films may be used as the tunnel insulating film. When an ONO film is used as the tunnel insulating film, erasure operation can be performed at a lower electric field compared to a single layer of silicon oxide film.

[0021] The blocking insulating film 22 prevents the charge accumulated in the charge storage film 23 from diffusing into the electrode layer WL. The blocking insulating film 22 includes, for example, a silicon nitride film 221 provided in contact with the electrode layer WL and a silicon oxide film 222 provided between the silicon nitride film 221 and the charge storage film 23. By providing a silicon nitride film 221, which has a higher dielectric constant than the silicon oxide film 222, in contact with the electrode layer WL, back-tunnel electrons injected from the electrode layer WL during erasure can be suppressed. In other words, by using a laminated film of silicon oxide and silicon nitride as the blocking insulating film 22, charge blocking properties can be improved.

[0022] As shown in Figures 2 and 3, a drain-side selection transistor STD is provided on the upper side of the first columnar portion 13a, and a source-side selection transistor STS is provided on the lower side of the other columnar portion. Memory cell MC, drain-side selection transistor STD, and source-side selection transistor STS are vertical transistors in which current flows in the stacking direction (Z direction) of the stacked structure.

[0023] The drain-side selection gate SGD functions as the gate electrode (control gate) of the drain-side selection transistor STD. An insulating film 26 (see Figure 3), which functions as the gate insulating film of the drain-side selection transistor STD, is provided between the drain-side selection gate SGD and the channel body 20. The channel body 20 of the drain-side selection transistor STD, which is provided on the first columnar portion 13a, is connected to the bit line BL above the drain-side selection gate SGD. Further below the source wire SL, a first source-side wiring layer 19a is provided within the interlayer insulating layer 18.

[0024] These multiple memory cells MC, drain-side selection transistor STD, and source-side selection transistor STS are connected in series through the channel body 20 to form an I-shaped memory string MS. Multiple memory string MS are arranged in the X and Y directions, so that multiple memory cells MC are arranged three-dimensionally in the X, Y, and Z directions.

[0025] Figure 1 shows the region on one end in the X direction of the first memory cell array 10a. At the edge of the first memory cell array region 28a, a stepped structure 29 is formed, consisting of one end of an electrode layer WL extending in the X direction. In the stepped structure 29, the end positions in the X direction of each electrode layer WL are arranged in a stepped pattern for each stacking position. In the first memory cell array 10a, the end of the electrode layer WL closest to the first surface Sa1 is the longest along the X direction, and the ends of the electrode layer WL located further away from the first surface Sa1 gradually become shorter. Therefore, the stepped structure 29 is formed so that its inclined portion 29a faces the second surface Sa2. Although Figure 1 only shows the region on one end in the X direction of the first memory cell array 10a, a similar stepped structure is also formed in the region on the other end in the X direction of the first memory cell array 10a.

[0026] Although the stepped structure in the region on the other end in the X direction is omitted in Figure 1, even in this stepped structure, the end of the electrode layer WL closest to the first surface Sa1 is the longest along the X direction, and the ends of the electrode layer WL formed further away from the first surface Sa1 gradually become shorter. Therefore, the stepped structure on the side that is omitted from the description is also formed so that its inclined portion faces the second surface Sa2. Furthermore, the multiple electrode layers WL formed in the memory cell array region 28a are arranged so as to form a trapezoidal contour in cross-sectional view when both the one end in the X direction shown in Figure 1 and the other end in the X direction (which is not shown in Figure 1) are combined. A step structure 29 is formed at a position corresponding to the hypotenuse of this trapezoidal contour in cross-sectional view. In other words, the first laminate 12a is configured such that, when viewed in cross-section, it forms a trapezoidal contour by combining the multiple electrode layers WL formed in the memory cell array region 28a shown in Figure 1 and the insulating layers formed between them.

[0027] The stepped structure 29 is provided with a plurality of contact plugs 30 connected to the electrode layers WL of each stepped layer. These contact plugs 30 penetrate the interlayer insulating layer 31 and are connected to the end side of each electrode layer WL that constitutes the stepped structure 29. The contact plugs 30 connected to the end side of each electrode layer WL extend toward the second surface Sa2.

[0028] In the staircase structure 29, the selection gates SG (drain-side selection gate SGD, source-side selection gate SGS) are connected to contact plugs 32. These contact plugs 32 also extend toward the second surface Sa2. The contact plug 30 connected to the electrode layer WL is connected to the word wiring layer 33. The contact plug 32 connected to the selection gate SG is connected to the selection gate wiring layer 34. The word wiring layer 33 and the selection gate wiring layer 34 are located adjacent to each other on the same layer near the second surface Sa2.

[0029] As shown in Figure 1, the first memory cell array layer 200 does not include a substrate. Furthermore, a first source-side wiring layer 19a is provided on the second surface Sa2 side of the first source line SL. At least portions of the word wiring layer 33 and the selection gate wiring layer 34 are led out as word line leads 35 and selection gate leads 36, respectively, outside the first memory cell array area 28a when viewed from a direction perpendicular to the second surface Sa2, by other wiring layers and plugs. The word line leads 35 and selection gate leads 36, which are led out outside the first memory cell array area 28a, are connected to a first signal line lead electrode 37a provided outside the first memory cell array area 28a.

[0030] Furthermore, the channel body 20 of the first columnar portion 13a is electrically connected to the first bit line 16a and the first source line 17a. In addition, at least a portion of the first bit line 16a and the first source line 17a are similarly led out as the first bit line lead-out and the first source line lead-out, respectively, outside the first memory cell array area 28a when viewed from a direction perpendicular to the second surface Sa2, by other wiring layers or plugs (not shown). The first bit line lead-out and the first source line lead-out, which are led out outside the first memory cell array area 28a, are connected to the first signal line lead-out electrode 37a provided outside the first memory cell array area 28a.

[0031] The first surface wiring layer 38a and the second surface wiring layer 39a are provided on the first surface Sa1 and the second surface Sa2 of the first memory cell array layer 200. The first surface wiring layer 38a and the second surface wiring layer 39a are embedded in the first surface Sa1 and the second surface Sa2, respectively, and their surfaces are exposed from an interlayer insulating layer (not shown). Here, for example, the first signal line extraction electrode 37a is electrically connected to the first surface wiring layer 38a and the second surface wiring layer 39a, which are provided on the first surface Sa1 and the second surface Sa2 of the first memory cell array layer 200, respectively. The first signal line extraction electrode 37a, the first surface wiring layer 38a, and the second surface wiring layer 39a penetrate the first memory cell array layer 200 in the Z direction.

[0032] As shown in Figure 1, the first external connection electrode 40a is provided outside the first memory cell array region 28a. That is, the first external connection electrode 40a is provided in a region even further outside the stepped structure portion 29 of the memory cell array. The first external connection electrode 40a is electrically connected to the first surface wiring layer 38a and the second surface wiring layer 39a, which are provided on the first surface Sa1 and the second surface Sa2 of the first memory cell array layer 200, respectively. The first surface wiring layer 38a and the second surface wiring layer 39a are embedded in the first surface Sa1 and the second surface Sa2, respectively, and their surfaces are exposed from an interlayer insulating layer (not shown). The first external connection electrode 40a, the first surface wiring layer 38a, and the second surface wiring layer 39a penetrate the first memory cell array layer 200 in the Z direction.

[0033] As shown in Figure 1, the control circuit layer 100 is provided on a circuit board 1. The circuit board 1 of the control circuit layer 100 is, for example, a silicon substrate. A control circuit 1A is formed on the circuit formation surface of the circuit board 1 of the control circuit layer. The control circuit 1A is formed as an integrated circuit including a transistor. The transistor has a MOSFET structure with a gate electrode, source / drain regions, etc. The source / drain regions of the MOSFET are connected to a circuit-side connection electrode 41 by other wiring layers or plugs. The circuit-side connection electrode 41 is electrically connected to a first circuit-side surface wiring layer 42 provided on the circuit formation surface of the control circuit layer 100. The first circuit-side surface wiring layer 42 is embedded in the circuit formation surface, and its surface is exposed from an interlayer insulating layer (not shown). A second circuit-side surface wiring layer 43 is provided adjacent to the first circuit-side surface wiring layer 42, and the second circuit-side surface wiring layer 43 is connected to the first surface wiring layer 38a on the first memory cell array layer 200 side. The second circuit-side surface wiring layer 43 is embedded in the circuit formation surface, and its surface is exposed from an interlayer insulating layer (not shown).

[0034] The second memory cell array layer 300 has the same configuration as the first memory cell array layer 200 shown in Figures 1 to 4. That is, the second memory cell array layer 300 has a third surface (bottom surface) Sb1 and a fourth surface (top surface) Sb2 opposite to the third surface in Figure 1, and has a three-dimensional second memory cell array 10b. Further explanation of other configurations in the second memory cell array layer 300 that are the same as those in the first memory cell array layer 200 will be omitted as appropriate.

[0035] The second memory cell array layer 300 does not include a substrate. Furthermore, a second source-side wiring layer 19b is provided on the fourth surface Sb2 side of the second source line SL. Similar to the first memory cell array layer 200, at least portions of the word wiring layer 33 and the selection gate wiring layer 34 are led out by other wiring layers and plugs to the outside of the second memory cell array region 28b, as a word line lead-out section 35 and a selection gate line lead-out section 36, when viewed from a direction perpendicular to the third surface Sb1. The word line lead-out section 35 and the selection gate line lead-out section 36, which are led out to the outside of the second memory cell array region 28b, are connected to a second signal line lead-out electrode 37b provided on the outside of the second memory cell array region 28b.

[0036] Furthermore, the channel body 20 of the second columnar portion 13b is electrically connected to the second bit line BL and the second source line SL. In addition, at least a portion of the second bit line BL and the second source line SL are led out as a second bit line lead-out and a second source line lead-out, respectively, outside the second memory cell array region 28b when viewed from a direction perpendicular to the third surface, by other wiring layers or plugs (not shown). The second bit line lead-out and the second source line lead-out, which are led out outside the second memory cell array region 28b, are connected to a second signal line lead-out electrode 37b provided outside the second memory cell array region 28b. Note that the configuration within the second memory cell array region 28b is the same as the configuration of the memory cell array region 28a of the first memory cell array layer 200, so the notation and explanation of reference numerals are omitted as appropriate.

[0037] The configuration within the second memory cell array area 28b is the same as that within the first memory cell array area 28a, but differs in that the configuration is inverted vertically. As previously described, the multiple electrode layers WL formed in the first memory cell array region 28a are arranged such that, when both the one side in the X direction shown in Figure 1 and the other side in the X direction (which is not shown in Figure 1) are combined, they form a trapezoidal contour in cross-sectional view.

[0038] In contrast, the multiple electrode layers WL formed in the second memory cell array region 28b are arranged such that, when both the one end in the X direction shown in Figure 1 and the other end in the X direction (which is not shown in Figure 1) are combined, they form an inverted trapezoidal contour in cross-sectional view. Therefore, the inclined portion 29a of the stepped structure 29 formed in the second memory cell array region 28b is oriented toward the third surface Sb1. In other words, the laminate 12a is arranged such that, when viewed in cross-section, the multiple electrode layers WL formed in the memory cell array region 28b shown in Figure 1 and the insulating layers formed between them form an inverted trapezoidal contour (wherein the inverted trapezoidal shape is inverted relative to the trapezoidal shape formed by the multiple electrode layers WL formed in the first memory cell array region 28a).

[0039] The third surface wiring layer 38b and the fourth surface wiring layer 39b are provided on the third surface Sb1 and the fourth surface wiring layer Sb2 of the second memory cell array layer 300. The third surface wiring layer 38b and the fourth surface wiring layer 39b are embedded in the third surface Sb1 and the fourth surface Sb2, respectively, and their surfaces are exposed from an interlayer insulating layer (not shown). Here, the second signal line extraction electrode 37b is electrically connected to the third surface wiring layer 38b and the fourth surface wiring layer 39b provided on the third surface Sb1 and the fourth surface wiring layer Sb2 of the second memory cell array layer 300, respectively. The second signal line extraction electrode, the third and fourth surface wiring layers penetrate the second memory cell array layer 300 in the Z direction.

[0040] Furthermore, as shown in Figure 1, a second external connection electrode 40b is provided outside the second memory cell array region 28b. That is, the second external connection electrode 40b is provided in a region even further outside the stepped structure portion 29 of the memory cell array. The second external connection electrode 40b is electrically connected to the third surface wiring layer 38b and the fourth surface wiring layer 39b, which are provided on the third surface Sb1 and the fourth surface Sb2 of the second memory cell array layer 300, respectively. The third surface wiring layer 38b and the fourth surface wiring layer 39b are embedded in the third surface Sb1 and the fourth surface Sb2, respectively, and their surfaces are exposed from an interlayer insulating layer (not shown). The second external connection electrode 40b, the third surface wiring layer 38b, and the fourth surface wiring layer 39b penetrate the second memory cell array layer 300 in the Z direction. An external connection pad 52 is provided on the surface wiring layer 39b of the fourth surface wiring layer 39b that is electrically connected to the second external connection electrode 40b.

[0041] As shown in Figure 1, the first surface wiring layer 38a provided on the first surface Sa1 is bonded and joined to the first and second circuit-side surface wiring layers 42 and 43 provided on the circuit-forming surface. The first surface wiring layer 38a and the first and second circuit-side surface wiring layers 42 and 43 are made of, for example, copper or a copper alloy mainly composed of copper. An insulating layer (not shown) is provided around the first surface wiring layer 38a and the first circuit-side surface wiring layer 42. The insulating layer is, for example, an inorganic film or a resin film. The first memory cell array layer 200 and the control circuit layer 100 are electrically connected via the first surface wiring layer 38a and the first and second circuit-side surface wiring layers 42 and 43.

[0042] Furthermore, as shown in Figure 1, the second surface wiring layer 39a provided on the second surface Sa2 is bonded to and electrically joined with the third surface wiring layer 38b provided on the third surface Sb1. The second surface wiring layer 39a and the third surface wiring layer 38b are made of, for example, copper or a copper alloy mainly composed of copper. An insulating layer (not shown) is provided around the second surface wiring layer 39a on the second surface and the third surface wiring layer 38b on the third surface Sb1. This insulating layer is, for example, an inorganic film and includes a silicon nitride film.

[0043] The first memory cell array layer 200 and the second memory cell array layer 300 are electrically connected via the second surface wiring layer 39a and the third surface wiring layer 38b. Since the second surface Sa2 of the first memory cell array layer 200 and the third surface Sb1 of the second memory cell array layer 300 are bonded together, the interface between the second surface Sa2 and the third surface Sb1 is referred to as the stacking interface bs. Furthermore, the stepped structure portion 29 of the first memory cell array layer 200 is stacked with its inclined portion 29a facing the stacking interface bs, and the stepped structure portion 29 of the second memory cell array layer 300 is stacked with its inclined portion 29b facing the stacking interface bs.

[0044] As explained earlier, the word line extraction section 35, the selection gate line extraction section 36, etc., formed in the first memory cell array layer 200 were formed in the layer closer to the second surface Sa2 in the first memory cell array layer 200. In contrast, the word line extraction section 35, the selection gate line extraction section 36, etc., formed in the second memory cell array layer 300 were formed in the layer closer to the third surface Sb1 in the second memory cell array layer 300.

[0045] Furthermore, if the insulating layer surrounding the wiring layer is an inorganic film, the wiring layers can be joined together at the joint surface, and hydrogen bonding between the inorganic films can also be used for joining. Therefore, using an inorganic film as the insulating layer is preferable because it reduces the likelihood of gaps forming at the joint surface, thus eliminating the need for underfill using a resin film.

[0046] "Manufacturing method for semiconductor memory devices" The semiconductor memory device SMD (Semiconductor Device) with the configuration shown in Figures 1 to 4 is prepared by forming multiple wirings, circuits, insulating layers, electrode layers, etc., in a grid-like pattern on a disc-shaped semiconductor substrate (semiconductor wafer) W as shown in Figure 5, and dividing the area into multiple regions. Then, multiple semiconductor substrates W are bonded together, and after bonding, cutting lines CL1...CL demarcate the grid-like regions. n (n is an arbitrary integer) and cutting line SL1...SL n Multiple SMD semiconductor memory devices shown in Figures 1 to 4 can be manufactured by cutting along a line (where n is an arbitrary integer). In the following explanation, to simplify the diagrams and descriptions, we will assume that one SMD semiconductor memory device is formed on a single substrate, and will describe the manufacturing method for the SMD.

[0047] To manufacture the aforementioned semiconductor memory device (SMD), a first wafer 61 is prepared, on which a first memory cell array layer 200 is formed on one surface of a first substrate 60, as shown in Figure 6, and a second wafer 63 is prepared, on which a second memory cell array layer 300 is formed on one surface of a second substrate 62. Then, the first substrate 60 and the second substrate 62 are bonded together as shown in Figure 6, with the insulating layers 200A of the first memory cell array layer 200 and the insulating layers 300A of the memory cell array layer 300 facing each other. When bonding substrates 60 and 62, they are bonded together so that the second surface wiring layer 39a and the third surface wiring layer 38b are joined. In the figures from Figure 6 onward, the insulating layers 200A and 300A are shown as outlined in white for clarity.

[0048] Both the first substrate 60 and the second substrate 62 are disc-shaped substrates, and their outer edges are chamfered, so that they have an appropriate curvature and rounded corners are formed in the rounded portions 60a and 62a. Since the peripheral edges of insulating layers such as the first memory cell array layer 200 and the second memory cell array layer 300 are formed on these rounded portions 60a and 62a, the peripheral edges 65 and 66 of these insulating layers also cover the rounded portions 60a and 62a.

[0049] As shown in Figure 6, Figure 9 shows a partially enlarged cross-section of the state in which the first substrate 60 and the second substrate 62 are bonded together. As shown in Figure 9, when bonding the first substrate 60 and the second substrate 62, the second surface wiring layer 39a on the first substrate 60 side and the third surface wiring layer 38b on the second substrate 62 side are aligned and bonded together, electrically connecting the wiring layers. In the first substrate 60 shown in Figure 9, the first memory cell array layer 200 is formed on one surface of the first substrate 60 via an insulating layer 50, and the second memory cell array layer 300 is formed on one surface of the second substrate 62 via an insulating layer 50.

[0050] The process of forming the first memory cell array layer 200 on the first substrate 60 and the process of forming the second memory cell array layer 300 on the second substrate 62 are equivalent processes, but the elements constituting both array layers 200 and 300 are inverted vertically. Therefore, when forming the first memory cell array layer 200 on the first substrate 60, multiple wirings, circuits, insulating layers, electrode layers, etc. are formed so that the source lines SL formed in the first memory cell array 10a are formed on the side closer to the first substrate 60. When forming the second memory cell array layer 300 on the second substrate 62, multiple wirings, circuits, insulating layers, electrode layers, etc. are formed so that the source lines SL formed in the second memory cell array 10b are formed on the side closer to the second substrate 62.

[0051] Figure 9 shows a state in which the second memory cell array layer 300 of the second substrate 62, which is inverted vertically, is superimposed on the first memory cell array layer 200 of the first substrate 60. Therefore, the stepped structures 29 formed on each memory cell array layer 200 and 300 are also formed facing each other via insulating layers 200A and 300A. Therefore, the surface where the first substrate 60 and the second substrate 62 are bonded together is the stacking interface bs, the surface on the stacking interface side of the first memory cell array layer 200 becomes the second surface Sa2, and the surface on the stacking interface side of the second memory cell array layer 300 becomes the third surface Sb1.

[0052] As shown in Figure 6, after bonding the first substrate 60 and the second substrate 62 together, the peripheral edge of the second substrate 62 is trimmed by grinding away the material, as shown in Figure 7. In the trimming process, the peripheral edge 62b of the bonded second substrate 62 and the peripheral edge 60b of the first substrate 60 facing the peripheral edge 62b are removed over a predetermined width, including the insulating layer between the two substrates. In this trimming process, the entire thickness of the peripheral edge 62b of the second substrate 62 is removed. A portion (about one-tenth) of the thickness of the peripheral edge 60b of the first substrate 60 is removed. The removal width of the peripheral edge 60b and the removal width of the peripheral edge 62b are assumed to be the same, and a corresponding width is removed. By trimming, a first trim portion 60d in the shape of a periphery step can be formed on the upper surface side of the peripheral edge 60b of the first substrate 60, and a second trim portion 62d with an outer surface without a rounded portion can be formed on the outer periphery of the second substrate 62. Furthermore, a first array layer trim portion 60f can be formed around the first memory cell array layer 200 on the first substrate 60 side, and a second array layer trim portion 62f can be formed around the second memory cell array layer 300 on the second substrate 62 side.

[0053] The width removed by trimming is set to a width that can remove at least the areas where the rounded portions 60a and 62a of the first substrate 60 and the second substrate 62 are formed. If this removal width is too large, in the actual manufacturing process, the area removed will be larger than the area outside the grid-like arrangement of regions formed on the semiconductor substrate W, as shown in Figure 5. Since the memory cell array layers formed in these removed regions are to be discarded, a large trim removal width reduces the number of memory cell array layers that can be manufactured from a single substrate, resulting in a decrease in yield.

[0054] Next, grinding is performed on the first substrate 60 from the side opposite to the side on which the first memory cell array layer 200 is formed to remove the remaining portion of the first substrate 60. A partially enlarged cross-section of the state after the first substrate 60 has been removed from the first memory cell array layer 200 is shown in Figure 10. Figure 10 shows the state after the first substrate 60 on the side where the first memory cell array layer 200 is formed has been removed, and the insulating layer 50 has also been removed. From the state shown in Figure 10, a first surface wiring layer 38a is formed to connect to the first external connection electrode 40a formed on the first memory cell array layer 200, and a first surface wiring layer 38a is formed to connect to the first signal line extraction electrode 37a.

[0055] Next, a third wafer 70 equipped with a control circuit layer 100 is prepared on a separately prepared third substrate 68, and the first memory cell array layer 200 and the control circuit layer 100 are connected by bonding, as shown in Figure 8. On the upper surface of the control circuit layer 100, a first circuit-side surface wiring layer 42 and a second circuit-side surface wiring layer 43 are formed, as shown in Figure 1. Therefore, by the bonding described above, the first circuit-side surface wiring layer 42 can be connected to one of the first surface wiring layers 38a, and the second circuit-side surface wiring layer 43 can be connected to the other first surface wiring layer 38a, as shown in Figure 11.

[0056] As shown in Figure 11, a stacked structure similar to that in Figure 1 can be obtained by bonding the second memory cell array layer 300 and the control circuit layer 100 together. By removing the second substrate 62 and the insulating layer 50 from the laminated structure shown in Figure 11 by grinding, and forming the external connection pad 52, the structure shown in Figure 1 can be obtained.

[0057] As explained above with reference to Figures 6 to 11, by employing a manufacturing method for producing semiconductor memory devices (SMDs), trimmed portions 60d and 62d can be formed on the first wafer 61 and the second wafer 63 in a single trimming step after bonding the first wafer 61 and the second wafer 63 together. In contrast, the manufacturing method of the comparative example described below requires two trimming steps.

[0058] "Manufacturing method of the comparative example" In the manufacturing method of the comparative example, a third wafer 70 having a control circuit layer 100 on a third substrate 68 is first prepared, and as shown in Figure 12, it is bonded to a first wafer 61 having a first memory cell array layer 200M on one side of the first substrate 60. A partially enlarged cross-section of the third wafer 70 and the first wafer 61 immediately before bonding is shown in Figure 15, and a partially enlarged cross-section of the third wafer 70 and the first wafer 61 after bonding is shown in Figure 16. Unlike the previous embodiment, the first memory cell array layer 200M does not have an inverted structure compared to the second memory cell array layer 300, but rather has a structure equivalent to that of the second memory cell array layer 300.

[0059] Furthermore, the first wafer 61 is pre-trimmed to form a first trimmed portion 60e on the peripheral edge of the first substrate 60. Furthermore, as shown in Figure 13, a second wafer 63 is prepared on which a second memory cell array layer 300 is formed on one surface of the second substrate 62, and a second trimming process is applied to the peripheral edge of the second substrate 62 to form a second trim portion 62e in the shape of a peripheral step.

[0060] Next, the first substrate 60 shown in Figure 12 is ground off from the top side to expose the first memory cell array layer 200. The reason for performing the trimming process described above to form the first trim portion 60e is as follows. When the thickness of the first substrate 60 shown in Figure 12 is reduced by grinding from the top side, if the substrate has a rounded edge on the peripheral edge where the first trim portion 60e is not formed, a sharp, knife-edge shaped peripheral edge will remain on the outer edge of the substrate at the final stage of grinding. This knife-edge shaped peripheral edge may break or crack in the substrate at the final stage of the substrate grinding process. If a broken portion occurs from the peripheral edge of the substrate during the grinding process, the broken portion may penetrate between the grinding tool and the substrate and damage the substrate surface. For this reason, it is necessary to form the first trim portion 60e on the first substrate 60.

[0061] After grinding and removing the first substrate 60 shown in Figure 12 to expose the first memory cell array layer 200M, the second memory cell array layer 300 formed on the second substrate 62 shown in Figure 13 is bonded to the first memory cell array layer 200M as shown in Figure 14. This bonding electrically connects the second surface wiring layer 39a of the first memory cell array layer 200M to the third surface wiring layer 38b of the second memory cell array layer 300.

[0062] As shown in Figure 14, after the second memory cell array layer 300 is bonded to the first memory cell array layer 200 on the third wafer 70, the second substrate 62 is ground and removed to expose the second memory cell array layer 300. In the final grinding step where the second substrate 62 is ground and removed, there is a risk that knife-edge shaped peripheral portions may remain on the periphery of the substrate, similar to the case of grinding the first substrate 60 described earlier. For this reason, it is necessary to form a second trim portion 62e on the second substrate 62 as well.

[0063] From the state shown in Figure 14, removing the second substrate 62 exposes the second memory cell array layer 300. By forming an external connection pad 52 on the insulating layer of the second memory cell array layer 300, the semiconductor memory device SMD# shown in Figure 17 can be obtained. The structure shown in Figure 17 is equivalent to the structure of the first memory cell array layer 200 in the embodiment described earlier, except that the orientation of the stepped structure portion 29 of the first memory cell array layer 200M is oriented toward the substrate 1 side (-Z direction side).

[0064] Even the semiconductor memory device SMD# shown in Figure 17, obtained by the manufacturing method of the comparative example, is a non-volatile semiconductor memory device that, like the semiconductor memory device SMD shown in Figure 1, allows for free electrical erasure and writing of data and retains stored content even when the power is turned off. However, as mentioned above, two trimming processes are required to manufacture SMD semiconductor memory devices. Trimming is a process of removing material from the substrate by grinding, and grinding the substrate is a time-consuming and complicated process. Therefore, reducing the number of trimming processes from two to one represents a significant labor saving in the manufacturing process of SMD semiconductor memory devices.

[0065] When trimming the edges of a substrate, the memory cell array layer in the trimmed area of ​​the substrate edge is inevitably discarded. Therefore, a manufacturing method that requires only one trimming step reduces the amount of discarded memory cell array layer compared to a method that requires two trimming steps. This increases the number of SMD semiconductor memory devices that can be manufactured from a single substrate, thus improving production efficiency.

[0066] Furthermore, in the case of the manufacturing method of the comparative example shown in Figure 14, when a third wafer 70 equipped with a control circuit layer 100 is prepared and the second memory cell array layer 300 is connected to the first memory cell array layer 200 on the third wafer 70 by bonding, a step d is created at the bonding surface. This step difference d is caused by changing the trim width when forming a trim portion 60e on the peripheral edge of the first substrate 60 shown in Figure 12, and when forming a second trim portion 62e on the second substrate 62 shown in Figure 13. If the trim width of trim section 62e is greater than the trim width of trim section 60e, it means that the number of items to be discarded in the second memory cell array layer 300 formed on the second substrate 62 side will increase.

[0067] As shown in Figure 5, when multiple regions are defined on a single disc-shaped semiconductor substrate W and a semiconductor memory device (SMD) is manufactured for each region, a circular dashed line L is shown slightly inward from the outer edge of the semiconductor substrate W. The region between this dashed line L and the outer edge of the semiconductor substrate W forms the trim portion. It can be seen that if the circle indicated by the dashed line L becomes even slightly smaller, in other words, if the trim width increases, the number of second memory cell array layers that are to be discarded increases.

[0068] In contrast, according to the manufacturing method described in the previous embodiment, as shown in Figure 7, a second substrate 62 having a second memory cell array layer 300 is first bonded to a first substrate 60 having a first memory cell array layer 200. After this bonding, trim portions 60d and 62d are formed simultaneously, so the trim width of the first substrate 60 and the trim width of the second substrate 62 can be made the same. Therefore, the number of memory cell array layers to be discarded can be the same for both the first substrate 60 and the second substrate 62, allowing for a greater number of semiconductor memory devices (SMDs) to be manufactured per substrate compared to the manufacturing method of the comparative example.

[0069] Furthermore, in the comparative example's manufacturing method, as shown in Figure 14, there was a step d between the first memory cell array layer 200M and the third memory cell layer 300. In contrast, in the above embodiment, in the bonded configuration shown in Figure 8, it is possible to have a configuration without a step between the first memory cell array layer 200 and the third memory cell array layer 300. [Explanation of symbols]

[0070] MC…Memory cell MS...memory string, SMD… Semiconductor memory device, WL...electrode layer, bs…Lamination boundary surface, 1...Circuit board, 10a...First memory cell array, 10b...Second memory cell array 11…Insulating layer, 12a...Laminate, 13a...First columnar part, 14, 15, 18... Interlayer insulating layer, 16a...First bit line, 17a...First source line, 19a...First source-side wiring layer, 28a...First memory cell array region, 28b...Second memory cell array region, 29...Stair structure part, 29a, 29b...slanted part, 30, 32... Contact plugs, 38a...First surface wiring layer, 39a...Second surface wiring layer, 38b...Third surface wiring layer, 39b...Fourth surface wiring layer, 42...First circuit-side surface wiring layer, 43...Second circuit-side surface wiring layer, 60...First circuit board, 60a... curved section, 60d...First trim section, 60f...First array layer trim section, 61...First wafer, 62...Second circuit board, 62a...Round section, 62d... Second trim section, 62f... Second array layer trim section, 63...Second wafer, 68... Third circuit board, 100...Control circuit layer, 200...First memory cell array layer, 200A...insulating layer, 300...Second memory cell array layer, 300A...Insulating layer.

Claims

1. A method for manufacturing a semiconductor memory device by bonding together a first substrate having an insulating layer and memory cells provided within the insulating layer, a second substrate having an insulating layer and memory cells provided within the insulating layer, and a third substrate having an insulating layer and control circuit provided within the insulating layer. The first substrate and the second substrate are bonded together via the insulating layers, and a trimming process is performed to remove the peripheral edges of the bonded first substrate and the second substrate, including the insulating layer between the first and second substrates, over a predetermined width, from the peripheral edge of the first substrate to the peripheral edge of the second substrate adjacent to the first substrate, and for the second substrate, a portion of the peripheral edge of the second substrate is removed over a predetermined width corresponding to the removal width of the first substrate, and then the remaining portion of the first substrate is removed by grinding to expose the insulating layer formed on the first substrate on the second substrate. The insulating layer of the third substrate is bonded to the exposed insulating layer. A method for manufacturing semiconductor memory devices.

2. After bonding the insulating layer of the third substrate to the exposed insulating layer, the remaining portion of the second substrate is removed, and a structure is obtained in which the insulating layer formed on the first substrate and the first memory cell array layer having the memory cells, and the insulating layer formed on the second substrate and the second memory cell array layer having the memory cells are laminated on the third substrate equipped with the control circuit. A method for manufacturing a semiconductor memory device according to claim 1.

3. The first substrate has a first surface wiring layer on the surface of its insulating layer, and the second substrate has a second surface wiring layer on the surface of its insulating layer. When bonding the insulating layer of the first substrate and the insulating layer of the second substrate, the first surface wiring layer and the second surface wiring layer are aligned and bonded together. A method for manufacturing a semiconductor memory device according to claim 1.

4. The memory cell is a memory cell having a laminate in which a plurality of electrode layers are stacked with a plurality of insulating layers in between, and the laminate is a laminate having a stepped structure in which the end positions of the plurality of electrode layers are shifted at each stacking position, When bonding the first substrate and the second substrate via the insulating layer, the inclined surface of the staircase structure is bonded toward the laminated interface of the bond between the first substrate and the second substrate. A method for manufacturing a semiconductor memory device according to claim 1.

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