Phase-mode bit-addressable sensing register

Abstract

The shift register elements of the phase mode bit addressable sense register sample the changing AC or DC bias values ​​provided to the operational RQL circuit on the RQL IC via the clock resonator or DC bias lines. The shift register may be composed of a phase mode D flip-flop and multiple JTLs as data and clock lines. A method of using the sense register includes the steps of shifting in a data bit pattern while the bias parameter (e.g., AC amplitude, DC value, or phase) is set to a nominal value, stopping the logic clock that controls the shifting of values ​​through the sense register, changing the bias parameter value, inputting one assertion SFQ pulse or reciprocal pulse pair to the logic clock, returning the bias parameter to the nominal value, restarting the logic clock to shift out the output data bit pattern, and observing the output data bit pattern to determine the effect of the change in the bias parameter value.

Description

[Technical Field]

[0001] This disclosure relates, in general terms, to superconducting circuits, and more specifically, to a phase-mode bit-addressable sensing register. [Background technology]

[0002] In the field of digital logic, well-known and highly developed complementary metal-oxide-semiconductor (CMOS) technology is widely used. As CMOS technology has begun to mature, there is growing interest in alternative technologies that can offer higher performance in terms of speed, power consumption, computational density, and interconnect bandwidth. As an alternative to CMOS technology, single-flux quantum (SFQ) circuits utilize superconducting Josephson junctions (JJ) with a typical signal power of about 4 nanowatts (nW), a typical data rate of more than 20 gigabits per second (Gb / s), and an operating temperature of about 4 Kelvin.

[0003] The family of SFQ circuits, known as reciprocal quantum logic (RQL), distributes one or more bias signals using one or more resonator networks and / or bias lines. The bias signals play a role in biasing the JJs within the logic gates of the RQL circuit and the Josephson transmission lines (JTLs), which are found within the gates of the RQL circuit or as inter-gate connecting lines for propagating SFQ signals within the RQL circuit. The AC bias signals can function as one or more global clock signals that can help eliminate clock jitter, such as that exhibited by earlier superconducting circuit techniques, such as rapid single-flux quantum (RSFQ) logic. For example, RQL can utilize a multiphase clock having an in-phase (I) clock signal and an orthogonal (Q) clock signal that is approximately 90° out of phase with the I clock signal. [Overview of the project]

[0004] An exemplary RQL integrated circuit (IC) includes a phase-mode shift register having a first plurality of JTLs arranged in series as a data path, a second plurality of JTLs arranged in series as a logic clock path trunk, and a plurality of phase-mode D flip-flops. Each phase-mode D flip-flop has (1) a data input coupled to the data path and configured to receive input from the data path, (2) a data output coupled to the data path and configured to provide output to the data path, and (3) a logic clock input coupled to a branch of an individual logic clock path coupled to the logic clock path trunk. The first plurality of JTLs and phase-mode D flip-flops in the data path are transformer-coupled to one or more AC clock resonators of the RQL IC to receive AC clock bias signals of two first AC clock phases separated by approximately 180° from each other. The second set of JTLs in the logic clock path trunk are transformer-coupled to one or more AC clock resonators of the RQL IC to receive AC clock bias signals of two second AC clock phases that are approximately 180° apart in phase from each other. The first two AC clock phases are different from the second two AC clock phases.

[0005] An exemplary method includes the steps of setting at least one bias signal parameter of the bias signal supplied to the RQL IC to its nominal value, and starting a logic clock signal supplied to the logic clock path of the phase-mode RQL shift register to shift in the input data bit pattern to the data path of the phase-mode RQL shift register. The logic clock is then stopped, and the value of at least one bias signal parameter supplied to the data path of the phase-mode RQL shift register is changed to a value different from the nominal value. A pair of assertion SFQ pulses, or a single SFQ pulse, is input to the logic clock path. When the value of at least one bias signal parameter is returned to its nominal value, the logic clock signal supplied to the logic clock path of the phase-mode RQL shift register is restarted, and the output data bit pattern is shifted out to the data path of the phase-mode RQL shift register. The output data bit pattern of the phase-mode RQL shift register is observed. Based on observation of the output data bit pattern, it is determined that the value of at least one bias signal parameter approaches (or has approached) its optimal value by changing the value of at least one bias signal parameter. The bias signal parameter to be changed may be the AC bias amplitude, DC bias value, or AC bias signal phase.

[0006] Another exemplary RQL superconducting bias level sensing circuit for sensing the bias level supplied to the operating RQL circuit of an RQL IC comprises a phase-mode logic (PML) shift register including a plurality of PML shift register elements coupled in series with each other. Each PML shift register element includes a PML D flip-flop having a data input, a data output, and a logic clock input, wherein the data input is configured to be coupled to either the data output of the previous element in the PML shift register or an input data bitstream source. Each PML shift register element further includes a data output path portion having an input coupled to the data output of the PML D flip-flop and an output configured to be coupled to either the data input of the next element in the PML shift register or a circuit configured to receive an output data bitstream from the PML shift register, wherein the data output path portion comprises first, second, and third JTL-based buffers coupled in series with each other between the input and output of the data output path portion. Each PML shift register element further includes a logic clock path trunk portion having an input configured to be coupled to either the logic clock path output or the logic clock source of the next element in the PML shift register, and an output configured to be coupled to either the logic clock path input of the previous element in the PML shift register and / or a branch of the logic clock path of the PML shift register element, wherein the logic clock path trunk portion comprises fourth, fifth, sixth, seventh, and eighth JTL-based buffers coupled in series with each other between the input and output of the logic clock path trunk portion. Each PML shift register element further includes a branch of the logic clock path having an input coupled to the output of the logic clock path trunk portion of the PML shift register element, and an output coupled to the logic clock input of a PML D flip-flop, wherein the branch of the logic clock path comprises ninth and tenth JTL-based buffers coupled in series with each other between the input and output of the branch of the logic clock path. [Brief explanation of the drawing]

[0007] [Figure 1]This is a block diagram of an exemplary RQL bias level detection and adjustment system. [Figure 2A] This is a block diagram of an exemplary set of RQL bias level sensors configured within a JTL-based RQL scan register bias level sensor wrapper for series output. [Figure 2B] This is a block diagram of an exemplary set of RQL bias level sensors configured within a JTL-based bias level sensor wrapper for parallel output. [Figure 2C] This is a block diagram of an exemplary set of RQL bias level sensors configured within a ring oscillator wrapper. [Figure 3] This is a graph of exemplary margin schmoo plots showing the nominal AC and DC bias level operating margins for a responsive RQL circuit and RQL bias level sensor. [Figure 4A] This is a graph of exemplary margin schmoo plots of AC and DC bias level operating margins for an operable RQL circuit and RQL bias level sensor, showing the effect of changes in the AC amplitude of the supplied bias signal. [Figure 4B-4D] Figure 4A is a one-dimensional time plot of output pulse reception for a bias level sensor wrapper similar to that in Figure 2A, showing the effect of changes in the AC amplitude of the supplied bias signal. [Figure 5A] This is a graph of exemplary margin schmoo plots of AC and DC bias level operating margins for an operable RQL circuit and RQL bias level sensor, showing the effect of changes in the DC value of the supplied bias signal. [Figures 5B-5D] Figure 5A is a one-dimensional time plot of output pulse reception against a bias level sensor wrapper similar to that in Figure 2A, illustrating the effect of changes in the DC value of the supplied bias signal. [Figure 6] This is a schematic diagram of an exemplary sampler stage configured for use with a bias level sensor, such as the one shown in Figure 2A, and includes a JTL to which the bias is supplied by a tap. [Figure 7] Figure 2A is an exemplary block diagram of a suppression logic unit. [Figure 8] This is a block diagram of an exemplary shift register, including four instances of the exemplary sampler stage shown in Figure 6, which can be used as a bias level sensor as shown in Figure 2A. [Figure 9] This is a block diagram of an exemplary shift register, including three instances of the exemplary sampler stage shown in Figure 6, which can be used as a bias level sensor as shown in Figure 2A. [Figure 10] This is a block diagram of an exemplary shift register, including one instance of the exemplary sampler stage in Figure 6, which can be used as a bias level sensor as shown in Figure 2A. [Figure 11] This is a block diagram of an exemplary shift register, including one instance of the exemplary sampler stage in Figure 6, which can be used as a bias level sensor as shown in Figure 2A. [Figure 12] This is a block diagram of an exemplary specific phase bias level sensor for the Q clock. [Figure 13] This is a block diagram of an exemplary specific phase bias level sensor for an I clock. [Figure 14] This is a block diagram illustrating the symbols used in Figures 12, 13, 16, and 18. [Figure 15] This is a block diagram illustrating the symbols used in Figures 12, 13, 16, and 18. [Figure 16] This is a block diagram of an exemplary specific I-clock (Q-clock independent) bias level sensor. [Figure 17] Figures 16 and 18 are illustrative AC and DC bias margin Schmoo plots for a specific I-clock (Q-clock independent) bias level sensor. [Figure 18] This is a block diagram of another exemplary specific I-clock (Q-clock independent) bias level sensor. [Figure 19]This is a graph of an exemplary minimum operating AC bias for a specific I clock and a specific Q clock bias level sensor as a function of the Q clock phase deviation from 90°. [Figure 20] This is a block diagram of an exemplary phase sampler. [Figure 21] This is a block diagram explaining the symbols used in Figure 20. [Figure 22] Figure 20 is a graph showing an example of clock amplitude versus phase error for an exemplary phase sampler. [Figure 23] Figure 20 is a graph showing the AC amplitude of an exemplary minimum operating bias signal for a phase sampler. [Figure 24] This is a block diagram of a part of a phase-mode logic (PML) bias level sensor. [Figure 25] This is a block diagram of an exemplary pulse generator-based bias level sensor, as shown in part of the wrapper similar to the wrapper in Figure 2A. [Figure 26A] This is a block diagram of an exemplary configuration of a bias level sensor placed within a DC SQUID-based bias level sensor. [Figure 26B] This is a block diagram of an exemplary DC SQUID-based output amplifier configured as a sensor for measuring the level of an externally supplied output bias current IBIASOUT and comparing it to an optimal level. [Figure 27A] This is a block diagram of an exemplary feedback system for detecting and tuning the AC amplitudes of the I clock and Q clock. [Figure 27B] This is a block diagram of an exemplary feedback system for detecting and tuning phase errors of the I clock and Q clock. [Figure 28] This flowchart illustrates an exemplary method for adjusting or optimizing AC and DC bias points using a bias level sensor integrated on an RQL IC. [Figure 29]This flowchart illustrates an exemplary method for adjusting or optimizing the AC (or, modified to DC) bias point using a PML shift register similar to that shown in Figure 24, integrated on an RQL IC. [Figure 30] This flowchart illustrates an exemplary method for adjusting or optimizing the relative phase difference between the I clock and the Q clock using a phase-sensitive bias level sensor integrated on an RQL IC. [Figure 31] This flowchart illustrates an exemplary method for adjusting or optimizing the AC bias amplitudes of the I clock and Q clock on an RQL IC, as well as the phase difference between the I clock and Q clock. [Modes for carrying out the invention]

[0008] The computational functions of the RQL system can be performed at least partially by an operable digital circuit that may include logic gates and JTLs. This operable circuit includes a JJ biased by one or more bias signals of the RQL system, which may include both AC bias and DC bias signals, and the AC signals may function as one or more clocks for the RQL system to synchronize data and / or provide a time-based flow of the RQL system's logic functions. The AC bias signals may supply clocks of different phases, such as a 0° or 180° clock supplied from an I clock resonator, or a 90° or 270° clock supplied from a Q clock resonator. The operable circuit can only operate correctly within certain margins of various operating parameters. Some of these operating parameters are related to the bias signals supplied to the RQL system (e.g., clocks). For example, if the DC bias level of the clock is too high or too low and falls outside the DC bias operating margin of a gate or JTL in the RQL system, the RQL system may malfunction. As another example, if the amplitude of the clock's AC bias signal is too large or too small, it may fall outside the AC bias operating margin of the gates or JTLs in the RQL system, which can cause another RQL malfunction. As yet another example, if the relative phase difference between different clocks, such as the I clock and the Q clock, is too large or too small, it may fall outside the clock phase difference operating margin of the gates or JTLs in the RQL system, which can also cause another RQL malfunction.

[0009] Magnetic flux, which is the time integral of voltage, is a key operating parameter that controls the function of RQL logic circuits, even when applied to conventional inductors or JJs. Due to other factors, including variations in the manufacturing process, there can be considerable variation in the AC and DC fluxes generated by the resonator and the tap transformer coupled to it, which supplies the bias signal to the RQL logic circuit. Variations in the inductors, dielectrics, and JJs that make up the operating RQL circuit cause variations in the amount of AC and DC flux required by those circuits. Temperature changes, as well as aging, can affect the performance of RQL circuits. Considering these changes and variations, the ideal values ​​of bias parameters such as AC amplitude, DC value, and gate flux bias current may not be the same for all RQL logic gates in the system.

[0010] One or more clock signals supplied to an RQL system may be generated by a function generator circuit operating at approximately room temperature (around 300K), but the system's RQL operating circuit may reside in a cryogenically cooled space operating at much lower temperatures, e.g., below approximately 4K, and may be several meters away from the function generator circuit. Due to the low operating temperature and thermal isolation requirements of the RQL system, it may not be possible to directly probe the integrated circuit (IC) on which the RQL system is implemented to examine bias signal parameters (DC level, AC amplitude, relative phase difference of AC clock signals, etc.) at various points on the IC and check whether the bias signal parameters actually supplied to the RQL operating circuit are as intended or within the operating margin of the circuit, which can operate otherwise.

[0011] Measuring the supplied bias levels, such as the AC voltage and DC current supplied on the RQL integrated circuit, as well as other bias parameters such as the relative phase difference between different bias signals, provides the necessary insights to adjust the bias levels generated by bias sources outside the cooling space, ensuring that the delivered bias levels and other parameters delivered to the operating RQL circuit within the cooling space match the optimal value within the operating margin of the operating RQL circuit, for example, the center of the operating margin of the operating RQL circuit. The measurement results for each RQL IC, or a portion of each IC, can be used to adjust the bias levels to improved, optimal, or near-optimal values, providing more reliable performance for the operating RQL circuit.

[0012] Accordingly, the bias level sensor may be provided as a sensing circuit fabricated on the RQL IC together with the operable circuit of the RQL system. The bias level sensor can detect the signal parameters of the bias signal supplied to the operable circuit at various locations on the IC. The detected signal parameters may be used in a manual or automatic feedback loop to signal adjustments to the bias signal supplied to the RQL system so that the bias supplied to the operable circuit of the RQL system remains within the operating margin of the operable circuit. In some examples, multiple bias level sensors may be embedded in a logic circuit referred to herein as a wrapper, which activates the bias level sensor by querying it, for example, with a sampling signal, and reads the result. As an example, the sensor may be incorporated into an RQL scan register or a JTL testbed register.

[0013] In some examples, the bias level sensing circuit architectures and related methods described in this application enable the determination of an improved, near-optimal, or optimal bias level by observing pulses generated by an ensemble of bias level sensing circuits. An exemplary bias level sensing circuit, called a sampler, serves as a substitute for an operational RQL circuit. The sampler may be configured such that, when the elements of the operational RQL circuit are at the optimal bias point, a specific portion of the sampler or one or more specific individual components of the sampler operate to transmit or generate bias level sensing output pulses as expected, while other samplers operate not to transmit or generate bias level sensing output pulses as expected. Which samplers and how many samplers generate bias level sensing output pulses reveals information about the current bias of the operational RQL circuit, e.g., the current bias point of the operational RQL circuit. Using digital logic, the bias level sensing output pulses can be counted, reordered, and / or classified, and search and optimization algorithms can be used to adjust bias signal generation parameters (e.g., bias levels) to improve the delivered bias level and / or bring the operating point closer to the optimal value.

[0014] The operating margin offset of a bias level sensor from the nominal operating margin of an operating RQL circuit can, in some examples, allow for bias level measurements without stopping the operating RQL circuit. As an example, the bias transformer flux may be altered from its normal level to ensure that a bias sensing circuit provides a useful output without needing to move the bias level beyond the operating range of the operating RQL circuit. One way to alter the bias transformer flux is to provide a bias level sensor with a transformer configured to produce a larger or smaller flux than normal by changing the mutual inductance with respect to the clock resonator. Another way to alter the bias transformer flux is to insert more or less inductance than nominal between the transformer and the bias level sensor. As another example, a dedicated bias sensing circuit may be configured to start or stop operation at levels within the operating range of the logic circuit. This can be done by increasing or decreasing the size of the JJ and inductor in the circuit. When the performance of the bias transformer and the associated clock resonator is paramount, it may be preferable to drive the JJ directly from a standard transformer, as only the variability of the JJ adds to the variability of the resonator and transformer. When the need for logic circuits for the outputs of the clock resonator and bias transformer is a concern, it may be advantageous to use a sensing circuit that is minimally different from the operating circuit. This latter objective can be achieved by inserting an additional inductance in series with the transformer while maintaining the transformer and the remaining logic sensing circuit in a standard configuration.

[0015] The operating margin offset may differ for each sensor in a group of bias level sensors, and these sensors may be grouped within a wrapper circuit configured to provide sampling inputs and outputs for bias level measurement. Variations in the operating margin offset between sensors can be intentionally introduced by design (staggered staging), for example, to cover a range around the nominal operating point of the operating RQL circuit. In such a case, the group of bias level sensors may be configured so that a certain proportion of the bias level sensors (e.g., about half of the bias level sensors) generate pulses when the operating logic is optimally biased with respect to the AC amplitude. Thus, the AC amplitude bias level required by the operating RQL circuit can be determined by counting the pulses generated by the group. In another example, the spread of elements in the operating level of bias level sensors resulting from manufacturing process variations can be used to provide a pulse count sensing output substantially equivalent to that of using the staggered sensors described above, without intentional staging of the operating margin offset of the bias level sensors. The reason for this is that when the operating circuit is optimally biased, and the bias to the sensor is close to the sensor's functional limit, the operating RQL circuit approaches its optimal bias condition when approximately half of the bias level of the sensor is biased within its own operating margin, even without design for intentional stepwise setting of the sensor's margin, and therefore generates a detection pulse when queried using a sampled signal via the wrapper circuit.

[0016] Figure 1 shows an exemplary RQL bias level sensing and adjustment system 100. An operational RQL circuit 102, which may include JTLs and logic gates, may be manufactured as a chip on IC 106 together with one or more associated clock resonators 104, and the chip may be enclosed in a cryogenic cooling space configured to lower the RQL operating temperature to, for example, a low single-digit Kelvin or lower. As used herein, the term “operational RQL circuitry” means the logic circuits and associated infrastructure circuits used to perform the useful computational operations on which the RQL IC 106 or the system is designed, and is distinct from the circuits 118 on RQL IC 106 used to perform sensing of parameters related to the bias signal supplied to RQL IC 106. The bias level sensor and wrapper 118 may be provided spatially distributed on IC 106 (for example, across the entire space on the IC occupied by the operational RQL circuitry) to improve the accuracy of bias level measurement.

[0017] The operating circuit 102 is coupled to one or more clock resonators 104 via a number of taps 108 (e.g., inductively coupled) to supply AC bias to the operating circuit 102. The operating circuit may also be coupled to a number of DC bias lines 124 to supply DC bias to the operating circuit 102. In some examples, the DC bias lines 124 may be configured to circulate around the clock resonator 104 to control the amount of DC bias applied to the operating RQL circuit 102 and / or the bias level sensor 118. In some examples, each bias tap 108 or 120 may have an AC transformer coupled to one or more ribs of the clock resonator 104, and another transformer may be coupled in series to the DC bias line 124. Outside the cooling space, the bias signal generator 110 (or multiple bias signal generators, e.g., different signal generators for supplying an I clock bias signal, a Q clock bias signal, and various DC bias signals) can generate one or more clock signals, such as the I clock 112 and the Q clock 114, for supply to the operating circuit 102 via the clock resonator 104 and associated taps 108 within the cooling space. Additionally, one or more bias signal generators 110 can generate DC bias signals for supply to the operating circuit 102 on the IC 106 via the DC bias line 124. The one or more clock signals and / or DC bias signals generated by the clock signal generator 110 may be based on different bias parameters 116, which may be in the form of adjustable or variable settings provided to or stored in the bias signal generator 110. Such bias parameters may include, for example, the clock frequency, the AC amplitude of the generated AC clocks (e.g., I clock and Q clock), or one or more DC values ​​of the generated DC bias, and the phase difference between the Q clock and the I clock at the time of clock generation (which may be nominally about 90°, but not exactly 90° in some cases).

[0018] Furthermore, the bias level sensor 118 may be manufactured on the same IC 106 as the operating RQL circuit 102 and may be configured to sample one or more bias signals (AC clock signal and / or DC bias signal) supplied by one or more resonators 104 via several (N) sampling taps 120 and / or via DC bias lines 124. The bias level sensor may be configured within a wrapper, which may be used to introduce the sampling signal to the bias level sensor 118 and output a signal based on the sampling signal indicating measurements of various clock parameters acquired by the bias level sensor. Such parameters may include any or all of the above parameters (parameters 116) used by the clock signal generator 110 to generate the clock signal outside the cooling space. The output of the bias level sensor and / or associated sensor wrapper 118 may be used via a feedback loop 122 to adjust the parameters supplied to the clock signal generator 110, thereby ensuring that the AC clock and / or DC bias signals supplied in the operating RQL circuit 102 provide a bias that meets the margin requirements of the operating RQL circuit 102. In some examples, the RQL bias level detection and adjustment system 100 can provide bias feedback and adjustment without requiring the deactivation or other method of disabling the operating RQL circuit 102.

[0019] Figure 2A shows an exemplary configuration of RQL bias level sensors 202–212 wrapped within a JTL-based RQL scan register bias level sensor wrapper, which is used to provide a series output from a very large number of bias level sensors that would otherwise be parallel outputs. The bias level sensors 202–212, also referred to herein as samplers, can be thought of as existing on the rungs of a ladder formed by the sensor wrapper. One such run is labeled 214 in Figure 2A. The ladder rails can be formed by JTLs 216–238, shown as triangles in Figure 2A, or other circuits configured to propagate SFQ pulses through the wrapper structure with interstage propagation delays. The example in Figure 2A is shown with one rail JTL between each ladder rung, but each JTL 216–238 can be configured to have as many as desired repeating RQL JTL circuit structures to generate SFQ signal propagation delays for one or more AC clock cycles.

[0020] The bias level sensors 202-212 can take on a number of different forms and may be configured to measure any of a number of different parameters, including AC bias signal amplitude, DC bias value, and interclock phase. Depending on the form of the bias level sensors 202-212, the stage may include suppression logic units (SLs) 240-250, which are configured to prevent assertions of multiple output pulses from propagating from the stage if the associated sampler is in a state where it spontaneously inverts due to a manufacturing defect or excessive bias. In some examples, the suppression logic units 240-250 on some or all of the stages of the wrapper may be omitted. The wrapper may also include an input transformer 252 configured to provide the wrapper with a sample signal consisting of at least one input SFQ pulse supplied from a positive input node INP and a negative input node INN. The wrapper may also include an output amplifier 254 configured to output a voltage signal between a positive output node OUTP and a negative output node OUTN. The output amplifier 254 can take the form of a binary vine tree (not shown) of a JTL, configured to split the input SFQ signal to supply multiple stacked DC SQUIDs (e.g., four DC SQUIDs) arranged as voltage adders.

[0021] In the exemplary configuration 200 in Figure 2A, the sampled signal, provided as an SFQ pulse via the input transformer 252, propagates along the upper rail from the proximal to the distal end of the wrapper ladder, branching along the ladder stages to generate multiple temporally separated output voltage pulses at the ladder output between output nodes OUTP and OUTN. Each rail JTL216-238 generates an interstage propagation delay of at least one AC clock cycle, so the output pulses are temporally separated; output pulses arriving earlier have propagated through the proximal stages of the wrapper ladder (stages closer to the input / output ends of the wrapper ladder), and output pulses arriving later have propagated through the distal stages of the wrapper ladder (stages further from the input / output ends of the wrapper ladder). More precisely, the number of output pulses generated for a given sampled input pulse depends on the number of samplers 202-212 operating with supplied bias signals (one or more) within the operating margin of each sampler 202-212. As will be explained in more detail below, in some examples, samplers 202-212 are, for example, AC bias amplitude XAC, DC bias value X DC , or the phase difference between clocks X phase In this nomenclature, the components may be manufactured to have intentionally stepped margins. In this nomenclature, "X" represents a multiplier of the nominal bias level. For example, if the nominal bias level is 0.2V, then an actually applied bias level of 0.22V would result in X being 1.1 (110%). In other examples, the sensing system may rely on variations in the manufacturing process to provide samplers 202-212 with widened (varying over a range) margins without intentionally designed stepped settings.

[0022] In some examples, such as Example 200 shown in Figure 2A, the first and last stages (the most proximal and most distal stages) of the wrapper ladder may be supplied with standard biases (without correction of the self-inductance and / or mutual inductance of sampler stage 600 in Figure 6) JTL256, 258 such that the first and last pulses provided at the output of the wrapper indicate the margin of the standard device for comparison with the margin of samplers 202-212. The pulses generated by the standard bias JTL256, 258 serve to indicate the start and end of the pulse train generated when input pulses are supplied to INP / INN. In other examples not shown, additional standard JTL stages may be provided at the positions of other stages scattered along the wrapper ladder. A logic circuit, e.g., a room-temperature semiconductor logic circuit (not shown), can individually evaluate the output of each sampler 202-212, or the total number of functional samplers (each represented by its pulse) can be used as a measure of the overall bias of the sensing system. As will be explained in more detail below, by introducing a gradation to the bias level detected by the bias level sensors 202-212 included in the RQL scan register 200, an output is generated that quantifies or digitizes the detected bias parameter. This quantification or digitization is performed by generating a number of output pulses in the output pulse stream proportional to the detected bias parameter, or by generating an output pulse that indicates the detected bias parameter through output timing.

[0023] Figure 2B shows an exemplary configuration 260 of RQL bias level sensors 262-272 arranged in parallel outputs. Configuration 260 is similar to the RQL scan register configuration 200 in Figure 2A, except that the outputs are provided in parallel rather than in series. The parallel output configuration 260 may also include suppression logic units (SLs) 280-290 configured to prevent assertions of multiple output pulses from propagating from each output if the associated sampler is in a state where it spontaneously inverts due to a manufacturing defect or excessive bias. Each bias level sensor 262-272 can be located at a different location on the RQL IC 106 and can be tapped to one or more bias resonators 104 at different points along the resonator(s) 104 via a bias coupling transformer (not shown in Figure 2C). The advantage of the series output configuration in Figure 2A over the parallel output configuration in Figure 2B is that the configuration in Figure 2A can save I / O on the RQL IC 106 in some examples. In some examples, the parallel outputs OUTA to OUTZ in Figure 2B may be provided to built-in self-test (BIST) readable registers implemented on the RQL IC106 for storage and subsequent retrieval in either a serial or parallel manner.

[0024] Figure 2C shows an exemplary configuration 290 of bias level sensors (each labeled BLS) arranged as a ring oscillator. The number of bias levels in the ring oscillator can be arbitrarily large. The output of one bias level sensor serves as a sample signal input for the next bias level sensor in the ring. Each bias level sensor can be located at a different location on the RQL IC 106 and can be connected to one or more bias resonators 104 at different points along the resonator 104 via bias coupling transformers (not shown in Figure 2C). Although not shown in Figure 2C, the bias level sensors in the ring 290 may be interspersed with conventional JTLs on the ring to facilitate the propagation of SFQ pulses between bias level sensors in the ring.

[0025] In the ring configuration 290 of Figure 2C, an initial sampling assertion signal (SFQ pulse or reciprocal pulse pair) can be supplied on the input RINGIN. The sampling pulse or pulse pair can propagate indefinitely within the ring 290 as long as all bias level sensors are operating (as long as the provided bias point is within the operating range of all bias level sensors in the ring). If the bias parameter is adjusted so that the provided bias parameter is outside the operating range of any one bias level sensor in the ring, the entire ring "breaks," and the sampling signal no longer propagates within the ring, instead stopping at the first non-operating bias level sensor reached. The continuous operation of the ring can be confirmed through the output RINGOUT, which, in a fully operating ring state, generates an SFQ pulse stream (or stream of reciprocal pulse pairs) at a rate related to the ring size (one output pulse or pulse pair is generated for each cycle of the sample pulse in the ring), and stops outputting when the ring breaks due to bias parameter adjustment. As will be explained in more detail below, X AC Parameter, X DC Parameters, and X phase The parameters can be scanned (iteratively adjusted) during the optimization procedure. The minimum X required for the ring oscillator to continue functioning to generate an output in RINGOUT. AC The level provides the optimal bias for the operating RQL circuit 102. In some examples, two or more input sample pulses can be supplied to the operating ring at once, for example, by multiple time-separated pulses, resulting in an increased frequency of output pulses.

[0026] In each of the above examples of FIGS. 2A - 2C, the bias level sensor can be a JTL - based bias level sensor as described with respect to FIGS. 6, 8A, 9A, 10A, 11A, 12, 13, 16, and 18, a PML flip - flop - based bias level sensor as described with respect to FIG. 25, a pulse generator - based bias level sensor as described with respect to FIG. 25, or other types of bias level sensors suitable for placement in a serial configuration, parallel configuration, or ring output configuration. Different bias level sensors in the same placement may be configured to detect any or all of X AC X DC X phase or other bias parameters.

[0027] The combination of the operating margins of the RQL circuit can be described by a shmoo plot. For example, the AC operating margin and the DC operating margin can be described by a two - dimensional shmoo plot. Graph 300 of FIG. 3 shows a first exemplary shmoo plot 302 representing the nominal AC and DC bias level operating margins for the operating RQL circuit 102, and a second exemplary shmoo plot 304 representing the average of the AC and DC bias level operating margins 304 for the RQL bias level sensors (e.g., samplers 202 - 212). The operating margin 302 of the operating RQL circuit, when represented in the X DC X AC space, has a clearly defined corner 308 herein referred to as the lower limit or X ACmin where the amplitude of the AC clock is minimized in each margin shmoo plot 302. The lower limit (X ACmin ) of the sampler is a unique point within the X DC X AC space of the sampler's margin shmoo plot, so it is the X AC and X DCIt can be used to provide clear measurements of both. Within the center of the nominal margin schmoo plot 302 (e.g., the centroid or geometric center of the nominal margin schmoo plot 302), the X of the margin schmoo plot 302 DC , X AC There exists an optimal bias point 306 for the operating RQL circuit, which is a unique point in space. The samplers (e.g., samplers 202-212) have a mean lower limit (X) of the sampler margin schmoo plot 304, as shown in Figure 3. ACmin ) can be designed and positioned so that at the optimal bias point 306, it lies in the center of the nominal margin Schmoo plot of the operating RQL circuit 102.

[0028] One or more parameters of the bias signal (e.g., clock, DC bias) supplied to the operating RQL circuit 102 (e.g., via one of the input lines 112, 114, 124 in Figure 1), such as DC value or AC amplitude, can be adjusted until the output of the bias level sensor wrapper matches the desired, improved, or ideal bias conditions. For example, the AC amplitude and DC level parameters can be adjusted (as shown in Figure 4C) X AC X of the set of samples arranged in a linear, stepwise manner AC Only the proximal half of the sampler returns an output pulse, and (as shown in Figure 5C) X DC X in the center of the linearly stepped arrangement of the sampler DC When the sampler is configured to return an output pulse, the operating RQL circuit 102 can be said to be ideally biased with respect to the AC and DC parameters of the provided clock. Setting the lower limit point of the sampler's schmoo 304 near the optimal bias point 306 of the operating circuit's schmoo 302 is, for example, to supply the corresponding bias signal to be measured to the sampler's JTL from its self-inductance and / or DC mutual inductance (X, respectively). AC or X DCThis can be achieved by setting the sampler's schmoo 304 near the optimal bias point 306 of the operating circuit's schmoo 302. Alternatively, setting the lower limit point of the sampler's schmoo 304 near the optimal bias point 306 of the operating circuit's schmoo 302 can be achieved, as an example, by setting one or more AC mutual inductances to supply one or more AC bias signals to the sampler's JTL, or, as an example, by inserting self-inductance between the JTL and the transformer (tap). Optimization procedures, such as procedure 2800 shown in Figure 28, may be used, for example, to calibrate the bias signals to an ideal calibration or a calibration close to an ideal calibration. If the sampler is set so that its lower limits are near the optimal bias point 306, optimization procedure 2800 may be performed so that the adjusted parameters of the clock(s) and / or DC bias signals fall within the operating margin of the operating RQL circuit 102, meaning that the calibration of the bias signals can be performed while the operating RQL circuit continues to operate, even while the bias parameters are being adjusted, improved, or optimized.

[0029] Graph 400 in Figure 4A shows the operable RQL circuit 102 and AC bias level sensor (X AC Graph 302 and 404 show exemplary Schmoo plots of the operating margins of the nominal AC and DC bias levels for the sampler, respectively. Graph 400 shows eight X AC Includes a margin of 404 for the sampler, X AC The number of samplers may be fewer or more than eight in some examples. Graph 400, seen in conjunction with the one-dimensional time plots in Figures 4B-4D, is an exemplary X that can run without interruption the operation of the operating RQL circuit 102 having a nominal operating margin 302. AC The performance of the optimization method is demonstrated. The AC amplitude of the supplied bias signal can be changed by essentially shifting the bias point vertically up or down on graph 400 until the optimal AC bias point 4C is determined. ACThe sampler may have, for example, a bias transformer having a self-inductance of varying value to generate a variable offset in the AC response, and a nominal DC mutual inductance. AC The increased self-inductance between the sampler's JTL and the corresponding sampler tap of the bias line causes the operating RQL circuit 102 to invert as the clock amplitude increases. AC This can have the additional beneficial effect of preventing the sampler from spontaneously inverting. AC The sampler set may be configured such that the lower bounds of each margin Schmoo plot are centered around the bias point 306 which is initially considered or assumed to be optimal for the operation of the operating RQL circuit 102. As shown in Figure 4A, X AC The lower limit of the sampler's margin Schmoo plot is centered around the middle of the nominal margin Schmoo plot 302 of the operating RQL circuit.

[0030] Figures 4B to 4D show, for example, a bias level sensor wrapper like the one in Figure 2A, with its bias level sensors 202 to 212 as X AC Indicates whether the output pulse has been received or not, when a sampler is included. In the illustrated example, X AC The sampler uses X to plot those schmoo plots. DC -X AC They are arranged within the wrapper in a level order that shifts upward in space. DC -X AC The sampler with the lowest Schmoo plot in space is positioned near the proximal end of the bias level sensor wrapper, X DC -X AC The sampler with the highest Schmoo plot in space is located near the distal end of the bias level sensor wrapper. The dashed line patterns of the output pulses in Figures 4B-4D correspond to the same dashed line patterns of the margin Schmoo plot 404 in Figure 4A, and pulses with certain dashed line patterns in Figures 4B-4D correspond to X with the same dashed line pattern drawn in Figure 4A. ACThis is generated by the sampler. Therefore, Figures 4B to 4D show the wrapper output effect due to the change in the AC amplitude of the supplied bias signal as shown in Figure 4A. If the supplied AC bias is too low, AC bias point 4B will have most X AC The number of pulses that fall within the sampler's operating margin is too low. Therefore, as shown in Figure 4B, the number of returning output pulses is relatively small. For example, as illustrated in Figure 4B, X AC If the samplers are arranged sequentially (e.g., linearly) in a stepped manner, and the sampler configured to have the lowest AC operating margin is positioned closest to the input / output terminals of the wrapper shown in Figure 2A, the returning output pulses may be limited to the return of earlier pulses. In contrast, if the supplied AC bias is too high, the AC bias point 4D will be most X AC It is too high to fit within the sampler's operating margin. Therefore, as shown in Figure 4D, the number of returning output pulses is relatively large. For example, as shown in Figure 4B, X AC If the samplers are arranged linearly in a stepped pattern, and the sampler configured to have the highest AC operating margin is positioned furthest from the input / output terminals of the wrapper shown in Figure 2A, the returning output pulses may include not only the return of earlier pulses but also the return of some later pulses. The supplied AC bias 4C may be considered optimal, for example, when the number of returning output pulses is in the middle range, an example of which is shown in Figure 4C, and is about half X AC The sampler operates, returns an output pulse, and approximately half of X AC The sampler is not operating and therefore does not return an output pulse. Figures 4B to 4D show X AC The sampler has a lower limit of AC along the length of the RQL scan register wrapper as shown in Figure 2A. AC An example is shown where the distribution is in ascending order by dimension, but in other examples, the RQL scan register wrapper, as shown in Figure 2A, is X ACSamplers may be configured to be arranged in a known order, including descending order, or in any other order that is not specific, and this order may be appropriately considered when analyzing the output of the RQL scan register wrapper to determine an improved or optimal bias level. In other examples where the analysis of the wrapper output involves counting the number of samplers operating under a given bias condition, such as when the spread of sampler margins is achieved solely by process variation, the order is not important and does not need to be considered when analyzing the wrapper output to determine an improved or optimized bias level.

[0031] Graph 500 in Figure 5A shows the operable RQL circuit 102 and DC bias level sensor (X DC Graph 302 and 504 show exemplary Schmoo plots of the operating margins of the nominal AC and DC bias levels for the sampler. Graph 500 shows eight X DC Includes a margin of 504 for the sampler, but X DC The number of samplers may be fewer or more than eight in some examples. Graph 500, seen in conjunction with the one-dimensional time plots in Figures 5B-5D, is an exemplary X that can run without interruption the operation of the operating RQL circuit 102 having a nominal operating margin 302. DC The performance of the optimization method is demonstrated. The DC value of the supplied bias signal can be changed by essentially shifting the bias point horizontally left or right on graph 500 until the optimal DC bias point 5C is determined. DC A sampler, for example, measures the changing DC mutual inductance (M DC A bias transformer having a nominal AC mutual inductance may be provided. For example, a DC bias point with a nominal operating margin of 302 may have X when the ideal current in the DC bias line is 2.0mA. DC The DC mutual inductance of the sampler is determined by the mutual inductance with the DC bias line at each of the corresponding transformers (one or more) of the sampler, and X when the current of the DC bias line changes between 1.5mA and 2.5mA. DCThe sampler can be arranged in stages to be optimally biased. Such a change in DC mutual inductance is, for example, given X DC For a sampler, given X DC This can be provided by changing the distance over which a DC transformer in the bias tap of a sampler is coupled to the corresponding DC bias line, and thus making such coupling distances shorter or longer. X in the example shown in Figure 4A AC Similar to the sampler, X DC The samplers may be composed in such a group that the lower bounds of their margin Schmoo plots are initially considered or assumed to be optimal for the operation of the operating RQL circuit 102, centered around bias point 306. As shown in Figure 5A, X DC The lower limit of the sampler margin Schmoo plot is centered around the middle of the nominal margin Schmoo plot 302 of the operating RQL circuit.

[0032] Figures 5B to 5D show a bias level sensor wrapper like the one in Figure 2A, with its bias level sensors 202 to 212 as X DC This indicates whether the output pulse is received or not when a sampler is present. The dashed line patterns of the output pulses in Figures 5B to 5D correspond to the same dashed line patterns in the margin schmoo plot 504 in Figure 5A, and pulses with certain dashed line patterns in Figures 5B to 5D have the same margin as the X drawn with the same dashed line pattern in Figure 5A. DC This is generated by the sampler. Therefore, Figures 5B to 5D show the wrapper output effect due to changes in the DC value of the supplied bias signal, as shown in Figure 5A. Optimization of the bias signal DC value can be performed by setting the bias signal AC amplitude to its optimal level, or to a level slightly higher than that optimal level. If the supplied DC bias is too low, X DCIf the samplers are arranged sequentially (e.g., linearly) in a stepped manner, and the sampler configured to have the lowest DC operating margin is positioned closest to the input / output terminals of the wrapper shown in Figure 2A, then, as shown in Figure 5B, the returning output pulses are limited to the return of one or more earlier pulses. In contrast, if the supplied DC bias is too high (5D), the returning output pulses are only the last one or the last few in time, which is the one or several X pulses furthest from the input / output terminals of the wrapper shown in Figure 2A, as shown in Figure 5D. DC This indicates that only the sampler is operational. The supplied DC bias 5C can be said to be optimal when there are only one or a few output pulses in the middle in time, as shown in Figure 5C, which is one or a few middle X DC Only the sampler is operational, and therefore returns the output pulse, but other X DC The sampler will not be returned. Figures 5B to 5D show X DC The sampler's lower limit of AC is X along the length of the RQL scan register wrapper as shown in Figure 2A. DC An example is shown where the distribution is in ascending order by dimension, but in other examples, the RQL scan register wrapper, as shown in Figure 2A, is X DC Samplers may be configured to be arranged in a known order, including descending order, or in any other order that is not specific, and this order may be appropriately considered when analyzing the output of the RQL scan register wrapper to determine an improved or optimal bias level. In other examples where the analysis of the wrapper output involves counting the number of samplers operating under a given bias condition, such as when the spread of sampler margins is achieved solely by process variation, the order is not important and does not need to be considered when analyzing the wrapper output to determine an improved or optimized bias level.

[0033] In various examples, the wrapper is X AC Only the sampler, X DC It can be configured to include only a sampler, or a mixture of different types of samplers. In some examples, X ACor X DC The stepped setting of the margin offset can be reversed from the ascending order described above, such that high-margin samplers are positioned proximal to the wrapper ladder and low-margin samplers are positioned distal to the wrapper ladder, or the stepped setting can employ a pattern other than the ordered stepped setting, in which case there will be a change in the expected pulse output. The linearly ordered low-to-high stepped setting described above is provided only as an example for illustrative purposes. In either example, whether the sampler's position is distal or proximal to the input / output terminals of the bias level sensor wrapper is not a factor determining the importance of bias level adjustment / optimization of the corresponding output pulse; rather, it is the margin offset set on the sampler that determines the importance of bias level adjustment / optimization of the sampler's corresponding output pulse.

[0034] After the one-dimensional scan procedure shown in Figures 4B-4D, which changes only the applied AC bias, is performed to first find the improved or optimal applied AC bias level, the one-dimensional scan procedure shown in Figures 5B-5D, which changes only the applied DC bias, leads to a more accurate evaluation or calibration of the applied DC bias level. Similarly, after the one-dimensional scan procedure shown in Figures 5B-5D, which changes only the applied DC bias, is performed to first find the improved or optimal applied DC bias level, the one-dimensional scan procedure shown in Figures 4B-4D, which changes only the applied AC bias, leads to a more accurate evaluation or calibration of the applied AC bias level. Therefore, these two one-dimensional scan procedures are X AC and X DC Both can be repeatedly run to approach (home in) improved or optimal values. The RQL scan registers 200, 260, and 290 in Figures 2A and 2C are used as bias level sensors 202-212 (or 262-272 or BLS) to provide outputs indicating, for example, AC or DC bias levels. AC Sampler and X DC It may be used with either or both of the samplers. ACWhen used to measure, any of the scan registers 200, 260, 290 also generates a specific number of pulses when it reaches the optimal level. X DC When used to measure, the result output by any of the scan registers 200, 260, 290 is operatively biased along the scan register X DC to indicate the average position of the sampler. Each of the RQL scan registers 200, 260, 290 can provide a numerical result in some exemplary operating modes, or in other exemplary operating modes, the output can indicate the bias level in other ways. For example, the RQL scan registers 200, 260, 290 can enable inspection of the output of a single bias level sensor disposed within the scan register to find its improved or optimal bias point by varying the applied AC and DC biases. In some examples, this procedure can be performed individually for multiple or all of the bias level sensors disposed within the scan register. In some examples, this procedure can be performed for individual bias level sensors disposed at various locations across the chip, not necessarily all elements of a single scan register or any scan register. In such examples, the average value of the individually measured improved or optimal applied AC and DC bias levels can be calculated and used as setpoints for the bias source.

[0035] X DC -X AC Different methods can be used to scan the space to find improved or optimal AC and DC applied bias levels. The first exemplary scan method samples at all X DC -X AC points within a range to X DC -X ACThis may include creating a complete two-dimensional map of the space. A second exemplary scanning method may include limiting the scan to the discovered boundaries of the working area, essentially "walking" in and out around the margin schmoo plot in a zigzag manner to determine the boundaries or surrounding contours. This second exemplary scanning method is a complete X of the first exemplary scanning method. DC -X AC It can have time-efficiency advantages over spatial sampling. A third exemplary scanning method is X DC -X AC This may include exploring space using spiral or conical scanning (traversing). A fourth exemplary scanning method may implement a successive approximation method, such as those used in analog-to-digital converters (ADCs). A fifth exemplary scanning method may implement a delta-sigma algorithm. Other exemplary scanning methods may implement variations or combinations of the above methods to approach improved or optimal applied AC and / or DC bias levels. In any of these examples, the selected scanning method can discover and stabilize the bias level using a closed loop, regardless of the type of scan(s) used and the on-chip configuration or arrangement of the bias level sensor used in the scanning method.

[0036] Samplers such as bias level sensors 202-212 in FIG. 2A can have any of a number of different forms. In some examples, the sampler consists of one or more JTLs or logic gates configured in series with each other, for example as a shift register, and at least one of the JTLs or logic gates in the shift register is specially configured to be more sensitive to bias in a different way than other JTLs or logic gates in the operational RQL circuit 102. FIG. 6 shows an exemplary sampler stage 600 having a sampler JTL 602 coupled to a sampler bias tap 604 configured for use in a bias level sensor such as any of the bias level sensors 202-212 in FIG. 2A. The SFQ-based sample signal provided at the sampler JTL input terminal ai can be transmitted (i.e., propagated) to the sampler JTL output terminal qo when the sampler JTL 602 is operable. The operability of the sampler JTL 602 depends at least on the sampler JTL 602 being biased within its operating margin. The bias is supplied to the sampler JTL 602 via a bias line 606 including bias lines 614, 616, 618 in the illustrated example. The sampler JTL 602 is inductively coupled to the bias line 606 via a sampler tap 604. In the example shown in FIG. 6, the sampler tap 604 includes a DC coupling transformer 608 for inductively coupling the sampler JTL 602 to the DC bias line 614, an I clock coupling transformer 610 for inductively coupling the sampler JTL 602 to the I clock bias line 616, and a Q clock coupling transformer 612 for inductively coupling the sampler JTL 602 to the Q clock bias line 618. The following table shows the relationship between the normalized mutual inductance and the tap phase of the sampler tap 204, and how changing the normalized AC mutual inductance M I , M Q can provide different clock phase biases to the sampler JTL 602. The normalized M DC can vary (from 1) with respect to the X DC sampler.

[0037]

Table 1

[0038] In contrast to the JTL or gate seen in the operating RQL circuit 102, the sampler JTL 602 is supplied from the sampler bias tap 604 via a larger self-inductance, which in some examples may be provided by increasing the bias inductor L2, or in other examples, as shown in Figure 6, an AC offset inductor L between the sampler JTL 602 and the tap 604. offsetAC An equivalent can be provided by including the following: In this latter example, the AC offset inductor L offsetAC The sampler JTL602, formed to exclude the sampler JTL, may otherwise be identical to the standard bias JTL used in the operating RQL circuit 102. Compared to the JTL found in the operating RQL circuit 102, the DC bias transformer 608 of the bias tap 604 has a greater or smaller mutual inductance M than the sampler JTL602 coupled to the DC bias line 614 in some examples. DC It may be configured to have: Increase the bias inductor L2 to provide greater self-inductance of the sampler stage 600, or increase the AC offset inductor L offsetAC By including this, the margin schmoo plot is X relative to the nominal margin of 302. DC -X AC This can provide an offset that is shifted vertically upward in space, as shown in Figure 4A. In some examples, the AC offset inductor L offsetAC By omitting the bias inductor L2 and making it smaller than usual (smaller than the JTL in the operating RQL circuit 102), the operating margin Schmoo plot of the bias level sensor is substantially reduced from the nominal operating margin 302 (X AC A reverse offset (not shown) that is shifted downwards (in dimensions) can be achieved. Bias inductor L2, and if present, AC offset inductor L offsetAC This can be provided, for example, by a guidance network.

[0039] In an exemplary bias level sensor with a reduced AC response, the AC offset inductor L in the sampler stage 600 is offsetAC This could be, for example, about 1.5 times the self-inductance of the sampler tap 604. AC offset inductor L offsetAC This self-inductance value corresponds to the bottom corner of the Schmoo plot of the corresponding sampler, and the X of the Schmoo plot 302 of the operating RQL circuit 102. AC It can have the effect of being placed approximately midway between dimensions. As an example, the AC offset inductor L in sampler stage 600 offsetAC This can provide a self-inductance of approximately 1.5 times that of the sampler tap 604, which can be set to approximately 29.25 pH, or, for example, approximately 19.3 pH. An instance of a bias level sensor having a sampler stage 600 is such that the bias level sensor is X AC In an example implemented as bias level sensors 202-212 in the context of the wrapper shown in Figure 2A, to function for relatively low values, the bias level sensors may respond to high AC bias levels by outputting a steady stream of RQL coded logic "1" (a positive SFQ pulse followed by a negative SFQ pulse) that inverts with each AC clock cycle. The corresponding suppression logic units 240-250 prevent this steady stream of RQL coded logic "1" by generating a stream of RQL coded logic "0" (no SFQ pulse) in response. The amplitude parameter of the AC bias can be calibrated using the detection of the lower limit of the margin Schmoo plot of the bias level sensors to stabilize the RQL clock in the operating RQL system, as described above with respect to Figures 4A-4D.

[0040] Margin Schmoo plot is higher X AC In an example bias level sensor where the value is shifted, the AC offset inductor L in the sampler stage 600 of the bias level sensor is shown. offsetACThis can be, for example, within a range of approximately 0.5 to 10 times the nominal tap self-inductance value, for example, the tap self-inductance value of the JTL or gate used in the operating RQL circuit 102. For example, the AC offset inductor L in the sampler stage 600 of the bias level sensor. offsetAC This can be made approximately 1.5 times the size of the tap self-inductance of the JTL and gate used in the operating RQL circuit 102. For example, if the nominal self-inductance value of the bias tap provided to the JTL or gate used in the operating RQL circuit 102 is approximately 19.3 pH, then the AC offset inductor L in the sampler stage 600 of the bias level sensor in Figure 6 can be made offsetAC The inductance value can be approximately 9.65 pH to approximately 193 pH, for example, approximately 40 pH to approximately 50 pH, for example, approximately 29.0 pH. A bias level sensor including an instance of sampler stage 600, where the bias level sensor is X AC In an example implemented as bias level sensors 202-212 in the context of the wrapper shown in Figure 2A, to function for relatively high values, the bias level sensors may respond to low AC bias levels by outputting a continuous stream of RQL coded logic "1" (a positive SFQ pulse followed by a negative SFQ pulse) that inverts with each AC clock cycle. The corresponding suppression logic units 240-250 prevent this continuous stream of RQL coded logic "1" by generating a stream of RQL coded logic "0" (no SFQ pulse) in response. Thus, the upper edge of the bias level sensor margin schmoo plot can be detected without filling the output of the RQL shift register wrapper with a continuous stream of "1". While detecting the upper edge of the bias level sensor margin schmoo plot may not be necessary to calibrate the AC bias amplitude parameter in an operating RQL system, in some examples it may be used as a diagnostic tool.

[0041] Figure 6 provides an example in which the JTL602 is used as a sample signal transmitting device. Although not shown, other exemplary sampler stages may be similar to the sampler stage 600 in Figure 6, but have an RQL gate as the sample signal transmitting device instead of the JTL602 sampler. The RQL gate provides a desired mutual inductance M to the AC bias line to provide the desired clock phase. Q M I And the desired X DC The RQL gate is biased by a modified bias of a sampler tap, such as the sampler tap 604, which has mutual inductance with respect to the DC bias line to provide offset. In some examples, the Schmoo plot (operating region) is higher X AC To raise it to the level of L in Figure 6, offsetAC It can also be equipped with an AC offset inductor like the one shown. The RQL gate, like the sampler JTL602, operates within its modified operating margin and fails outside of it (either producing an unexpected output or no output at all).

[0042] Figure 7 shows an exemplary suppression logic unit 700 that may be used to implement any instance of the suppression logic units 240-250 in Figure 2A. The suppression logic unit 700 includes a first superconducting path to the non-inverting input of the RQL A-NOT-B gate 704 (a two-input AND gate with a single inverting input) and a second path through several (e.g., four) JTLs 702 to generate a one-cycle delay to the inverting input of the A-NOT-B gate. If the bias to the sampler is too high, the sampler may generate a "spin" (generating a continuous stream of logic "1" outputs) which can disable the RQL scan register wrapper in Figure 2A. The suppression logic unit 700 prevents such spins (repeated triggers). The A-NOT-B gate 704 allows the first logic "1" from the sampler to pass through, but does not allow subsequent "1s" from the sampler to pass through, which would generate a stream of reciprocal SFQ pulses due to defects or excessive bias. In some cases, the suppression logic unit 700 can be omitted. Excessive AC bias amplitude is lowered to the lower limit (X ACmin X is higher than standard AC The standard logic in the read register spins approximately 2 dB earlier than the sampler, once it's pulled up to level. Furthermore, the suppression logic circuit itself may have a defect that causes it to start spinning, for example, due to the use of the RQLA-NOT-B gate 704, which has a narrow operating margin.

[0043] In some examples, a bias level sensor can be provided by using multiple instances of sampler stage 600 arranged in series as a shift register. Since a single JTL receives a substantial portion of its operating flux from the cell driving the JTL and the cell driven by the JTL, it may be necessary to arrange several sensing JTL600s (each with a similarly shifted bias margin) in series before the true effect of the bias shift appears at the output of the shift register that constitutes the bias level sensor. As an example, four or more sensing JTLs in series may be sufficient so that the sensing elements operate independently of the JTLs before and after them.

[0044] Figure 8 shows an exemplary shift register 800 configured as a bias level sensor, including four instances 804, 806, 808, and 810 of the exemplary sampler stage 600 in Figure 6. The shift register 800 may further include an input stage 802 and an output stage 812, each of which may be implemented as one or more JTLs and / or logic gates with standard biases (e.g., without modifications to the self-inductance and / or mutual inductance of the sampler stage 600 in Figure 6). Figure 9 shows an exemplary shift register 900, including three instances 904, 906, and 908 of the exemplary sampler stage 600 in Figure 6. The shift register 900 may further include an input stage 902 and an output stage 912, each of which may be implemented as one or more JTLs and / or logic gates with standard biases (e.g., without modifications to the self-inductance and / or mutual inductance of the sampler stage 600 in Figure 6). Figure 10 shows an exemplary shift register 1000, which includes one instance 1004 of the exemplary sampler stage 600 of Figure 6. The shift register 1000 may further include an input stage 1002 and an output stage 1012, each of which may be implemented as one or more JTLs and / or logic gates with standard biases (e.g., without modifications to the self-inductance and / or mutual inductance of the sampler stage 600 of Figure 6). Figure 11 shows an exemplary shift register 1100, which includes one instance 1104 of the exemplary sampler stage 600 of Figure 6. The shift register 1100 may further include an input stage 1102, which may be implemented as one or more JTLs and / or logic gates with standard biases (e.g., without modifications to the self-inductance and / or mutual inductance of the sampler stage 600 of Figure 6). For example, any of the shift registers 800, 900, 1000, or 1100 may be implemented as any of the bias level sensors 202, 204, 206, 208, 210, or 212 in Figure 2A, any of the bias level sensors 262, 264, 266, 268, 270, or 272 in Figure 2B, or any of the bias level sensors BLS in Figure 2C.

[0045] Figure 12 shows an exemplary specific phase bias level sensor 1200 for the Q clock. Thus, the specific phase Q sampler 1200 in Figure 12 provides a sampler that responds to variations in the amplitude of the Q clock but not to variations in the amplitude of the I clock. Figure 13 shows an exemplary specific phase bias level sampler 1300 for the I clock. Thus, the specific phase I sampler 1300 in Figure 13 provides a sampler that responds to variations in the amplitude of the I clock but not to variations in the amplitude of the Q clock. Thus, samplers 1200 and 1300 allow for independent adjustment of the AC amplitudes of the I and Q clocks. Figures 14 and 15 illustrate the signs of the sensing used in Figures 12, 13, 16 and 18.

[0046] In the specific phase Q sampler 1200 of Figure 12, four quad ("x4") sampler stages 1202, 1204, 1206, and 1208 are arranged in series with respect to each other, and each of the four quad sampler stages 1202, 1204, 1206, and 1208 is biased by an RQL clock signal of a different phase. The first quad sampler stage 1202 has a configuration of four JTL and / or logic gates with standard bias, without the self-inductance and / or mutual inductance correction of the sampler stage 600 of Figure 6. An extension of such a standard bias quad sampler stage is shown as the standard bias JTL and / or series gate 1400 in Figure 14. The first quad sampler stage 1202 is biased by a 0° clock. The second quad sampler stage 1204 comprises a configuration of four JTL and / or logic gates with a modified AC bias having self-inductance and / or mutual inductance correction of the sampler stage 600 in Figure 6. An extension of such a modified bias quad sampler stage is shown as a modified bias JTL and / or series gate 1500 in Figure 15. The second quad sampler stage 1204 is biased by a 90° clock (a clock shifted by 90° relative to the AC waveform of a clock with an AC waveform of 0°). The third quad sampler stage 1206 is a quad standard bias sampler stage 1400 biased by a 180° clock. The fourth quad sampler stage 1208 is a quad standard bias sampler stage 1400 biased by a 270° clock. As described in Table 1 above, the 0° and 180° clocks may be supplied from the I clock resonator, and the 90° and 270° clocks may be supplied from the Q clock resonator. Sampler stages 1202, 1204, 1206, and 1208 are shown in exemplary configuration 1200 as quad sampler stages, each having four series JTLs and / or logic gates, although the number of JTLs and / or logic gates in each sampler stage may be greater or less in other examples. The number of JTLs and / or logic gates in each sampler stage may be determined as a design parameter.In one example (not shown), sampler stage 1204 has four or more series JTLs and / or logic gates to prevent the influence of current sharing from sampler stages 1202 and 1206, while sampler stages 1202, 1206, and 1208 consist of fewer than four series JTLs and / or logic gates.

[0047] In the specific phase I sampler 1300 shown in Figure 13, the four quad sampler stages 1302, 1304, 1306, and 1308 are arranged in series with respect to each other, and each of the four quad sampler stages 1302, 1304, 1306, and 1308 is biased by an RQL clock signal of a different phase. The first quad sampler stage 1302 is a quad standard bias sampler stage 1400 biased by a 0° clock. The second quad sampler stage configuration 1304 is a quad standard bias sampler stage 1400 biased by a 90° clock. The third quad sampler stage 1306 is a quad modified bias sampler stage 1500 biased by a 180° clock. The fourth quad sampler stage 1308 is a quad standard bias sampler stage 1400 biased by a 270° clock. Sampler stages 1302, 1304, 1306, and 1308 are shown in an exemplary configuration 1300 as quad sampler stages, each having four series JTLs and / or logic gates, although the number of JTLs and / or logic gates in each sampler stage can be greater or smaller in other examples. The number of JTLs and / or logic gates in each sampler stage can be determined as a design parameter. In one example (not shown), sampler stage 1306 has four or more series JTLs and / or logic gates to prevent the effects of current sharing from sampler stages 1304 and 1308, and sampler stages 1302, 1304, and 1308 each consist of fewer than four series JTLs and / or logic gates.

[0048] In the extended quad standard bias sampler stage 1400 shown in Figure 14, each individual component stage 1402, 1404, 1406, 1408 of each sampler stage 1202, 1206, 1208, 1302, 1304, 1308 has a standard bias tap self-inductance, i.e., the same bias tap self-inductance used to supply the JTL and gate in the operating RQL circuit 102 (e.g., AC offset inductance L offsetAC Includes JTLs or gates (without having a JTL). Each individual component stage 1402, 1404, 1406, 1408 JTL or gate is biased with an AC clock signal of the same phase ("phase°").

[0049] In the extended 1500 of the quad modified bias sampler stage shown in Figure 15, each individual component stage 1502, 1504, 1506, 1508 of each sampler stage 1204, 1306 is an AC offset inductor L inserted between the JTL or gate and its corresponding bias tap. offsetAC The JTL or gate includes an AC offset inductor L2 (or equivalently, an enlarged bias tap inductor L2) through which the bias is supplied, and the AC offset inductor L2 offsetAC This provides a bias self-inductance greater than the bias self-inductance in the JTL and gate in the operating RQL circuit 102. Therefore, each individual component stage 1502, 1504, 1506, 1508 provides a bias self-inductance greater than the bias self-inductance in the JTL or gate in the operating RQL circuit 102. DC -X AC It has a margin Schmoo plot that rises in space. The JTL or gate of each individual component stage 1502, 1504, 1506, 1508 is biased with an AC clock signal of the same phase ("phase°").

[0050] Because magnetic flux tends to be shared between the driven JTL or driven logic gate and the driving JTL or driving logic gate, if a single JTL or logic gate operates with a clock phase 90° behind the JTL or logic gate it drives and with a clock phase 90° ahead of the JTL or logic gate it drives, it may be impossible to obtain an accurate measurement of the amplitude of the clock of a specific phase biasing that JTL or logic gate. However, by using four or more individual component stages (e.g., sampler stages 1502, 1504, 1506, 1508, or 1402, 1404, 1406, 1408) biased with the clock signal of the phase to be sampled, magnetic flux sharing can be effectively limited to the first and last JTL or logic gate, leaving the remaining JTLs and / or logic gates largely unaffected by magnetic flux sharing. In this way, the phase to be detected can be accurately measured. In the specific phase samplers 1200 and 1300 shown in Figures 12 and 13, the series arrangement of individual component stages 1402, 1404, 1406, and 1408 is, for example, X AC AC offset inductor L exists to raise the lower limit. offsetAC Using a weakened bias tap, the individual component stages 1202, 1206, 1208, 1302, 1304, and 1308 are biased through a weakened bias tap, while the series arrangement of the individual component stages 1502, 1504, 1506, and 1506 has a standard bias tap to form a support infrastructure. The individual component stages 1502, 1504, 1506, and 1508 of the sensing sampler stage 1204 or 1306 respond independently to either the I or Q clock bias. When the I / Q phase angle is close to nominal 90°, the phase sensitivity of the JTL or gate of the weakened taps of I and Q has a slope in the opposite direction.

[0051] Figure 16 shows an exemplary specific I-clock (Q-clock independent) bias level sensor 1600. The standard bias quad sampler stages 1602, 1606, and 1610 are the same as those extended in Figure 14, and the modified bias quad sampler stages 1604 and 1608 are the same as those extended in Figure 15. Thus, the exemplary sampler 1600 includes 20 JTLs and / or gates in series with each other. In the exemplary specific I-clock (Q-clock independent) bias level sensor 1600, the X of the sensing sampler stages (sensing JTLs and / or gates in the quad configuration 1604, 1608) is provided with 0° and 180° clocks. AC The operating margin is, for example, 1.5 times the nominal tap self-inductance (e.g., 1.5 × 19.3 pH) of the AC offset inductor L offsetAC By inserting, X DC -X AC It is shifted upward in space. Only in these sensing JTLs or gates is the AC amplitude of the I clock changed during the margin sweep optimization procedure that determines the optimal AC bias level for the I clock signal. In contrast, in sampler stages 1602, 1606, and 1610, the AC offset inductance L offsetAC is equal to 0 (AC offset inductor L offsetAC (Therefore, X does not exist) AC The margin is the X of the JTL and gate in the operating circuit 102. AC It is the same as the margin. The amplitude of the Q clock supplied to the quad sampler stages 1602, 1606, and 1610 remains fixed during the margin sweep optimization procedure (while sweeping the AC amplitude of the I clock supplied to the sampling JTL or gate in the quad sampler stages 1604 and 1608).

[0052] The graph in Figure 17 shows exemplary AC and DC bias margin plots for the specific I-clock (Q-clock independent) bias level sensor 1600 in Figure 16. Various X values ​​for JTL operating at the Q clock.AC Applying bias levels (nominal, 1 dB lower than nominal, 2 dB lower than nominal) can be observed as different plot curves in Figure 17, showing the effect on the margin Schmoo plot of a particular I sampler 1600. The lower limit 1702 of the margin Schmoo plot of the I sampler 1600 remains constant with respect to the variation in Q bias (unaffected by the intensity of the clock signal applied to the Q wrapper), confirming that the I bias level can be measured independently of the variation in the Q bias level.

[0053] Figure 18 shows another exemplary specific I-clock (Q-clock independent) bias level sensor. The standard bias quad sampler stages 1802 and 1806 are similar to those extended in Figure 14, and the modified bias quad sampler stage 1804 is similar to those extended in Figure 15. In the exemplary specific I-clock (Q-clock independent) bias level sensor 1800, the margin schmoo plot of the sampler stage (sampler stage in quad configuration 1804) provided with a 180° clock shows, for example, an AC offset inductor L with a value of 1.5 times the nominal tap self-inductance (e.g., 1.5 × 19.3 pH). offsetAC By inserting, X DC -X AC It is shifted upward in space. AC offset inductors are not used in the standard bias sampler stages 1802 and 1806 (as are the JTL and gate in the operating circuit 102). Sampler 1800 achieves a structural simplification of sampler 1600 without incurring performance loss. Sampler 1800 has a margin schmoo plot similar to that of sampler 1600 shown in Figure 17. In contrast to sampler 1600, sampler 1800 has an X AC To define the lower limit of 1702, only clocks with a 180° phase are used, and no clocks with a 0° phase are used. The lower limit of 1702 in the margin Schmoo plot of the I sampler 1800 remains constant with respect to the variation in the Q bias, confirming that the I bias level can be measured independently of the variation in the Q bias level.

[0054] A challenge with the RQL circuit is that, at the level of the RQL IC 106 in a cooled space, the I and Q clock signals 112,114, which are generated to be 90° apart and orthogonal when measured at the signal generator 110 in a warm space, may not be 90° apart from each other due to components in the clock resonator network 104 that introduce undesirable phase shifts. The offset from 90° in the phase difference between the I and Q clock signals at the level of the RQL IC 106 can cause operational problems in the operating RQL circuit 102, including a reduction in the operating margin. The circuit described herein can indirectly provide a measurement of phase error by effectively converting phase variations into amplitude variations, thereby measuring the effect of different clock phase differences on the operation of the sampler.

[0055] In addition to being highly sensitive to the I and Q clock amplitudes, the specific phase samplers 1200, 1300, 1600, and 1800 in Figures 12, 13, 16, and 18 are also highly sensitive to the phase difference between the I clock and the Q clock. When the phase difference between the I clock and the Q clock in the RQL IC 106 is 90°, the minimum X of the I and Q specific phase samplers AC They are equal. Therefore, the I and Q specific phase samplers 1200, 1300, 1600, and 1800 can be used to determine the optimal phase difference between the I clock and the Q clock, such as that generated in source 110, which is necessary to obtain exactly 90° of phase difference between the I clock and the Q clock in the RQL IC 106. The graph in Figure 19 shows the deviation of the Q clock phase from 90° (X at the lower limit of the margin schmoo plot for specific I and specific Q samplers). AC The following shows an exemplary minimum operating AC bias for specific I clock and specific Q clock bias level sensors as a function of ). For the sampler used to generate the graph in Figure 19, the AC offset inductance L of the I and Q sensing JTL or gate is shown. offsetACThis is 1.5 times the nominal tap self-inductance (the tap self-inductance used in the JTL or gate in the operating RQL circuit 102). The phase difference between the I clock and the Q clock varies by ±45° around the nominal value of 90°. The horizontal axis of the graph in Figure 19 is the deviation of the inter-clock phase difference from 90°. ACmin This is equal at 1902 for both I and Q detection JTL or gate when the I / Q phase difference is 90°.

[0056] Figure 20 is X as used herein. phase A 45° shift register 2000 is shown, which can be used as a phase sampler, also known as a sampler, and has JTL or logic gates supplied with a clock at 45°, 135°, 225°, and 315°. phase A sampler can indirectly detect the phase difference between two AC clocks (for example, between the I clock and the Q clock). In the phase sampler 2000 of Figure 20, four hex sampler stages 2002, 2004, 2006, and 2008 are arranged in series with each other, and each of the four hex sampler stages 2002, 2004, 2006, and 2008 is biased by a clock signal of a different phase, which can be generated, for example, as a combination of other clock signals (for example, as shown in Table 1 above). Figure 21 shows the sign extension of the hex sampler stages used for each of the hex sampler stages 2002, 2004, 2006, and 2008 in Figure 20. The first hex sampler stage 2002 is biased by a 45° clock. The second hex sampler stage 2004 is biased by a 135° clock. The third hex sampler stage 2006 is biased by a 225° clock. The fourth hex sampler stage 2008 is biased by a 315° clock. Combined clock waveforms providing 45°, 135°, 225°, or 315° phase clocks can be provided by transformer coupling to both the I (0° or 180°) and Q (90° or 270°) clock resonators (as shown in Table 1 above). X in Figure 20 phaseUsing sampler 2000 to directly measure the phase error between the I clock signal and the Q clock signal may first involve equalizing the amplitudes of the I clock signal and the Q clock signal using separate sensors (e.g., an I-independent clock amplitude sensor such as the specific phase I sampler 1300 in Figure 13, and a Q-independent clock amplitude sensor such as the specific phase Q sampler 1200 in Figure 12).

[0057] In the extensions 2100 of each of the hex sampler stages 2002, 2004, 2006, and 2008 in Figure 21, each individual component stage 2102, 2104, 2106, 2108, 2110, and 2112 of each sampler stage 2002, 2004, 2006, and 2008 has an AC offset inductor L inserted between the JTL or gate and its corresponding bias tap. offsetAC The JTL or gate includes an AC offset inductor L2 (or equivalently, an enlarged bias tap inductor L2) through which the bias is supplied, and the AC offset inductor L2 offsetAC This provides a bias self-inductance greater than that of the JTL and gate in the operating RQL circuit 102. Therefore, each sampler stage 2102, 2104, 2106, 2108, 2110, 2112 provides a bias self-inductance greater than that of the JTL or gate in the operating RQL circuit 102. DC -X ACIt has a raised margin Schmoo plot in space. The JTLs or gates of each sampler stage 2102, 2104, 2106, 2108, 2110, 2112 are biased with an AC clock signal of the same phase ("phase °"). As described above, linking several sampler stages that are all biased with the same AC clock phase reduces the effect of shared current (or, alternatively, magnetic flux) between adjacent JTLs biased with clock signals of different clock phases. The specific number of sensing JTLs required to provide this insensitivity depends on the details of the JTLs and / or gates and their individual bias taps. In some examples, linking between four sampler stages and six sampler stages may be sufficient to provide the desired reduction in magnetic flux sharing. Figure 20 shows an example of a phase sampler 2000 having six identical clock phase driven sampler stages for each set 2002, 2004, 2006, 2008, i.e., each sampler stage 2002, 2004, 2006, 2008 contains a set of six identical clock phase driven sampler stages directly coupled in series with each other. However, other examples may have more or fewer identical clock phase driven sampler stages directly coupled in series with each other, for example, four, five, or seven identical clock phase driven JTLs or gates directly coupled in series with each other in each set, or various numbers of identical clock phase driven JTLs or gates directly coupled in series with each other in different sets.

[0058] min x ACThe clock amplitude, i.e., the amplitude of the AC magnetic flux supplied by the transformers of the combined 45° and 135° clocks, is plotted in Figure 22 according to the phase error (phase difference between the I clock and the Q clock). The sampler stage corresponds to these differences in clock amplitude. Therefore, the phase error can be calibrated based on information about the operating margin observed in the sampler stage while varying the I / Q phase. In the 45° shift register 2000 in Figure 20, as the inter-clock phase difference (phase error) increases relative to 90°, the clock amplitudes of the 45° and 225° transducers decrease, and the clock amplitudes of the 135° and 315° transducers increase. The clock amplitude versus phase error graph in Figure 22 illustrates this relationship for the exemplary phase sampler 2000 in Figure 20. The AC amplitude graph of the minimum operating bias signal in Figure 23 shows how this characteristic is applied to the phase-sensitive X phase The configuration of the phase sampler 2000 in Figure 20 illustrates how the sampler is formed. As shown in Figure 23, the lower limit (X) of the operating margin Schmoo plot of the shift register consisting of 45°, 135°, 225°, and 315° sampler stages is shown. ACmin ) is the minimum X when the phase difference (phase error) between the I clock and Q clock measured on the RQL IC106 is 90°. AC It is located at level 2302. Figure 20 shows an example with six sampler stages, each with specific phase sampler stages 2002, 2004, 2006, and 2008, but X phase Other exemplary shift registers configured as samplers may have more or fewer sampler stages, each configuration 2102, 2104, 2106, and 2108. A method 3000 for calibrating the phase of a clock signal using a phase-sensitive sampler, such as the phase sampler 2000 shown in Figure 20, is shown in Figure 30 and described in more detail below.

[0059] Figure 24 shows a typical portion of a phase-mode logic (PML) bias level sensing configuration 2400 that can sense and read out the bias amplitude using flip-flops (e.g., flip-flops 2402, 2404, 2406) and phase-mode shift registers (e.g., shift registers 2408, 2410, 2412, 2414, 2416, 2418, 2420, 2422, 2424). Thus, the PML bias level sensing configuration 2400 in Figure 24 can provide similar functionality to the ladder wrapper configuration in Figure 2A, and the PML bias level sensing configuration 2400 can be individually tested for their operating range under variable RQL bias conditions and can be placed in multiple locations on the RQL IC 106, but provides sensors with a different structure and usage method than the configuration in Figure 2A. Testing and adjusting the bias level using the configuration 2400 in Figure 24 involves changing the AC level in the resonator during the test, which in different examples is done with an I-resonator (as shown) or a Q-resonator (not shown). Similar to the RQL scan register or JTL testbed in Figure 2A, multiple sensors are activated and their responses are read out using a shift register circuit structure.

[0060] Structure 2400 in Figure 24 forms a shift register, and each time a logic clock assertion signal (provided, for example, as a reciprocal pair of SFQ pulses, or in some cases, as the first positive SFQ pulse of such a pulse pair) travels through the logic clock path 2426 (from right to left in the orientation of Figure 24) and is provided to the clocking input of a D flip-flop (e.g., D flip-flops 2402, 2404, 2406), the pattern signal provided on the data path 2428 travels through the shift register 2400 by only one shift register element (from left to right in the orientation of Figure 24). A single element of the shift register 2400 is enclosed by a dashed box 2430, which has one D flip-flop 2416 and JTL-based shift registers 2410, 2416, 2422. Register 2400 can contain any number of elements such as elements 2430 arranged in series with each other, and each element is located on the RQL IC106 so as to connect to the clock resonator in that part of IC106. Thus, each element observes a different physical connection (tap) 120 to the AC clock network 104 within the RQL IC106. In Figure 24, each small triangle represents a buffer, for example, a JTL-based buffer. The flip-flops of the shift register 2400 (e.g., flip-flops 2402, 2404, and 2406) may be implemented as, for example, PML flip-flops, examples of which are described in U.S. Patent No. 10,615,783, titled “RQL D Flip-Flops”, and U.S. Patent No. 10,756,712, titled “RQL Phase-Mode Flip-Flop”, both of which are incorporated herein by reference. The number (degrees) above each flip-flop or buffer represents the phase of the clock supplied to the flip-flop or buffer below it. Clocks of different phases may be supplied by connecting different clock resonators 104 on the RQL IC 106 via different transformers, or, optionally, by connecting different combinations of transformers.

[0061] In some examples of the shift register 2400, the elements of the shift register may be designed and manufactured so that each has a different operating margin offset from one another, and these offsets may be configured linearly or in some other stepwise manner, as described above, in the same way that the bias level sensors 202-212 of the ladder wrapper configuration 200 in Figure 2A may be intentionally configured with stepwise operating margin offsets. In some examples, the bias transformer connecting the AC clock network to the D flip-flops in the shift register 2400 may be changed from its normal value so that all the D flip-flops in the shift register 2400 are underbiased or overbiased by the same amount, or underbiased or overbiased by different degrees of underbiasing or overbiasing. Therefore, it can be expected that a D flip-flop will fail with an AC bias that varies at a higher AC bias point (a higher AC bias point) than the AC amplitude at which a JTL-based buffer will fail with the same amplitude variation of AC bias. (It will fail because the AC bias point is outside the AC operating margin of the D flip-flop.) Because D flip-flops are not as robust as JTLs with respect to their operating margins, even if a D flip-flop is not intentionally underbiased, it may fail at an AC bias point higher than the AC bias point at which a JTL-based buffer fails, for the same amplitude variation of AC bias.

[0062] The PML flip-flop-based bias sampler in the shift register configuration 2400 shown in Figure 24 responds to variations in the clock resonator, bias-coupled transformer, and all other circuit parameters. Therefore, the use of the PML flip-flop-based bias sampler in the shift register configuration 2400 shown in Figure 24 can help determine the required bias level for the operating RQL circuit 102, which can be expected to be affected by variations in all process parameters. Specifically, the PML flip-flop-based bias sampler is highly sensitive to the self-inductance of the bias-coupled transformer, the mutual inductance between the bias-coupled transformer and the corresponding clock resonator, the magnitude of the current in the clock line, the inductance of the coupling transformer, the inductance in the JTL and gate, and the critical current of the Josephson junction (JJ).

[0063] In Example 2400 illustrated in Figure 24, the Q clock resonator is driven at a nominal bias level to ensure that a logic clock signal is reliably supplied to all flip-flops in the shift register 2400 (e.g., flip-flops 2402, 2404, and 2406), while the I resonator is driven with a fluctuating AC amplitude to test whether the shift operation is successful over a range of different AC amplitudes. For example, the operating range of each flip-flop can be determined independently for each flip-flop by performing method 2900 shown in the flowchart of Figure 29. With the AC amplitudes of the Q and I clocks set to nominal values ​​(2902) and the logic clock operating, a bit pattern of test data can be shifted in to the data path 2428 (2904). The logic clock can be performed by inputting a continuous stream of reciprocal pulse pairs to the logic clock path 2426. Thus, the shift-in of the initial data (2904) is performed while driving the I resonator at the nominal AC bias amplitude level. After the test data bit pattern is shifted into the PML shift register 2400, and the logic clock is subsequently stopped (2906), the bias amplitude of the I-resonator AC may be modified to test AC bias amplitude levels greater than or less than the nominal level (2908). A single logic clock assertion (e.g., a single positive SFQ pulse or reciprocal pulse pair) may then be input to the logic clock path 2426 (2910). The AC bias amplitude of the I-resonator may then be returned to the nominal value (2912), the logic clock may be restarted, and the output data bit pattern may be shifted out onto the data path 2428 (2914). The output data bit pattern may be observed, for example, following the output of the data bit pattern via the input / output circuit of the RQL IC 106 (2916). Observation may be performed, for example, by conventional semiconductor circuitry (e.g., CMOS circuitry) outside the cooling space of the RQL IC 106.

[0064] If the output data bit pattern does not match the input data bit pattern, it can be determined that at least one of the elements 2430 of the PML shift register 2400 is outside the operating margin under the conditions of the changed bias amplitude of the I-resonator AC. More precisely, which element 2430 is outside the operating margin can be identified by a point in the output data bit pattern where the output data bit pattern no longer matches the input data bit pattern (e.g., by a single bit error found in the output data bit stream). In some examples, multiple shift errors in the data bit pattern (e.g., multiple single bit errors between the input data bit stream and the output data bit stream) can be used to identify multiple shift register elements operating outside their respective margins.

[0065] By observing the data output when one of the elements of shift register 2400 has failed (for example, due to the provided 2908 bias point being outside the operating margin of that element), and comparing the output data bit pattern with the input data bit pattern, for example, it may become clear at some point in the output bit data stream that bit failed to pass through shift register 2400 in the bit data stream. For example, if the input data bit pattern consists of alternating pairs of "0" and "1", the output data bit pattern may contain somewhere in its bit stream three "0"s followed by one "1" ("0001"), or three "1"s followed by one "0" ("1110"). The location of the extra bit can indicate the identification of the element of shift register 2400 that was outside its operating margin during the progress of a single clock. An example input data bit pattern may consist of a series of alternating pairs of logical "1"s and "0"s, triplets, etc., depending on the length of the PML shift register 2400, such as "0011001100110011" for a 16-bit shift register. Method 2900 or a part thereof may be repeated in some examples using bit pattern offsets, thereby ensuring that transitions reach different flip-flops in the shift register 2400 and providing complete data probing of the shift register 2400. For example, the bit patterns "0011001100110011" or "1100110011001100" may be capable of detecting only errors caused by odd-numbered elements in shift register 2400, while the bit patterns "1001100110011001" or "0110011001100110" may be capable of detecting only errors caused by even-numbered elements in shift register 2400. Other input data bit patterns can also be used.Conventional semiconductor circuits (e.g., CMOS circuits) located outside the cooling space of the RQL IC106 can perform a comparison between the input data bit pattern and the output data bit pattern, or otherwise detect anomalies in the output data bit pattern that indicate a flip-flop failure due to a variation in the bias parameter.

[0066] Referring further to Figure 29, after the output data bit pattern provided on the data path 2428 of the shift register 2400 in Figure 24 has been observed for its difference from the input data bit pattern (2916), it can be evaluated whether the AC bias amplitude parameter has been optimized (2918). For example, if a number of different AC bias amplitudes are supplied to the shift register 2400, data can be compiled showing which AC bias amplitude is furthest from the value that causes an error in the output data bit pattern, from which a conclusion can be drawn regarding which AC bias amplitude is optimal. As an example, an AC bias amplitude (e.g., the mean value) that lies between two extreme values ​​of the AC bias amplitude within the operating margin may be selected as the optimal AC bias amplitude. As another example, if the bias tap values ​​of the D flip-flops are set incrementally to supply different amounts of AC bias for each flip-flop, the output data bitstream can be analyzed to determine which D flip-flops failed to adjust the AC bias and which did not, and the optimal AC bias can be determined based on the operating margins of the flip-flops that were operating and those that failed during the test. If insufficient data is collected to draw conclusions about the optimality of the bias parameters, the test can be repeated by resetting the AC bias amplitude to its nominal value (2902), restarting the logic clock (2904), and shifting the same or a different input data bit pattern (2904), and repeating part of the test process 2902-2918. This part of the test process can be repeated as many times as necessary to be confident that the AC bias amplitude is optimized for the AC clock resonator under test (e.g., the I resonator in the example shown in Figure 24) (2920). In some cases, the AC bias amplitude is not optimized, but is improved from, for example, the starting value or nominal value.

[0067] The method in Figure 29 outlines AC bias adjustment or optimization, but similar methods may be used for DC bias adjustment or optimization, or for phase error adjustment or optimization. In DC bias adjustment or optimization, the DC bias value of the bias signal supplied to the D flip-flop may be changed, rather than the AC amplitude value (2908). In some examples, the coupling strength of the transformer to the DC bias line of the D flip-flop of the phase-mode shift register under test is set in steps, each having a different DC bias coupling strength, and multiple flip-flops are X relative to each other, as shown in Figure 5A. DC The goal is to show different operating margin schmoo plots that are shifted in dimensions. Phase error adjustment or optimization can change the phase difference between the I clock signal and the Q clock signal supplied to the D flip-flop, in addition to the AC amplitude value (2908), as shown in 2D X. AC -X phase A search can be performed, and each D flip-flop is biased by an AC bias signal, which is a mixture of the I clock signal and the Q clock signal. In some examples, the transformer coupling strength to the AC bias line of the D flip-flops of the phase-mode shift register under test is set in steps, and each D flip-flop has an AC bias coupling of different strengths to the clock signal of the mixed resonator, so that the flip-flops are X relative to each other, as shown in Figure 5A. AC This will show different behavioral margin schmoo plots that are shifted in dimensions.

[0068] Conventional RQL shift registers can proceed with at least four phases (e.g., 0°, 90°, 180°, 270°) in all paths, but the PML shift register 2400 is configured such that the logic clock path 2426 is coupled to the clock resonator 104 to receive only two phases (90° and 270° in the illustrated example) in the logic clock path trunks 2420, 2422, and 2424, and the data path 2428 is coupled to the clock resonator 104 to receive only the other two phases (0° and 180° in the illustrated example). Thus, the trunk of the logic clock path 2426 is powered by only one clock resonator (the Q resonator in the illustrated example), and the data path 2428 is powered by only the other clock resonator (the I resonator in the illustrated example). This configuration ensures that even if the data path 2428 is stressed and fails by changing the bias parameter outside the operating margin of the data path for one or more shift register elements, the logic clock path 2426 remains functional, and thus the logic clock signal reaches all flip-flops in the shift register 2400, including flip-flops that have become non-functional due to bias parameter adjustment. Thus, by phase assignment, the operation of the flip-flops is isolated to one AC clock resonator, and the logic clocks exciting the flip-flops are isolated to different AC clock resonators. The 0° buffers in branches 2414, 2416, and 2418 in the logic clock path can be considered as part of the corresponding flip-flop circuits 2406, 2404, and 2402 in the above description. In illustrated example 2400, the buffers driving the clock pins of individual flip-flops may need to be on the same clock phase as the flip-flops.

[0069] Buffers shown as dashed lines in Figure 24, such as buffers 2432 and 2434 in the logic clock path 2426 and buffer 2436 in the data path 2428, may have a different design from the buffers shown as solid lines in Figure 24. Each of the dashed buffers in Figure 24 may include an additional Josephson junction grounded at the input of the individual JTL, which allows for reliable operation with a 180° phase difference (phase delta) from the previous cell. Without this additional Josephson junction, it may become ambiguous whether the SFQ pulse waiting at the boundary propagates forward or backward when the AC bias signal supplied to the corresponding buffer rises.

[0070] Similar to the shift register 2400, but in another exemplary PML shift register not shown, a 90° AC clock phase can be added to all phase values ​​shown in Figure 24 to provide a bias level sensing configuration that tests the Q clock resonator instead of the I clock resonator. In such an example, the trunk of the logic clock path is driven by the I resonator, and the data path is driven by the Q resonator. In such an example, the “resonator under test” in method 2900 in Figure 29, and the resonator whose AC amplitude is changed as part of method 2900 (2908), becomes the Q resonator instead of the I resonator. In another exemplary modification of the PML shift register 2400, the JTL-based buffer in the logic clock path may be provided with an offset bias transformer as shown in Figure 6 and described above with respect to Figure 6. Such a modification can effectively shift the operating margin of the clock supply, which may allow sampling when the operating logic is close to the nominal AC bias.

[0071] Similar to the shift register 2400, but in other exemplary PML shift registers not shown, a 45° or 135° AC clock phase can be added to all the phase values ​​shown in Figure 24 to provide a bias level sensing configuration in which the trunks of the data path and logic clock path receive a bias signal which is a mixture of a 0° I clock and a 90° Q clock. For example, the data path may be driven by AC signals with 45° and 225° phases, and the trunk of the logic clock path may be driven by signals with 135° and 315° phases. In another example, the data path may be driven by AC signals with 135° and 315° phases, and the trunk of the logic clock path may be driven by signals with 45° and 225° phases. Such examples may be useful in determining the phase error between the I clock signal and the Q clock signal and improving or optimizing the phases of the I clock and Q clock to true quadrature phase. In another exemplary modification of the PML shift register 2400, the JTL-based buffer in the logic clock path may include the offset bias transformer shown in Figure 6 and described above with respect to Figure 6. Such a modification can effectively shift the operating margin of the clock supply, thereby potentially allowing samples to be obtained when the operating logic is close to the nominal AC bias.

[0072] Figure 25 shows an exemplary proximal portion of configuration 2500, in which pulse generators 2502, 2508 are connected to RQL gates (AND gates 2504, 2510 in the illustrated example) to form a bias level sensor (sampler). A portion of the wrapper for the pulse generator-based bias level sensor is shown in Figure 25, which is similar to the ladder configuration shown in Figure 2A and has a repeating circuit pattern of stages (e.g., the first two stages 2512, 2514) and rails (2516, 2518) between the proximal input / output terminal (shown at the bottom of Figure 25) and the distal terminal (not shown in Figure 25), with the stages positioned between the input rail 2516 and the output rail 2518 of the wrapper ladder. The rails 2516, 2518 may extend, for example, along the entire length of the clock resonator connected by the wrapper. As an example, the wrapper has approximately 2,000 stages, each stage having a pulse generator-based sampler that individually samples the clock resonator at different positions along the clock resonator. The JTL, represented as a triangle in Figure 25, provides a timing delay. The sample signal input 2506 provides the wrapper ladder with an SFQ pulse as a sample signal, which propagates along the input rail 2516 (upward in the orientation of Figure 25), branches and replicates along each stage, and either returns to output OUT along the output rail 2518 (downward in the orientation of Figure 25) or does not return, depending on whether the individual samplers embedded in the stages of the wrapper ladder are within the operating margin. Thus, in the wrapper shown in Figure 25, a single sample SFQ pulse provided at input 2506 results in a series of temporally separated output SFQ pulses at output OUT.

[0073] Each pulse generator in configuration 2500 (e.g., pulse generators 2502, 2508) comprises a Josephson junction having a first end grounded via an inductor and a second end inductively coupled to an AC bias transformer (e.g., via a coupling transformer). The second end substantially provides the output of the pulse generator. Each pulse generator outputs an SFQ pulse to its corresponding ladder stage for each cycle of the AC clock driving the pulse generator, provided that the pulse generator is driven within its operating range, for example, provided that the amplitude of the AC clock driving the pulse generator is within the AC operating margin of the pulse generator. To help reduce variations in the pulse generator's Josephson junction, the pulse generator's Josephson junction can be larger in size than the Josephson junction used in the JTL and gate of the operating RQL circuit 102, and therefore can have a larger critical current. The output of each pulse generator is gate-controlled by a sampled signal via the corresponding gate (e.g., gates 2504, 2510 in Figure 25). Therefore, each pulse generator operates continuously to repeatedly provide an SFQ output to its corresponding stage, as long as the provided AC bias is within the pulse generator's operating margin, but only SFQ outputs generated substantially simultaneously with the arrival of sample signal pulses on the same stage (e.g., within the same AC clock cycle or half-clock cycle) propagate down the output rail 2518 to output OUT.

[0074] The operating range of each pulse generator in the detection system of Figure 25 can be individually set, for example, by configuring each pulse generator to increase or decrease the coupling strength to one or more AC clock resonators and / or DC bias lines that provide (drive) bias to the pulse generator. For example, the X of the pulse generator-based sampler in the detection system of Figure 25 ACBy shifting (offsetting) the margin, the pulse generator can start and stop operating in accordance with the fluctuating level of the AC bias provided (the fluctuating amplitude of the driving AC clock), and the operating levels can be determined by the bias point fluctuations that enable detection, even while the operating RQL circuit 102 is able to remain within its operating margin.

[0075] X AC Margin shift can be implemented in some examples by increasing the critical current of the JJ in the pulse generator. Increasing the critical current of the JJ in the pulse generator in a pulse generator-based sampler results in X as shown in Figure 3. DC -X AC In the plot, this has the effect of shifting the margin Schmoo plot of the corresponding sampler upward and to the right, because a higher DC and AC bias amplitude than usual is required to invert the JJ of the pulse generator due to the increase in critical current. The critical current of JJ is when the AC and DC bias generated by the bias-coupled transformer of the pulse generator is within the margin Schmoo plot (operating region) of the operating JTL circuit 102. DC -X AC The bias point can be selected to be a threshold that triggers the pulse generator's JJ for each AC clock cycle. For example, the margin Schmoo plot (operating region) of the pulse generator-based sampler may be located within the margin Schmoo plot of the operating JTL circuit 102, so the pulse generator-based sampler can be driven to enter or leave the operating region that generates pulses by changing the bias delivered to both the pulse generator-based sampler and the operating RQL circuit 102, while the delivered bias remains within the operating region of the operating RQL circuit 102, so the operating RQL circuit 102 continues to function. Similar to the example in Figure 2A, the pulse generator-based sampler in Figure 25 has its X AC and / or X DCThe operating margin offset can be set in steps, and such steps can be, for example, a linear arrangement along the ladder from the lowest AC margin to the highest AC margin, or from the highest AC margin to the lowest AC margin, or any other arrangement that can be taken into consideration when evaluating the output. DC The stepwise setting in the pulse generator-based sampler in Figure 25 involves, for example, changing the length of the DC portion of the coupling transformer, so that the respective margin schmoo plots of the pulse generator-based sampler are as shown in Figure 5A. DC -X AC This can be provided by substantially shifting it left or right within space.

[0076] The pulse generator-based sampler in Figure 25 can be positioned on the RQL IC 106 to connect to the clock resonator 104 at various points along the resonator. Although not shown in Figure 25, the input sampled SFQ pulse may be supplied to input 2506 using an input transformer coupled to input 2506, similar to the input transformer 252 shown in Figure 2A, and the output SFQ pulse may be converted into a voltage pulse using an output amplifier coupled to output OUT, similar to the output amplifier 254 shown in Figure 2A.

[0077] The pulse generators in configuration 2500 (e.g., pulse generators 2502, 2508) are highly sensitive to manufacturing variations in the JJs that constitute them, as well as variations in the clock resonators and coupling transformers, and are relatively less sensitive to other circuit parameters compared to JTL or gate-based samplers with large self-inductance as described above with respect to Figures 6, 8A, 9A, 10A, 11A, 12, 13, 16, and 18. For example, the pulse generator-based sampler in Figure 25 is not particularly sensitive to variations in the circuit-side inductance of the ground plane in the RQL IC 106. Therefore, configuration 2500 is particularly well suited for evaluating the performance of clock resonators and coupling transformers, and is useful, for example, when evaluating the self-inductance of the coupling transformers, the mutual inductance between the coupling transformers and the clock resonators they are coupled to, and the magnitude of the current in the clock resonators.

[0078] The pulse generator in configuration 2500 may be configured to measure a specific I (Q-independent) or specific Q (I-independent) reading by coupling the sampler to a suitable clock bias resonator, as described above with respect to Figures 12, 13, 16, and 18 and listed in Table 1. The pulse generator in configuration 2500 may also be configured to measure the phase difference between the I clock and the Q clock (in some examples, with the AC bias amplitude first calibrated for both the I clock bias signal and the Q clock bias signal), and this measurement may be performed by driving multiple pairs of pulse generators in a single wrapper, or by driving multiple pulse generators in different wrappers with a mixed clock signal separated by 90°, for example, a first pulse generator (or a first pair in a first wrapper of a pulse generator-based bias level sensor) This is done by driving the first pulse generator (or the second set of pulse generators in the second wrapper of the pulse generator-based bias level sensor) with a 45° clock and driving the second pulse generator (or the second set of pulse generators in the second wrapper of the pulse generator-based bias level sensor) with a 135° clock, or by driving the first pulse generator (or the first set of pulse generators in the first wrapper of the pulse generator-based bias level sensor) with a 225° clock and driving the second pulse generator (or the second set of pulse generators in the second wrapper of the pulse generator-based bias level sensor) with a 315° clock. The outputs of the pulse generators driven at 45° and 135° (or pulse generators driven at 225° and 315°, etc.) are equal only if the phase difference between the two drive clocks is 90° and the AC amplitudes of the AC signals provided by the I clock resonator and the Q clock resonator are equal. Therefore, this mixed clock setup can be used to determine the true quadrature phase between the I clock signal and the Q clock signal, and can also be used to indicate or instruct adjustments to the I clock phase and the Q clock phase, or to the phase difference between the I clock phase and the Q clock phase, in order to improve or optimize the orthogonality with respect to the 90-degree phase difference between the I clock and the Q clock.As an example, using the process described with reference to Figure 30 in configuration 2500, the optimal phase difference between the I clock and the Q clock to drive the I clock and Q clock in a room temperature environment can be determined in order to achieve true quadrature phase (90° phase separation) between clocks in the operating RQL circuit 102 on the RQL IC 106 in a cooled space.

[0079] Figure 26A shows an exemplary configuration of samplers 2602-2610 arranged within a DC SQUID-based bias level sensor 2600. Samplers 2602-2610 can be based on JTL or RQL gates, as described above with respect to Figure 6, and may comprise one or more sampler stages in series with respect to Figures 15 and 21. Samplers 2602-2610 function as triggers for DC SQUIDs 2612-2620. Each sampler 2602-2610 has its parameter (X) such that the number of DC SQUIDs 2612-2620 activated in the stack when an input pulse is applied to the sample signal input on the left side of Figure 26A changes according to the bias level supplied to the samplers 2602-2610. AC or X DCOne of the following is set in steps. Therefore, the voltage level of the output pulse generated by the stack of DC SQUID 2612~2620 changes depending on the supplied bias level. Thus, configuration 2600 can be considered as a single bias level sensor having a voltage output that changes depending on the number of individual samplers 2602~2610 biased within the operating region when a sample signal pulse is supplied to the sample signal input. The output voltage may indicate the detected bias parameter (AC bias amplitude or DC bias value) set to be measured by sensor 2602, given that appropriate stepwise settings of the bias coupling strength of sensors 2600~2610 are provided, for example, as described above with respect to Figures 4A and 5A. Since sensor 2600 can measure the outputs of individual sensors 2602~2610 in parallel and simultaneously, sensor 2600 may have a higher output throughput than the configuration in Figures 2A~2C. The sensor 2600 generates an output voltage pulse each time an input SFQ pulse is applied to the sample signal input, which can occur once per AC clock cycle.

[0080] Each DC SQUID 2612-2620 in the sensor 2600's DC SQUID stack receives input from individual samplers 2602-2610 via individual transformer couplings to the DC SQUID. Each individual transformer coupling is shown in Figure 26A as a dashed line between each sampler 2602-2610 and the individual DC SQUID 2612-2620 that transformer-couples with the sampler. Each sampler may be, for example, a JTL. The JTL is a desired X from the nominal AC A separate AC offset inductor L provides both an offset (as shown in Figure 3) and a desired stepped setting (variation between samplers). offsetACThe size is adjusted. In the example in Figure 26A, the DC SQUID stack is shown as containing multiple stages (five samplers 2602-2610 and five corresponding DC SQUIDs 2612-2620), but in other examples, the stack may contain more or fewer stages (more or fewer samplers and corresponding DC SQUIDs), and more stages may provide finer resolution of the output voltage signal or enable the detection of multiple bias parameters. For example, some of the samplers 2602-2610 may be configured to detect the AC bias amplitude and others to detect the DC bias value, or some of the samplers 2602-2610 may be configured to detect the AC bias amplitude of one clock resonator, I or Q, or several combinations of clock signals, and others may be configured to detect the AC bias amplitude of different clock resonators or several different combinations of clock signals. In a different example, the structure of sensor 2600 in Figure 26A may have 5-10 stages.

[0081] The sample signal input may be provided to each of the samplers 2602-2610, for example, via a JTL binary vine tree (not shown), so that in some examples the sample signals arrive at each of the samplers 2602-2610 substantially simultaneously. Similar to the examples described above (e.g., the examples in Figures 2A and 25), the samplers use the variation in mutual inductance for individual AC resonators or DC bias lines measured by each sampler to X AC Shift, and / or X AC Step-by-step setting and / or X DC Step-by-step settings are possible. The DC bias current I is insufficient on its own to trigger any of the SQUID2612~2620. BIASOUT Since the current supplied between OUTP and OUTN biases the SQUID stack, the current supplied by the input sample pulses distributed to SQUIDs 2612-2620 via samplers 2602-2610 is sufficient to trigger individual SQUIDs. BIASOUTThe signal from the sensor 2600 can be supplied from outside the RQL IC 106 on which it is mounted, and the voltage signal between OUTP and OUTN becomes available on the pads of the RQL IC 106. Therefore, the signal from the sensor in Figure 26A can be used for direct measurement by, for example, an external test instrument, without requiring any logic to process or interpret its output.

[0082] In the example shown in Figure 26A, the five samplers 2602-2610 are represented by the value X shown in the box representing sampler 2602-2610. AC1 ~X ACN X is affected by the AC amplitude margin variation given by AC These are set in stages. For example, the resonant clock network can be fabricated on the RQL IC106 to operate under samplers 2602-2610, with different AC offset inductors L offsetAC By providing this to each sampler 2602-2610, power can be interconnected to individual samplers based on the I and Q bias signals required for the desired clock phase to be provided to the sampler. In Figure 26A, 100% X AC The value represents the sampler's rated bias level, X AC The variation in values ​​indicates a larger or smaller AC bias level coupled to the sampler. Figure 26A shows X values ​​of 75%, 87.5%, 100%, 112.5%, and 125%. AC The values ​​are shown as an example of a linear, stepped setting of a five-sampler configuration as shown in Figure 26A. During operation, when a sample signal input pulse is supplied to sensor 2600, the strength of the bias level supplied to all samplers 2602-2610 can be changed externally, and different bias strengths to each of samplers 2602-2610 result in a different number of SQUIDs 2612-2620 contributing to the potential difference between the output voltage terminals OUTP and OUTN, depending on how many samplers are operating under the provided bias conditions.

[0083] For example, sampler 2610 is an AC offset inductor L with an appropriate inductance value.offsetAC Due to being configured to be biased via X, 125% X AC Sampler 2610, which has a value, requires a higher AC bias level to transfer the input sampler pulse to its corresponding DC SQUID 2620, while sampler 2602 has a smaller AC offset inductor L offsetAC Due to being configured to be biased through X, 75% of X AC Sampler 2602 with a value requires a relatively low AC bias level to operate. In contrast, 75% X AC Sampler 2602, which has a value of 125% X AC Even if a sampler 2610 with a value cannot continue to operate (because the AC bias level falls below its operating range and is therefore outside its operating range), it can continue to operate with a higher bias current (because the higher supply bias current is within its operating range).

[0084] For example, in configuration 2600 of Figure 26A, if each SQUID 2612-2620 generates a potential difference of approximately 0.5mV when activated by the corresponding sampler 2602-2610 in operation, the voltage output between OUTP and OUTN is approximately 2.5mV when the supplied bias level is within the individual operating region of all samplers 2602-2610. This output voltage decreases when fewer samplers than all of samplers 2602-2610 are biased within their individual operating regions. For example, in the five-stage example in Figure 26A, the output voltage of configuration 2600 may be approximately 2mV when only four samplers 2602-2610 are operating depending on the supplied bias level, approximately 1.5mV when only three samplers 2602-2610 are operating depending on the supplied bias level, approximately 1mV when only two samplers 2602-2610 are operating depending on the supplied bias level, approximately 0.5mV when only one of the samplers 2602-2610 is operating depending on the supplied bias level, and approximately 0mV when none of the samplers 2602-2610 are operating depending on the supplied bias level. The AC bias amplitude can be considered calibrated if the amplitude is changed to obtain approximately three-fifths of the maximum output voltage pulse height. In the five-stage example in Figure 26A, the AC bias amplitude can be considered calibrated if samplers 2602 and 2604 are within their operating range and therefore supply the divided input sample signal to their corresponding SQUIDs 2612 and 2614, samplers 2608 and 2610 are outside their operating range and therefore do not supply the divided input sample signal to their corresponding SQUIDs 2618 and 2620, and sampler 2606 is just within its operating range and therefore supply the divided input sample signal to its corresponding SQUID 2616.

[0085] The RQL circuit 102 in Figure 1 shows an output bias current I at an appropriate current level. BIASOUTThe output amplifier may include a structure similar to that of the sensor in Figure 26A, which may be required to be biased by a current level that may vary due to variations in the circuit manufacturing process and / or system setup. Figure 26B shows, for example, the output bias current I BIASOUT The applied level of the output bias current I BIASOUT An output bias current I can detect how well it meets the requirements of the output amplifier to which the bias current is applied. BIASOUT An exemplary DC SQUID-based output amplifier 2650 configured as a level sensor is shown. Configuration 2650 in Figure 26B is similar to configuration 2600 in Figure 26A, but with the AC offset inductor L of the corresponding samplers 2602-2610. offsetAC Instead of setting the inductance values ​​in steps, the self-inductance of the standard bias samplers 2652~2660 is not different from each other (for example, AC offset inductor L offsetAC (There is no) Instead, the critical current Ic of the JJ of the corresponding DC SQUID2662~2670 is set stepwise to individual offsets from the nominal value. In the exemplary configuration 2650 shown in Figure 26B, the JJ of SQUID2666 is set to the nominal value (I C3 Although they have a critical current of 100%, other SQUIDs in the stack have a lower critical current (for example, SQUIDs 2662 and 2664 have a critical current of 100%). C1 =75% and I C2 (Having 87.5% JJ) or a higher critical current (e.g., SQUID2668 and 2670 have a critical current of 1 JJ each) C4 =112.5% ​​and I CN The JJ is manufactured to have a JJ of 125%. Similar to the example shown in Figure 26A, the example in Figure 26B can have more or fewer DC SQUIDs in its DC SQUID stack, and more stages provide finer output voltage signal resolution.

[0086] In Example 2650 in Figure 26B, the output bias current I is supplied between the output terminals OUTP and OUTN. BIASOUTThis can be changed to determine the optimal DC bias on the bias line of the output amplifier, i.e., the optimal bias current for SQUID2662, 2664, 2666, 2668, and 2670. For example, when a stack of five SQUIDs is used as shown in Figure 26B, with each sample SFQ pulse supplied to the sample signal input, the output bias current I of the output amplifier can be changed to obtain approximately 3 / 5 of the total output voltage pulse height. BIASOUT The output bias current I supplied to the output amplifier on the RQL IC106 may be changed. The exemplary configuration 2650 in Figure 26B does not separate the effects of the AC bias and DC bias, respectively, on the samplers 2652-2660 that trigger SQUIDs 2662-2670 or other JTLs in the circuit. The exemplary configuration 2650, for example, the output bias current I supplied to the output amplifier on the RQL IC106 BIASOUT It can be used to calibrate X AC and X DC The output bias current I of the output amplifier was initially independently adjusted, improved, or optimized. BIASOUT It can then be adjusted, improved, or optimized.

[0087] The output amplifier-based configurations 2600 and 2650 in Figures 26A and 26B instantaneously show the number of samplers operating in the configuration for each provided sample signal. Therefore, these configurations improve the output throughput of bias level sensing compared to RQL scan register configurations such as Figure 2A or Figure 25, ring oscillator configurations such as Figure 2C, or PML shift register configurations such as Figure 24. Each of these configurations may take longer than the output amplifier-based configurations to provide a complete output showing the detected bias parameter. In some examples (not shown), different amounts of time delay can be added to each branch of the output amplifier-based configurations 2600 and 2650 in Figures 26A and 26B to enable time-division multiplexing (for example, by adding a different number of additional standard bias JTLs to the samplers of each branch of the output amplifier-based configurations 2600 and 2650 in Figures 26A and 26B). For example, phase shifts may be added in 90° or 45° increments. In one example, each branch of the output amplifier structure 2600 or 2650 in Figures 26A and 26B has a time delay (e.g., from top to bottom) to assign phases such as 0°, 45°, 90°, 135°, and 180°. This exemplary configuration provides a time-based step function signal to the output, which increases by 0.5mV increments at each time step, or does not increase, depending on whether the SQUID of the corresponding stage of the output amplifier configuration has been induced to operate. In the example of Figure 26A, this depends on whether the corresponding JTL-based samplers 2602-2610 are within their operating range. The time-shifted output can then be used to determine which of the samplers 2602-2610 delivered a signal to the corresponding SQUIDs 2612-2620 and triggered the corresponding SQUIDs 2612-2620.

[0088] A series output ladder wrapper (RQL scan register) structure, as shown in Figure 2A, can also be used to calibrate the output bias current of an output amplifier by implementing its bias level sensors 202-212 as output amplifier emulators. A JTL-based bias level sensor configured as an output amplifier emulator may have the following characteristic features: Firstly, each bias level sensor configured as an output amplifier emulator may have a corresponding JTL(s) AC bias transformer(s)(s)(s) coupled to the clock resonator via a lower-than-standard mutual inductance. Secondly, each bias level sensor configured as an output amplifier emulator may have a corresponding JTL(s) DC bias transformer(s)(s)(s) coupled to the output bias current of the output amplifier (I(I(I(I(I(I) BIASOUT ) can be coupled to each other. Each output amplifier emulator thus obtains its DC bias from the output bias line of the output amplifier of the RQL IC106. Thirdly, the sensitivity of the JTL in each output amplifier emulator to the output bias current of the output amplifier can be set to be similar to the sensitivity of the SQUID in the output amplifier configured to be emulated by the output amplifier emulator. For example, the JJ in the JTL of the output amplifier emulator can be sized to have a critical current that approximates the critical current of the JJ in the DC SQUID of the output amplifier configured to be emulated by the output amplifier emulator. When the bias level sensors 202 to 212 of the series output ladder configuration 200 in Figure 2A are configured as output amplifier emulators having the three characteristics described above, the pulse counts provided at the output of the ladder configuration 200 configured using the output amplifier emulators as bias level sensors 202 to 212 represent how well the output bias current of the output amplifier is adjusted to the SQUID in the output amplifier configured to be emulated by the output amplifier emulator.

[0089] As described above, with respect to a bias level detection configuration configured to calibrate the AC bias amplitude or DC bias value, the mutual inductance with respect to the output bias line of the output amplifier of each bias level sensor configured as an output amplifier emulator is such that each output amplifier emulator has a desired X OA The settings can be changed in stages to provide the desired effect. For example, with respect to the exemplary configuration 200 in Figure 2A, if each bias level sensor 202-212 is implemented as an output amplifier emulator, the mutual inductance of output amplifier emulator 202 with respect to the output bias line of the output amplifier can be smaller than that of output amplifier emulator 204, and the mutual inductance of output amplifier emulator 204 with respect to the output bias line of the output amplifier can be smaller than that of output amplifier emulator 206, and so on for each stage of the wrapper ladder configuration 200. Thus, changing the output bias of the output amplifier will cause more or fewer output amplifier emulators 202-212 to generate pulses, changing the pulse count of the series output of the wrapper.

[0090] With respect to the above example of an output amplifier emulator, the output bias current of the output amplifier can be adjusted, improved, or optimized by directly observing the output of the output amplifier without using an output amplifier emulator. Such fluctuations in the output bias current of the output amplifier when directly observing the output of the output amplifier may require varying the output bias current of the output amplifier within a range that includes disabling the output amplifier under observation. After the optimal bias has been determined in such a way, pulse counts from a series output wrapper ladder sensor having bias level sensors 202-212 configured as an output amplifier emulator can be recorded and used to maintain the optimal output bias current of the output amplifier even while the output amplifier is operating continuously. This is possible because the output bias current of the output amplifier is kept within the operating range of the emulated output amplifier. In such a case, the output amplifier emulator does not need to emulate the critical current characteristics of the SQUID JJ of the emulated output amplifier; that is, the output amplifier emulator does not need to be configured to satisfy the third characteristic described above.

[0091] Figures 27A and 27B show exemplary feedback systems 2700 and 2750 that may be used to detect and tune the AC amplitude (Figure 27A) and phase (Figure 27B) of the I clock and Q clock. In each of Figures 27A and 27B, two RQL bias level sensors 2702, 2704, 2708, and 2710 may be implemented as shown in Figure 26A or Figure 26B. Sensors 2702, 2704, 2708, and 2710 may be implemented as all or part of sensor 118 on the RQL IC 106 in a cooling space.

[0092] In the example shown in Figure 27A, the first sensor 2702 is powered by a 90° clock (Q clock). The second sensor 2704 is powered by a 0° clock (I clock). The AC bias amplitude supplied to the I and Q clocks can be detected simultaneously by the two sensors 2702 and 2704. The outputs OUTPQ and OUTPI of sensors 2702 and 2704 have the form of a voltage pulse train in which the voltage height changes over time. The pulses in the pulse train can be configured to be generated, for example, once per AC clock cycle. The individual output signals OUTPQ and OUTPI provided by sensors 2702 and 2704 each have a voltage amplitude large enough to be analyzed, for example, by an AC amplitude adjustment logic unit 2706 which may be provided as part of a feedback loop 122 to a bias signal generator (one or more) 110 located outside the cooling space. The AC amplitude adjustment logic unit 2706 can be implemented, for example, in a conventional semiconductor circuit (e.g., a CMOS circuit). A third input to the AC amplitude adjustment logic unit 2706, labeled AMPREF, provides an AC or DC signal representing the desired ideal nominal level to be provided by the two sensors 2702 and 2704. The output QOUT at the top of the logic unit 2706 instructs a change in the output of the clock source for the Q clock (a 90° clock source), the output IOUT at the bottom of the logic unit 2706 instructs a change in the output of the clock source for the I clock (a 0° clock source), and the amplitude reference signal AMPREF describes or represents the level at which the clock sources should be regulated. The reference signal AMPREF may represent, for example, the height of the pulses generated by sensors 2702 and 2704.

[0093] The AC amplitude adjustment logic unit 2706 may be configured to perform a voltage comparison of the provided bias detection signals OUTPQ and OUTPI and generate one or more control signals based on the comparison between the OUTPQ and OUTPI signals. For example, if the AC amplitudes of the 0° I clock and 90° Q clock detected on the RQL IC 106 by sensors 2702 and 2704 are close to or match the optimal AC bias point 306, the outputs OUTPQ and OUTPI of sensors 2704 and 2702 will be equal, and the outputs QOUT and IOUT of the logic unit 2706 will not indicate any change in the AC amplitude of either clock 112 or 114. However, if the AC amplitudes of the 0° I clock and the 90° Q clock detected on the RQL IC 106 by sensors 2702 and 2704 are different, or if either of them does not match the optimal AC bias setting for the corresponding clock, the outputs OUTPQ and OUTPI of sensors 2704 and 2702 will not be equal, and one or both of the outputs QOUT and IOUT of the logic circuit 2706 will indicate a change in the AC amplitude of either clock 112 or 114.

[0094] Following the AC amplitude calibration of the I-clock and Q-clock performed by the configuration in Figure 27A, the configuration in Figure 27B may be used to detect and calibrate the relative phase of the I-clock and Q-clock to ensure that the phase difference between the I-clock and Q-clock supplied to the operating RQL circuit 102 on the RQL IC 106 in the cooling space is 90°. The bias level sensor configuration in Figure 27B is structurally identical to the configuration in Figure 27A, except that the first sensor 2708 in Figure 27B is supplied with a 45° clock formed by connecting both the I-resonator and Q-resonator, rather than a 90° clock formed by connecting only the Q-resonator as in the sensor 2702 in Figure 27A, and the second sensor 2710 in Figure 27B is supplied with a -45° (315°) clock formed by connecting both the Q-resonator and I-resonator, rather than a 0° clock formed by connecting only the I-resonator. The clock signals generated by the 45° or 135° transformers on the RQL IC106 depend on both the phase difference and amplitude of the I clock and Q clock. A phase mismatch between the I clock and Q clock at the level of the RQL IC106 in the cooling space can cause fluctuations in the AC amplitude of the 45° and 135° signals. As shown in Figure 27B, supplying power to the sampler in sensor 2708 with a 45° clock results in an output voltage mismatch between the output OUTPIQ of the 45° sensor 2708 and the output OUTPQI of the -45° sensor 2710, which exhibits a phase difference different from the 90° between the I clock and Q clock. This is because, after the AC amplitudes of the I clock and Q clock become equal, the only factor that can cause such a difference in the output voltage of a sensor is the phase error between the clocks.

[0095] Accordingly, the AC phase adjustment logic unit 2712 may be configured to perform a voltage comparison of the provided bias detection signals OUTPIQ and OUTPQI and generate one or more control signals based on the comparison between the OUTPIQ and OUTPQI signals. For example, if the phase error between the 0° I clock and the 90° Q clock detected on the RQL IC 106 by sensors 2708 and 2704 indicates true orthogonality (exactly a 90° phase difference), then the outputs OUTPIQ and OUTPQI of sensors 2708 and 2710 will be equal, and the outputs QOUT and IOUT of the logic unit 2712 will not indicate any AC phase change of either clock 112 or 114. However, if the phase errors between the 0° I clock and the 90° Q clock detected on the RQL IC 106 by sensors 2708 and 2702 are different, the outputs OUTPIQ and OUTPQI of sensors 2708 and 2710 will not be equal, and one or both of the outputs QOUT and IOUT of the AC phase adjustment logic unit 2712 will instruct a phase change of either clock 112 or 114.

[0096] The output amplifier-based structures shown in Figures 26A and 26B have the advantage of being able to generate relatively large output voltages with relatively high throughput. They can be used to adjust the AC amplitude and phase and tune the resonator clock, as shown in Figures 27A and 27B.

[0097] Figure 28 shows an exemplary optimization method 2800 that can be used to calibrate a bias signal to, for example, an ideal calibration or near an ideal calibration using one or more configurations of bias level sensors. A sampled signal (e.g., an SFQ pulse or a reciprocal pulse pair) is X AC The sampler is input to a sampler wrapper having a sampler (2802). For example, the wrapper can be a series output RQL scan register as shown in Figure 2A or Figure 25, a parallel output configuration as shown in Figure 2B, a ring oscillator as shown in Figure 2C, a DC SQUID-based configuration as shown in Figure 26A or Figure 26B, or a PML shift register configuration as shown in Figure 24. ACThe sampler may, for example, be a JTL-based or RQL gate-based sampler as shown in Figure 6, a shift register-based sampler as shown in any of Figures 8, 9, 10, 11, 12, 13, 16, or 18, a PML flip-flop-based sampler as shown in Figure 24, or a pulse generator-based sampler as shown in Figure 25. AC The sampler output can be observed, for example, by a circuit that counts pulses in the output pulse train generated by the sampler wrapper, such as the pulses shown in Figures 4A-4D, in the case of a series pulse output by a wrapper as shown in Figure 2A; by a circuit that compares the input pulse stream with the output pulse stream, in the case of a PML shift register configuration as shown in Figure 24; or by a voltage comparison circuit, in the case of a DC SQUID-based configuration as shown in Figure 26A or 26B, which outputs a voltage pulse having a value on the order of millivolts (2804). The circuit that observes the bias level sensor output can be a conventional semiconductor circuit (e.g., a CMOS circuit) operating in the ambient temperature environment of system 100 and does not need to be mounted on the RQL IC 106 or elsewhere in a cooled environment. Observation (2804) can be performed by a human user using a human-in-the-loop feedback technique in some examples, where the human user is X AC The sampler output is observed (2804), optimization decisions are made (2806), and the AC clock amplitude is manually changed (2808).

[0098] For example, X AC Two or more of the samplers (AC bias samplers) include at least one JTL or pulse generator having a weakened AC clock resonator bias tap to the AC clock resonator of the RQL IC, compared to the bias tap of the AC clock resonator of the JTL in the operating RQL circuit 102. The weakened AC clock resonator bias tap means that a larger amplitude AC bias signal is required to drive the JTL or pulse generator within its respective AC operating margin, and therefore the X of the AC bias samplerDC -X AC The margin Schmoo plot is shifted upward relative to the margin Schmoo plot of the operating RQL circuit 102, for example, as shown in Figure 3. As another example, X AC Two or more samplers include pulse generators having Josephson junctions with a critical current greater than that of the Josephson junction in the operating RQL circuit.

[0099] X AC Based on observations of the sampler output (2804), it can be evaluated whether the AC bias amplitude parameters have been optimized (2806). For example, if a number of different AC bias amplitudes are provided to the sampler wrapper, data can be compiled to show which AC bias amplitude produces the optimal or near-optimal output result. For example, X with linearly stepped AC operating margin offsets. AC For the series output wrapper in Figure 2A with a bias level sensor, a moderate number of X values ​​are used, as shown in Figure 4C. AC The optimal result is generated when the sampler is operating. If sufficient data has not been collected to draw such a conclusion, the AC clock amplitude of the AC clock resonator under test may be changed to a different value (2808), and a new sample signal may be input (2802). Part of this process 2802-2808 may be repeated iteratively as many times as necessary to provide confidence that the AC bias amplitude has been optimized for the AC clock resonator under test (e.g., I-resonator or Q-resonator) (2810). In some exemplary methods similar to method 2800, the AC bias amplitude is improved even if it is not optimized at 2810. The improvement in the AC bias amplitude shows a result consistent with the AC clock amplitude provided at 2808 approaching the optimal bias point 306 of the operating RQL circuit 102 X AC This can be determined by observing the sampler output (2804).

[0100] After the AC bias signal is calibrated in 2098, process 2800 can continue to calibrate the DC bias. The sampled signal is X DCThe sampler is input to a sampler wrapper having a sampler (2812). The wrapper may be the same wrapper as the one used to calibrate the AC bias amplitude in the AC bias calibration portion of method 2800, or a different wrapper. DC Samplers can also be of the forms listed and described above. DC The sampler output can be observed, for example, by a circuit that counts pulses in the output pulse train generated by the sampler wrapper, such as the pulses shown in Figures 4A-4D, in the case of a series pulse output by a wrapper as shown in Figure 2A; or by a circuit that compares the input pulse stream with the output pulse stream, in the case of a PML shift register configuration as shown in Figure 24; or by a voltage comparison circuit, in the case of a DC SQUID-based configuration as shown in Figure 26A or 26B, which outputs a voltage pulse having a value on the order of millivolts (2814). The circuit that observes the bias level sensor output can be a conventional semiconductor circuit (e.g., a CMOS circuit) operating in the ambient temperature environment of system 100 and does not need to be mounted on the RQL IC 106 or elsewhere in a cooled environment. Observation 2814 can also be performed by a human user using a human-in-the-loop feedback technique, where the human user is X DC Observe the sampler output (2814), make an optimization decision (2816), and manually change the DC bias value (2818).

[0101] X DC Based on observations of the sampler output (2814), it can be evaluated whether the DC bias value parameters have been optimized (2816). For example, if a number of different DC bias values ​​are provided to the sampler wrapper, data can be compiled to show which DC bias value produces the optimal or near-optimal output result. X has a linearly stepped DC operating margin offset. DC For the series output wrapper in Figure 2A, which has a bias level sensor, for example, as shown in Figure 5C, the intermediate offset range of X DCThe optimal result is produced when only the sampler is operating. If sufficient data has not been collected to draw such a conclusion, the DC bias value supplied to the DC bias line under test may be changed to a different value (2818), and a new sample signal may be input (2812). Part of this process 2812-2818 may be repeated iteratively as many times as necessary to provide confidence that the DC bias value has been optimized for the DC bias line under test (2820). Thus, both the AC and DC bias signals are calibrated (2820). Calibration method 2800 or any part thereof may be performed while the operating RQL circuit 102 is operating continuously, even while its bias parameters are being adjusted, improved, or optimized, in some examples. In some exemplary methods similar to method 2800, the DC bias value is improved in 2820, even if it is not optimized. The improvement in the DC bias value shows a result consistent with the DC bias value provided in 2818 approaching the optimal bias point 306 of the operating RQL circuit 102 X DC This can be determined by observing the sampler output (2814).

[0102] The PML-based optimization method 2900 shown in Figure 29 is described above in relation to the description of the PML shift register structure, which is partially shown in Figure 24. Although the illustrated and described method 2900 relates to the calibration of the AC bias amplitude, method 2900 may be modified to provide calibration of the DC bias value, i.e., by using flip-flops of various PML shift register elements with stepped DC bias operating margin offsets (e.g., by manufacturing flip-flop bias transformers to have different, e.g., stepped DC bias line-coupled transformer lengths), stopping the logic clock (2906), changing the DC bias value instead of the AC amplitude (2908), advancing a single clock cycle (or half cycle) (2910), and restarting the logic clock (2914), and observing the output data bit pattern (2916), after which X AC Not optimization, but emiX DC This can be fixed by checking for optimization (2918).

[0103] Figure 30 shows an exemplary optimization method 3000 that can be used to calibrate the phase difference between different AC clock bias signals, for example, between the I clock and the Q clock. In some examples, the AC amplitudes of the I and Q clocks are first calibrated independently of each other 3002, 3004, which can be done using either method 2900 or 2900 by using bias level sensors that are independent of the I clock or independent of the Q clock, for example, as shown in Figures 12, 13, 16, 18, or 24. In method 3000, a sampled signal, for example, an SFQ pulse or a reciprocal pulse pair, is X phase Sampler or multiple X phase The signal is input to a sampler wrapper having a sampler (3002). The wrapper can be a series output RQL scan register as shown in Figure 2A or Figure 25, a parallel output configuration as shown in Figure 2B, a ring oscillator as shown in Figure 2C, or an output amplifier-based configuration as shown in Figure 26A or Figure 26B (for example, configured as shown in Figure 27B). phase The sampler(s) can be, for example, a JTL-based sampler as shown in Figure 21, and has four mixed resonator clock inputs with different phases of 90° apart from each other. phase The weakest biased JTL or gate in the sampler is X phase The minimum AC operating point (X) at which the sampler operates. ACmin ) defines X phase The sampler output can be observed, for example, by a circuit that counts the pulses of the output pulse train generated by the sampler wrapper (3004). Such a circuit can be a conventional semiconductor circuit (e.g., a CMOS circuit) operating in the ambient temperature environment of system 100 and does not need to be mounted on the RQL IC 106 or elsewhere in a cooled environment.

[0104] X phaseBased on observation of the sampler output (3004), it can be evaluated whether the clock phase difference parameter has been optimized (3006). For example, in a two-dimensional search, a number of clock phase difference values ​​over a number of AC bias amplitudes can be one or more X in the sampler wrapper. phase If provided to a sampler, data indicating which clock phase difference value produces the optimal or near-optimal output result may be edited. For example, X phase When the Sampler 2000 is used, as shown in point 2402 of Figure 24, X phase X is the lower limit of the operating margin of the Sampler 2000. ACmin (X phase The lowest AC bias amplitude at which the Sampler 2000 continues to operate is such that X ACmin The optimal result is produced when there is a phase error that is lowest over a range dependent on the phase error of the point. Another example is X of a specific I or Q as shown in Figures 12, 13, 16, or 18. AC When a sampler is used, as shown at point 1902 in Figure 19, the X of a specific sampler ACmin The phase error-dependent plot of X for a specific Q sampler ACmin The optimal result is produced when there is a phase error that intersects with the phase error dependency plot. Another example is X with mixed resonator clocks separated by 90°, such as a 45° clock sampler and a 135° sampler. AC When a sampler is used, as shown at point 2302 in Figure 23, the X of the first mixed resonator sampler ACmin The phase error dependency plot shows the X of the second mixed resonator sampler supplied with an AC bias signal that is 90° away from the phase of the AC bias signal supplied to the first mixed resonator sampler. ACmin The optimal result is generated when there is a phase error that intersects with the phase error-dependent plot.

[0105] X phase If not enough data is collected to conclude that the value has been optimized, X AC and X phaseMore data can be collected by performing a two-dimensional search of the values ​​of each X. phase For the value, X AC By changing the X of the phase sampler (one or more), ACmin X can be discovered. AC If the sweep is not completed for the current X phase value (3008), a different X AC To provide the input values ​​to the phase sampler(s), the AC amplitude of the supplied bias (whether I clock resonator, Q clock resonator, or both) is changed (3010), and a new input sample signal is provided to the sampler wrapper (3002). The AC sweep portion of the process 3002-3010 is given X phase X with respect to the phase sampler (one or more) for the value ACmin This can be repeated until it is identified. X with respect to the phase sampler for the current phase difference between the I clock and the Q clock. ACmin When this is detected, the phase difference between the I clock and the Q clock may be changed to a different value (3012), and a new sample signal may be input (3002). phase The sweep process section 3002-3012 is the X of the phase sampler (single or multiple). ACmin The number of times required to discover that the clock phase difference is optimized for the AC clock resonator under test (3014) is the X required to provide confidence that the clock phase difference is optimized for the AC clock resonator under test. phase This can be repeated as many times as the number of values ​​of X. AC Sweep and X phase The sweep does not have to be a linear sweep; for example, a binary search process can be used for each X. phase X in value ACmin And, X phase X as a function of ACmin X is the smallest value phase It can be approached more quickly with both the value and the X. ACmin The phase offset that minimizes (for example, using phase sampler 2000 in Figure 20, as shown at point 2302 in Figure 23), or the X of samplers separated by 90°. ACThe phase offset at which the plots intersect (e.g., points 1902 or 2202 in Figures 19 and 22, respectively) indicates the optimal phase offset between the I clock and Q clock in a room-temperature environment, where the clock should be driven to achieve true orthogonality (90° separation) in the operating RQL circuit 102 on the RQL IC 106 in a cooled space. DC The level is X ACmin It is located at X. Therefore, X AC Similarly, X DC By searching for the value of X AC Once the minimum value of X is found, DC The optimal value will also be determined.

[0106] Figure 31 shows an exemplary optimization method 3100 that can be used to optimize the clock bias signal delivered to the RQL IC 106 by calibrating the I and Q clock AC amplitude parameters and the I and Q clock phase parameters, for example, using an output amplifier-based sensor 2600 or 2650 shown in Figures 26A and 26B and two sensor feedback systems shown in Figures 27A and 27B. The first and second sensors are driven by the I and Q clock signals, respectively (3102). Each sensor may be supplied with a sample signal, e.g., an SFQ pulse, at its corresponding input and may provide an output voltage signal at its corresponding output. The outputs of the first and second sensors may be compared (3104). The comparison 3104 may be performed, for example, outside the cooling space where the RQL IC 106 is located, and may be performed by a conventional semiconductor circuit (e.g., a CMOS circuit) configured to receive the output voltage signals of the first and second sensors and perform the comparison 3104. Based on a comparison of the outputs of the first and second sensors (3104), in some examples, it may be evaluated whether the AC clock amplitude parameters of the I and Q clocks have been optimized, further based on a reference signal (3106). For example, if the comparison (3104) shows no difference between the sensor outputs of the first and second sensors (e.g., OUTPQ and OUTPI in Figure 27A) and both outputs are within the acceptable range of values ​​indicated by the reference signal, it may be determined that the AC amplitude parameters have been calibrated (3110), and method 3100 can proceed to calibrate the phase error between the I clock and the Q clock. However, if the comparison (3104) shows a difference between the sensor outputs, for example, based on the output of a comparison circuit in a room temperature environment, one or both of the AC clock amplitudes for the I and Q clocks may be changed (3108), and the outputs of the first and second sensors may be recompared (3104). Parts 3102-3108 of this process may be repeated iteratively as many times as necessary to provide confidence that the AC clock amplitudes of the I and Q clock signals have been optimized (3110).

[0107] When the AC clock amplitudes of the I and Q clock signals are optimized (3110), the first and second sensors can be biased with a 90° phase-separated clock signal formed from a mixture of the I and Q resonator signals. For example, the first sensor may be driven with a 45° AC clock signal, and the second sensor may be driven with a -45° (315°) AC clock signal. The AC clock signal for the mixed resonator can be formed according to Table 1 above. The first and second sensors driven with the 90° phase-separated mixed resonator clock signal (3112) may be the same sensors as those driven with the I and Q clock signals (3102) (in which case a mechanism is provided for switching between these sensors and different resonators or combinations of resonators), or one or both of them may be different from the sensors driven with the I and Q clock signals (3102). For example, the first sensor (e.g., sensor 2710 in Figure 27B) may be driven with a clock signal nominally -45° (e.g., by transformer coupling the first sensor to both the Q and I clock resonators) (3112), and the second sensor (e.g., sensor 2708 in Figure 27B) may be driven with a clock signal nominally 45° (e.g., by transformer coupling the second sensor to both the I and Q clock resonators) (3112). In another example, the 90° phase-separated clock signals biasing the first and second sensors may be pure I clock signals and Q clock signals, respectively (e.g., 0° and 90°, 90° and 180°, or 180° and 270°). A method for detecting phase by comparing the outputs of a pair of bias parameter sensors formed from a combination of I and Q clock signals (e.g., ±45°, or 45° and 135°, 135° and 225°, etc.) has the advantage of being more sensitive to phase matching than a configuration consisting of a pair of bias parameter sensors operating on pure I and Q clock signals (e.g., at 0° and 90°, 90° and 180°, or 180° and 270°).

[0108] The outputs of the first and second sensors can be compared (3114). The comparison (3114) can be performed, for example, outside the cooling space where the RQL IC 106 is located, and can be performed, for example, by a conventional semiconductor circuit (e.g., a CMOS circuit) configured to receive the output voltage signals of the first and second sensors and perform the comparison 3114. The comparison circuit can be the same or a different circuit as the one used to perform the comparison (3104) of the AC amplitude indicator outputs in the first part of method 3100. Based on the comparison (3114) of the outputs of the first and second sensors, in some further examples, it can be evaluated, further based on a reference signal, whether the phase error of the AC clock is optimized to provide true orthogonality between the I clock phase and the Q clock phase, i.e., whether there is a 90° separation of the Q clock phase from the I clock phase, as observed on the RQL integrated circuit 106 (3116). For example, if the comparison (3114) indicates no difference between the sensor outputs of the first and second sensors (e.g., OUTPIQ and OUTPI in Figure 27B), it can be determined that the AC phase error parameter has been calibrated (3120). However, if the comparison (3114) indicates a difference between the sensor outputs of the first and second sensors, for example, if one or both of the AC clock phases with respect to the I and Q clocks have been changed based on the output of the comparison circuit in a normal temperature environment (3118), the outputs of the first and second sensors may be recompared (3114). Parts 3112-3118 of this process may be repeated iteratively as many times as necessary to provide confidence that the AC clock phase error of the I and Q clock signals has been optimized (3120).

[0109] In the exemplary circuit structures and methods described above, the operating region of the test circuit may be established by electronic testing, in which the bias level is changed to determine the individual operating range of the test circuit. The operating range of the test circuit may differ from that of the operating RQL circuit due to manufacturing differences, such as differences in the mutual inductance values ​​of the AC clock resonator or DC bias line-coupled transformer, and due to the addition of self-inductance between the taps and the individual JTLs or gates driven by the taps. In each of the different examples described, the electronic testing involves applying a stimulus in the form of a logic signal and observing the presence or absence of an expected logic output indicating the operation of the test circuit. The boundaries of the operating region may be determined by verifying that each test circuit operates correctly or fails at various applied bias levels.

[0110] In some cases, the bias level sensor and related methods of this application can favorably determine how close the operating point of the operating RQL circuit is to the optimal operating point while the operating RQL circuit continues to operate, i.e., without causing bias-related failures in the operating RQL circuit. By placing a sampler having an operating range configured to change systematically with respect to the operating range of other samplers on the RQL IC 106, it is possible to numerically confirm the currently applied bias level of the RQL IC 106 as observed on the RQL IC 106. If the sampler is housed in a wrapper having a ladder configuration as shown in Figure 2A or Figure 25, the numerical determination of the current bias level can be performed, for example, by counting the number of pulses provided at the output of the sampler wrapper each time a sampler pulse is supplied to the input of the sampler wrapper. Thus, the bias level sensor and related methods of this application can evaluate the bias state on the RQL IC 106 without interfering with the operation of the operating RQL circuit 102 on the IC 106. The bias level sensor and related methods of this application are particularly useful for calibrating the bias operating points of RQL systems having multiple RQL ICs. The bias level sensor and related methods of this application can function as an on-chip device for evaluating the performance of a circuit that is affected by variations in circuit (wafer) processing, i.e., a process control monitor. The bias level sensor and related methods of this application can be implemented in human-in-the-loop feedback control or in fully automated feedback control that can continuously or periodically measure bias signal parameters and instruct adjustments to the bias signal parameters using a combination of RQL circuits inside a cooling space and non-RQL circuits outside the cooling space (e.g., CMOS or other semiconductor circuits).

[0111] The above description is an example of the present invention. Naturally, it is not possible to describe all possible combinations of components or methods that could be used to describe the invention, but those skilled in the art will recognize that many further combinations and substitutions of the invention are possible. Accordingly, the invention is intended to encompass all such changes, modifications, and variations that fall within the scope of this application, including the appended claims. In addition, where this disclosure or the claims list “one (a),” “an,” “a first,” or “another” component, or their equivalents, it should be interpreted as including one or more such components, and not as requiring or excluding two or more such components. As used herein, the term “includes” means including but not limited to, and the term “including” means including but not limited to. The term “based on” means based at least in part. The technical concepts that can be understood from the above embodiments are described below as an addendum. [Note 1] A reciprocal quantum logic (hereinafter referred to as RQL) integrated circuit (hereinafter referred to as IC), A phase mode shift register is provided, and the phase mode shift register is A first set of multiple Josephson transmission lines (hereinafter referred to as JTLs) arranged in series as a data path, A second set of multiple JTLs arranged in series as a logic clock path trunk, A plurality of phase-mode D flip-flops, each having a data input coupled to the data path and configured to receive input from the data path, a data output coupled to the data path and configured to provide output to the data path, and a logic clock input coupled to a branch of an individual logic clock path coupled to the logic clock path trunk, The first plurality of JTLs and the plurality of phase-mode D flip-flops in the data path are transformer-coupled to one or more AC clock resonators of the RQL IC to receive AC clock bias signals of two first AC clock phases separated by approximately 180° from each other. The second plurality of JTLs in the logic clock path trunk are transformer-coupled to one or more AC clock resonators of the RQL IC to receive AC clock bias signals of two second AC clock phases separated by approximately 180° from each other. The first two AC clock phases are different from the second two AC clock phases in the RQL IC. [Note 2] The first of the two AC clock phases is approximately 90° away from the first of the two AC clock phases. The system as described in Appendix 1, wherein the second of the two first AC clock phases is approximately 90° away from the second of the two second AC clock phases. [Note 3] The first of the two AC clock phases mentioned above has a phase of approximately 0°. The first of the two AC clock phases mentioned above has a phase of approximately 90°. The second of the two AC clock phases mentioned above is approximately 180°, The second of the two AC clock phases described above is approximately 270°, as per the system described in Appendix 2. [Note 4] The first of the two AC clock phases mentioned above has a phase of approximately 0°. The first of the two AC clock phases mentioned above has a phase of approximately 90°. The second of the two AC clock phases mentioned above is approximately 180°, The second of the two AC clock phases described above is approximately 270°, as in the system described in Appendix 2. [Note 5] The first of the two AC clock phases mentioned above has a phase of approximately 45°. The first of the two AC clock phases mentioned above has a phase of approximately 135°. The second of the two AC clock phases mentioned above is approximately 225°. The second of the two AC clock phases described above is approximately 315°, as per the system described in Appendix 2. [Note 6] The first of the two AC clock phases mentioned above has a phase of approximately 45°. The first of the two AC clock phases mentioned above has a phase of approximately 135°. The second of the two AC clock phases is approximately 225°. The second of the two AC clock phases described above is approximately 315°, as in the system described in Appendix 2. [Note 7] The system as described in Appendix 1, wherein each of the plurality of phase-mode D flip-flops is transformer-coupled to the one or more AC clock resonators at different points along the one or more AC clock resonators. [Note 8] The system as described in Appendix 1, wherein each of the plurality of phase-mode D flip-flops is transformer-coupled to an AC bias signal source or a DC bias signal source weaker or stronger than the JTL of the operating RQL circuit on the RQL IC that is not part of the phase-mode shift register. [Note 9] The system as described in Appendix 8, wherein the individual transformer coupling of each of the plurality of phase-mode D flip-flops is set in steps such that the strength of the individual transformer coupling of each phase-mode D flip-flop changes relative to one another. [Note 10] The system as described in Appendix 8, wherein the lower limit of the AC operating range of at least one of the plurality of phase-mode D flip-flops is approximately at the centroid of the operating range of the operating RQL circuit. [Note 11] The system as described in Appendix 1, wherein each of the second plurality of JTLs in the logic clock path trunk is biased by an AC bias signal source less strongly than the JTLs of the operating RQL circuit on the RQL IC that are not part of the phase mode shift register. [Note 12] The system as described in Appendix 11, wherein the lower limit of the AC operating range of each of the second plurality of JTLs in the logic clock path trunk is approximately at the centroid of the operating range of the operating RQL circuit. [Note 13] It is a method, The steps include setting at least one bias signal parameter of the bias signal supplied to a reciprocal quantum logic (RQL) integrated circuit (IC) to a nominal value, The steps include: starting a logic clock signal supplied to the logic clock path of a phase-mode RQL shift register and shifting in an input data bit pattern to the data path of the phase-mode RQL shift register; Steps to stop the logical clock, The steps include changing the value of the at least one bias signal parameter provided to the data path of the phase-mode RQL shift register, The steps include inputting one assertion SFQ pulse pair or a single SFQ pulse into the logic clock path, A step of returning the value of at least one bias signal parameter to the nominal value, The steps include restarting the logic clock signal supplied to the logic clock path of the phase-mode RQL shift register and shifting out the output data bit pattern to the data path of the phase-mode RQL shift register, The steps include observing the output data bit pattern of the phase-mode RQL shift register, A method comprising the step of determining that the value of the at least one bias signal parameter has approached the optimal value of the at least one bias signal parameter by changing the value of the at least one bias signal parameter based on observing the output data bit pattern. [Note 14] The method according to Appendix 13, wherein the at least one bias signal parameter includes the AC amplitude of the AC bias signal supplied to the data path of the phase-mode RQL shift register. [Note 15] The method according to Appendix 13, wherein the at least one bias signal parameter includes a DC bias value of the DC bias signal supplied to the data path of the phase-mode RQL shift register. [Note 16] The method according to Appendix 13, wherein the at least one bias signal parameter includes a phase difference between the I clock signal and the Q clock signal supplied to the RQL IC. [Note 17] The step of observing the output data bit pattern includes identifying one or more differences between the output data bit pattern and the input data bit pattern in the output data bit pattern, The method according to Appendix 13, wherein the determination step is based on determining which element of the phase-mode RQL shift register has been biased outside its operating region, or which multiple elements of the phase-mode RQL shift register have been biased outside their respective operating regions, while a single assertion SFQ pulse pair or a single SFQ pulse is input to the logic clock path when the value of at least one bias signal parameter is changed. [Note 18] An RQL superconducting bias level detection circuit for detecting the bias level supplied to the operating RQL circuit of a reciprocal quantum logic (hereinafter referred to as RQL) integrated circuit (IC), wherein the bias level detection circuit comprises a PML shift register including a plurality of phase-mode logic (hereinafter referred to as PML) shift register elements coupled in series with each other, and each PML shift register element is A PML D flip-flop having a data input, a data output, and a logic clock input, wherein the data input is configured to be coupled to either the data output of the previous element in the PML shift register or an input data bitstream source, A data output path portion having an input coupled to the data output of the PML D flip-flop and an output configured to be coupled to either the data input of the next element in the PML shift register or a circuit configured to receive an output data bitstream from the PML shift register, wherein the data output path portion comprises first, second, and third Josephson transmission line (hereinafter referred to as JTL) based buffers coupled in series with each other between the input and the output of the data output path portion, A logic clock path trunk portion having an input configured to be coupled to either the logic clock path output or the logic clock source of the next element in the PML shift register, and an output configured to be coupled to either the logic clock path input of the previous element in the PML shift register and / or a branch of the logic clock path of the PML shift register element, wherein the logic clock path trunk portion comprises fourth, fifth, sixth, seventh, and eighth JTL-based buffers coupled in series with each other between the input and the output of the logic clock path trunk portion, A bias level sensing circuit comprising: a branch of the logic clock path having an input coupled to the output of the logic clock path trunk portion of the PML shift register element and an output coupled to the logic clock input of the PML D flip-flop, the branch of the logic clock path comprising a ninth and a tenth JTL-based buffer coupled in series between the input and the output of the branch of the logic clock path. [Note 19] The PML D flip-flop and the first and tenth JTL-based buffers are driven by an AC bias signal having a first phase value. The fifth and sixth JTL-based buffers are driven by a second AC bias signal having a second phase value that is approximately 90° greater than the first phase value. The second and third JTL-based buffers are driven by a third AC bias signal having a third phase value that is approximately 90° greater than the second phase value. The bias level sensing circuit according to Appendix 18, wherein the fourth, seventh, eighth, and ninth JTL-based buffers are driven by a fourth AC bias signal having a fourth phase value approximately 90° greater than the third phase value. [Note 20] The bias level sensing circuit according to Appendix 19, wherein the second, fifth, and seventh JTL-based buffers each include at least one additional Josephson junction at their respective inputs, compared to the first, third, fourth, sixth, eighth, ninth, and tenth JTL-based buffers.

Claims

1. A reciprocal quantum logic (hereinafter referred to as RQL) integrated circuit (hereinafter referred to as IC), A phase mode shift register is provided, and the phase mode shift register is A first set of multiple Josephson transmission lines (hereinafter referred to as JTLs) arranged in series as a data path, A second set of multiple JTLs arranged in series as a logic clock path trunk, A plurality of phase-mode D flip-flops, each having a data input coupled to the data path and configured to receive input from the data path, a data output coupled to the data path and configured to provide output to the data path, and a logic clock input coupled to a branch of an individual logic clock path coupled to the logic clock path trunk, The first plurality of JTLs and the plurality of phase-mode D flip-flops in the data path are transformer-coupled to one or more AC clock resonators of the RQL IC to receive AC clock bias signals of two first AC clock phases separated by approximately 180° from each other. The second plurality of JTLs in the logic clock path trunk are transformer-coupled to one or more AC clock resonators of the RQL IC to receive AC clock bias signals of two second AC clock phases separated by approximately 180° from each other. The first two AC clock phases are different from the second two AC clock phases, RQL IC.

2. The first of the two AC clock phases is approximately 90° away from the first of the two AC clock phases. The RQL IC according to claim 1, wherein the second of the first two AC clock phases is separated by approximately 90° from the second of the second two AC clock phases.

3. The first of the two AC clock phases mentioned above has a phase of approximately 0°. The first of the two AC clock phases mentioned above has a phase of approximately 90°. The second of the two AC clock phases mentioned above is approximately 180°, The second of the two AC clock phases is approximately 270° or The first of the two AC clock phases mentioned above has a phase of approximately 0°. The first of the two AC clock phases mentioned above has a phase of approximately 90°. The second of the two AC clock phases mentioned above has a phase of approximately 180°. The RQL IC according to claim 2, wherein the second of the two first AC clock phases is approximately 270°.

4. The first of the two AC clock phases mentioned above has a phase of approximately 45°. The first of the two AC clock phases mentioned above has a phase of approximately 135°. The second of the two AC clock phases described above is approximately 225°, The second of the two AC clock phases is approximately 315° or The first of the two AC clock phases mentioned above has a phase of approximately 45°. The first of the two AC clock phases mentioned above has a phase of approximately 135°. The second of the two AC clock phases mentioned above has a phase of approximately 225°. The RQL IC according to claim 2, wherein the second of the two first AC clock phases is approximately 315°.

5. The RQL IC according to claim 1, wherein each of the plurality of phase-mode D flip-flops is transformer-coupled to the one or more AC clock resonators at different points along the one or more AC clock resonators.

6. The RQL IC according to claim 1, wherein each of the plurality of phase-mode D flip-flops is transformer-coupled to an AC bias signal source or a DC bias signal source weaker or stronger than the JTL of the operating RQL circuit on the RQL IC that is not part of the phase-mode shift register.

7. The RQL IC according to claim 6, wherein the individual transformer coupling of each of the plurality of phase-mode D flip-flops is set in steps such that the strength of the individual transformer coupling of each phase-mode D flip-flop changes relative to one another.

8. The RQL IC according to claim 6, wherein the lower limit of the AC operating range of at least one of the plurality of phase-mode D flip-flops is approximately at the centroid of the operating range of the operating RQL circuit.

9. The RQL IC according to claim 1, wherein each of the second plurality of JTLs in the logic clock path trunk is biased by an AC bias signal source less strongly than the JTLs of the operating RQL circuit on the RQL IC that are not part of the phase mode shift register.

10. The RQL IC according to claim 9, wherein the lower limit of the AC operating range of each of the second plurality of JTLs in the logic clock path trunk is approximately at the centroid of the operating range of the operating RQL circuit.

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