Control device for a multilevel power conversion system and multilevel power conversion system

Abstract

The control device for a multilevel power conversion system includes a multilevel power conversion device having a plurality of semiconductor switching elements and a plurality of neutral point elements. vessel Multilevel power conversion system using carrier level shift modulation method of The control device performs the following processes: generating a modulated wave based on voltage command values ​​for each phase; generating a carrier wave that is a triangular wave signal having a predetermined carrier period; generating an injected carrier that changes within a predetermined amplitude range and is a signal with the same carrier period but opposite phase to the carrier wave; generating a modulated wave that has undergone carrier injection control to superimpose the modulated wave and the injected carrier; and generating a gate signal that controls the operation of multiple semiconductor switching elements and multiple neutral point elements in the multilevel power converter based on the result of comparing the modulated wave that has undergone carrier injection control with the multiple carrier waves.

Description

Technical Field

[0001] The present invention relates to a control device for a multilevel power conversion system and a multilevel power conversion system.

Background Art

[0002] Conventionally, for example, a multilevel power converter including a plurality of DC capacitors connected in series on the DC side and a plurality of semiconductor switching elements connected to the series connection points of the plurality of DC capacitors is known (see, for example, Patent Document 1). Hereinafter, in this specification, drawings, etc., the DC connection points of the plurality of DC capacitors are also referred to as "DC neutral points", and the plurality of semiconductor switching elements connected to the DC connection points (DC neutral points) of the plurality of DC capacitors are also referred to as "neutral point elements".

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Figure 31 shows an example of the configuration of a multilevel power converter 130A according to one embodiment. In Figure 31, the configuration of a 3-level NPP (Neutral Point Piloted) multilevel power converter 130A is shown for three phases as example configuration 1 of the multilevel power converter. As shown in Figure 31, in the multilevel power converter 130A, two DC capacitors Cp and Cn are connected in series via a DC neutral point C, and two semiconductor switching elements (neutral point elements) Q2 and Q3 are connected in reverse series to the DC neutral point C for each of the three phases. In the example shown in Figure 31, the semiconductor switching elements (neutral point elements) Q2 and Q3 are connected in reverse series with the collector side of the IGBT (Insulated Gate Bipolar Transistor) in common. However, this is not limited to this, and although not shown in the figure, the semiconductor switching elements (neutral point elements) Q2 and Q3 may be connected in reverse series with the emitter side in common.

[0005] Figure 32 shows an example of the configuration of a multilevel power converter 130B according to another embodiment. In Figure 32, the configuration of a 3-level NPC (Neutral Point Clamped) multilevel power converter 130B is shown for three phases as example configuration 2 of the multilevel power converter. As shown in Figure 32, in the multilevel power converter 130B, two DC capacitors Cp and Cn are connected in series via a DC neutral point C, and the neutral point potential of the DC neutral point C is clamped by diodes D5 and D6. With this configuration, the multilevel power converter 130B uses this DC neutral point C to create multiple voltage levels.

[0006] Figure 33 shows an example of the configuration of a multilevel power converter 130C according to another embodiment. Figure 33As an example of a multilevel power converter configuration 3, the configuration of a 5-level NPP type multilevel power converter 130C is shown for one phase. As shown in Figure 33, in the multilevel power converter 130C, a total of four DC capacitors Cp and Cn are connected in series via three DC neutral points C, and two semiconductor switching elements (neutral points) Q2 and Q3 are connected in reverse series to each DC neutral point C. In the example shown in Figure 33, the semiconductor switching elements (neutral points) Q2 and Q3 are connected in reverse series with the collector side of the IGBT in common. However, this is not the only option, and although not shown in the figure, the semiconductor switching elements (neutral points) Q2 and Q3 may also be connected in reverse series with the emitter side in common.

[0007] Figure 34 shows an example of the configuration of a multilevel power converter 130D according to another embodiment. In Figure 34, the upper section shows the configuration of a 9-level MMC (Modular Multilevel Converter) type multilevel power converter 130D for three phases as example configuration 4 of the multilevel power converter. As shown in the upper section of Figure 34, in the multilevel power converter 130D, multiple chopper cells Cell#1 to Cell#4 of the same element are connected to form an arm. The lower section of Figure 34 shows an example of a half-bridge chopper cell and an example of a full-bridge chopper cell. In the MMC type multilevel power converter 130D shown in the upper section of Figure 34, either a half-bridge chopper cell or a full-bridge chopper cell, as shown in the lower section of Figure 34, is arranged inside the chopper cells Cell#1 to Cell#4.

[0008] Incidentally, conventionally, multilevel power converters 130A to 130D, as shown in Figures 31 to 34, employ, for example, a carrier-level shift modulation scheme. In multilevel power converters 130A to 130D that employ a carrier-level shift modulation scheme, the output voltage of each phase generates harmonics that are integer multiples of the carrier frequency, and sidebands, which are harmonics that arise from the relationship between the carrier frequency and the fundamental frequency (modulation frequency).

[0009] For example, harmonic components in the relatively high frequency range are not a major problem because their energy can be easily attenuated by filters. On the other hand, attenuating harmonic components in the relatively low frequency range requires large filters, which can lead to larger equipment and increased costs. For this reason, many power conversion systems require the suppression of harmonics near the carrier frequency, which are relatively low frequency harmonics.

[0010] Therefore, the present disclosure aims to suppress harmonics near the carrier frequency, which are relatively low-frequency harmonic components, in a multilevel power converter using a carrier-level shift modulation scheme, compared to conventional methods. [Means for solving the problem]

[0011] A control device for a multilevel power conversion system according to one embodiment includes a multilevel power conversion system having a plurality of semiconductor switching elements and a plurality of neutral point elements. The vessel A multilevel power conversion system that employs a carrier level shift modulation scheme. of A control device characterized by performing the following processes: generating a modulated wave based on the voltage command value of each phase; generating a carrier wave which is a triangular wave signal having a predetermined carrier period; generating an injected carrier which is a signal that changes within a predetermined amplitude range and has the same carrier period and opposite phase as the carrier wave; generating a modulated wave on which carrier injection control is performed by superimposing the modulated wave and the injected carrier; and generating a gate signal that controls the operation of multiple semiconductor switching elements and multiple neutral point elements in a multilevel power converter based on the result of comparing the modulated wave on which carrier injection control is performed with multiple carrier waves.

[0012] A multilevel power conversion system according to one embodiment is a multilevel power conversion system using a carrier level shift modulation scheme, comprising: a multilevel power converter having a plurality of DC capacitors connected in series between a positive terminal connected to a DC power supply or DC load and a negative terminal via a DC neutral point; a plurality of semiconductor switching elements connected between the positive terminal and the negative terminal and an AC terminal connected to an AC power supply or AC load; and a plurality of neutral point elements connected between the DC neutral point and the AC terminal; and a control device that performs the following: a process of generating a modulated wave based on the voltage command value of each phase; a process of generating a carrier wave which is a triangular wave signal having a predetermined carrier period; a process of generating an injected carrier which is a signal that changes within a predetermined amplitude range and is in opposite phase to the carrier wave and has the same carrier period; a process of generating a modulated wave on which carrier injection control is performed to superimpose the modulated wave and the injected carrier; and a process of generating a gate signal that controls the operation of the plurality of semiconductor switching elements and the plurality of neutral point elements in the multilevel power converter based on the result of comparing the modulated wave on which carrier injection control is performed with the plurality of carrier waves. [Effects of the Invention]

[0013] According to this disclosure, in a multilevel power converter using a carrier-level shift modulation scheme, harmonics near the carrier frequency, which are relatively low-frequency harmonic components, can be suppressed more effectively than in conventional methods. [Brief explanation of the drawing]

[0014] [Figure 1] This figure shows an example of the configuration of a multilevel power conversion system according to one embodiment. [Figure 2] Figure 1 is a circuit diagram showing an example of the circuit configuration of a multilevel power converter in the multilevel power conversion system shown. [Figure 3] Figure 1 shows an example of the configuration of a control device in a multilevel power conversion system. [Figure 4] Figure 3 shows an example of the control configuration in the voltage command generation unit of the control unit shown in Figure 3. [Figure 5] It is a diagram showing an example of a control configuration in a gate signal generation unit of a control unit shown in FIG. 3. [Figure 6] It is a diagram showing an example of a control configuration in a gate signal generation unit according to a comparative example. [Figure 7] It is a diagram showing an example of carrier level shift modulation in a gate signal generation unit according to the comparative example shown in FIG. 6. [Figure 8] It is a diagram showing an example of a switching pattern in carrier level shift modulation. [Figure 9] It is a diagram showing an example of each gate signal of each semiconductor element in carrier level shift modulation of the switching pattern shown in FIG. 8. [Figure 10] It is an image diagram of the harmonic spectrum of each phase output voltage of a power converter using carrier level shift modulation. [Figure 11] It is a diagram showing an enlarged view near the zero cross of FIG. 7 and an example of each gate signal of each semiconductor element at that time. [Figure 12] It is a schematic diagram showing an example of the relationship between a modulation wave, a carrier wave, and each phase output voltage near the peak of the modulation wave shown in FIG. 7. [Figure 13] It is a diagram showing an example of the Fourier series expansion of the rectangular wave of each phase output voltage shown in FIG. 12. [Figure 14] It is a diagram showing an example of the relationship between the sign of a modulation wave and the slope of the modulation wave. [Figure 15] It is a schematic diagram showing an example of the relationship between a modulation wave, a carrier wave, and each phase output voltage in pattern 1 shown in FIG. 14. [Figure 16] It is a schematic diagram showing an example of the relationship between a modulation wave, a carrier wave, and each phase output voltage in pattern 2 shown in FIG. 14. [Figure 17] It is a schematic diagram showing an example of the relationship between a modulation wave, a carrier wave, and each phase output voltage in pattern 3 shown in FIG. 14. [Figure 18] It is a schematic diagram showing an example of the relationship between a modulation wave, a carrier wave, and each phase output voltage in pattern 4 shown in FIG. 14. [Figure 19]Figure 5 shows an example of the relationship between the carrier wave and the modulated wave when carrier injection control is performed in the gate signal generation unit according to one embodiment of the present invention. [Figure 20] Figure 19 shows a magnified view of the area around the 0 crossover and an example of the gate signals of each semiconductor element at that time. [Figure 21] This is a schematic diagram illustrating an example of the relationship between the modulated wave, carrier wave, and each phase output voltage during a period when the slope of the modulated wave is negative. [Figure 22] This is a schematic diagram illustrating an example of the relationship between the modulated wave, carrier wave, and each phase output voltage during a period when the slope of the modulated wave is positive. [Figure 23] This figure shows an example of the harmonic spectrum of the DC voltage-normalized inter-line output voltage, both when carrier injection control is not performed and when carrier injection control is performed. [Figure 24] This figure shows an example of a carrier wave and a modulated wave under the condition that the DC voltage is small compared to the AC output voltage. [Figure 25] This figure shows a magnified view of the area near the peak of the modulated wave in Figure 24, along with an example of the gate signal at that time. [Figure 26] This figure shows an example of a carrier wave and a modulated wave with carrier injection control under the condition that the DC voltage is small relative to the AC output voltage. [Figure 27] This figure shows a magnified view of the area near the peak of the modulated wave in Figure 26, along with an example of the gate signal at that time. [Figure 28] This figure shows an example of the charging and discharging of a DC capacitor voltage in a single-phase circuit configuration of the 3-level NPP system shown in Figure 2. [Figure 29] This figure shows an example of a control configuration in a gate signal generation unit according to a modified embodiment. [Figure 30] Figures 1 to 5 and 19 to 29 are conceptual diagrams showing examples of the hardware configuration of the processing circuit of a control device in one embodiment and its modified form. [Figure 31] This figure shows an example of the configuration of a multilevel power converter according to one embodiment. [Figure 32]This figure shows an example of the configuration of a multilevel power converter according to another embodiment. [Figure 33] This figure shows an example of the configuration of a multilevel power converter according to another embodiment. [Figure 34] This figure shows an example of the configuration of a multilevel power converter according to another embodiment. [Modes for carrying out the invention]

[0015] The control device and embodiments of the multilevel power conversion system related to this disclosure will be described below with reference to the drawings.

[0016] <Example of configuration in one embodiment> Figure 1 shows an example of the configuration of a multilevel power conversion system 20 according to one embodiment.

[0017] As shown in Figure 1, the multilevel power conversion system 20 is connected to the solar cell 11 via a DC cable 12 on the DC side (left side in Figure 1). The multilevel power conversion system 20 is also connected to the AC power system 15 via an AC cable 13 and a transformer 14 on the AC side (right side in Figure 1). The multilevel power conversion system 20 converts the DC power obtained from the solar cell 11 into AC power, and outputs the converted AC power to the AC power system 15 via the transformer 14. Hereinafter, in this specification and in the drawings, the multilevel power conversion system 20 will also be referred to as the "power conversion system 20".

[0018] The photovoltaic solar cell (PV) 11, also called a solar panel, is connected to the input terminal (DC input / output section 31 (see Figure 2)), which is one end of the power conversion system 20, via a DC cable 12. The solar cell 11 generates electricity using sunlight, and the generated DC power is supplied to the power conversion system 20 via the DC cable 12. The solar cell 11 is an example of a "DC power source or DC load," which may be a DC power source such as an "energy storage system (ESS)" or other DC loads.

[0019] One end of the DC cable 12 is connected to the solar cell 11, and the other end is connected to the DC terminal (DC input / output section 31 (see Figure 2)) of the multilevel power converter 30 in the power conversion system 20, which will be described later. The DC cable 12 has a positive electrode cable and a negative electrode cable, and supplies DC power supplied from the solar cell 11 to the multilevel power converter 30, which will be described later.

[0020] One end of the AC cable 13 is connected to the AC terminal (AC input / output section 32 (see Figure 2)) of the multilevel power converter 30 described later in the power conversion system 20, and the other end is connected to the AC power system 15 via the transformer 14. The AC cable 13 is a three-phase three-wire three-phase AC circuit that supplies three-phase AC power by combining three single-phase AC circuits with phases shifted relative to each other, using three wires, cables, and conductors. The AC cable 13 supplies the AC power converted by the multilevel power converter 30 described later to the AC power system 15.

[0021] The transformer 14 is connected via an AC cable 13 to the output side, which is the other end of the power conversion system 20, at one end, and to the AC power grid 15 at the other end. The transformer 14 transforms the AC power output from the power conversion system 20 to a predetermined voltage level and outputs it to the AC power grid 15.

[0022] The AC power system (power system) 15 is connected to a transformer 14 and is an integrated system of power generation, transformation, transmission, and distribution for supplying AC power transformed by the transformer 14 to the power receiving equipment of consumers. For example, unspecified loads are connected to it. Hereinafter in this specification and drawings, the AC power system 15 will also be simply referred to as "power system 15" or "system 15". Note that power system 15 is an example of an "AC power source or AC load," which may be a power system, for example, an electric motor, a generator, or other AC load.

[0023] The multilevel power conversion system (power conversion system) 20 is, for example, a power conversion system for solar power generation (solar cells). The power conversion system 20 converts the DC power supplied from the solar cells 11 into AC power and outputs the converted AC power to the power grid 15 via the transformer 14. The power conversion system 20 is not limited to solar power generation, and may be, for example, a power conversion system for storage batteries. In this specification and in the drawings, the power conversion system 20 will also be referred to as "PCS (Power Conditioning System) 20". Furthermore, a power conversion system for solar power generation will also be referred to as "PV-PCS (Photovoltaics-Power Conditioning System)". Furthermore, a power conversion system for storage batteries will also be referred to as "ESS-PCS (Energy Storage System-Power Conditioning System)".

[0024] The multilevel power conversion system (power conversion system) 20 includes a DC switch 21, an AC reactor 22, an AC capacitor 23, an AC switch 24, a DC voltage sensor 25, an AC current sensor 26, a multilevel power converter 30, and a control device 40. The DC switch 21 and the DC voltage sensor 25 are arranged in the DC cable 12 between the solar cell 11 and the multilevel power converter 30. The AC reactor 22, the AC capacitor 23, the AC switch 24, and the AC current sensor 26 are arranged in the AC cable 13 between the multilevel power converter 30 and the transformer 14. In this specification and in the drawings, the multilevel power converter 30 is also referred to as the "n-level power converter 30," the "power converter 30," or the "inverter 30."

[0025] The multilevel power conversion system 20 may also be a system that converts AC power to DC power. In this case, for example, in Figure 1, the power grid 15 is an AC power source that supplies AC power, and a DC load may be connected to the DC cable 12 instead of the solar cell 11.

[0026] The DC switch (DC circuit breaker) 21 is installed in series between the solar cell 11 and the power converter 30 in the DC cable 12. The DC switch 21 is, for example, an electrical contactor that can be switched on or off by instructions from the control device 40. The DC switch 21 switches the DC cable 12 between the solar cell 11 and the power converter 30 on (connects) or off (disconnects) according to on or off instructions from the control device 40, a higher-level device (not shown), or an operator. The DC switch 21 may also be, for example, a DC circuit breaker that is normally operated manually and automatically disconnects the DC cable 12 when it detects an overcurrent such as a short-circuit current. When the DC switch 21 is opened, the DC power supplied from the solar cell 11 is cut off from flowing into the power converter 30.

[0027] The AC reactor 22 is connected in series with the AC cables 13 of each phase at the output terminal (AC input / output section 32 (see Figure 2)) of the power converter 30. The AC reactor 22 is a smoothing element that has effects such as reducing noise and suppressing surge voltage. The AC reactor 22, together with the AC capacitor 23 connected in an L-shape, for example, constitutes an LC filter circuit (filter circuit) that reduces ripple (vibration) generated when the semiconductor switching elements of the power converter 30, described later, switch.

[0028] The AC capacitor 23 is connected in an L-shape to the AC cables 13 of each phase at the output terminal of the power converter 30 via branching points. The AC capacitor 23 is an electronic component that stores or releases electricity (charge). The AC capacitor 23, for example, together with the AC reactor 22 connected in an L-shape, constitutes an LC filter circuit (filter circuit) that reduces ripple (oscillation) generated when the semiconductor switching elements of the power converter 30, described later, switch. By constituting a filter circuit together with the AC reactor 22, the AC capacitor 23 suppresses the outflow of harmonics (harmonic currents) to the power system 15.

[0029] The AC switch (AC circuit breaker) 24 is installed in series between the AC reactor 22 (filter circuit) and the transformer 14 in each phase of the AC cable 13. The AC switch 24 closes (connects) or opens (disconnects) the AC cable 13 between the power converter 30 and the power system 15 according to, for example, an AC switch operation signal from the control device 40, or an closing or opening instruction from a higher-level device or operator (not shown). When the AC switch 24 is opened, the outflow of AC power supplied from the power converter 30 to the power system 15 is interrupted.

[0030] The DC voltage sensor 25 is, for example, a known DC voltmeter or DC voltage sensor, and is placed between the solar cell 11 and the power converter 30 to detect the DC voltage value Vdc. The position in which the DC voltage sensor 25 is placed is not limited to the position shown in Figure 1, but can be anywhere as long as the DC voltage value Vdc can be detected. Hereinafter in this specification and drawings, the DC voltage value Vdc will also be referred to as "DC voltage Vdc", "voltage measurement value Vdc", or simply "voltage Vdc". The DC voltage Vdc detected by the DC voltage sensor 25 is acquired by the control device 40.

[0031] The AC current sensor 26 is, for example, a known AC ammeter or AC current sensor, and is placed between the power converter 30 and the transformer 14 to detect the three-phase AC current values ​​Iu, Iv, and Iw. The position in which the AC current sensor 26 is placed is not limited to the position shown in Figure 1, but can be anywhere as long as it is possible to detect the three-phase AC current values ​​Iu, Iv, and Iw. Hereinafter in this specification and drawings, the AC current values ​​Iu, Iv, and Iw will also be referred to as "AC current Iu, Iv, and Iw," "current measurement values ​​Iu, Iv, and Iw," or simply "current Iu, Iv, and Iw." The AC currents Iu, Iv, and Iw detected by the AC current sensor 26 are acquired by the control device 40.

[0032] The multilevel power converter (power converter) 30 has one end, which is the DC terminal (DC input / output section 31 (see Figure 2)), connected to a DC switch 21 via a DC cable 12. The other end of the power converter 30, which is the AC terminal (AC input / output section 32 (see Figure 2)), is connected to an AC reactor 22 (filter circuit) via an AC cable 13. The power converter 30 is constructed of multiple semiconductor switching elements (switching elements), such as IGBTs. The power converter 30 is controlled by a pulse width modulation (PWM) signal, which is a gate drive signal (gate signal G) for the switching elements generated by the control device 40. In other words, the power converter 30 is controlled by a gate signal G for operating the power converter 30.

[0033] The power converter 30 acquires DC power supplied from the solar cell 11 at one end, which is the input terminal, and, in accordance with control by a pulse width modulation signal (gate signal G), converts the acquired DC power into AC power and outputs it from the other end, which is the output terminal, to supply to the AC cable 13. In other words, the power converter 30 is operated in accordance with control by the gate signal G. Note that the power converter 30 may also convert AC power into DC power. Details of the power converter 30 will be described later (see Figure 2, etc.).

[0034] The control device 40 is installed, for example, inside or outside the power conversion system 20. Although some wiring is omitted in the figure, it is electrically connected to each component of the power conversion system 20, including the power converter 30, by wire or wireless means. The control device 40 may also be implemented as a function of an inverter control circuit (not shown). The control device 40 may also operate according to instructions from a higher-level device (not shown) or from an operator (not shown) via an operation unit (not shown). The higher-level device (not shown) may, for example, comprehensively monitor and control multiple power conversion systems 20 and may be connected to each power conversion system 20 by wire or wireless means.

[0035] Figure 2 is a circuit diagram showing an example of the circuit configuration of the multilevel power converter 30 in the multilevel power conversion system 20 shown in Figure 1. In Figure 3, for the sake of simplicity, an example of the circuit configuration of the multilevel power converter 30 is shown, specifically the circuit configuration (circuit diagram) for one phase (e.g., U phase) of a 3-level NPP system.

[0036] In practice, the multilevel power converter 30 has a three-phase circuit configuration, for example, by arranging three circuits as shown on the AC side in Figure 2 and connecting the DC side in parallel (see, for example, Figure 31). However, in this disclosure, the number of phases in the circuit configuration of the multilevel power converter 30 is not limited to three phases, and may be single-phase or multiple phases other than three phases.

[0037] In the following explanation, a 3-level power converter 30 will be used as an example of a multilevel power converter 30. However, in this disclosure, the multilevel power converter 30 is not limited to a 3-level power converter 30, but may be an n-level power converter 30 other than a 3-level converter.

[0038] As shown in Figure 2, the power converter 30 has a DC input / output section 31 and an AC input / output section 32. The power converter 30 also has a positive terminal P, a negative terminal N, a DC capacitor Cp, a DC capacitor Cn, and a DC neutral point C. The power converter 30 also has semiconductor switching elements Q1 and Q4, semiconductor switching elements (neutral point elements) Q2 and Q3, an AC terminal AC, and a non-connection terminal NC. In this specification and drawings, the AC terminal AC is also referred to as the "AC (Alternating Current) terminal," and the non-connection terminal NC is also referred to as the "NC (No Connection) terminal."

[0039] The DC input / output section 31 is the DC terminal of the power converter 30 and has a positive terminal P and a negative terminal N that are connected to the solar cell 11 (DC power source or DC load).

[0040] The AC input / output section 32 is the AC terminal of the power converter 30 and has an AC terminal AC that is connected to the power system 15 (AC power source or AC load).

[0041] The positive terminal P and the negative terminal N are connected to the positive (P) and negative (N) sides of the solar cell (DC power supply) 11, respectively, via a DC cable 12.

[0042] Between the positive terminal P and the negative terminal N, a DC capacitor Cp and a DC capacitor Cn are connected in series via a DC neutral point C. Also, between the positive terminal P and the negative terminal N, a semiconductor switching element Q1 and a semiconductor switching element Q4 are connected in series with the same polarity via an AC terminal AC (AC terminal).

[0043] Between the DC neutral point C and the AC terminal AC, a semiconductor switching element (neutral point element) Q3 and a semiconductor switching element (neutral point element) Q2 are connected in series with reverse polarity via a non-connecting terminal NC (NC terminal).

[0044] Each semiconductor switching element Q1 to Q4 has a freewheeling diode D1 to D4, and the semiconductor switching elements Q1 to Q4 and the freewheeling diodes D1 to D4 are connected in antiparallel. The semiconductor switching elements Q1 to Q4 are semiconductor switching elements composed of, for example, IGBTs, and their on / off (conductive / non-conductive) operation is controlled by a gate signal G (see Figure 1, etc.) output from the control device 40.

[0045] In this specification and in the drawings, semiconductor switching elements Q1 and Q4 will also be referred to as "semiconductor elements Q1 and Q4," or simply "elements Q1 and Q4," respectively. Similarly, semiconductor switching elements Q2 and Q3 will also be referred to as "neutral point elements Q2 and Q3," "semiconductor elements Q2 and Q3," or simply "elements Q2 and Q3," respectively.

[0046] The freewheel diodes D1 to D4 are connected in antiparallel to the semiconductor switching elements Q1 to Q4, respectively, and are freewheel diodes that freewheel energy when, for example, the IGBT is turned off (non-conductive). In this specification and the drawings, the freewheel diodes D1 to D4 will also be referred to as "antiparallel diodes D1 to D4" or simply "diodes D1 to D4".

[0047] Figure 3 shows an example of the configuration of the control device 40 in the multilevel power conversion system 20 shown in Figure 1.

[0048] The control device 40 acquires the DC voltage Vdc detected by the DC voltage sensor 25 and the AC currents Iu, Iv, Iw detected by the AC current sensor 26, and outputs a gate signal G (see Figure 1, etc.) according to the control method described later. The control device 40 includes an acquisition unit 41, an output unit 42, a storage unit 43, a system bus 45, and a control unit 50. The acquisition unit 41, the output unit 42, the storage unit 43, and the control unit 50 are interconnected via the system bus 45.

[0049] The acquisition unit 41 is connected to the DC voltage sensor 25, the AC current sensor 26, and the system bus 45. The acquisition unit 41 may also be connected to a higher-level device (not shown). The acquisition unit 41 acquires, for example, the DC voltage Vdc detected by the DC voltage sensor 25 and the AC currents Iu, Iv, Iw detected by the AC current sensor 26. The acquisition unit 41 outputs, for example, each acquired voltage value and each current value to each component of the control device 40 via the system bus 45.

[0050] The output unit 42 is connected to the AC switch 24, the power converter 30, and the system bus 45. The output unit 42 may also be connected to higher-level devices, etc. (not shown). The output unit 42 outputs a gate signal G to the power converter 30 according to instructions received from the control unit 50 via the system bus 45, for example.

[0051] The storage unit 43 is a volatile or non-volatile storage medium such as an HDD (Hard Disk Drive), SSD (Solid State Drive), or other semiconductor memory, and is connected to the system bus 45. The storage unit 43 stores, for example, programs necessary for the operation of each part of the control device 40, and various types of information are written to and read from the storage unit 43 by each part of the control device 40. The storage unit 43 also stores, for example, values ​​detected by various sensors such as the DC voltage sensor 25 and the AC current sensor 26, instructions given by a higher-level device or operator (not shown), various calculation formulas and coefficients used in calculations by the control unit 50, predetermined thresholds and judgment values, etc.

[0052] The storage unit 43 is connected to various parts of the control device 40 via a system bus 45 or the like, enabling input and output of various types of information. The storage unit 43 may be located outside the control device 40 and connected to it by wire or wireless connection. Furthermore, the storage unit 43 may be an external storage medium such as a memory card or DVD (Digital Versatile Disc), or it may be online storage. Also, the storage unit 43 may be the same as the memory 92 (see Figure 30) described later.

[0053] The system bus (bus) 45 is a data transmission path (bus) that connects each component within the control device 40, and it interconnects the acquisition unit 41, the output unit 42, the storage unit 43, and the control unit 50 so that various types of information can be input and output.

[0054] The control unit 50 includes a processor 91 (see Figure 30), such as a CPU (Central Processing Unit), which operates by executing a program. The control unit 50 comprehensively controls the operation of the power conversion system 20 by operating the processor 91, for example, by executing a predetermined program stored in the storage unit 43 or the memory 92 (see Figure 30), which will be described later. The control unit 50 may also control the operation of the power conversion system 20 according to instructions received from a higher-level device (not shown) or instructions received from an operator (not shown) via an operation unit (not shown).

[0055] The control unit 50 functions as follows by executing a predetermined program stored in, for example, the storage unit 43 or the memory 92 (see Figure 30) described later. The control unit 50 functions as, for example, an operation control unit 51, a voltage command generation unit 52, and a gate signal generation unit 53. Note that each of the above functions may be realized by a program executed by the processor 91 (see Figure 30) described later in the processing circuit 90 (see Figure 30) of the control device 40 described later, or by the hardware 93 (see Figure 30) described later. Note that the operation control unit 51, the voltage command generation unit 52, and the gate signal generation unit 53 perform the following processing by executing a predetermined program.

[0056] The operation control unit 51 outputs an AC switch operation signal (see Figure 1, etc.) to the AC switch 24 based on predetermined conditions, and also comprehensively controls the operation of each part of the power conversion system 20.

[0057] The voltage command generation unit 52 generates three-phase voltage command values ​​Vu_ref, Vv_ref, and Vw_ref based, for example, on a predetermined output power command value P_ref and the three-phase AC currents Iu, Iv, and Iw detected by the AC current sensor 26. The voltage command generation unit 52 then outputs the generated three-phase voltage command values ​​Vu_ref, Vv_ref, and Vw_ref to the gate signal generation unit 53. Details of the control configuration or processing (operation) of the voltage command generation unit 52 in the control unit 50 (control block) will be described later (see Figure 4, etc.).

[0058] The gate signal generation unit 53 acquires the voltage command values ​​Vu_ref, Vv_ref, and Vw_ref output from the voltage command generation unit 52, and the DC voltage Vdc detected by the DC voltage sensor 25. The gate signal generation unit 53 also acquires triangular wave carriers (carrier waves) CA1 and CA2 having a predetermined carrier period, and an injection carrier CAin for predetermined carrier injection control. In this specification and drawings, the injection carrier CAin is a triangular wave signal in opposite phase to the triangular wave carriers (carrier waves) CA1 and CA2, and carrier injection control is the control of superimposing (injecting) the injection carrier CAin onto the modulated waves Du, Dv, and Dw.

[0059] The gate signal generation unit 53 generates a gate signal G (see Figure 1, etc.) based, for example, voltage command values ​​Vu_ref, Vv_ref, Vw_ref, DC voltage Vdc, triangular wave carriers CA1, CA2, and a predetermined injected carrier CAin. The gate signal generation unit 53 outputs the generated gate signal G to the power converter 30 to control the on / off (conductive / non-conductive) operation of semiconductor switching elements Q1 to Q4 (see Figure 2, etc.). Details of the control configuration or processing (operation) of the gate signal generation unit 53 in the control unit 50 (control block) will be described later (see Figures 5, 19 to 22, etc.).

[0060] <Example of a control configuration in one embodiment> Figure 4 shows an example of the control configuration in the voltage command generation unit 52 of the control unit 50 shown in Figure 3. Figure 4 illustrates the control configuration examples for the U-phase, V-phase, and W-phase, but in the following explanation, the control of the U-phase will be used as an example to explain the control common to each phase.

[0061] In step S11, the voltage command generation unit 52 obtains a predetermined output power command value P_ref and outputs a U-phase current command value Iu_ref based on the obtained output power command value P_ref. The predetermined output power command value P_ref is obtained, for example, based on the maximization of the amount of power generated from the solar cell 11, or based on predetermined calculation results based on predetermined power supply and power demand, or it is obtained from the storage unit 43 or a higher-level device (not shown).

[0062] In step S12, the voltage command generation unit 52 acquires the U-phase current command value Iu_ref output in the processing of step S11. The voltage command generation unit 52 also acquires the U-phase AC current Iu (U-phase current measurement value Iu) detected by the AC current sensor 26 (see Figure 1), for example, via the acquisition unit 41 (see Figure 3). Then, the voltage command generation unit 52 subtracts the acquired U-phase current measurement value Iu from the acquired U-phase current command value Iu_ref and outputs the subtracted value.

[0063] In step S13, the voltage command generation unit 52 performs proportional control based on the value output in the processing of step S12 and the proportional control gain Kp, and outputs the U-phase voltage command value Vu_ref obtained by proportional control to the gate signal generation unit 53 (see Figures 3, 5, etc.).

[0064] In steps S11 to S13, the voltage command generation unit 52 determines the V-phase voltage command value Vv_ref and the W-phase voltage command value Vw_ref, similar to the U-phase, and outputs the determined V-phase voltage command value Vv_ref and W-phase voltage command value Vw_ref to the gate signal generation unit 53.

[0065] The processing performed by the voltage command generation unit 52, as explained in Figure 4, is similar to the processing generally performed in the control of a typical power converter.

[0066] Figure 5 shows an example of the control configuration in the gate signal generation unit 53 of the control unit 50 shown in Figure 3. Figure 5 illustrates the control configuration examples for the U-phase, V-phase, and W-phase, but in the following explanation, the control of the U-phase will be used as an example to explain the control common to each phase.

[0067] In step S21, the gate signal generation unit 53 acquires the U-phase voltage command value Vu_ref(x) output from the voltage command generation unit 52 (see Figures 3 and 4, etc.). The gate signal generation unit 53 also acquires the value (y) obtained by applying a low-pass filter to the DC voltage Vdc detected by the DC voltage sensor 25 and dividing it by 1 / 2. The gate signal generation unit 53 divides the acquired value (x) by the acquired value (y) using a divider (x / y) to obtain the U-phase modulated wave Du, and outputs the obtained U-phase modulated wave Du. The modulated wave D is, for example, a voltage command value normalized by 1 / 2 of the DC voltage. In this case, it is obtained by dividing the voltage command value V_ref by the DC voltage Vdc obtained by applying a low-pass filter and dividing it by 1 / 2.

[0068] In step S22, the gate signal generation unit 53 acquires the U-phase modulated wave Du output in step S21 and the injected carrier CAin generated by the injected carrier generator 60. The gate signal generation unit 53 adds the acquired U-phase modulated wave Du and the acquired injected carrier CAin in an adder and performs carrier injection control to superimpose the U-phase modulated wave Du onto the injected carrier CAin, thereby generating a U-phase modulated wave Duca with carrier injection control. The gate signal generation unit 53 outputs the generated U-phase modulated wave Duca with carrier injection control.

[0069] Here, the injection carrier generator 60 generates an injection carrier CAin, which is a triangular wave signal that changes between a and -a, at the same carrier period as the carrier generators 61 and 62 that generate the triangular wave carriers CA1 and CA2. The injection carrier CAin is a triangular wave signal that is in opposite phase to the triangular wave carriers CA1 and CA2. The injection carrier generator 60 is added to the gate signal generation unit 53, for example, via software. Note that "between a and -a" is an example of "a predetermined amplitude range".

[0070] The value of a may be a value obtained by calculation, experiment, or simulation based on, for example, power demand or power supply, or a value instructed by a higher-level device or operator (not shown). The value of a is at least between 0 and 1, for example, 0.2 to 0.3 (20 to 30% of the amplitude of carrier waves CA1 and CA2). That is, the injected carrier CAin generated by the injected carrier generator 60 varies, for example, between 0.2 to 0.3(a) and -0.2 to -0.3(-a) (within a predetermined amplitude range), and is a triangular wave signal with the same carrier period and opposite phase as carrier waves CA1 and CA2.

[0071] Note that the value of a is not fixed, but may be dynamically varied according to the DC voltage conditions, modulation rate, etc. For example, when the DC voltage is low, increasing the value of a may increase the capacitor current, and when the DC voltage is high, increasing the value of a may decrease the capacitor current. Therefore, from the viewpoint of suppressing the capacitor current, when the DC voltage is low, the value of a may be decreased, and when the DC voltage is high, the value of a may be increased. For example, the gate signal generation unit 53 may decrease the value of a when the DC voltage Vdc detected by the DC voltage sensor 25 is below a predetermined threshold, and increase the value of a when it is above the predetermined threshold. In this way, by dynamically varying the value of a according to, for example, the DC voltage conditions, modulation rate, etc., rather than using a fixed value, the capacitor current can be suppressed according to the conditions more effectively than in the conventional method.

[0072] In step S23a, the gate signal generation unit 53 compares the carrier-injected U-phase modulated wave Duca output in step S22 with the triangular wave carrier CA1 generated by the carrier generator 61 using a comparator. The gate signal generation unit 53 outputs a signal of 1 if the carrier-injected U-phase modulated wave Duca is larger than the triangular wave carrier CA1, and outputs a signal of 0 if the U-phase modulated wave Duca is smaller than the triangular wave carrier CA1. The triangular wave carrier CA1 is a triangular wave signal that changes between 0 and 1 over a certain carrier period, i.e., the upper carrier wave. Hereinafter, in this specification and drawings, the triangular wave carrier CA1 will also be referred to as the "upper carrier wave CA1" or simply as the "carrier wave CA1".

[0073] In step S23b, the gate signal generation unit 53 compares the carrier-injected U-phase modulated wave Duca output in step S22 with the triangular wave carrier CA2 generated by the carrier generator 62 using a comparator. The gate signal generation unit 53 outputs a signal of 1 if the carrier-injected U-phase modulated wave Duca is larger than the triangular wave carrier CA2, and outputs a signal of 0 if the U-phase modulated wave Duca is smaller than the triangular wave carrier CA2. The triangular wave carrier CA2 is a triangular wave signal that changes between -1 and 0 over a certain carrier period, i.e., the lower carrier wave. Hereinafter, in this specification and drawings, the triangular wave carrier CA2 will also be referred to as the "lower carrier wave CA2" or simply the "carrier wave CA2".

[0074] In step S24a, the gate signal generation unit 53 generates a signal by delaying the value of the signal output in step S23a using a dead time generator and outputs it as the gate signal Gu1. Here, the gate signal Gu1 is a gate signal G1 that controls the switching operation of the U-phase semiconductor switching element Q1 (see Figure 2, etc.). The dead time generator is used to prevent short circuits caused by simultaneous conduction of semiconductor switching elements Q1 to Q4, and outputs a signal with a delayed rise time of the pulse command value.

[0075] In step S24b, the gate signal generation unit 53 generates a signal by delaying the negative logic (NOT) value of the signal output in step S23a using a dead time generator, and outputs it as the gate signal Gu3. That is, the gate signal generation unit 53 generates a signal by delaying the signal output in step S23a by 1 when it is 0, and by delaying it by 0 when it is 1, and outputs it as the gate signal Gu3. Here, the gate signal Gu3 is a gate signal G3 that controls the switching operation of the U-phase semiconductor switching element (neutral point element) Q3 (see Figure 2, etc.).

[0076] In step S24c, the gate signal generation unit 53 generates a signal that is delayed by the dead time generator from the signal output in step S23b and outputs it as the gate signal Gu2. Here, the gate signal Gu2 is a gate signal G2 that controls the switching operation of the U-phase semiconductor switching element (neutral point element) Q2 (see Figure 2, etc.).

[0077] In step S24d, the gate signal generation unit 53 generates a signal by delaying the negative logic (NOT) value of the signal output in step S23b using a dead time generator, and outputs it as the gate signal Gu4. That is, the gate signal generation unit 53 generates a signal by delaying the signal output in step S23b by 1 when it is 0, and by delaying it by 0 when it is 1, and outputs it as the gate signal Gu4. Here, the gate signal Gu4 is a gate signal G4 that controls the switching operation of the U-phase semiconductor switching element Q4 (see Figure 2, etc.).

[0078] Furthermore, the gate signal generation unit 53 performs the same processing in the V-phase and W-phase as in the U-phase, as shown in steps S21 to S24d above. That is, the gate signal generation unit 53 generates and outputs gate signals Gv1 to Gv4 and Gw1 to Gw4 (G1 to G4) that control the operation of the semiconductor switching elements Q1 to Q4 in the V-phase and W-phase, respectively, just as in the U-phase.

[0079] As described above, the control configuration example of one embodiment shown in Figures 1 to 5 includes control content that differs from the control of a 3-level (multilevel) power converter that uses a normal carrier-level shift modulation method. In other words, normally, the control is performed by comparing the modulated wave D, which is obtained by normalizing the voltage command value V_ref of each phase, with the triangular wave carriers CA1 and CA2, then feeding the result into a dead time generator before generating and outputting gate signals G1 to G4.

[0080] On the other hand, in one embodiment shown in Figures 1 to 5, the gate signal generation unit 53 acquires a modulated wave D obtained by normalizing the voltage command value V_ref of each phase, and an injected carrier CAin generated by the injected carrier generator 60. The injected carrier CAin changes between a and -a (within a predetermined amplitude range) and is a triangular wave signal with the same carrier period and opposite phase as the carrier waves CA1 and CA2. The gate signal generation unit 53 then performs carrier injection control to superimpose the modulated wave D onto the injected carrier CAin, thereby generating a modulated wave Dca under carrier injection control. The gate signal generation unit 53 then compares the modulated wave Dca under carrier injection control with the triangular wave carriers CA1 and CA2, feeds the result into a dead time generator, and generates and outputs gate signals G1 to G4.

[0081] In other words, in one embodiment, the gate signal generation unit 53 has a distinctive configuration of an injection carrier generator 60 that generates an injection carrier CAin, which is a triangular wave signal that changes between a and -a and has the same carrier period and opposite phase as the carrier waves CA1 and CA2. The gate signal generation unit 53 is characterized by generating and outputting gate signals G1 to G4 based on a modulated wave Dca, on which carrier injection control is performed to superimpose a modulated wave D onto the injection carrier CAin.

[0082] <Principle of Harmonic Generation> Before describing the processing (operation) and effects of one embodiment shown in Figures 1 to 5, the principle of harmonic generation will be explained using a comparative example multilevel power conversion system 120 that employs a normal carrier-level shift modulation scheme. Similar to the embodiment shown in Figures 1 to 5, the following comparative example will use a three-level power conversion system 120 as an example of the multilevel power conversion system 120. Hereafter, in this specification and the drawings, the multilevel power conversion system 120 and the three-level power conversion system 120 will also be simply referred to as "power conversion system 120".

[0083] Figure 6 shows an example of the control configuration in the gate signal generation unit 153 according to a comparative example. Figure 6 illustrates the control configuration examples for the U-phase, V-phase, and W-phase, but in the following explanation, the control of the U-phase will be used as an example to explain the control common to each phase.

[0084] In the following comparative examples, the gate signal generation unit 53 shown in Figures 3 and 5 of the power conversion system 20 according to one embodiment shown in Figures 1 to 5 is replaced by a gate signal generation unit 153. The other components of the power conversion system 120 in the following comparative examples are the same as or similar to those of the power conversion system 20 according to one embodiment shown in Figures 1 to 5. Therefore, in the following comparative examples, the same or similar components as those of the power conversion system 20 according to one embodiment shown in Figures 1 to 5 are denoted by the same reference numerals, and detailed descriptions and illustrations are omitted.

[0085] Step S121 involves the same or similar processing as step S21 shown in Figure 5, so its explanation is omitted. Here, as shown in Figure 6, the gate signal generation unit 153 according to the comparative example differs from the gate signal generation unit 53 according to one embodiment shown in Figure 5 in that it does not have an injection carrier generator 60. Therefore, the gate signal generation unit 153 according to the comparative example shown in Figure 6 does not perform the processing of step S22 in the gate signal generation unit 53 according to one embodiment shown in Figure 5.

[0086] In step S123a, the gate signal generation unit 153 compares the U-phase modulated wave Du output in step S121 with the triangular wave carrier (upper carrier wave) CA1 generated by the carrier generator 61 using a comparator. The gate signal generation unit 153 outputs a signal of 1 when the U-phase modulated wave Du is greater than the triangular wave carrier CA1, and outputs a signal of 0 when the U-phase modulated wave Du is less than the triangular wave carrier CA1.

[0087] In step S123b, the gate signal generation unit 153 compares the U-phase modulated wave Du output in step S121 with the triangular wave carrier (lower carrier wave) CA2 generated by the carrier generator 62 using a comparator. The gate signal generation unit 153 outputs a signal of 1 when the U-phase modulated wave Du is greater than the triangular wave carrier CA2, and outputs a signal of 0 when the U-phase modulated wave Du is less than the triangular wave carrier CA2.

[0088] In step S124a, the gate signal generation unit 153 generates a signal by delaying the value of the signal output in step S123a using a dead time generator, and outputs it as the gate signal Gu1.

[0089] In step S124b, the gate signal generation unit 153 generates a signal by delaying the negative logic (NOT) value of the signal output in step S123a using a dead time generator, and outputs it as the gate signal Gu3.

[0090] In step S124c, the gate signal generation unit 153 generates a signal that is delayed by the dead time generator from the signal output in step S123b and outputs it as the gate signal Gu2.

[0091] In step S124d, the gate signal generation unit 153 generates a signal by delaying the negative logic (NOT) value of the signal output in step S123b using a dead time generator, and outputs it as the gate signal Gu4.

[0092] Furthermore, the gate signal generation unit 153 performs the same processing as in the U phase for the V phase and W phase, as shown in steps S121 to S124d above, to generate and output gate signals Gv1 to Gv4 and Gw1 to Gw4.

[0093] Figure 7 shows an example of carrier level shift modulation in the gate signal generation unit 153 related to the comparative example shown in Figure 6. In Figure 7, the vertical axis represents voltage and the horizontal axis represents time. The thick solid line in the center shows the waveform of the modulated wave D, the dashed line in the upper panel shows the waveform of the upper carrier wave CA1, and the solid line in the lower panel shows the waveform of the lower carrier wave CA2. In the following explanation, the circuit configuration of the power converter (inverter) 30 on which carrier level shift modulation is performed is assumed to be the 3-level NPP circuit configuration shown in Figure 2.

[0094] As shown in Figure 7, the carrier-level shift modulation scheme is a modulation method that generates gate signals G1 to G4 for each semiconductor element Q1 to Q4 by comparing carrier waves CA1 and CA2, which have a DC offset superimposed on them, with the modulated wave D. In other words, in carrier-level shift modulation, a DC offset is superimposed equally on each carrier wave CA1 and CA2, and the magnitudes of the carrier waves CA1 and CA2 and the modulated wave D are compared to generate a gate signal G according to a predetermined switching pattern described later (see Figure 8).

[0095] Figure 8 shows an example of a switching pattern in carrier-level shift modulation. In Figure 8, Uu represents the voltage of the upper carrier wave CA1 shown in Figure 7, Ul represents the voltage of the lower carrier wave CA2 shown in Figure 7, and Um represents the voltage of the modulated wave D shown in Figure 7. Also in Figure 8, Q1 to Q4 represent the semiconductor elements Q1 to Q4 shown in Figure 2, and ON and OFF represent the on and off states of the gate signals G1 to G4 of each semiconductor element Q1 to Q4.

[0096] As shown in Figure 8, for example, when Um > Uu > Ul, semiconductor element Q1 is ON (conducting), semiconductor element Q2 is ON (conducting), semiconductor element Q3 is OFF (non-conducting), and semiconductor element Q4 is OFF (non-conducting). Similarly, for example, when Uu > Um > Ul, semiconductor element Q1 is OFF (non-conducting), semiconductor element Q2 is ON (conducting), semiconductor element Q3 is ON (conducting), and semiconductor element Q4 is OFF (non-conducting). Similarly, for example, when Uu > Ul > Um, semiconductor element Q1 is OFF (non-conducting), semiconductor element Q2 is OFF (non-conducting), semiconductor element Q3 is ON (conducting), and semiconductor element Q4 is ON (conducting).

[0097] Figure 9 shows an example of gate signals G1 to G4 for each semiconductor element Q1 to Q4 in carrier level shift modulation of the switching pattern shown in Figure 8. In Figure 9, Figure 9(a) shows an example of carrier level shift modulation in a 3-level NPP scheme related to the comparative example shown in Figure 7, and Figures 9(b) to 9(e) show examples of gate signals G1 to G4 for each semiconductor element Q1 to Q4 corresponding to Figure 9(a). In Figures 9(b) to 9(e), when the pulse line is positioned at the top, it indicates that the gate signal G1 to G4 is ON (1), and when it is positioned at the bottom, it indicates that the gate signal G1 to G4 is OFF (0).

[0098] As shown in Figure 9, the gate signals G1 to G4 of each semiconductor element Q1 to Q4 are generated according to a predetermined switching pattern shown in Figure 8. Note that the ON (1) and OFF (0) states of each gate signal G1 to G4 correspond to the ON (conducting) and OFF (non-conducting) states of each semiconductor element Q1 to Q4.

[0099] That is, as shown in Figures 8 and 9, for example, gate signal G1 is ON (1) if Um>Uu>Ul, OFF (0) if Uu>Um>Ul, and OFF (0) if Uu>Ul>Um. Similarly, for example, gate signal G2 is ON (1) if Um>Uu>Ul, ON (1) if Uu>Um>Ul, and OFF (0) if Uu>Ul>Um. Similarly, for example, gate signal G3 is OFF (0) if Um>Uu>Ul, ON (1) if Uu>Um>Ul, and ON (1) if Uu>Ul>Um. Similarly, for example, gate signal G4 is OFF (0) if Um>Uu>Ul, OFF (0) if Uu>Um>Ul, and ON (1) if Uu>Ul>Um.

[0100] Figure 10 is a schematic diagram of the harmonic spectra of the output voltages of each phase of a power converter 30 using carrier-level shift modulation. In Figure 10, the vertical axis represents the magnitude of the harmonic spectrum, and the horizontal axis represents the frequency. Furthermore, fc represents the carrier frequency, and fo represents the fundamental frequency (modulation frequency).

[0101] As shown in Figure 10, each phase output voltage has harmonics that are integer multiples of the carrier frequency fc, and harmonics called sidebands that arise from the relationship between the carrier frequency fc and the fundamental frequency fo. For example, in Figure 10, harmonics that are integer multiples of the carrier frequency fc are, for example, 3fc. Note that 2fc is not shown in Figure 10 because, due to its positive and negative relationship, it cancels out when calculated (added). Also, in Figure 10, harmonics called sidebands refer to frequency components that occur in the high and low frequencies centered around the carrier frequency fc (or frequency components that are integer multiples of the carrier frequency fc), such as fc±2fo.

[0102] Here, a low-pass filter, such as an LC filter, is used as the filter for the power converter (inverter) 30 to suppress the harmonic components of the output voltage. Harmonic components in the relatively high frequency band (for example, the right side of Figure 10) do not pose a major problem because their energy can be easily attenuated by this filter. On the other hand, attenuating harmonic components in the relatively low frequency band (for example, the left side of Figure 10) requires a large filter, which poses a problem.

[0103] In other words, a low-pass filter can attenuate the energy of signals above the cutoff frequency, with the higher the frequency, the more the signal energy is reduced. Therefore, it is easy for a low-pass filter to attenuate high-frequency components, but difficult to attenuate low-frequency components. To attenuate low-frequency components, for example, in the case of an LC filter, one would need to increase the size of the filter by increasing the L and C values, but this would lead to larger equipment and increased costs. Consequently, there is a need to suppress harmonics around the carrier frequency fc, which are relatively low-frequency harmonics.

[0104] Figure 11 shows an enlarged view of the area around the 0 crossing in Figure 7 and an example of the gate signals G1 to G4 for each semiconductor element Q1 to Q4 at that time. Figure 11(a) shows an enlarged view of the area around the 0 crossing in Figure 7. Figure 11(b) shows an example of the gate signals G1 and G4 for semiconductor elements Q1 and Q4 corresponding to Figure 11(a). Figure 11(c) shows an example of the gate signals G2 and G3 for semiconductor elements Q2 and Q3 corresponding to Figure 11(a).

[0105] In Figure 11(a), as in Figure 7, the vertical axis represents voltage and the horizontal axis represents time. The thick solid line in the center shows the waveform of the modulated wave D, the dashed line in the upper panel shows the waveform of the upper carrier wave CA1, and the solid line in the lower panel shows the waveform of the lower carrier wave CA2. In Figures 11(b) and (c), as in Figures 9(b) to 9(e), the gate signals G1 to G4 of each semiconductor element Q1 to Q4 are generated according to the predetermined switching pattern shown in Figure 8.

[0106] As shown in Figures 11(a) to 11(c), in the comparative example where carrier injection control is not performed, the number of switching cycles is small near the 0-crossing point. On the other hand, when carrier injection control according to one embodiment is performed, due to the influence of the injected carrier CAin, a section occurs near the 0-crossing point where semiconductor elements Q1 and Q4 conduct instead of semiconductor elements (neutral point elements) Q2 and Q3. As a result, when carrier injection control according to one embodiment is performed, the number of switching cycles near the 0-crossing point increases, for example, by about twice as much (see Figure 20, etc.).

[0107] Figure 12 is a schematic diagram showing an example of the relationship between the modulated wave D, carrier waves CA1 and CA2, and the output voltages of each phase near the peak of the modulated wave D shown in Figure 7. In Figure 12, as in Figure 7, the vertical axis represents voltage and the horizontal axis represents time. The thick solid line in the upper panel shows the waveform of the modulated wave D, the dashed line in the upper panel shows the waveform of the upper carrier wave CA1, the solid line in the middle shows the waveform of the lower carrier wave CA2, and the dashed lines in the lower panel show the output voltage pulses of each phase.

[0108] As shown in Figure 12, near the peak of the modulated wave D in the upper panel, the slope of the modulated wave D is almost 0 (zero), and the center of each phase output voltage pulse in the lower panel coincides with the troughs of the carrier waves CA1 and CA2. In this case, the fundamental frequency fo of each phase voltage is equal to the carrier frequency fc.

[0109] Figure 13 shows an example of the Fourier series expansion of the square waves of each phase output voltage shown in Figure 12. In Figure 13, the vertical axis represents voltage and the horizontal axis represents time. In Figure 13, the solid lines represent the waveforms of each phase output voltage, and each sine wave represents the components that arise when each phase output voltage is expanded into a Fourier series. The largest sine wave, drawn with a large dashed line, represents the carrier frequency fc, the slightly smaller sine wave, drawn with a solid line, represents a frequency of 3fc (3 times the carrier frequency), and the smallest sine wave, drawn with a fine dashed line, represents a frequency of 5fc (5 times the carrier frequency).

[0110] As shown in Figure 13, each phase output voltage, when subjected to a Fourier transform (Fourier series expansion), has frequency components that are integer multiples of the carrier frequency fc. The harmonics (3fc, 5fc, etc.) that are integer multiples of the carrier frequency fc, as explained in Figure 10 above, are generated by the principle shown in Figure 13.

[0111] Here, the slope of the modulated wave D is almost zero near the peak of the modulated wave D, but it gradually changes significantly as it approaches the zero-cross point. Therefore, next we will examine the vicinity of the zero-cross point of the modulated wave D.

[0112] Figure 14 shows an example of the relationship between the sign of the modulated wave D and its slope. The center column of Figure 14 shows the sign of the modulated wave D, the right column shows the sign of the modulated wave D, and the left column shows the various patterns of these relationships.

[0113] As shown in Figure 14, Pattern 1 is the case where the sign of the modulated wave D is positive and the slope of the modulated wave D is also positive. Similarly, Pattern 2 is the case where the sign of the modulated wave D is positive and the slope of the modulated wave D is negative, Pattern 3 is the case where the sign of the modulated wave D is negative and the slope of the modulated wave D is also negative, and Pattern 4 is the case where the sign of the modulated wave D is negative and the slope of the modulated wave D is positive. When considering the vicinity of the 0 crossover of the modulated wave D, we will consider the sign and slope of the modulated wave D and examine the following four patterns of intervals shown in Figure 14.

[0114] Figure 15 is a schematic diagram showing an example of the relationship between the modulated wave D, carrier waves CA1 and CA2, and the output voltages of each phase in Pattern 1 shown in Figure 14. In Figure 15, as in Figure 12, the vertical axis represents voltage and the horizontal axis represents time. The thick solid line in the upper panel shows the waveform of the modulated wave D, the dashed line in the upper panel shows the waveform of the upper carrier wave CA1, the solid line in the center shows the waveform of the lower carrier wave CA2, and the dashed lines in the lower panel show the output voltage pulses of each phase. Note that in Figure 15, since the modulated wave D intersects with the upper carrier wave CA1, the upper part of the dashed pulse in the lower panel is DC voltage and the lower part of the pulse is 1 / 2 DC voltage.

[0115] As shown in Figure 15, in Pattern 1, where the sign of the modulated wave D is positive and the slope of the modulated wave D is also positive, the center of each phase output voltage pulse shifts to the right. Therefore, a phase difference occurs between the center of each phase output voltage pulse in the lower section and the troughs of the carrier waves CA1 and CA2. Also, since the slope of a sine wave increases as it approaches zero crossing, the phase shift is considered to be larger for pulses closer to zero crossing. Consequently, the period T of each phase output voltage becomes shorter than the period of the carrier.

[0116] In other words, in Pattern 1, as shown in Figure 15, the period T from the center of one output voltage pulse to the center of the next output voltage pulse is shorter than the period from the dashed line extending downward from one carrier trough to the dashed line extending downward from the next carrier trough. In other words, in the section of Pattern 1, the frequency of each phase output voltage is higher than the carrier frequency. This is the cause of the generation of sidebands, which are high-frequency and low-frequency components centered around the carrier frequency.

[0117] Figure 16 is a schematic diagram showing an example of the relationship between the modulated wave D, carrier waves CA1 and CA2, and the output voltages of each phase in pattern 2 shown in Figure 14. In Figure 16, the vertical axis, horizontal axis, and the meanings of each line are the same as in Figure 15. Note that in Figure 16, since the modulated wave D intersects with the upper carrier wave CA1, the upper part of the dashed-dotted pulse in the lower section is the DC voltage, and the lower part of the pulse is the 1 / 2 DC voltage.

[0118] As shown in Figure 16, in pattern 2, where the sign of the modulated wave D is positive and the slope of the modulated wave D is negative, the center of each phase output voltage pulse shifts to the left. Therefore, a phase difference occurs between the center of each phase output voltage pulse in the lower section and the troughs of the carrier waves CA1 and CA2. Also, since the slope of a sine wave increases as it approaches zero, the pulses closer to zero are thought to have a larger phase shift. Consequently, the period T of each phase output voltage becomes shorter than the period of the carrier.

[0119] In other words, in pattern 2, as shown in Figure 16, the period T from the center of one output voltage pulse to the center of the next output voltage pulse is shorter than the period from the dashed line extending downward from one carrier trough to the dashed line extending downward from the next carrier trough. In other words, in the section of pattern 2, the frequency of each phase output voltage is higher than the carrier frequency. This is the cause of the generation of sidebands, which are high-frequency and low-frequency components centered around the carrier frequency.

[0120] Figure 17 is a schematic diagram showing an example of the relationship between the modulated wave D, carrier waves CA1 and CA2, and the output voltages of each phase in pattern 3 shown in Figure 14. In Figure 17, the vertical axis, horizontal axis, and the meanings of each line are the same as in Figure 15. Note that in Figure 17, since the modulated wave D intersects with the lower carrier wave CA2, the upper part of the dashed-dotted pulse in the lower section is 1 / 2 DC voltage, and the lower part of the pulse is 0.

[0121] As shown in Figure 17, in pattern 3, where the sign of the modulated wave D is negative and the slope of the modulated wave D is also negative, the center of each phase output voltage pulse shifts to the left. Therefore, a phase difference occurs between the center of each phase output voltage pulse in the lower section and the troughs of the carrier waves CA1 and CA2. Also, since the slope of a sine wave increases as it approaches zero crossing, the phase shift is considered to be larger for pulses closer to zero crossing. Consequently, the period T of each phase output voltage becomes longer than the period of the carrier.

[0122] In other words, in pattern 3, as shown in Figure 17, the period T from the center of one output voltage pulse to the center of the next output voltage pulse is longer than the period from the dashed line extending downward from one carrier trough to the dashed line extending downward from the next carrier trough. In other words, in the section of pattern 3, the frequency of each phase output voltage is lower than the carrier frequency. This is the cause of the generation of sidebands, which are high-frequency and low-frequency components centered around the carrier frequency.

[0123] Figure 18 is a schematic diagram showing an example of the relationship between the modulated wave D, carrier waves CA1 and CA2, and the output voltages of each phase in pattern 4 shown in Figure 14. In Figure 18, the vertical axis, horizontal axis, and the meanings of each line are the same as in Figure 15. Note that in Figure 18, since the modulated wave D intersects with the lower carrier wave CA2, the upper part of the dashed-dotted pulse in the lower section is 1 / 2 DC voltage, and the lower part of the pulse is 0.

[0124] As shown in Figure 18, in pattern 4, where the sign of the modulated wave D is negative and the slope of the modulated wave D is positive, the center of each phase output voltage pulse shifts to the right. Therefore, a phase difference occurs between the center of each phase output voltage pulse in the lower section and the troughs of the carrier waves CA1 and CA2. Also, since the slope of a sine wave increases as it approaches zero crossing, the pulse closer to zero crossing is thought to have a larger phase shift. Consequently, the period T of each phase output voltage becomes longer than the period of the carrier.

[0125] In other words, in pattern 4, as shown in Figure 18, the period T from the center of one output voltage pulse to the center of the next output voltage pulse is longer than the period from the dashed line extending downward from one carrier trough to the dashed line extending downward from the next carrier trough. In other words, in the section of pattern 4, the frequency of each phase output voltage is lower than the carrier frequency. This is the cause of the generation of sidebands, which are high-frequency and low-frequency components centered around the carrier frequency.

[0126] As shown in Figures 14 to 18 above, in the section where the slope of the modulated wave D is large, the frequency of each phase output voltage shifts slightly from the carrier frequency fc. This frequency component that is slightly shifted from the carrier frequency fc becomes the sideband component. In other words, when each phase output voltage, which has a frequency component that is slightly shifted from the carrier frequency, is subjected to a Fourier transform (Fourier series expansion) as shown in Figure 13, it is decomposed into frequency components that are slightly shifted from the harmonic components shown in Figure 13. These frequency components that are slightly shifted from the harmonic components become the sideband components.

[0127] Furthermore, sideband components with large spectra that are close to the carrier frequency fc occur near the 0 crossover point where the rate of change in slope is small. In other words, as explained in patterns 1 to 4 in Figures 15 to 18, the change in the slope of the modulated wave D causes the frequency of each phase output voltage to shift from the carrier frequency fc, and this frequency shift is the cause of sideband generation.

[0128] Here, the magnitude of the frequency shift decreases as the rate of change of the slope of the modulated wave D decreases. Near the 0 crossing of the modulated wave D, the rate of change of the slope is small, so the frequency shift of each phase output voltage is relatively small. Therefore, it is thought that the sidebands with relatively low frequency bands (frequency components relatively close to the carrier frequency fc) in Figure 10 are generated near the 0 crossing of the modulated wave D. On the other hand, near the peak of the modulated wave D, the rate of change of the slope is large, so the frequency shift of each phase output voltage is relatively large. Therefore, it is thought that the sidebands with relatively high frequency bands (frequency components relatively far from the carrier frequency fc) in Figure 10 are generated near the peak of the modulated wave D.

[0129] As explained in Figure 10, harmonic components in the relatively high frequency band (e.g., the right side of Figure 10) do not pose a major problem because their energy can be easily attenuated by filtering. On the other hand, attenuating harmonic components in the relatively low frequency band (e.g., the left side of Figure 10) requires a large filter, which poses a problem. In this regard, when carrier injection control according to one embodiment is performed, the switching pattern changes near the 0 crossover, so countermeasures can be taken precisely near the 0 crossover (see Figure 20, etc.). As a result, when carrier injection control according to one embodiment is performed, sideband components with large spectra near the carrier frequency fc, which is in the relatively high frequency band, can be suppressed precisely and effectively (see Figure 23, etc.).

[0130] <Processing (operation) of one embodiment> Based on the harmonic generation principle explained above using the comparative examples shown in Figures 6 to 18, the processing (operation) of one embodiment shown in Figures 1 to 5 will now be described.

[0131] Figure 19 shows an example of the relationship between carrier waves CA1, CA2 and modulated wave Dca when carrier injection control is performed in the gate signal generation unit 53 according to one embodiment shown in Figure 5. In Figure 19, as in Figure 7, the vertical axis represents voltage and the horizontal axis represents time. The thick solid line in the center shows the waveform of the modulated wave Dca under carrier injection control, the dashed line in the upper panel shows the waveform of the upper carrier wave CA1, and the solid line in the lower panel shows the waveform of the lower carrier wave CA2.

[0132] As shown in Figure 19, the carrier level shift modulation scheme when carrier injection control is performed is a modulation scheme that generates the gate signals G1 to G4 for each semiconductor element Q1 to Q4 by comparing the carrier waves CA1 and CA2 with the modulated wave Dca under carrier injection control. That is, in carrier level shift modulation with carrier injection control, as explained in Figure 5, the gate signal generation unit 53 superimposes the modulated wave Dca under carrier injection control onto the injected carrier CAin to obtain the modulated wave Dca under carrier injection control. The gate signal generation unit 53 then compares the magnitude of the carrier waves CA1 and CA2 generated by the carrier generators 61 and 62 with the obtained modulated wave Dca and generates gate signals G1 to G4 according to a predetermined switching pattern, for example, as shown in Figure 8. The injected carrier CAin changes between a and -a (within a predetermined amplitude range), as described in Figure 5, and is a triangular wave signal with the opposite phase and the same carrier period as the triangular wave carriers (carrier waves) CA1 and CA2.

[0133] Figure 20 shows an enlarged view of the vicinity of the 0 crossing in Figure 19 and an example of the gate signals G1 to G4 for each semiconductor element Q1 to Q4 at that time. Figure 20(a) shows an enlarged view of the vicinity of the 0 crossing in Figure 19. Figure 20(b) shows an example of the gate signals G1 and G4 for semiconductor elements Q1 and Q4 corresponding to Figure 20(a). Figure 20(c) shows an example of the gate signals G2 and G3 for semiconductor elements Q2 and Q3 corresponding to Figure 20(a).

[0134] In Figure 20(a), as in Figure 7, the vertical axis represents voltage and the horizontal axis represents time. The thick solid line in the center shows the waveform of the modulated wave Dca under carrier injection control, the dashed line in the upper panel shows the waveform of the upper carrier wave CA1, and the solid line in the lower panel shows the waveform of the lower carrier wave CA2. In Figures 20(b) and (c), as in Figures 11(b) and (c), the gate signals G1 to G4 of each semiconductor element Q1 to Q4 are generated according to a predetermined switching pattern, for example, as shown in Figure 8.

[0135] As shown in Figures 20(a) to 20(c), when carrier injection control is performed, the number of switching cycles near the 0 crossover increases compared to when carrier injection control is not performed, as shown in Figures 11(a) to 11(c), increasing by, for example, about twice as much. This is because, when carrier injection control is performed, due to the influence of the injected carrier CAin, a section occurs near the 0 crossover where semiconductor elements Q1 and Q4 conduct instead of semiconductor elements (neutral point elements) Q2 and Q3.

[0136] Figure 21 is a schematic diagram showing an example of the relationship between the modulated wave Dca, carrier waves CA1 and CA2, and the output voltages of each phase during a period when the slope of the modulated wave Dca is negative. In Figure 21, as in Figures 15 to 18, the vertical axis represents voltage and the horizontal axis represents time. The thick solid line in the upper panel shows the waveform of the modulated wave Dca under carrier injection control, the dashed line in the upper panel shows the waveform of the upper carrier wave CA1, the solid line in the middle shows the waveform of the lower carrier wave CA2, and the dashed line in the lower panel shows the output voltage pulses of each phase. Note that in Figure 21, since the modulated wave Dca intersects both the upper carrier wave CA1 and the lower carrier wave CA2, the top of the dashed line pulse in the lower panel is a DC voltage, the middle of the pulse is a 1 / 2 DC voltage, and the bottom of the pulse is 0.

[0137] As shown in Figure 21, in patterns 2 and 3 shown in Figure 14, where the slope of the modulated wave Dca is negative during certain periods, the center of the peak of each phase output voltage pulse shifts to the left from the carrier trough. Conversely, in this case, the center of the trough of each phase output voltage pulse shifts to the right from the carrier peak. Therefore, the frequency of each phase output voltage in section T1 is lower than the carrier frequency fc. On the other hand, the frequency of each phase output voltage in section T2 is higher than the carrier frequency fc.

[0138] In other words, in Figure 21, when the slope of the modulated wave Dca is negative, the interval T1 from the center of the peak of the left output voltage pulse to the center of the trough of the next output voltage pulse is longer than the period from the dashed line extending downward from the trough of the left carrier to the dashed line extending downward from the peak of the next carrier. In other words, as shown in Figure 21, since interval T1 is longer than half a period of carrier waves CA1 and CA2, the frequency of each phase output voltage in interval T1 is smaller than the carrier frequency fc.

[0139] On the other hand, in this case, in Figure 21, the interval T2 from the center of the trough of the central output voltage pulse to the center of the peak of the next output voltage pulse is shorter than the period from the dashed line extending downward from the peak of the central carrier to the dashed line extending downward from the trough of the next carrier. In other words, as shown in Figure 21, since interval T2 is shorter than half a period of carrier waves CA1 and CA2, the frequency of each phase output voltage in interval T2 is greater than the carrier frequency fc.

[0140] Thus, in patterns 2 and 3 shown in Figure 14, where the slope of the modulated wave Dca is negative during certain periods, each phase output voltage has a period T1 with a frequency lower than the carrier frequency fc and a period T2 with a frequency higher than the carrier frequency fc within one period.

[0141] Figure 22 is a schematic diagram showing an example of the relationship between the modulated wave Dca, carrier waves CA1 and CA2, and the output voltages of each phase during a period when the slope of the modulated wave Dca is positive. In Figure 22, as in Figures 15 to 18, the vertical axis represents voltage and the horizontal axis represents time. The thick solid line in the upper panel shows the waveform of the modulated wave Dca under carrier injection control, the dashed line in the upper panel shows the waveform of the upper carrier wave CA1, the solid line in the middle shows the waveform of the lower carrier wave CA2, and the dashed line in the lower panel shows the output voltage pulses of each phase. Note that in Figure 22, since the modulated wave Dca intersects both the upper carrier wave CA1 and the lower carrier wave CA2, the top of the dashed line pulse in the lower panel is a DC voltage, the middle of the pulse is a 1 / 2 DC voltage, and the bottom of the pulse is 0.

[0142] As shown in Figure 22, in patterns 1 and 4 shown in Figure 14, where the slope of the modulated wave Dca is positive, the center of the peak of each phase output voltage pulse shifts to the right from the carrier trough. Conversely, in this case, the center of the trough of each phase output voltage pulse shifts to the left from the carrier peak. Therefore, the frequency of each phase output voltage in section T3 is greater than the carrier frequency fc. On the other hand, the frequency of each phase output voltage in section T4 is less than the carrier frequency fc.

[0143] In other words, in Figure 22, when the slope of the modulated wave Dca is positive, the interval T3, from the center of the peak of the left output voltage pulse to the center of the trough of the next output voltage pulse, is shorter than the period from the dashed line extending downward from the trough of the left carrier to the dashed line extending downward from the peak of the next carrier. In other words, as shown in Figure 22, since interval T3 is shorter than half a period of carrier waves CA1 and CA2, the frequency of each phase output voltage in interval T3 is greater than the carrier frequency fc.

[0144] On the other hand, in this case, in Figure 22, the period from the center of the trough of the central output voltage pulse to the center of the peak of the next output voltage pulse is longer than the period from the dashed line extending downward from the peak of the central carrier to the dashed line extending downward from the trough of the next carrier. In other words, as shown in Figure 22, since the period T4 is longer than half a period of the carrier waves CA1 and CA2, the frequency of each phase output voltage in the period T4 is smaller than the carrier frequency fc.

[0145] Thus, in patterns 1 and 4 shown in Figure 14, where the slope of the modulated wave Dca is positive during certain periods, each phase output voltage has a period T3 with a frequency higher than the carrier frequency fc and a period T4 with a frequency lower than the carrier frequency fc within one period.

[0146] As shown in Figures 21 and 22 above, a 180-degree phase difference exists between the output voltages of each phase when the slope of the modulated wave Dca is positive and when the slope of the modulated wave Dca is negative. In this case, the sidebands generated when the slope of the modulated wave Dca is positive and the sidebands generated when the slope of the modulated wave Dca is negative cancel each other out. That is, for example, assuming that the period T of the Fourier series expansion is the fundamental frequency fo (e.g., 50 Hz or 60 Hz), high-frequency components with equal amplitude and a 180-degree phase difference will cancel each other out through integral calculation within the period T of the Fourier series expansion. Therefore, these components do not appear in the harmonic spectrum. Consequently, when carrier injection control is performed, the sideband components at carrier frequency fc can be suppressed.

[0147] <Effects of one embodiment> Figure 23 shows an example of the harmonic spectrum of the DC voltage-normalized line output voltage in the case where carrier injection control is not performed and in the case where carrier injection control is performed. Figure 23(a) shows an example of the harmonic spectrum of the DC voltage-normalized line output voltage in a power conversion system 120 in which carrier injection control is not performed, according to the comparative example shown in Figures 6 to 18. Figure 23(b) shows an example of the harmonic spectrum of the DC voltage-normalized line output voltage in a power conversion system 20 in which carrier injection control is performed according to one embodiment shown in Figures 1 to 5 and Figures 19 to 22.

[0148] In Figures 23(a) and (b), the vertical axis represents the magnitude of the harmonic spectrum, and the horizontal axis represents the frequency. Furthermore, fc represents the frequency component of the carrier frequency, and 2fc to 4fc represent the frequency components that are integer multiples of the carrier frequency fc.

[0149] As shown in Figure 23(a), when carrier injection control is not performed, sideband components are spread to the high and low frequencies of each harmonic that is an integer multiple of the carrier frequency fc, and sideband components are also spread near the carrier frequency fc in the relatively low frequency band. On the other hand, as shown in Figure 23(b), when carrier injection control is performed, sideband components are spread to the high and low frequencies of each harmonic that is an integer multiple of the carrier frequency fc, but sideband components are not spread near the carrier frequency fc in the relatively low frequency band.

[0150] In other words, as shown in Figures 23(a) and (b), when carrier injection control is used, the sideband components near the carrier frequency fc are smaller and suppressed compared to when carrier injection control is not used. As a result, it is thought that the output harmonic current of the power converter (inverter) 30 is reduced because the harmonics of the output line voltage are reduced by the carrier injection control according to one embodiment.

[0151] Accordingly, according to one embodiment shown in Figures 1 to 5 and Figures 19 to 22, in a power converter 30 using a carrier level shift modulation scheme, harmonics near the carrier frequency fc, which are relatively low-frequency harmonic components, can be suppressed more effectively than in conventional designs. As a result, according to one embodiment, the output harmonic current can be suppressed more effectively than in conventional designs, as explained in Figures 23 and 24.

[0152] Furthermore, according to one embodiment shown in Figures 1 to 5 and Figures 19 to 22, it is possible to suppress the enlargement of the device and the increase in cost. That is, as explained in Figure 10, conventionally, in order to attenuate harmonic components in the relatively low frequency band, the size of the filter had to be increased, which led to the enlargement of the device and the increase in cost. On the other hand, when carrier injection control according to one embodiment is performed, instead of attenuating harmonics that occur near the carrier frequency fc, which are harmonic components in the relatively low frequency band, it is possible to suppress the harmonics (or their occurrence) near the carrier frequency fc more than conventionally. Moreover, since this can be processed in software, it is possible to suppress costs compared to adding hardware (rather than physically increasing the filter size). For this reason, according to one embodiment, since it can be processed in software, there is no need to physically increase the size of the filter, and the enlargement of the device and the increase in cost can be suppressed more than conventionally.

[0153] Furthermore, according to one embodiment shown in Figures 1 to 5 and Figures 19 to 22, the harmonics of the output voltage are reduced by carrier injection control. Therefore, according to this embodiment, when a filter capacitor is used on the AC side, the AC capacitor current flowing through the filter capacitor can be suppressed more than in the conventional method. As a result, the heat generation of the capacitor can be suppressed more than in the conventional method by reducing the AC capacitor current, and the lifespan of the capacitor can be extended more than in the conventional method.

[0154] Figure 24 shows an example of carrier waves CA1 and CA2 and modulated wave D under the condition that the DC voltage is small compared to the AC output voltage. In Figure 24, as in Figure 7, the vertical axis represents voltage and the horizontal axis represents time. The thick solid line in the center shows the waveform of modulated wave D, the dashed line in the upper panel shows the waveform of the upper carrier wave CA1, and the solid line in the lower panel shows the waveform of the lower carrier wave CA2.

[0155] Generally, the effective value of the output line voltage relative to the DC voltage is called the DC voltage utilization rate. The purpose of a power converter (inverter) 30 is to convert a DC voltage into power and obtain a desired AC voltage. Therefore, a power converter (inverter) 30 with a high DC voltage utilization rate is required. Here, we consider the case where the power converter (inverter) 30 is operated under the condition that the DC voltage is small compared to the AC output voltage. In this case, as shown in Figure 24, the maximum value of the modulated wave D becomes larger than the maximum values ​​of the carrier waves CA1 and CA2, resulting in overmodulation.

[0156] Figure 25 shows a magnified view of the area near the peak of the modulated wave D in Figure 24 and an example of the gate signal G1 at that time. Figure 25(a) shows a magnified view of the area near the peak of the modulated wave D in Figure 24. Figure 25(b) shows an example of the gate signal G1 of semiconductor element Q1 corresponding to Figure 25(a).

[0157] In Figure 25(a), as in Figure 24, the vertical axis represents voltage and the horizontal axis represents time. The thick solid line in the center shows the waveform of the modulated wave D, the dashed line in the upper panel shows the waveform of the upper carrier wave CA1, and the solid line in the lower panel shows the waveform of the lower carrier wave CA2. In Figure 25(b), the gate signal G1 of the semiconductor element Q1 is generated, for example, according to a predetermined switching pattern shown in Figure 8.

[0158] Here, for example, in the circuit shown in Figure 2, when semiconductor element Q1 or Q4 conducts, the amplitude of the output voltage of the power converter (inverter) 30 becomes a DC voltage, and the output voltage is equal to the magnitude of the DC voltage. On the other hand, when semiconductor element (neutral point element) Q2 or Q3 conducts, the DC neutral point C conducts, so the amplitude of the output voltage of the power converter (inverter) 30 becomes half the value of the DC voltage, and the output voltage is smaller than when semiconductor element Q1 or Q4 conducts. The power converter (inverter) 30 basically extracts the DC voltage to generate the AC output voltage. Therefore, when semiconductor element Q1 or Q4 conducts, the DC voltage itself is extracted, so a large output is obtained, but when semiconductor element (neutral point element) Q2 or Q3 conducts, the DC neutral point C conducts, so a small voltage is output. Consequently, within one cycle of the fundamental wave, the longer the conduction period of semiconductor element Q1 or Q4, the larger the AC output voltage. Furthermore, the larger the amplitude of the modulated wave D, the longer the conduction period of semiconductor element Q1 or Q4.

[0159] Here, as shown in Figure 25(a), when the maximum value of the modulated wave D becomes larger than the maximum values ​​of the carrier waves CA1 and CA2, resulting in overmodulation, a section where switching cannot be performed occurs, as shown in Figure 25(b), and thus proper control is not achieved.

[0160] For example, when the AC voltage is larger than the DC voltage, the power converter (inverter) 30 must output the larger AC voltage, and therefore needs to increase the conduction period of semiconductor elements Q1 and Q4 as much as possible. However, as shown in Figure 25(a), when the modulated wave D is larger than the carrier waves CA1 and CA2 (in this case, it is generally called overmodulation), the power converter (inverter) 30 has sections where switching is not possible, and therefore cannot output the desired AC voltage. For this reason, when the DC voltage is smaller than the AC output voltage, the power converter (inverter) 30 cannot output the desired AC voltage in sections where switching is not possible, resulting in poor DC voltage utilization.

[0161] Figure 26 shows an example of carrier waves CA1 and CA2 and a modulated wave Dca under the condition that the DC voltage is small relative to the AC output voltage, with carrier injection control applied. In Figure 26, as in Figure 7, the vertical axis represents voltage and the horizontal axis represents time. The thick solid line in the center shows the waveform of the modulated wave Dca, the dashed line in the upper panel shows the waveform of the upper carrier wave CA1, and the solid line in the lower panel shows the waveform of the lower carrier wave CA2.

[0162] Figure 26, similar to Figures 24 and 25, shows that the maximum value of the modulated wave Dca is greater than the maximum values ​​of the carrier waves CA1 and CA2. However, carrier injection control is performed on the modulated wave Dca, in which an injected carrier CAin with the same carrier period but opposite phase (i.e., a 180-degree phase difference) is injected between CA1 and CA2.

[0163] Figure 27 shows a magnified view of the area near the peak of the modulated wave Dca in Figure 26 and an example of the gate signal G1 at that time. Figure 27(a) shows a magnified view of the area near the peak of the modulated wave Dca in Figure 26. Figure 27(b) shows an example of the gate signal G1 of semiconductor element Q1 corresponding to Figure 27(a).

[0164] In Figure 27(a), as in Figure 26, the vertical axis represents voltage and the horizontal axis represents time. The thick solid line in the center shows the waveform of the modulated wave Dca, the dashed line in the upper panel shows the waveform of the upper carrier wave CA1, and the solid line in the lower panel shows the waveform of the lower carrier wave CA2. In Figure 27(b), the gate signal G1 of the semiconductor element Q1 is generated, for example, according to a predetermined switching pattern shown in Figure 8.

[0165] As explained in Figure 25, within one cycle of the fundamental wave, the longer the conduction period of semiconductor element Q1 or Q4, the larger the AC output voltage. Furthermore, the larger the amplitude of the modulated wave Dca, the longer the conduction period of semiconductor element Q1 or Q4. In this regard, as shown in Figure 27(a), carrier injection control is performed on the modulated wave Dca, in which an injected carrier CAin with a 180-degree phase difference with CA1 and CA2 is injected. Therefore, the modulated wave Dca can have many intersection points with the carrier waves CA1 and CA2. In this case, as shown in Figure 27(b), even near the peak of the modulated wave Dca, semiconductor element Q1 is switched by the gate signal G1. As a result, when carrier injection control is performed, the section in which switching cannot be performed is reduced, so the power converter (inverter) 30 can output the desired AC voltage even under conditions where the DC voltage is small compared to the AC output voltage. For this reason, when carrier injection control is performed, the DC voltage utilization rate can be improved compared to conventional methods.

[0166] Therefore, according to one embodiment shown in Figures 1 to 5 and Figures 19 to 22, since carrier injection control is used, the desired AC voltage can be output with a smaller DC voltage than when carrier injection control is not used. As a result, according to one embodiment in which carrier injection control is used, the DC voltage utilization rate of the power converter (inverter) 30 can be improved compared to when carrier injection control is not used.

[0167] Figure 28 shows an example of charging and discharging the voltages of DC capacitors Cp and Cn in a single-phase circuit configuration of the 3-level NPP system shown in Figure 2. Figure 28(a) shows an example of charging and discharging the voltages of DC capacitors Cp and Cn when the current is positive in a single-phase circuit configuration of the 3-level NPP system shown in Figure 2. Figure 28(b) shows an example of charging and discharging the voltages of DC capacitors Cp and Cn when the current is negative in a single-phase circuit configuration of the 3-level NPP system shown in Figure 2.

[0168] Here, we will consider the switching pattern in which the semiconductor elements (neutral point elements) Q2 and Q3 conduct in the case shown in Figure 28. For example, as shown in Figure 28(a), when the current is positive, the DC capacitor Cp is charged and the DC capacitor Cn is discharged. On the other hand, as shown in Figure 28(b), when the current is negative, the DC capacitor Cp is discharged and the DC capacitor Cn is charged. Therefore, in a power converter (inverter) 30 having a DC neutral point C, the conduction of the semiconductor elements (neutral point elements) Q2 and Q3 causes pulsation in the DC neutral point voltage.

[0169] In other words, as shown in Figures 28(a) and (b), in a power converter (inverter) 30 having a DC neutral point C, each time the semiconductor elements (neutral point elements) Q2 and Q3 conduct, charging or discharging occurs in the DC capacitors Cp and Cn, causing pulsation in the DC capacitor voltage. As a result, pulsation occurs at the DC neutral point C according to the switching pattern. In this respect, when carrier injection control is performed, the period during which the modulated wave Dca is larger than the upper carrier wave CA1 or smaller than the lower carrier wave CA2 increases, and the conduction period of semiconductor elements Q1 and Q4 increases. In other words, the period during which the modulated wave Dca exists between the upper carrier wave CA1 and the lower carrier wave CA2 decreases, and the conduction period of semiconductor elements (neutral point elements) Q2 and Q3 decreases. Consequently, the patterns in which the pulsating semiconductor elements (neutral point elements) Q2 and Q3 conduct decrease, and the pulsation of the capacitor voltage itself decreases. Therefore, according to one embodiment, since the conduction period of the semiconductor elements (neutral point elements) Q2 and Q3 is reduced near the 0 crossover, the pulsation of the DC neutral point voltage can be suppressed more effectively than in the conventional method.

[0170] Therefore, according to one embodiment shown in Figures 1 to 5 and Figures 19 to 22, carrier injection control is performed, so the flow rate through the semiconductor elements (neutral point elements) Q2 and Q3 is reduced compared to when carrier injection control is not performed. As a result, according to one embodiment in which carrier injection control is performed, the pulsation of the DC neutral point voltage can be suppressed compared to when carrier injection control is not performed.

[0171] Furthermore, according to one embodiment shown in Figures 1 to 5 and Figures 19 to 22, carrier injection control is performed, and as described above, the flow rate through the semiconductor elements (neutral point elements) Q2 and Q3 decreases compared to when carrier injection control is not performed. As a result, according to one embodiment, the conduction loss of the semiconductor elements (neutral point elements) Q2 and Q3 is reduced, and therefore, heat generation of the semiconductor elements (neutral point elements) Q2 and Q3 can be suppressed compared to when carrier injection control is not performed.

[0172] In the embodiment shown in Figures 1 to 5 and Figures 19 to 22, an example was described where the injected carrier is a triangular wave. However, the invention is not limited to this, and the injected carrier may be a signal other than a triangular wave, as long as it has the same period and opposite phase as the carrier waves CA1 and CA2. Even if the injected carrier is a wave other than a triangular wave, such as a sine wave or a square wave, the same effects and advantages as those shown in the embodiment in Figures 1 to 5 and Figures 19 to 22 will be achieved.

[0173] <Modification of one embodiment> Figure 29 shows an example of the control configuration in the gate signal generation unit 53A according to a modified embodiment. Figure 29 shows examples of control configurations for the U-phase, V-phase, and W-phase, but in the following description, as with Figure 5, the control of the U-phase will be used as an example to explain the control common to each phase.

[0174] In the modified example of one embodiment shown in Figure 29, the gate signal generation unit 53 shown in Figures 3 and 5 of the power conversion system 20 according to one embodiment shown in Figures 1 to 5 and Figures 19 to 22 is replaced with a gate signal generation unit 53A. Also, although not shown, in the modified example of one embodiment shown in Figure 29, the 3-level power converter 30 in the power conversion system 20 according to one embodiment is replaced with an n-level power converter 30A. Other configurations in the power conversion system 20A according to the modified example of one embodiment described below are the same as or similar to the configurations in the power conversion system 20 according to one embodiment shown in Figures 1 to 5 and Figures 19 to 22. For this reason, in the modified example of one embodiment described below, the same or similar reference numerals are used for configurations that are the same as or similar to those in the power conversion system 20 according to one embodiment shown in Figures 1 to 5 and Figures 19 to 22, and detailed descriptions and illustrations are omitted.

[0175] As explained in Figures 1 to 5 and Figures 19 to 22, the gate signal generation unit 53 in one embodiment was the gate signal generation unit 53 in a 3-level power converter (inverter) 30. On the other hand, the gate signal generation unit 53A according to a modified example of one embodiment shown in Figure 29 is the gate signal generation unit 53A in an n-level power converter (inverter) 30A. Therefore, the gate signal generation unit 53A according to a modified example of one embodiment shown in Figure 29 has carrier generators 63, 64, ..., 6n-1 in addition to carrier generators 61, 62. As a result, the gate signal generation unit 53A generates carrier waves CA3, CA4, ..., CAn-1 in addition to carrier waves CA1, CA2. As a result, the gate signal generation unit 53A generates and outputs gate signals Gu1 to Gu4, as well as gate signals G corresponding to the n level. Furthermore, the gate signal generation unit 53A generates and outputs gate signals Gv1~Gv4 and Gw1~Gw4 in the V phase and W phase, respectively, in the same manner as the U phase, as well as a gate signal G corresponding to the n level.

[0176] As described above, the modified embodiment shown in Figure 29 provides the same effects and advantages as the embodiment shown in Figures 1 to 5 and Figures 19 to 22. That is, in the embodiment shown in Figures 1 to 5 and Figures 19 to 22, a 3-level power conversion system 20 was described as an example of a multi-level power conversion system 20. In this respect, the n-level power conversion system 20A is also an example of a multi-level power conversion system 20. Therefore, the n-level power conversion system 20A according to the modified embodiment shown in Figure 29 also provides the same effects and advantages as the 3-level power conversion system 20 described in Figures 23 to 28.

[0177] In the modified embodiment shown in Figure 29, an example was described where the injected carrier is a triangular wave. However, the invention is not limited to this, and the injected carrier may be a signal other than a triangular wave, as long as it has the same period and opposite phase as the carrier waves CA1, CA2, ..., CAn-1. Even if the injected carrier is a signal other than a triangular wave, such as a sine wave or a square wave, it will produce the same effects as the modified embodiment shown in Figure 29.

[0178] <Example Hardware Configuration> Figure 30 is a conceptual diagram showing an example of the hardware configuration of the processing circuit 90 of the control device 40 in one embodiment and its modified form shown in Figures 1 to 5 and Figures 19 to 29. Each of the functions described above is realized by the processing circuit 90. In one embodiment, the processing circuit 90 comprises at least one processor 91 and at least one memory 92. In another embodiment, the processing circuit 90 comprises at least one dedicated hardware 93.

[0179] When the processing circuit 90 includes a processor 91 and memory 92, each function is realized by software, firmware, or a combination of software and firmware. At least one of the software and firmware is written as a program. At least one of the software and firmware is stored in memory 92. The processor 91 realizes each function by reading and executing the program stored in memory 92.

[0180] If the processing circuit 90 includes dedicated hardware 93, the processing circuit 90 may be, for example, a single circuit, a composite circuit, a programmed processor, or a combination thereof. Each function is realized by the processing circuit 90.

[0181] Each function of the control device 40 may be partially or entirely comprised of hardware, or it may be comprised of a program executed by a processor. In other words, the control device 40 can also be implemented by a computer and a program, and the program may be stored on a storage medium or provided via a network.

[0182] <Supplementary information on the embodiment> The embodiments shown in Figures 1 to 5 and Figures 19 to 29 above describe an NPP-type multilevel power converter 30 as one aspect of the present disclosure, but the disclosure is not limited thereto. The present disclosure may also be applied to other types of multilevel power converters 30, such as an NPC-type multilevel power converter 30 or an MMC-type multilevel power converter 30.

[0183] Furthermore, while the embodiments shown in Figures 1 to 5 and Figures 19 to 29 describe a power conversion system 20, 20A and its control device 40 (control unit 50) as an example of one aspect of the disclosure, the disclosure is not limited to this. The disclosure can also be implemented as a control method in which processing steps are performed in each part of the control device 40 (control unit 50).

[0184] Furthermore, this disclosure can also be implemented as a control program that causes a computer to execute processing steps in each part of the control device 40 (control unit 50).

[0185] Furthermore, this disclosure can also be implemented as a storage medium (non-temporary computer-readable storage medium) on which the control program is stored. The control program can be stored and distributed on removable media such as a CD (Compact Disc), DVD (Digital Versatile Disc), or USB (Universal Serial Bus) memory. The control program may also be uploaded to a network via a network interface (not shown) of the control device 40, or downloaded from the network and stored in the storage unit 43 or memory 92.

[0186] The features and advantages of the embodiments will become clear from the detailed description above. This is intended to be so as not to deviate from the spirit and scope of the claims, that the features and advantages of the embodiments described above are included. Furthermore, any improvement and modification should be readily conceivable to a person with ordinary skill in the art. Therefore, there is no intention to limit the scope of inventive embodiments to those described above, and it is also possible to rely on appropriate improvements and equivalents that fall within the scope disclosed in the embodiments. [Explanation of Symbols]

[0187] 11...Solar cell; 12...DC cable; 13...AC cable; 14...Transformer; 15...AC power system (power system, system); 20...Multilevel power conversion system (3-level power conversion system, power conversion system); 20A...Multilevel power conversion system (n-level power conversion system, power conversion system); 21...DC switch; 22...AC reactor; 23...AC capacitor; 24...AC switch; 25...DC voltage sensor; 26...AC current sensor; 30...Multilevel power converter (3-level power converter, power converter, inverter); 30A...Maru N-level power converter (n-level power converter, power converter, inverter); 31…DC input / output section; 32…AC input / output section; 40…Control device; 41…Acquisition section; 42…Output section; 43…Memory section; 45…System bus; 50…Control unit; 51…Operation control unit; 52…Voltage command generation unit; 53, 53A…Gate signal generation unit; 60…Injection carrier generator; 61, 62, 63, 64…Carrier generator; 90…Processing circuit; 91…Processor; 92…Memory; 93…Hardware; 120…Multilevel power conversion system (3-level power conversion system, power conversion system); 130A~130D…(3-level power converter, n-level power converter, power converter, inverter); 153…Gate signal generation unit; AC…AC terminal; C…DC neutral point; CA1…Triangular wave carrier (upper carrier wave, carrier wave); CA2…Triangular wave carrier (lower carrier wave, carrier wave); CA3, CA4…Triangular wave carrier (carrier wave); CAin…Injection carrier; Cell#1~Cell#4…Chopper cell; Cn, Cp…DC capacitor; D…Modulated wave; D1~D4…Freewheeling diode (reverse parallel diode, diode); D5, D6…Diode ;Dca…Modulated wave;Du,Dv,Dw…Modulated wave;Duca,Dvca,Dwca…Modulated wave;fc…Carrier frequency;fo…Fundamental frequency (fundamental frequency, modulated wave frequency);G…Gate signal;G1~G4…Gate signal;Gu1~Gu4,Gv1~Gv4,Gw1~Gw4…Gate signal;Iu,Iv,Iw…AC current value (AC current, current measurement value, current);I_ref,Iu_ref,Iv_ref,Iw_ref…Current command value;Kp…Proportional control gain;N…Negative terminal;NC…Disconnected terminal;P…Positive terminal;P_ref…Output power command value (power command value);Q1, Q4…Semiconductor switching element (semiconductor element, element); Q2, Q3…Semiconductor switching element (neutral point element, semiconductor element, element); T…Period; T1~T4…Interval; V_ref, Vu_ref, Vv_ref, Vw_ref…Voltage command value; Vdc…DC voltage value (DC voltage, voltage measurement value, voltage);

Claims

1. A control device for a multilevel power conversion system having a multilevel power converter having a plurality of semiconductor switching elements and a plurality of neutral point elements, wherein a carrier level shift modulation scheme is used, A process for generating a modulated wave based on the voltage command value of each phase, A process for generating a carrier wave, which is a triangular wave signal having a predetermined carrier period, A process for generating an injected carrier that changes within a predetermined amplitude range and has the same carrier period and opposite phase as the carrier wave, A process for generating a modulated wave in which the modulated wave and the injected carrier are superimposed by carrier injection control, A process to generate gate signals that control the operation of the multiple semiconductor switching elements and the multiple neutral point elements in the multilevel power converter, based on the result of comparing the modulated wave on which the carrier injection control has been performed with the multiple carrier waves, A control device characterized by performing the following.

2. In the control device according to claim 1, The predetermined amplitude range in the injected carrier is smaller than the amplitude of the carrier wave. A control device characterized by the following features.

3. In the control device according to claim 2, The predetermined amplitude range in the injected carrier is in the range of 20% to 30% of the amplitude of the carrier wave. A control device characterized by the following features.

4. In the control device according to claim 1, The predetermined amplitude range in the injected carrier is dynamically varied according to the DC voltage conditions and modulation rate. A control device characterized by the following features.

5. In the control device according to claim 4, The predetermined amplitude range in the injected carrier is made smaller when the DC voltage is low and larger when the DC voltage is high. A control device characterized by the following features.

6. In the control device according to claim 1, The injected carrier is a triangular wave signal that varies within a predetermined amplitude range and has the same carrier period and opposite phase as the carrier wave. A control device characterized by the following features.

7. A multilevel power conversion system using a carrier level shift modulation scheme, Multiple DC capacitors connected in series between a positive terminal connected to a DC power supply or DC load and a negative terminal, via a DC neutral point, A plurality of semiconductor switching elements connected between the positive terminal and the negative terminal and an AC terminal connected to an AC power supply or an AC load, A plurality of neutral point elements connected between the DC neutral point and the AC terminal, A multilevel power converter having, A process for generating a modulated wave based on the voltage command value of each phase, A process for generating a carrier wave, which is a triangular wave signal having a predetermined carrier period, A process for generating an injected carrier, which is a signal that changes within a predetermined amplitude range, is in opposite phase to the carrier wave, and has the same carrier period as the carrier wave, A process for generating a modulated wave in which the modulated wave and the injected carrier are superimposed by carrier injection control, A process to generate gate signals that control the operation of the multiple semiconductor switching elements and the multiple neutral point elements in the multilevel power converter, based on the result of comparing the modulated wave on which the carrier injection control has been performed with the multiple carrier waves, A control device that performs the following: A multilevel power conversion system characterized by comprising the following features.

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