Information processing device, information processing method, and program

Abstract

To improve the accuracy of classifying the state of a bank of a DRAM.SOLUTION: An information processor has: detection means for detecting an event for changing states of at least one or more banks constituting a DRAM; and classification means for classifying the states of at least one or more banks into at least one of an operating state, an inoperable state, and a resting state on the basis of the event detected by the detection means. The classification means, with respect to a predetermined bank included in at least one or more banks, classifies the predetermined bank as being in the inoperable state, when a preceding first control command and a second control command following spacing at an interval longer than a predetermined period from the first control command are detected and when a control command to a bank different from the predetermined bank in the predetermined period is detected.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to an information processing apparatus, an information processing method, and a program for analyzing the state of a DRAM.

Background Art

[0002] Techniques for analyzing the performance of DRAM in system LSIs have been widely used for a long time. Before explaining performance analysis techniques, let's explain DRAM. DRAM stands for Dynamic Random Access Memory and is one of the memory devices used in many modern digital devices such as PCs (Personal Computers), smartphones, digital televisions, and digital cameras. SRAM (Static Random Access Memory) is a memory device that is often compared to DRAM. Compared to SRAM, DRAM requires a periodic memory retention operation called a refresh, so it generally consumes more power. On the other hand, its structure makes it easy to achieve high integration, and it has the advantage of being able to provide large capacity at a low cost, so it has been used as a large-capacity memory device for a long time. With the recent increase in pixel counts such as 4K (image size of approximately 4000 pixels vertically and 2000 pixels horizontally) and 8K (image size of approximately 8000 pixels vertically and 4000 pixels horizontally), the size of digital data for still and moving images continues to increase, and the application range of DRAM shows no signs of waning. As DRAM is the main memory device for digital devices, there is a high demand for improving its access speed. In response to this, DRAM has addressed these demands through structural advancements such as SDRAM (Synchronous DRAM) and RDRAM (Rambus DRAM), speed improvements through increased clock frequencies within the same structure, and various functions that enable higher speeds. Here, we will explain using SDRAM as an example. SDRAM evolved from SDR (Single Data Rate), which operates only on the rising edge of the clock signal, to DDR (Dual Data Rate), which operates on both the rising and falling edges of the clock signal, theoretically doubling its access rate. Furthermore, DDR, DDR2, DDR3, and DDR4 have evolved, mainly through improvements in clock frequency and capacity, along with the definition of the standards. In addition, LP (Low Power) versions such as LPDDR2, LPDDR3, LPDDR4, and LPDDR5 have also been standardized.The standards are defined and standardized by the JEDEC Solid State Technology Association, and have evolved to prevent companies involved in DRAM manufacturing from using their own proprietary standards.

[0003] As mentioned above, SDRAM access performance has evolved, but the control method remains fundamentally the same for all types, including SDR, DDR, and LPDDR, and is controlled by control signals called commands. The command-based control method will be explained using DDR3 as an example. However, as previously stated, the control method does not differ significantly between SDR, DDR, DDR2, DDR3, DDR4, LPDDR2, LPDDR3, LPDDR4, and LPDDR5. Figure 5 shows a list of DDR3 commands. In Figure 5, 501 and 502 indicate the meaning and command notation of the corresponding command when the signals 503 through 513 match that state. The ACT command is used to select the row address of the DRAM. This operation is called activation, and since the memory space at the same row address is treated as a page and preparation for access to the page is made, it is called page open. After selecting the row address with the ACT command, the column address is selected with the RD command and WR command to read and write data to the DRAM memory elements. There are two addresses for selecting the DRAM memory elements: row address and column address. Basic read and write operations involve first selecting a row address with the ACT command, then selecting a column address with the RD and WR commands to determine the address of the target memory element. In SDRAM, a method called page mode has been devised to speed up data access, where data with different column addresses but the same row address are read and written sequentially. This allows for high-speed access even if the column address is different, as long as the row address is the same. On the other hand, if the row address is different, the activated row address must be returned to a deselected state by an operation called precharge using the PRE command, and then re-activated. This precharge is called page close, in contrast to page open for activation. Due to the structure of DRAM, it is difficult to shorten the time for this series of page close (precharge) and page open (activate) operations, and this has not been significantly shortened even with advancements in standards. Generally, this series of operations is called a page miss. Page misses always occur when the row address changes, so they cannot be avoided.However, a structure has been devised to conceal this page error and improve access efficiency. The mechanism is simple: the entire memory space selected by row address and column address is constructed in units called banks, and by implementing multiple banks, page errors are concealed. In other words, during the period when a page error occurs in one bank and access is impossible, access to other banks is performed in parallel, effectively concealing all or part of the page error. However, since banks share row addresses, column addresses, and signal lines through which data flows, functional expansion can be achieved without expanding the DRAM's circuit board wiring. Figure 10 shows the penalty due to a page error and the operation of other banks to conceal it. In Figure 10, 1001 is an RD command to bank 0. According to the DDR3-SDRAM standard, there are 4-beat access, which accesses data four times consecutively, and 8-beat access, which accesses data eight times consecutively. Since consecutive accesses are performed once on the rising and falling edges of the clock, 4-beat access consumes 2 clock cycles, and 8-beat access consumes 4 clock cycles. In this example, assuming only 8-beat access is issued, the next RD command can be issued 4 clock cycles after the previous RD command is issued. RD command 1002 is issued to bank 0, 4 clock cycles after 1001, and is issued at the shortest possible timing considering 8-beat access. Subsequently, a page miss occurs in bank 0, and the PRE command 1003 and the ACT command 1004 are issued consecutively, followed by the issuance of RD command 1005 to a different page. That is, it can be determined that the period from 4 clock cycles after RD command 1002 to RD command 1005 is a penalty due to a page miss. On the other hand, RD command 1006 is issued in bank 1 4 clock cycles after RD command 1002. Regardless of the bank, 4 clock cycles is the shortest possible timing, meaning that RD commands 1002 to 1006 are accessed at the shortest possible timing. Similarly, RD commands 1007, 1008, and 1009 are also issued at 4-clock cycle intervals, and are accessed at the shortest possible timing during this period as well.As a result, the next RD command can only be issued 4 clock cycles after RD command 1009. Looking at this only in bank 0, the 18 clock cycles from 4 clock cycles after RD command 1002 to RD command 1005 are penalized due to page misses. On the other hand, looking at the DRAM as a whole, RD commands 1002, 1006, 1007, 1008, and 1009 are all issued at the fastest possible timing, so there is no penalty. In other words, the 16 clock cycles from 4 clock cycles after RD command 1002 to 4 clock cycles after RD command 1009 can be considered to have concealed the penalty due to page misses. Consequently, in the DRAM as a whole, only the 2 clock cycles from 4 clock cycles after RD command 1009 to RD command 1005 are considered to be penalized due to page misses.

[0004] Another typical control operation for DRAM is called refresh, a memory retention operation performed by the REF command. DRAM memory elements represent their values ​​by the stored charge. This stored charge is gradually lost due to leakage current within the memory element, making it difficult to distinguish between a state with no charge and a state with no charge. Therefore, it is necessary to periodically replenish the charge. This is refresh. Refresh is basically performed on a bank-by-bank basis, but the target bank must have a non-selected row address and must be closed beforehand. Also, due to its structure, the refresh operation takes a certain amount of time, and there is a period during which access is unavailable after the refresh command is issued.

[0005] In addition, DRAM also has a calibration function (periodically adjusting the phase relationship between signal lines and the clock), and this function is also achieved by issuing commands. Similar to penalties for page errors and refreshes, there is a period of time during which access is unavailable after issuing these commands.

[0006] Patent Document 1 classifies the state of each bank of a DRAM based on its control commands into one of three categories: an operational state where data is being transferred, an inoperable state where data cannot be transferred due to predetermined constraints, or a dormant state where there are no constraints but data is not being transferred. Furthermore, Patent Document 1 discloses a technique for classifying the state of a DRAM from its bank state. Some DRAM control commands have constraints on the issuance interval defined in the DRAM standard. Prior Art Document 1 introduces an example in which, if the issuance interval of two control commands with constraints on the issuance interval matches the constraint defined in the standard, it is determined that the command issuance was delayed due to the constraint on the command issuance interval, and the control commands are classified as inoperable.

[0007] Generally, commands to DRAM are issued using a hardware block called a memory controller. When a memory controller can issue commands to multiple banks, it primarily issues commands in a way that minimizes penalties. For example, consider a bank A that can issue RD and WR commands, and a bank B that needs to issue PRE and ACT commands due to a page miss. In this case, to minimize the penalty due to the page miss, it is conceivable to issue PRE and ACT commands to bank B, which has already experienced a page miss, and then prioritize issuing RD and WR commands to bank A during the page miss penalty period. In this way, the penalty period due to the page miss in bank B can be masked by the transfer period based on the RD and WR commands issued to bank A. Thus, the memory controller intentionally selects and issues commands from among the commands that can be issued to multiple banks in order to minimize the penalty period. Various methods have been devised for determining which command the memory controller prioritizes, but these methods themselves are not directly related to this proposal, so they will not be explained in detail. This paper clarifies that memory controllers may prioritize issuing one of several commands that can be issued simultaneously using various methods; in other words, the issuance of one of the commands may be delayed compared to the timing at which it could normally be issued.

[0008] Let's take the banks and command issuance status in Figure 11 as an example. Consider a case where, due to the DRAM standard, there is a constraint that requires at least 8 cycles to pass between the ACT command and the RD command, similar to Figure 10. In bank 1, the ACT command 1106 is issued in the 3rd cycle, so the RD command 1107 could normally be issued in the 11th cycle. However, in order to complete page close and page open as early as possible and issue the RD command 1105 to bank 0 as soon as possible, the memory controller may prioritize issuing the PRE command 1103 to bank 0 over the RD command 1107. [Prior art documents] [Patent Documents]

[0009] [Patent Document 1] Patent Application No. 2019-083241 [Overview of the Initiative] [Problems that the invention aims to solve]

[0010] In the method for classifying a bank as inoperable in prior art 1, there are cases where it cannot be classified as inoperable despite the command issuance interval constraint being the cause. Specifically, this is the case when the memory controller prioritizes issuing commands to other banks, as explained using Figure 11. Originally, the RD command 1107 in Figure 11 is delayed by the PRE command 1103, but its issuance is delayed due to the command issuance interval constraint between the ACT command and the RD command. Therefore, the period between the ACT command 1106 and the RD command 1107 should be classified as inoperable. However, in prior art 1, the interval exceeds the command issuance interval constraint, and it is classified as a dormant state. The present invention has been made in view of the above problem and aims to improve the accuracy of classifying the state of DRAM banks. [Means for solving the problem]

[0011] The information processing apparatus of the present invention comprises detection means for detecting an event that causes a transition in the state of at least one bank constituting a DRAM, and classification means for classifying the state of the at least one bank into at least one of operating state, non-operating state, or idle state based on the event detected by the detection means, wherein the classification means classifies a predetermined bank included in the at least one bank as being in a non-operating state when a preceding first control command and a second control command that follows the first control command at an interval longer than a predetermined period are detected, and a control command for a bank other than the predetermined bank is detected within the predetermined period. [Effects of the Invention]

[0012] According to the present invention, which has been made in view of the above problems, it is possible to improve the accuracy of classifying the state of DRAM banks. [Brief explanation of the drawing]

[0013] [Figure 1] This is a conceptual diagram illustrating the entire performance analysis process of the present invention. [Figure 2] This is a diagram showing the configuration of the test bench being simulated. [Figure 3] This is a diagram showing the configuration of a computer system that performs performance analysis. [Figure 4] These are the signal lines that make up the DDR3-SDRAM interface. [Figure 5] This is a list of commands for DDR3-SDRAM. [Figure 6] This is an example of the output result of the detection means 101 in the first embodiment. [Figure 7] This is a flowchart illustrating the processing of the bank state classification means 103 in the first embodiment. [Figure 8] This is a table showing the constraints between commands in the first embodiment. [Figure 9]This shows the processing results of the bank state classification means 103 on the output results of Figure 6. [Figure 10] This diagram illustrates the penalty for page errors in DDR3-SDRAM and the actions taken to conceal them. [Figure 11] This figure shows an example where issuing a PRE command takes precedence over an RD command in DDR3-SDRAM. [Modes for carrying out the invention]

[0014] (First embodiment) The information processing device of the first embodiment will be described using Figures 1 to 9.

[0015] Figure 2 is a diagram of the test bench configuration including the system LSI and peripheral modules to be simulated in this embodiment. In Figure 2, 200 is the system LSI. The CPU 201 is for executing various controls of the system LSI 200. The image processing unit 202 performs image processing of still images and moving image data handled within the system LSI 200. The audio processing unit 203 performs audio processing of audio data handled within the system LSI 200. The network processing unit 204 transmits and receives data between the system LSI 200 and an external network. The ROM 210 stores the boot program executed when the CPU 201 starts up and various data, and is accessed via the ROMC 206. The DRAM 209 mainly stores control programs for processing by the CPU 201 and provides a workspace for when the CPU 201 executes various controls. In addition, it stores still images and moving image data handled by the image processing unit 202, audio data handled by the audio processing unit 203, and external communication data handled by the network processing unit 204. The DRAM 209 has eight banks 220 to 227 that constitute it. The bank numbers correspond to banks 220 through 227, with banks 0 through 7 corresponding to banks 220 through 227. The image processing unit 202, audio processing unit 203, and network processing unit 204 access their respective data via DMA (Dynamic Memory Access). Access to the DRAM 209 is performed by the memory controller 205 receiving an access request, converting it into a control command, which is then converted into an analog signal by the PHY 207 and issued externally. The specific access method is as described in the background information and will be omitted here. The same applies when the image processing unit 202, audio processing unit 203, and network processing unit 204 access the DRAM. The bus 208 interconnects the CPU 201, image processing unit 202, audio processing unit 203, and network processing unit 204, which issue access requests, with the memory controller 205 and ROMC 206, which receive these access requests. In this embodiment, the DRAM 209 is assumed to be an SDRAM compliant with the DDR3-SDRAM standard.A monitor 211 is connected to the control signal between the system LSI 200 and the DRAM 209, and has a function of monitoring commands generated on the control signal during the execution of the simulation. The signals monitored by the monitor 211 are DDR3-SDRAM interface signals shown in FIG. 4. The system LSI 200, the DRAM 209, the ROM 210, and the monitor 211 are arranged in the test bench 212 and are connected by respective signals.

[0016] FIG. 3 is a configuration diagram of a computer device that performs performance analysis processing including simulation processing of the test bench 212. In FIG. 3, the CPU 301 is for executing various controls in the computer device. The ROM 302 is for storing a boot program and various data that are executed when the computer device is started up. The RAM 303 stores a control program for the CPU 301 to process and provides a work area when the CPU 301 executes various controls. The keyboard 304 and the mouse 305 are for providing various input operation environments by the user. 306 is an HDD (hard disk) that stores various data.

[0017] 307 is a display that displays the performance analysis result. The network interface 308 enables communication with an external network via a LAN cable. The bus 309 is for connecting the above-described respective components. Note that the CPU, the ROM, and the bus also exist in the system LSI 200, but it should be noted that these are different things.

[0018] The performance analysis of this embodiment will now be described. The performance analysis process is performed on the computer device. Figure 1 is a conceptual diagram of the overall performance analysis process. In Figure 1, 101 is a detection means that detects events that cause state transitions in banks 220 to 227 that constitute the DRAM 209, which is the target of performance analysis. More specifically, the events are commands issued by the memory controller 205 in the system LSI 200 to control the DRAM 209. The event information 102 detected by the detection means is temporarily stored in the HDD 306 and input to the next bank state classification means 103. The bank state classification means 103 transitions the state of banks 220 to 227 based on the events that have occurred. This determines the state of banks 220 to 227 in chronological order. The bank state information 104 of banks 220 to 227 classified by the bank state classification means 103 is stored in the HDD 306 in the same way as the event information 102. The above is the overall flow of the performance analysis process of this embodiment. The following provides a detailed explanation of each element in the performance analysis process shown in Figure 1.

[0019] The detection means 101 is implemented by the monitor 211 in the simulation processing of the test bench 212 by the computer device. The simulation processing by the computer device is implemented by the CPU 301 using RAM 303 as a work area and executing simulation software stored in HDD 306. As described in the prior art, typical simulation software includes Incisive (registered trademark of Cadence), VCS (registered trademark of Synopsys), and Questasim (registered trademark of Mentor). These simulation software programs simulate the same operation as the system LSI 200 actually operates, and the results are stored in HDD 306. Specifically, these include simulation log files and waveform files output by the simulation software, and event information output by monitor 211.

[0020] The monitoring of signal lines between the system LSI 200 and DRAM 209 by the monitor 211, i.e., the detection means 101 of this embodiment, will now be described. The monitor 211 monitors the signal lines between the system LSI 200 and DRAM 209 during the simulation process. Specifically, these are the signal lines that constitute the DDR3-SDRAM interface shown in Figure 4. 401 is the clock and serves as the reference for all signals. That is, at the timing of the rising edge of the clock 401 (change from 0 to 1), the state of signals other than the clock 401 is evaluated and it is detected which command has been issued. Specifically, the command is detected based on the table shown in Figure 5. In Figure 5, 503 to 513 indicate the values ​​of the signal lines shown in Figure 4. 504 to 513 indicate the state of each signal at a predetermined rising edge timing of the clock 401, but it is important to note that only 503 indicates the state at the rising edge timing of the clock 401 one timing prior to that timing. In Figure 5, L means Low=0 and H means High=1. X is Don't Care and can be either 0 or 1. RFU stands for Reserved for Future Use and, like X, can be any value. V is Valid, meaning that the corresponding signal has the desired meaning for the target command. The specific meaning is omitted as it is not relevant to the explanation of this invention. BA, RA, and CA mean bank address, row address, and column address, respectively, and when a command is detected by a signal other than these, it is determined to be an address. 501 and 502 indicate the meaning and command notation of the corresponding command when the signals 503 to 513 match that state. The detection means will be explained using the ACT command as an example. Based on 503, it is determined whether the CKE signal was high at the rising edge timing of the previous clock 401. Next, based on 504, it is determined whether the CKE signal was high at the rising edge timing of the current clock 401. Similarly, it is determined that CS=L, RAS=L, CAS=H, and WE=H, and the ACT command is detected when all of these conditions are met. In this case, the BA signal means bank address, and the A signal means RA, i.e., column address.Commands other than ACT are also determined based on the values ​​of the signal lines according to the table in Figure 5, and the issued commands are detected. The special command NOP command 540 will be explained further. The NOP command 540 is detected when CKE=H→H (meaning the rising edge of the previous clock was H and the rising edge of the current clock is H), CS=L, and RAS / CAS / WE are all H. The NOP command 540 is an abbreviation for No Operation and means that no command has been generated. In this embodiment, NOP commands are excluded from detection, and all other commands are detected. This concludes the explanation of the detection means 101. In this embodiment, the detection means was explained using the detection of commands based on the DDR3-SDRAM standard as an example, but it is not limited to the type of standard. That is, even with other DDR2, DDR4, DDR5, LPDDR2, LPDDR3, and LPDDR4, commands are similarly defined based on the values ​​of the signal lines, so the detection means can be implemented as events. Furthermore, the events detected by the detection means are not limited to commands. The detection method involves monitoring the signal line between the system LSI 200 and the DRAM 209 to detect events. Regardless of whether the value of the monitored signal is defined in the standard, any change in the signal line can be defined as an event.

[0021] The monitor 211, which implements the detection means 101, outputs the commands detected during the simulation period as log information, which becomes the event information 102. Figure 6 shows an example of the contents of the event information 102 output by the monitor 211. In Figure 6, 601 is the occurrence time, which is the elapsed time in the simulation. In this embodiment, the unit is ps (picosecond = 0.000000000001 seconds). 602 is the command, which indicates the command detected by the detection means. 603, 604, and 605 are the bank address, row address, and column address, respectively, and are indicated by the BA and A signals when each command is detected. Depending on the command, the bank address, row address, and column address may or may not be indicated, and are therefore displayed in the event information 102 accordingly.

[0022] Before describing the processing details of the bank state classification means 103 itself, we will first explain the types of bank states of banks 220 to 227 that are classified by the bank state classification means 103. In this embodiment, the following three bank states are defined. State 1: Operating state State 2: Hibernation State 3: Unable to operate

[0023] The operating state is the state in which data access to the target bank is being performed as read or write. Specifically, the operating state is defined as the period of 4 clock cycles after the issuance of the RD command and 4 clock cycles after the issuance of the WR command. According to the DDR3-SDRAM standard, there are 4-beat access, which accesses data four times consecutively, and 8-beat access, which accesses data eight times consecutively. Since consecutive accesses are performed once on the rising and falling edges of the clock, 4-beat access consumes 2 clock cycles and 8-beat access consumes 4 clock cycles. In this embodiment, it is assumed that only 8-beat access is issued, and the operating state is defined as lasting 4 clock cycles after the issuance of the RD and WR commands. When performing consecutive reads, according to the standard, the next RD command can be issued after 4 clock cycles in 8-beat access. That is, a 4-clock cycle operating state occurs consecutively. The same applies when performing consecutive writes.

[0024] An unoperable state is a state in which data access to a bank cannot be performed due to predetermined constraints and the system is waiting. For example, in the DDR3-SDRAM standard, no commands can be issued for a period of time defined by the tREF parameter after the issuance of a REF (refresh) command. As explained in the prior art, this is a constraint that inevitably occurs with refresh operations and applies regardless of the type of DRAM. In this embodiment, the period of the tREF parameter after the issuance of a REF command is defined as one of the unoperable states. The tREF parameter in this case is assumed to be 500 clock cycles. However, it is also possible to define an unoperable state only when the REF command is made to wait for the issuance of an RD or WR command. That is, an unoperable state is defined only when an ACT command is issued immediately after the tREF parameter period following the issuance of a REF command. In this embodiment, an unoperable state is defined regardless of the presence or absence of an ACT command, but it goes without saying that the present invention can also be applied when an unoperable state is defined only when an ACT command occurs. Furthermore, in the DDR3-SDRAM standard, a period of time defined by the tRCD parameter must be left between the issuance of an ACT command and the issuance of an RD or WR command. Similarly, it is assumed that there are constraints between the ACT, PRE, RD, and WR commands that commonly occur during normal data access, as defined in the table in Figure 8. The DDR3-SDRAM standard has many other commands, as shown in Figure 5, and there are also constraints between these commands. However, in this embodiment, it is assumed that only the constraints shown in the table in Figure 8 exist, and if there is a gap of a certain number of clock cycles between each command, this period is defined as one of the periods during which operation is impossible. However, this premise does not limit the scope of application of the present invention; even if there are constraints other than those between the commands shown in Figure 8, the present invention can be applied as long as those constraints are defined as a certain period after the issuance of a predetermined command and a certain period between predetermined commands. Furthermore, although not shown in Figure 8, the present invention can also be applied even if there are constraints defined by a predetermined sequence of three or more commands, as long as these can be determined by conditional branching.For example, if the PRE, ACT, and RD commands occur in sequence, the period from the PRE command to the RD command can be determined as a constraint period due to a page miss. Similarly, if the REF, ACT, and WR commands occur in sequence, the period from the REF command to the WR command can be determined as a constraint period due to refresh and page open. In either case, the present invention can be applied if the conditional branching can be clearly defined. The above defines the non-operational state, but how to define a non-operational state for a certain period after any command, between any two commands, or in any command sequence three positions above is not a prerequisite for the present invention. If the non-operational state can be defined by the number of cycles (or a numerical constraint that can be converted thereto) based on the event occurrence detected by the detection means, it goes without saying that the present invention can be applied regardless of the content of that definition. Furthermore, in this embodiment, the period during which commands cannot be issued for a certain period after the REF command was defined by the tREF parameter, but the memory controller 205 can control the period during which commands are not issued after the REF command regardless of the tREF parameter. For example, setting it to less than the tREF parameter would violate the standard and is therefore not possible, but it is possible to control it to leave a gap of clock cycles equal to or greater than the tREF parameter. In this case, it is also possible to define the non-operational state based on the number of cycles set in the memory controller 205.

[0025] Finally, let's explain the dormant state. The dormant state is defined as a state that is neither the operating state nor the inoperable state described above. In this embodiment, the operating state and inoperable state were defined first, followed by the dormant state, but this correlation can be reversed. That is, the operating state and dormant state can be defined first, and everything else can be defined as the inoperable state.

[0026] The bank state classification means 103 will now be explained using Figure 7. The bank state classification means 103 takes event information 102 as input and is executed on the computer device as a separate process after the simulation process. The bank state classification means 103 may determine an inoperable state by checking the number of clock cycles between two events. Therefore, instead of determining the state after an event occurs, the mechanism determines the state from the previous event to the current event when an event occurs. Figure 7 is a flowchart for classifying the states of banks 220 to 227. However, this flowchart is executed independently for each bank. That is, the process shown in the flowchart of Figure 7 is executed on the computer device for eight times, corresponding to the number of banks. Since the flowchart can be used for any bank, the bank number is received in the argument input of step 701, thereby identifying the target bank. In Figure 7, the bank number is received as an argument in step 701. In steps 702 and 703, the variables used in this process are initialized. In step 702, the state confirmation time (FIX_TIME) is reset. Specifically, FIX_TIME is set to 0. The usage of the state confirmation time FIX_TIME will be explained later, but this value means that the bank state has been determined up to that time. In step 703, the time and type of the previous command are reset. Specifically, SAME_PRE_TIME, which indicates the time of the previous command for the bank indicated by the argument bank number, is set to 0, and SAME_PRE_CMD, which indicates the same type, is set to UNDEF, meaning undefined. Also, DIFF_PRE_TIME, which indicates the time of the previous command for banks other than the argument bank number, is set to 0, and DIFF_PRE_CMD, which indicates the same type, is set to UNDEF, meaning undefined. Next, in step 704, one event information entry is read from the input event information 102. This corresponds to one line in the example of event information 102 in Figure 6. From here, steps 707 to 729 classify the bank state. As mentioned above, the bank states to be classified are the three states: operating state, non-operating state, and dormant state.

[0027] First, in step 707, it is determined whether the bank address 603 of the current event information entry matches the bank number in the argument. If they do not match, no state transition occurs for the target bank in the current event information entry. In step 727, DIFF_PRE_CMD and DIFF_PRE_TIME are updated based on the command 602 and occurrence time 601 of the current event information entry. That is, DIFF_PRE_CMD is set to the command 602 of the current event information entry, and DIFF_PRE_TIME is set to the occurrence time 601 of the current event information entry. On the other hand, if the bank address 603 of the current event information entry matches the bank number in the argument, the process proceeds to step 708. In step 708, it is determined whether the previous command for the target bank, i.e., SAME_PRE_CMD, is an RD command or a WR command. When the determination is made for the first time at the branch in step 708, SAME_PRE_CMD is set to UNDEF, so it is always determined to be No. If SAME_PRE_CMD is an RD command or a WR command, step 709 classifies the period from FIX_TIME to 4 clock cycles as operational. The classification result is output as bank status information 104, along with the occurrence time (FIX_TIME at this time) and the occurrence cycle of 4 cycles. Then, in step 710, 4 clock cycles are added to FIX_TIME to update the time when the state was determined. On the other hand, if it is determined to be No in step 708, step 711 determines whether the previous command for the target bank, i.e., SAME_PRE_CMD, is a REF command. When the determination is made at the branch in step 711 for the first time, SAME_PRE_CMD is set to UNDEF, so it will always be determined to be No. If SAME_PRE_CMD is a REF command, step 712 classifies the period from FIX_TIME to 500 clock cycles as non-operational. The classification result is output as bank status information 104, along with the occurrence time (FIX_TIME at this time) and the occurrence cycle of 500 cycles. Then, in step 713, 500 clock cycles are added to FIX_TIME to update the time when the state was confirmed.If steps 710 and 713 have been processed, or if step 711 is determined to be No, proceed to step 714. In step 714, the previous command for the target bank, i.e., SAME_PRE_CMD, and the command 602 of the current event information entry are used to determine if they match the cycle set to match the conditions in the table in Figure 8. For example, if the command 602 of the current event information entry is an ACT command and SAME_PRE_CMD is a PRE command, then according to the table in Figure 8, 40 cycles are set. In this case, it is determined whether the period from the occurrence time of the previous PRE command, SAME_PRE_TIME, to the occurrence time of the target ACT command, i.e., the occurrence time of the current event information entry, 601, matches 30 cycles. The same determination is made for other commands based on the table in Figure 8. If the number of clock cycles is not set in the table in Figure 8, it is determined to be No. If the result of the determination is Yes, in step 715 the period from FIX_TIME to the occurrence time of the current event information entry, 601, is classified as an inoperable state. The classification results are output as bank status information 104, along with the occurrence time (FIX_TIME at this time) and occurrence cycle. It is important to note that this is not the period from SAME_PRE_TIME, which is the occurrence time of the previous command for the target bank, to the occurrence time 601 of the current event information entry. The reason for this will be explained using the example where the command 602 of the current event information entry is a PRE command and SAME_PRE_CMD is an RD command. In this example, 50 cycles are set based on the table in Figure 8. Therefore, it is determined whether the period from SAME_PRE_TIME, which is the occurrence time of the RD command, to the occurrence time 601 of the current PRE command is 50 cycles. At this time, FIX_TIME and SAME_PRE_TIME do not match. This is because FIX_TIME has already had 4 clock cycles added in step 710 because SAME_PRE_CMD is an RD command.Therefore, if we classify the 50 cycles from SAME_PRE_TIME to the current event information entry occurrence time of 601 as an inoperable state, we would be classifying the 4 clock cycles from SAME_PRE_TIME twice. To avoid this, we classify the difference of 46 clock cycles from FIX_TIME as an inoperable state. Now, after classifying as an inoperable state in step 715, in the following step 716, we add the difference from the current event information entry occurrence time of 601 to FIX_TIME and update the time when the state was determined. As a result, FIX_TIME = current event information entry occurrence time of 601. On the other hand, if no constraints are set in the table in Figure 8 in step 714, or if the set constraints do not match the period from SAME_PRE_TIME to the current event information entry occurrence time of 601, we proceed to step 729. Step 729 is a process to detect when a command was issued to the argument bank at the timing of the constraint set in the table in Figure 8, but the command could not be issued because priority was given to issuing commands to banks other than the argument bank. Figure 11 is used as an example to explain when this case occurs. This example assumes an 8-cycle gap between ACT and RD commands. Similarly, it assumes a 4-cycle gap between RD commands, a 6-cycle gap between RD commands and PRE commands, and an 8-cycle gap between PRE commands and ACT commands. In this case, RD command 1107 for bank 1 can be issued in the 11th cycle, 8 cycles after ACT command 1106. On the other hand, PRE command 1103 for bank 0 can be issued in the 11th cycle, 6 cycles after RD command 1102. That is, in the 11th cycle, both RD command 1107 for bank 1 and PRE command 1103 for bank 0 are available. Under these circumstances, in this example, PRE command 1103 for bank 0 is issued, and RD command 1107 for bank 1, which could have been issued in the same cycle, is issued in the next cycle.From this issuance result, it can be considered that in the 11th cycle, the PRE command 1103 for bank 0 took priority, and as a result, the RD command 1107 for bank 1 was delayed. In this issuance result, we will explain how to classify the state between the ACT command 1106 and the RD command 1107 for bank 1. There is a constraint that there should be an 8-cycle gap between the ACT command and the RD command, but there is a 9-cycle gap. As a result, in comparison with the constraint, it is classified as a paused state rather than an inoperable state. However, as explained above, although the RD command 1107 was in a state where it could be issued in the 11th cycle, 8 cycles after the ACT command 1106, it can be considered that it was delayed because the issuance of the PRE command 1103 for bank 0 took priority. In other words, the state between the ACT command 1106 and the RD command 1107 can be classified as an inoperable state. In this proposal, when the above state is detected, it is characterized by being classified as an inoperable state.

[0028] The process for step 729 to detect the cases described above will now be explained. First, it is determined whether the issuance interval of the command DIFF_PRE_CMD for banks other than the previous argument and the command DIFF_SAME_CMD for the argument bank are set at the timing of the command issuance interval constraint set in the table in Figure 8. Next, it is determined whether the command 602 of the current event information entry was issued in the cycle immediately following the issuance of the command for the bank other than the argument. The specific process will be explained. First, it is determined whether the cycle set to match the conditions in the table in Figure 8 is obtained using the command for the argument bank, i.e., SAME_PRE_CMD, the command 602 of the current event information entry, and the occurrence time of the command for the bank other than the argument, i.e., DIFF_PRE_TIME. For example, if the command 602 of the current event information entry is an RD command and SAME_PRE_CMD is an ACT command, then according to the table in Figure 8, 30 cycles are set. In this case, it will be determined whether the period from SAME_PRE_TIME to DIFF_PRE_TIME matches 30 cycles. If they match, determine whether the current event information entry occurrence time 601 is one cycle after DIFF_PRE_TIME. If step 729 is Yes, proceed to step 715. If No, proceed to step 717. From step 717 onwards, check the constraints from the previous command for banks other than the target bank, similar to how constraints from the previous command for the argument bank were checked in steps 714 to 716. Before checking the constraints, check whether the occurrence time of the previous command for banks other than the target bank, i.e., DIFF_PRE_TIME, is later than FIX_TIME. In this flowchart, as branched in step 707, the bank state transition is checked and the bank state is classified only if the command 602 of the current event information entry is for the target bank. As a result, SAME_PRE_TIME, which is the occurrence time of the command for the target bank, will always match FIX_TIME at step 707.Also, since FIX_TIME can only be incremented in subsequent processing, FIX_TIME >= SAME_PRE_TIME always held. However, if the command 602 in the current event information entry is the previous command for a bank other than the target bank, a branch occurs at step 707 and no state transition takes place. As a result, FIX_TIME < DIFF_PRE_TIME can occur. When this condition (FIX_TIME < DIFF_PRE_TIME) holds, it is necessary to set the period until this command to a paused state before analyzing the constraints from the previous command for a bank other than the target bank. At step 718, the period from FIX_TIME to the occurrence time of the previous command for a bank other than the target bank, that is, up to DIFF_PRE_TIME, is classified as a paused state. The classified result is output as bank state information 104 together with the occurrence time (FIX_TIME at this time) and the occurrence cycle. Subsequently, at step 719, the difference up to DIFF_PRE_TIME is added to FIX_TIME to advance the time when the state is determined. As a result, FIX_TIME = DIFF_PRE_TIME. Now, if FIX_TIME < DIFF_PRE_TIME does not hold at step 717, and after processing step 719, the process proceeds to step 720. At step 720, it is determined whether the previous command for a bank other than the target bank, that is, DIFF_PRE_CMD, matches the cycle set for the condition that matches the table in FIG. 8, using the command 602 in the current event information entry. For example, if the command 602 in the current event information entry is a WR command and DIFF_PRE_CMD is an RD command, 15 cycles are set based on the table in FIG. 8. In this case, it is determined whether the period from DIFF_PRE_TIME, which is the occurrence time of the RD command, to the occurrence time of the target WR command, that is, the occurrence time 601 of the current event information entry, matches 15 cycles. Other commands are also determined based on the table in FIG. 8 in the same manner. If the number of clock cycles is not set in the table in FIG. 8, it is determined as No.If the result of the judgment is Yes, in step 721 the period from FIX_TIME to the occurrence time of the current event information entry 601 is classified as an inoperable state. The classification result is output as bank status information 104 along with the occurrence time (FIX_TIME at this time) and occurrence cycle. It is important to note that this is not the period from DIFF_PRE_TIME, which is the occurrence time of the previous command for a bank other than the target bank, to the occurrence time of the current event information entry 601. The reason for this is the same as explained earlier in step 715. After classifying it as an inoperable state in step 721, in the following step 722 the difference from the occurrence time of the current event information entry 601 is added to FIX_TIME, updating the time when the state was determined. As a result, FIX_TIME = occurrence time of the current event information entry 601. On the other hand, if no constraints are set in the table in Figure 8 in step 720, or if the set constraints do not match the period from DIFF_PRE_TIME to the occurrence time of the current event information entry 601, the process proceeds to step 723. In step 723, the period from FIX_TIME to the occurrence time 601 of the current event information entry is classified as a dormant state. The classification result is output as bank status information 104, along with the occurrence time (FIX_TIME at this time) and occurrence cycle. In the following step 724, the difference from the occurrence time 601 of the current event information entry is added to FIX_TIME, updating the time when the state was determined. As a result, FIX_TIME = occurrence time 601 of the current event information entry. Now, if steps 716, 722, or 724 have been processed, proceed to step 725. In step 725, SAME_PRE_CMD and SAME_PRE_TIME are updated based on the command 602 and occurrence time 601 of the current event information entry. That is, SAME_PRE_CMD is set to the command 602 of the current event information entry, and SAME_PRE_TIME is set to the occurrence time 601 of the current event information entry. Finally, in step 726, it is determined whether the input event information 102 contains the next event information entry. If so, the process returns to step 704 and is repeated.On the other hand, if there is no event information entry, processing is terminated. The above describes the contents of the bank state classification means 103 in this embodiment. In this embodiment, the explanation was given on the premise that no multiple constraints occur simultaneously between commands. However, in reality, it is possible that a command indicated by the event information entry to be processed may be simultaneously constrained by multiple commands issued before it. For example, suppose an ACT command, an RD command, and a PRE command are issued in order. In this case, when processing the last PRE command, there is a constraint defined by the tRAS parameter between the ACT command and the PRE command. Similarly, there is another constraint between the RD command and the PRE command. In most cases, the timing of the PRE command is determined by one of the constraints, but in some cases, constraints may be applied simultaneously. In any case, the bank state classification means 103 in this embodiment only retains information about the one command issued immediately before as history (SAME_PRE_TIME and SAME_PRE_CMD). Therefore, in the above example, the constraint from the ACT command cannot be determined. However, this premise does not limit the present invention in any way. That is, the above example can be handled by having at least two or more histories and determining each constraint in step 714. In addition, by listing the constraints that may arise due to the specifications of the SDRAM being analyzed and the limitations of the memory controller 205, and modifying the system to retain a history sufficient to address all of them, there should be no constraints that cannot be addressed.

[0029] The following describes the processing of the bank state classification means 103 in detail, using the example of using event information entries 610 to 615 in Figure 6 as the actual input for bank 220, i.e., bank number 0. In this example, we assume that 1 clock cycle = 1000 ps. Figures 9, 1001 to 1016, show the processing results when event information entries 610 to 615 are input. The processing of event information entries 610 to 615 will be explained below with reference to the processing results. First, before the input of the event information entries, bank number 0 is input in step 701. In steps 702 and 703, FIX_TIME=0, SAME_PRE_TIME=0, SAME_PRE_CMD=UNDEF, DIFF_PRE_TIME=0, and DIFF_PRE_CMD=UNDEF are reset, respectively. Next, in step 704, event information entry 610 is read. The bank address 603 of the event information entry is 0, which matches the bank number in the argument. Therefore, in step 707, it is determined to be Yes. At this point, SAME_PRE_CMD is UNDEF, so steps 708, 711, and 714 all result in No. Furthermore, at this point, FIX_TIME=0, DIFF_PRE_TIME=0, and DIFF_PRE_CMD=UNDEF, so steps 717 and 720 all result in No. As a result, in step 723, one clock cycle from FIX_TIME=0 to the occurrence time of the current event information entry 610 (1000) is classified as a hibernation state. Subsequently, in step 724, FIX_TIME is set to 1000. In Figure 99, the hibernation state of 901 and one cycle are confirmed, and then in step 725, SAME_PRE_CMD=ACT and SAME_PRE_TIME=1000 are set, and the process returns to step 704 via step 726.

[0030] Next, event information entry 611 is read and its processing begins. The bank address 603 of event information entry 611 is 1, which does not match the bank number in the argument. Therefore, it is determined to be No in step 707. In this case, in step 727, DIFF_PRE_CMD=ACT and DIFF_PRE_TIME=31000 are set, and the process returns to step 704 via step 726.

[0031] In processing event information entry 612, bank address 603 is 0, which matches the bank number in the argument. Therefore, step 707 determines it as Yes. At this point, SAME_PRE_CMD is the ACT command, so steps 708 and 711 both determine it as No. In step 714, in the table in Figure 8, SAME_PRE_CMD = ACT command, and the command 602 of the current event information entry 612 is the RD command, so 30 cycles are applicable. On the other hand, the occurrence time 601 of the current event information entry 612 is 31000, so the period from SAME_PRE_TIME is 32000 - 1000 = 31000, which is 31 clock cycles. The results do not match, so the determination in step 714 is No, and the process proceeds to step 729. Since DIFF_PRE_TIME=31000, the difference with SAME_PRE_TIME is 31000-1000=30000, which is 30 clock cycles, and matches the 30 clock cycles set in the table in Figure 8. Furthermore, the difference between the occurrence time of event information entry 612, 32000, and SAME_PRE_TIME is 33000-32000=1000, which is 1 clock cycle, and is determined to be Yes in step 729. Next, in step 715, the 31 clock cycles from FIX_TIME=1000 to the current occurrence time of event information entry 612, 601, at 32000 are classified as an inoperable state. Subsequently, in step 716, FIX_TIME is set to 32000. In Figure 9, the inoperable state of 902 and 31 cycles are confirmed. Then, in step 725, SAME_PRE_CMD=RD and SAME_PRE_TIME=32000 are set, and the process returns to step 704 via step 726.

[0032] In processing event information entry 613, bank address 603 is 0, which matches the bank number in the argument. Therefore, step 707 determines it as Yes. At this point, the command is SAME_PRE_CMD=RD, so step 708 determines it as Yes. Accordingly, step 709 classifies the period from FIX_TIME 32000 to 4 clock cycles into the operational state. Next, step 710 sets FIX_TIME to 36000. Steps 714 and 729 determine it as No. Furthermore, at this point, FIX_TIME=36000, DIFF_PRE_TIME=31000, and DIFF_PRE_CMD=ACT, so steps 717 and 720 both determine it as No. As a result, step 723 attempts to classify the period from FIX_TIME=36000 to the current event information entry 613's occurrence time 601 at 36000 into the hibernation state, but since the difference is 0, no classification is ultimately performed. Therefore, in step 724, FIX_TIME=36000 matches the current event information entry 613's occurrence time 601, which is 36000, so no actual update occurs. In Figure 9, the operating state of 903, 4 cycles, is confirmed. Subsequently, in step 725, SAME_PRE_CMD=RD and SAME_PRE_TIME=36000 are set, and the process returns to step 704 via step 726.

[0033] In processing event information entry 614, bank address 603 is 0, which matches the bank number in the argument. Therefore, step 707 determines it as Yes. At this point, the SAME_PRE_CMD=RD command is used, so step 708 determines it as Yes. Consequently, in step 709, four clock cycles from FIX_TIME 36000 are classified as operational. Next, in step 710, FIX_TIME is set to 40000. Subsequent steps 714 and 729 determine it as No. Furthermore, at this point, FIX_TIME=40000, DIFF_PRE_TIME=31000, and DIFF_PRE_CMD=ACT, so both steps 717 and 720 determine it as No. As a result, in step 723, unlike in the case of event information entry 613, one clock cycle from FIX_TIME=40000 to 41000 (the occurrence time 601 of the current event information entry 614) is classified as a paused state. Next, in step 724, FIX_TIME is set to 41000. In Figure 9, the operating state of 904, 4 cycles, and the idle state of 905, 1 cycle, are now confirmed. After that, in step 725, SAME_PRE_CMD=RD and SAME_PRE_TIME=41000 are set, and the process returns to step 704 via step 726.

[0034] From this point onward, the processing of bank 221 is carried out in the same way as that already described for bank 220. As a result, 908 to 909 in Figure 9 are finalized. For banks 222 to 227, since no control commands were generated in event information 102 in Figure 6, they all enter a dormant state.

[0035] In this embodiment, information on commands to banks other than the argument bank is retained for only one instance in the past. Therefore, if two or more commands to banks other than the argument bank take precedence, and the issuance interval between command 602 in the current event information entry and the previous command DIFF_SAME_CMD to the argument bank is two or more cycles longer than the command issuance interval constraint set in the table in Figure 8, it cannot be classified as an inoperable state. However, by retaining information on two or more instances of commands to banks other than the argument bank, it is also possible to define an inoperable state if commands to banks other than the argument bank take precedence and the issuance interval is two or more cycles longer.

[0036] Furthermore, in this embodiment, since only one piece of command information for the argument bank and for banks other than the argument bank is stored in the past, when a command for a bank other than the argument bank takes precedence, the period between two or more previous commands for banks other than the argument bank and the command 602 in the current event information entry cannot be classified as an inoperable state. However, by storing two or more pieces of command information for banks other than the argument bank in the past, the period between two or more previous commands for banks other than the argument bank and the command 602 in the current event information entry can be similarly defined as an inoperable state.

[0037] Furthermore, in this embodiment, as shown in the flowchart of Figure 7, the inoperability status classification by the two commands issued to the argument bank is processed before the inoperability status classification by the commands issued to banks other than the argument bank and the commands issued to the argument bank, and only one of them is processed at a time. Therefore, if both occur simultaneously, the inoperability status classification by the two commands issued to the argument bank takes precedence. However, by changing the processing order, it is possible to prioritize the inoperability status classification by the commands issued to banks other than the argument bank and the commands issued to the argument bank. Also, regardless of the inoperability status classification, it is possible to sum the periods for the two classifications by executing both processes.

[0038] (Other embodiments) The present invention can also be realized by supplying a program that implements one or more of the functions of the above-described embodiments to a system or device via a network or storage medium, and by having one or more processors in the computer of that system or device read and execute the program. It can also be realized by a circuit (e.g., an ASIC) that implements one or more functions. [Explanation of Symbols]

[0039] 101 Detection means 102 Event Information 103 Bank status classification means 104 Bank Status Information

Claims

1. A detection means for detecting an event that causes a state transition in at least one bank constituting the DRAM, The system includes a classification means that, based on the events detected by the detection means, classifies the state of at least one of the following: operating state, non-operating state, and idle state. The classification means applies to a predetermined bank included in at least one of the banks: When a preceding first control command and a second control command that follows the first control command at an interval longer than a predetermined period are detected, An information processing device characterized in that, if a control command to a bank other than the predetermined bank is detected within the predetermined period, the predetermined bank is classified as being in an inoperable state.

2. The classification means applies to a predetermined bank included in at least one of the banks: When a preceding first control command and a second control command that follows the first control command at an interval longer than a predetermined period are detected, The information processing device according to claim 1, characterized in that if no control command to a bank other than the predetermined bank is detected within the predetermined period, the predetermined bank is classified as being in a dormant state.

3. The information processing apparatus according to claim 1 or 2, characterized in that the aforementioned operating state is a state in which data is being transferred.

4. The information processing apparatus according to any one of claims 1 to 3, characterized in that the aforementioned inoperable state is a state in which data cannot be transferred due to predetermined constraints.

5. The information processing apparatus according to any one of claims 1 to 4, characterized in that the aforementioned pause state is a state in which there are no restrictions but no data is being transferred.

6. The information processing apparatus according to any one of claims 1 to 5, further comprising control means for displaying the results classified by the classification means on a display means.

7. The information processing apparatus according to any one of claims 1 to 6, characterized in that the first control command and the second control command are commands for accessing DRAM.

8. A detection step in which the detection means detects an event that causes a transition in the state of at least one bank constituting the DRAM, The classification means includes a classification step of classifying the state of at least one of the following: operating state, non-operating state, and idle state, based on the events detected in the detection step. In the classification step, for a predetermined bank included in at least one of the banks, When a preceding first control command and a second control command that follows the first control command at an interval longer than a predetermined period are detected, An information processing method characterized in that if a control command to a bank other than the predetermined bank is detected within the predetermined period, the predetermined bank is classified as being in an inoperable state.

9. Computers, A detection means for detecting an event that causes a state transition in at least one bank constituting the DRAM, The system includes a classification means that, based on the events detected by the detection means, classifies the state of at least one of the following: operating state, non-operating state, and idle state. The classification means applies to a predetermined bank included in at least one of the banks: When a preceding first control command and a second control command that follows the first control command at an interval longer than a predetermined period are detected, A computer program for functioning as an information processing device, characterized in that if a control command to a bank other than the predetermined bank is detected within the predetermined period, the predetermined bank is classified as being in an inoperable state.

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