Diamond semiconductor structure and method for manufacturing the same

Abstract

To provide a diamond semiconductor structure in which a p-type diamond semiconductor layer is formed to be buried at a target position in an n-type diamond semiconductor layer, and a method of manufacturing the same.SOLUTION: A diamond semiconductor structure 10 of the present invention is characterized in that a p-type diamond semiconductor layer 2 (3) is buried in a recess formed on a surface of an n-type diamond semiconductor layer 1, the surface being the {111} plane. A method of manufacturing a diamond semiconductor structure of the present invention is characterized to include: a recess formation step of forming a recess on a surface of an n-type diamond semiconductor layer by etching, the surface being the {111} plane; and a p-type diamond semiconductor layer burying step of burying a p-type diamond semiconductor layer in the recess by lateral growth of a p-type diamond semiconductor layer precursor along the in-plane direction of the surface from a side surface of the recess.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a diamond semiconductor structure in which a p-type diamond semiconductor region is embedded in an n-type diamond semiconductor layer, and to a method for manufacturing the same. [Background technology]

[0002] Diamond has a wide bandgap compared to silicon, and also possesses high melting point, thermal conductivity, dielectric breakdown resistance, carrier velocity limit, hardness and elastic constants, chemical stability, and radiation resistance, giving it extremely high potential as a material for forming power devices.

[0003] However, it is difficult to achieve localized impurity doping in diamond by applying the ion implantation techniques that are established for silicon. Therefore, a method has been proposed to selectively deposit a p-type diamond semiconductor layer on an n-type diamond semiconductor layer using chemical vapor deposition (CVD), and to process the shape of the p-type diamond semiconductor layer as needed, thereby forming a device structure in which an n-type diamond semiconductor layer and a p-type diamond semiconductor layer are arranged at the desired positions (see Patent Document 1 and Non-Patent Document 1).

[0004] According to this proposal, for example, inverting MOSFET operation can be realized using the diamond semiconductor device 100 shown in Figure 1. Figure 1 is an explanatory diagram showing an example configuration of a conventional diamond semiconductor device. Specifically, the diamond semiconductor device 100 is configured to include an n-type diamond semiconductor layer 101, a source region 102 and a drain region 103 composed of a p-type diamond semiconductor layer stacked on the n-type diamond semiconductor layer 101, a gate electrode 105 disposed on the n-type diamond semiconductor layer 101 between the source region 102 and the drain region 103 via a gate insulating film 104, a source electrode 106 disposed on the source region 102, and a drain electrode 107 disposed on the drain region 103. In the diamond semiconductor device 100 configured in this way, inverted MOSFET operation is realized by controlling the gate voltage to the gate electrode 105, causing a drain current to flow between the source region 102 and the drain region 103 through an inversion layer channel 108 formed in the n-type diamond semiconductor layer 101 directly beneath the gate electrode 105.

[0005] However, in the diamond semiconductor device 100, since the source region 102 and drain region 103 are deposited on the n-type diamond semiconductor layer 101, the inversion layer channel 108 and the source region 102 and drain region 103 come into contact only at extremely limited locations, as shown by the black circles in the enlarged section of Figure 1. As a result, there is a problem in that it is difficult to obtain the desired drain current.

[0006] Incidentally, the aforementioned chemical vapor deposition (CVD) method is effective for forming diamond layers, and a technique for forming diamond layers that are grown laterally in the in-plane direction of the layer by adjusting the growth conditions during the growth of single-crystal diamond has been reported (see Non-Patent Document 2). This formation technique is highly innovative and can solve problems in diamond growth using the chemical vapor deposition (CVD) method, such as stacking faults.

[0007] However, there are no reported cases of forming p-type diamond semiconductor layers containing p-type impurities using lateral growth technology, and this remains unclear. [Prior art documents] [Patent Documents]

[0008] [Patent Document 1] Patent No. 6717470 [Non-patent literature]

[0009] [Non-Patent Document 1] Tsubasa. Matsumoto et al. Scientific Reports 6, 31585 (2016).

Non-Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0010] An object of the present invention is to solve the above problems in the prior art and provide a diamond semiconductor structure in which a p-type diamond semiconductor layer is embedded and formed at a target position in an n-type diamond semiconductor layer, and a method for manufacturing the same.

Means for Solving the Problems

[0011] Means for solving the above problems are as follows. That is, <1> A p-type diamond semiconductor layer is embedded in a recess formed on the surface of an n-type diamond semiconductor layer whose surface is a {111} plane At least one of the p-type diamond semiconductor layer surface and the n-type diamond semiconductor layer surface is an atomically flat surface. A diamond semiconductor structure characterized by being <2> The diamond semiconductor structure according to <1>, wherein the surface of the p-type diamond semiconductor layer is an atomically flat surface. <3> The diamond semiconductor structure according to <1> or <2>, wherein the surface of the n-type diamond semiconductor layer is an atomically flat surface. <4> The diamond semiconductor structure according to any one of <1> to <3>, wherein an atomically flat surface is formed between the surface of the p-type diamond semiconductor layer and the surface of the n-type diamond semiconductor layer. <5> The diamond semiconductor structure according to any one of <1> to <4>, wherein the p-type diamond semiconductor layer is a layer containing boron. <6> The diamond semiconductor structure according to <5>, wherein the boron concentration in the p-type diamond semiconductor layer is 1×10 19 cm -3 or more. <7> Two recesses formed on the surface of the n-type diamond semiconductor layer are each filled with a p-type diamond semiconductor layer, and the p-type impurity concentration of the p-type diamond semiconductor layer is 1×10 19 cm -3 ~1×10 21 cm -3 and the n-type impurity concentration of the n-type diamond semiconductor layer is 1×10 14 cm -3 ~1×10 18 cm -3 The diamond semiconductor structure according to any one of <1> to <6> above, having a structural portion with such a structure. <8> A recess forming step of forming a recess by etching on the surface of an n-type diamond semiconductor layer whose surface is a {111} plane, and a p-type diamond semiconductor layer embedding step of embedding a p-type diamond semiconductor layer in the recess by lateral growth of a p-type diamond semiconductor layer precursor along the in-plane direction of the surface from the side surface of the recess. A method for manufacturing a diamond semiconductor structure, characterized by including the steps.

Effect of the Invention

[0012] According to the present invention, the above-mentioned various problems in the prior art can be solved, and a diamond semiconductor structure in which a p-type diamond semiconductor layer is embedded and formed at a target position in an n-type diamond semiconductor layer and a method for manufacturing the same can be provided.

Brief Description of the Drawings

[0013] [Figure 1] It is an explanatory diagram showing a configuration example of a diamond semiconductor device according to a conventional example. [Figure 2] It is an explanatory diagram showing a configuration example of a diamond semiconductor device to which the diamond semiconductor structure according to the present invention is applied. [Figure 3(a)] It is an explanatory diagram (1) for explaining a step of forming an n-type diamond semiconductor layer by a lateral growth method. [Figure 3(b)] It is an explanatory diagram (2) for explaining a step of forming an n-type diamond semiconductor layer by a lateral growth method. [Figure 3(c)]This is an explanatory diagram (3) illustrating the process of forming an n-type diamond semiconductor layer by the lateral growth method. [Figure 4] This is an explanatory diagram illustrating the outline of the recess formation process. [Figure 5] This is an explanatory diagram illustrating the outline of the p-type diamond semiconductor layer embedding process. [Figure 6(a)] Figure (1) shows an explanatory model of lateral growth in the p-type diamond semiconductor layer embedding process. [Figure 6(b)] Figure (2) shows an explanatory model for lateral growth in the p-type diamond semiconductor layer embedding process. [Figure 6(c)] Figure (3) shows an explanatory model for lateral growth in the p-type diamond semiconductor layer embedding process. [Figure 6(d)] Figure (4) shows an explanatory model of lateral growth in the p-type diamond semiconductor layer embedding process. [Figure 7(a)] This figure shows a microscopic image of the surface of the prepared diamond substrate 1. [Figure 7(b)] This figure shows a microscopic image of the surface of the diamond substrate 1 after the formation of recesses. [Figure 7(c)] This figure shows a microscopic image of the surface of diamond substrate 1 after the first lateral growth procedure. [Figure 7(d)] This figure shows a microscopic image of the surface of diamond substrate 1 after the second lateral growth procedure. [Figure 8] This figure shows the AFM image in Figure 7(c) with the analysis results added. [Figure 9] This figure shows the B concentration imaging results for the region correlated with the LM image region enclosed by a rectangle in Figure 7(d). [Figure 10] This figure shows the quantitative B concentration distribution obtained by dynamic SIMS analysis. [Figure 11] This figure shows a surface potential microscope (KFM) image taken at the same location as the AFM image in Figure 7(d'). [Figure 12(a)] This figure shows the location of the AFM image to be analyzed. [Figure 12(b)]This figure shows the results of the analysis of the elevation difference between the embedded area and the surrounding area. [Figure 13(a)] This is an explanatory diagram illustrating the implantation region in a state where B-doping has not been performed. [Figure 13(b)] This is an explanatory diagram illustrating the embedded region in a B-doped state. [Modes for carrying out the invention]

[0014] (Diamond semiconductor structure and method for manufacturing the same) An example of applying the diamond semiconductor structure of the present invention to a diamond semiconductor device operating as an inverting MOSFET will be described with reference to Figure 2. Figure 2 is an explanatory diagram showing an example configuration of a diamond semiconductor device to which the diamond semiconductor structure of the present invention is applied.

[0015] As shown in Figure 2, the diamond semiconductor device 10 includes an n-type diamond semiconductor layer 1, a p-type diamond semiconductor layer 2 constituting a source region, a p-type diamond semiconductor layer 3 constituting a drain region, a gate electrode 5 disposed on the n-type diamond semiconductor layer 1 between the p-type diamond semiconductor layer (source region) 2 and the p-type diamond semiconductor layer (drain region) 3 via a gate insulating film 4, a source electrode 6 disposed on the p-type diamond semiconductor layer 2, and a drain electrode 7 disposed on the p-type diamond semiconductor layer 3.

[0016] In comparison with a conventional diamond semiconductor device 100 (see Figure 1), the gate insulating film 4, gate electrode 5, source electrode 6, and drain electrode 7 are configured similarly to the gate insulating film 104, gate electrode 105, source electrode 106, and drain electrode 107, and are formed by conventionally known methods.

[0017] On the other hand, the structure composed of an n-type diamond semiconductor layer 1, a p-type diamond semiconductor layer (source region) 2, and a p-type diamond semiconductor layer (drain region) 3 has a different configuration from the source region 102 and drain region 103, which are composed of two p-type diamond semiconductor layers stacked on the n-type diamond semiconductor layer 1. Specifically, the structure is constructed by embedding a p-type diamond semiconductor layer (source region) 2 and a p-type diamond semiconductor layer (drain region) 3 in two recesses formed on the surface of an n-type diamond semiconductor layer 1.

[0018] In the diamond semiconductor device 10 configured in this way, similar to the conventional diamond semiconductor device 100, inverting MOSFET operation is achieved by controlling the gate voltage to the gate electrode 5, thereby enabling drain current to flow through an inversion layer channel 8 formed in the n-type diamond semiconductor layer 1 directly beneath the gate electrode 5.

[0019] However, in the diamond semiconductor device 10 having the above structure, unlike the conventional diamond semiconductor device 100, the embedding effect of the p-type diamond semiconductor layers 2 and 3 in the n-type diamond semiconductor layer 1 causes the sides of these embedded layers to be in surface contact with the inversion layer channel 8 at the interface (see enlarged section in Figure 2). Therefore, in the diamond semiconductor device 10, the conventional problem (see enlarged section in Figure 1) in which the inversion layer channel 108 and the source region 102 and drain region 103 make contact only at extremely limited locations can be resolved, and device performance that matches the theoretical design can be obtained based on a stabilized drain current.

[0020] The problem lies in whether it is possible to selectively embed and form a p-type diamond semiconductor layer 2(3) in an n-type diamond semiconductor layer 1 to which the ion implantation technology established for silicon cannot be applied. This problem is solved by the following method for manufacturing diamond semiconductor structures.

[0021] First, an n-type diamond semiconductor layer 1 with a {111} plane is prepared. As the n-type diamond semiconductor layer 1, the following two formation methods are used to obtain an n-type impurity concentration of 1 × 10⁻¹⁶ that is suitable for inverting MOSFET operation. 14 cm -3 ~1 × 10 18 cm -3 It is said that it can be formed as an n-type diamond semiconductor layer.

[0022] A first method for forming the n-type diamond semiconductor layer 1 is to uniformly deposit the forming material onto a known diamond substrate having an off-angle such that its surface is a {111} plane by a plasma vapor deposition method using a source gas containing methane and an n-type conductive material (phosphorus or nitrogen), thereby forming an n-type diamond semiconductor layer whose surface is a {111} plane that conforms to the surface properties of the diamond substrate.

[0023] Furthermore, a second method for forming the n-type diamond semiconductor layer 1 is the lateral growth method described in Non-Patent Document 2. According to the lateral growth method, an n-type diamond semiconductor layer 1 with an atomically flat surface can be obtained. In this specification, "atomic flat surface" refers to a surface having irregularities of at least 1 to 3 step heights, with the step height of a single bi-layer (BL) on the {111} plane of diamond as an element. It means that the surface roughness RMS measured with an atomic force microscope (e.g., Shimadzu SPM-9700 atomic force microscope system) in an arbitrarily selected 500 nm × 500 nm surface region is 0.3 nm or less. Furthermore, the surface roughness RMS is more preferably 0.2 nm or less, and particularly preferably 0.1 nm or less.

[0024] The process for forming the n-type diamond semiconductor layer 1 by the lateral growth method will be explained with reference to Figures 3(a) to 3(c). First, a known diamond substrate is prepared, which has been processed to a predetermined size by mesa processing or the like, and whose surface has an off-angle (θ: approximately 1° to 5°) such that it is a {111} plane (see Figure 3(a)). Next, precursor 1' is grown by plasma vapor deposition using a source gas containing methane and n-type conductive materials (phosphorus and nitrogen). When the growth conditions are adjusted to a low methane concentration, precursor 1' selectively grows only in the lateral direction (the direction of terrace extension) from the step edge of the diamond substrate (indicated by the downward arrow in Figure 3(a)) (see Figure 3(b)). Finally, the precursor 1' grows laterally to completely cover the surface of the original diamond substrate, forming a step-free n-type diamond semiconductor layer 1 with an atomically flat surface (Figure 3(c)). In this specification, "lateral growth" means crystal growth in a direction along the in-plane direction of an n-type diamond layer whose surface is a {111} plane.

[0025] Next, recesses H are formed on the surface of the n-type diamond semiconductor layer 1 by etching, as shown in Figure 4 (recess formation process, see Figure 4). Figure 4 is an explanatory diagram illustrating the overview of the recess formation process. There are no particular restrictions on the etching method; for example, known inductively coupled plasma (ICP) etching methods can be used. There are no particular restrictions on the opening width W (maximum diameter) of the recess (etched hole) H, but from the viewpoint of processing accuracy, it is preferable to have an opening width of approximately 100 nm to 1 mm. Furthermore, there are no particular restrictions on the depth D of the recess (etched hole) H, but it is preferable that it be about 5 nm to 100 nm from the viewpoint of contact resistance with the channel.

[0026] Next, as shown in Figure 5, p-type diamond semiconductor layers 2 and 3 are embedded in the recess H by lateral growth of a p-type diamond semiconductor layer precursor (also simply called a precursor) along the in-plane direction of the surface from the side surface of the recess H (p-type diamond semiconductor layer embedding process). Figure 5 is an explanatory diagram illustrating the outline of the p-type diamond semiconductor layer embedding process.

[0027] As a method for forming the p-type diamond semiconductor layers 2 and 3 by lateral growth of the aforementioned precursor, a plasma vapor deposition method using a source gas containing methane and a p-type conductive material (boron) can be mentioned. In other words, even when p-type impurities are present, lateral growth can be applied by adjusting the growth conditions. Typical lateral growth conditions for p-type diamond semiconductor layers 2 and 3 in recess H include a temperature of 1,160°C, plasma input power of 1,050W, hydrogen gas flow rate of 500 sccm, methane gas flow rate of 0.97 sccm, trimethylborane gas flow rate of 1.52 sccm, methane concentration in the gas (CH4 / H2) of 0.2 volume%, boron / carbon (B / C) ratio in the gas phase of 15,000 ppm, and pressure of 30 kPa. By the plasma vapor deposition method based on these lateral growth conditions, it is possible to form p-type diamond semiconductor layers 2 and 3 whose surfaces (exposed surfaces) are atomically flat when embedded. Furthermore, the p-type diamond semiconductor layers 2 and 3, as constituent layers of the source region and the drain region, have a p-type impurity concentration of 1 × 10, which is suitable for inverting MOSFET operation. 19 cm -3 ~1 × 10 21 cm -3 It is said that it can be formed as a p-type diamond semiconductor layer. These findings form the core of the technology in this invention.

[0028] The lateral growth of the p-type diamond semiconductor layers 2 and 3 in the recess H will be explained in detail with reference to Figures 6(a) to (d). Figures 6(a) to (d) are diagrams illustrating the explanatory model of lateral growth in the p-type diamond semiconductor layer embedding process. First, the precursor 2'(3') of the p-type diamond semiconductor layer 2(3) begins to grow from the bottom side of the etching hole. The growth is lateral growth starting from the side of the etching hole (see Figure 6(a)). Next, once one layer of precursor 2'(3') is formed at the bottommost surface, other layers similarly grow laterally on top of this first layer (see Figure 6(b)). As the lateral growth of precursor 2'(3') progresses, the layered structure of the first layer and the other layer is sequentially formed toward the open end. When lateral growth progresses in this model, a roughly inverted triangular depression can be observed in cross-sectional view in the region where the etching hole is formed (see Figure 6(c)). Finally, when the layer closest to the open end is stacked, the etching holes are completely filled, and the embedding of the p-type diamond semiconductor layers 2 and 3 is completed (see Figure 6(d)). At the same time, since there is no side surface of the etching hole that serves as the starting point for lateral growth at the position on the outermost open end of the layer, the growth of the p-type diamond semiconductor layers 2 and 3 also stops. In other words, the excess growth stops automatically, governed by the shape of the etching hole (height of the side surface), regardless of the control of the plasma vapor deposition apparatus.

[0029] Referring again to Figure 5, the features of the diamond semiconductor structure according to the present invention will be explained. As shown in Figure 5, in the diamond semiconductor structure, a p-type diamond semiconductor layer 2(3) is embedded in a recess H formed on the surface of an n-type diamond semiconductor layer 1 whose surface is a {111} plane. This allows for the formation of a p-type diamond semiconductor layer 2(3) at the desired location on the n-type diamond semiconductor layer 1, enabling stabilization of the drain current by these embedded layers (see enlarged section in Figure 2).

[0030] Furthermore, since the embedded p-type diamond semiconductor layer 2(3) is formed by lateral growth, its surface (exposed surface) is an atomically flat surface. This enables good contact between the source electrode 6 and the drain electrode 7.

[0031] Furthermore, when the surface of the n-type diamond semiconductor layer 1 is made atomically flat in a step-free manner by the second formation method, its flatness is maintained even after the p-type diamond semiconductor layer embedding process. This is because the growth of the p-type diamond semiconductor layers 2 and 3 is governed by the shape of the etching holes (height of the sides), and in addition to their own excess growth, deposition and growth at unwanted locations on the n-type diamond semiconductor layer 1 are suppressed. In other words, the surface of the n-type diamond semiconductor layer 1 can be made atomically flat even with the p-type diamond semiconductor layers 2 (3) embedded.

[0032] Incidentally, in conventional diamond semiconductor devices 100 (see Figure 1), as reported in Reference 1 below, the surface roughness of the n-type diamond semiconductor layer 101 is large, and the surface has wavy undulations called bunching steps. These bunching steps are factors that hinder the generation of surface roughness scattering and surface OH termination, and generate interface states, which are defect states, between this surface and the gate insulating film 104 formed on it. As a result, the carrier channel mobility decreases significantly, causing the device performance of the diamond semiconductor device 100 to fall far below the theoretical design. Therefore, ensuring that the surface of the n-type diamond semiconductor layer 1 is atomically flat is of extremely important significance in suppressing the decrease in channel mobility and improving the device performance of the diamond semiconductor device 10 (see Figure 2). Reference 1: T. Matsumoto et al. Appl. Phys. Lett. 114, 242101 (2019).

[0033] In addition, the fact that the growth of the p-type diamond semiconductor layers 2 and 3 in the recess H is governed by the shape of the etching hole (height of the side surface) suppresses the occurrence of height differences in the direction perpendicular to the surface between the surface of the p-type diamond semiconductor layer 2 (3) and the surface of the n-type diamond semiconductor layer 1, making it possible to form an atomically flat surface between the surfaces of the p-type diamond semiconductor layers 2 and 3 and the surface of the n-type diamond semiconductor layer 1, thereby providing an atomically flat surface over the entire surface. This facilitates the fabrication of various device structures formed on the diamond semiconductor structure.

[0034] The diamond semiconductor structure and its manufacturing method of the present invention serve as an alternative technology to ion implantation technology for silicon, but provide the diamond semiconductor structure with an ideal surface free from ion implantation marks, thereby enabling the provision of an ideal diamond semiconductor device that cannot be achieved with ion implantation technology. The following describes embodiments of the present invention, but the technical concept of the present invention is not limited to these embodiments. [Examples]

[0035] The diamond semiconductor structure according to the embodiment was manufactured as follows. Here, the diamond semiconductor structure is manufactured in accordance with the structure shown in Figure 5, and the reference numerals are the same as those used in Figures 4 and 5.

[0036] First, a diamond substrate (Type Ib substrate) 1 was prepared, which was offset at a slight inclination angle of 2.5° and had a {111} plane on its surface. After mesa processing, the diamond substrate 1 is subjected to step flow growth under a nitrogen atmosphere (see Figures 3(a) to (c)) to make its surface atomically flat. Furthermore, the nitrogen concentration in the substrate, as measured by a SIMS (secondary ion mass spectrometry) instrument (CAMECA, IMS-7f), is 1 × 10⁻⁶. 18 cm -3 This is an n-type substrate, and the n-type diamond semiconductor layer is denoted by the symbol 1, and the explanation continues.

[0037] Next, using a photolithography apparatus (Mikasa Corporation, MA-20), an Au / Ti mask was formed on the surface of the diamond substrate 1 so as to cover all areas except for the positions where the recesses H (see Figure 4) were to be formed. Next, anisotropic etching was performed on the diamond substrate 1 using an inductively coupled plasma etching apparatus (ICP apparatus, ULVAC, CE-300I) in a direction perpendicular to the in-plane direction of the surface, thereby forming recesses H in the diamond substrate 1 by etching holes (see Figure 4). The conditions for forming the recesses H were: etching gas: O2; 95 sccm and CF4; 2 sccm, RF power: 500 W, bias: 50 W, pressure: 2 Pa. The opening shape of the recesses H was a square shape of 10 μm × 10 μm, and the etching depth was 0.085 μm.

[0038] Next, a cleaning process using a cleaning solution (H2SO4, H2O2) was performed at a temperature of 120°C to remove the mask from the diamond substrate 1.

[0039] Next, the diamond substrate 1 was mounted on a microwave plasma-assisted chemical vapor deposition (MPCVD) system (manufactured by Arios Inc., Tokyo, Japan) and subjected to hydrogen plasma treatment to remove defects on the diamond substrate 1 caused by ICP etching. The conditions for the hydrogen plasma treatment were: power: 650W, pressure: 30kPa, and treatment time: 3 minutes.

[0040] Next, a p-type diamond semiconductor layer 2(3) was formed as a boron-doped layer in the recess H using the microwave plasma-assisted chemical vapor deposition system (see Figure 5). Lateral growth mode (see Figures 6(a)-(d)) was applied to form the p-type diamond semiconductor layer 2(3), with the following growth conditions: substrate temperature: 1,160°C, plasma input power: 1,050W, hydrogen gas flow rate: 500 sccm, methane gas flow rate: 0.97 sccm, trimethyl borate gas flow rate: 1.52 sccm, methane concentration in gas (CH4 / H2): 0.2 volume%, boron / carbon (B / C) ratio in the gas phase: 15,000 ppm, and pressure: 30 kPa. Lateral growth of the p-type diamond semiconductor layer 2(3) was carried out in two separate time steps under the aforementioned growth conditions, with the first step lasting over 5 minutes and the second step lasting over 8 minutes. The reason for carrying out the growth in two steps was to observe the state of the precursor 2'(3') (see Figures 6(a)~(c)) during the growth process at the end of the first step. Based on the above, the diamond semiconductor structure according to the embodiment was manufactured.

[0041] The surface morphology on the diamond substrate 1 at each manufacturing stage of the diamond semiconductor structure according to the embodiment will be described with reference to Figures 7(a) to (d). Figure 7(a) is a microscopic image of the surface of the prepared diamond substrate 1, Figure 7(b) is a microscopic image of the surface of the diamond substrate 1 after recess formation, Figure 7(c) is a microscopic image of the surface of the diamond substrate 1 after the first lateral growth, and Figure 7(d) is a microscopic image of the surface of the diamond substrate 1 after the second lateral growth. In all figures, the upper microscopic image (x) shows the LM image, and the lower microscopic image (x') shows the AFM image of the region correlated with the region enclosed by a rectangle in the LM image. For acquiring LM images, an Olympus LEXT OLS4100 laser microscope system was used, and for acquiring AFM images, a Shimadzu SPM-9700 atomic force microscope system was used.

[0042] The root mean square (RMS) surface roughness of the diamond substrate 1 surface, as analyzed from the lower AFM image in Figure 7(a), was 0.05 nm. This value corresponds to the noise level of the atomic force microscope used, indicating that the surface of diamond substrate 1 is atomically flat. Furthermore, as can be seen from the microscopic image in Figure 7(b), recesses H with a size of 10 μm × 10 μm × 0.085 μm (85 nm) are formed on the surface of the diamond substrate 1. Furthermore, as can be seen from the microscope image in Figure 7(c), at the time of the first lateral growth, the p-type diamond semiconductor layer 2(3) is still growing, and a hole shape with a depth of 82 nm is maintained at its deepest point. On the other hand, as can be seen from the microscopic image in Figure 7(d), at the time of the second lateral growth, the hole has disappeared and is completely filled with the p-type diamond semiconductor layer 2(3). Furthermore, surprisingly, the RMS surface roughness of both the embedded region, which is the surface of the p-type diamond semiconductor layer 2(3), and its surrounding region (the surface of the diamond substrate 1) is 0.04 ± 0.01 nm, indicating that the surface of the p-type diamond semiconductor layer 2(3) remains atomically flat, just as the surface of the diamond substrate 1 remains atomically flat.

[0043] Here, we examine the lateral growth of the p-type diamond semiconductor layer 2(3) while referring to Figure 8, which adds the analysis results to the AFM image in Figure 7(c). As shown in the upper part of Figure 8, the growth of precursor 2'(3') was observed in three directions, and all of these directions correspond to the crystal orientation <112>. In other words, precursor 2'(3') grows laterally from the side surface of recess H toward the center of recess H. Furthermore, as is evident from the cross-sectional structure shown in the lower part of Figure 8, the shape of the recess H changes from its original rectangular shape to a roughly inverted triangular depression due to partial backfilling caused by the lateral growth of precursor 2'(3'). These results first confirm that the backfilling of the p-type diamond semiconductor layer 2(3) proceeds independently of vertical depositional growth from the bottom surface of the recess H upwards. Second, it can be confirmed that the lateral growth of the precursor 2'(3') begins from the bottom surface of the recess H and proceeds in a manner in which another layer of precursor 2'(3') grows laterally on top of a layer of precursor 2'(3') that has grown laterally from the side surface of the recess H. These findings strongly support the establishment of the backfilling process for the p-type diamond semiconductor layer 2(3), as explained with reference to Figures 6(a) to (d), and clearly suggest that the lateral growth layers of the precursor 2'(3') are sequentially stacked from the bottom side toward the opening side, ultimately forming a backfilling layer of the p-type diamond semiconductor layer 2(3) (see Figure 7(d)) ​​throughout the entire recess H.

[0044] Next, the doping status of B in the diamond semiconductor structure according to the embodiment will be explained with reference to Figure 9. Figure 9 shows the B concentration imaging results of a region correlated with the LM image region enclosed by a rectangle in Figure 7(d). The B concentration imaging is an image of the dynamic SIMS analysis results by the SIMS analyzer, and in the figure, the B concentration of the embedded region and its surrounding region in the XY plane (upper center), XZ cross section (lower center), and YZ cross section (right side) is imaged with color according to the concentration.

[0045] From the imaging results of the XY plane (upper center) in Figure 9, it can be confirmed that the embedded region of the p-type diamond semiconductor layer 2(3) is doped with B at a higher concentration than the surrounding region. Furthermore, the imaging results of the XZ cross section (lower center) and the YZ cross section (right side) show that this B-doped region extends to the depth of the recess H (85 nm), indicating that the B-doped structure can be selectively formed only in the target region of the diamond substrate 1, i.e., the region where the recess H is formed. In Figure 9, the imaging results for the XY plane (upper center), XZ cross section (lower center), and YZ cross section (right side) show that the whitish coloring indicates B-doping, and in the central part of the B-doped region, darker coloring (strong side) indicates even higher concentrations of B-doping.

[0046] Next, Figure 10 shows the quantitative B concentration distribution obtained by dynamic SIMS analysis. As shown in Figure 10, the embedded area is approximately 2 × 10 20 atoms / cm 3 It is confirmed that B is doped at this concentration. This value is sufficient to obtain inverting MOSFET operation and can also be changed depending on the source gas concentration of B.

[0047] Next, Figure 11 shows a surface potential microscope (KFM) image taken at the same location as the AFM image in Figure 7(d). The KFM image was acquired using the atomic force microscope system described above.

[0048] As shown in Figure 11, a surface potential difference of approximately 0.02 ± 0.004 V was detected between the embedded region and the surrounding region. The error value of ±0.004 V was calculated using statistical processing with Gaussian fitting. The surface potential difference of 0.02±0.004V is smaller than the potential difference between a typical B-doped film and a nitrogen-doped film, which is thought to be due to problems in the imaging environment. The measurement results in Figure 11 show different potentials between the embedded region and the surrounding region, which is thought to indicate that a backfill layer (see Figure 7(d)) ​​of the p-type diamond semiconductor layer 2(3) was formed in the recess H of the n-type diamond substrate 1.

[0049] Incidentally, in the analysis of the AFM image in Figure 7(d), it was confirmed that the surface height position of the embedded region is slightly higher than that of the surrounding region. This point will be explained with reference to Figures 12(a) and (b). Figure 12(a) shows the analysis target position of the AFM image, and Figure 12(b) shows the analysis results of the height difference between the embedded region and the surrounding region. The height difference analysis was performed by using the rectangular region enclosed by the black line at the bottom of Figure 12(a) as the analysis target, and averaging the surface height positions measured between the embedded region and the surrounding region at regular intervals, using the lateral position in the x direction in the figure as a function.

[0050] As shown in Figure 12(b), the surface height position of the embedded region is approximately 0.04 ± 0.01 nm higher than the surface height position of the surrounding region. The error value of ±0.001 nm was calculated using statistical processing with Gaussian fitting. This height difference is far smaller than the typical step height (approximately 0.21 nm) of a single bi-layer (BL) on the {111} plane of a diamond substrate. Therefore, this difference in height is thought to be due to the fluctuation in the lattice constant caused by the large amount of B doping. The lattice constant of diamond (3.5670 Å) is known to increase with increasing B doping concentration, and the rate of increase in the lattice constant is 0.176 × 10⁻⁶. -23 Å / cm 3 It is known that this is the case. Therefore, 2 × 10 20 atoms / cm 3 In the case of the B-doping concentration, the increase in the lattice constant is 0.000352 Å, which can be obtained by multiplying the B-doping concentration by the rate of increase. Considering the three-dimensional expansion of the unit cell, the expansion rate per unit volume can be calculated as shown in equation (1).

[0051]

number

[0052] From the above calculations, the volume change rate is estimated to be 0.000296. Here, the size of the recess H is 10 μm × 10 μm × 85 nm, and assuming that the volume expansion in the 10 μm vertical × 10 μm horizontal direction of the opening surface is blocked by the body of the diamond substrate 1, it can be inferred that the volume expansion will only affect the direction of the opening height of 85 nm. Therefore, from the perspective of the increase in the lattice constant and the subsequent volume expansion due to B doping, the approximate value of the surface height in the embedded region can be calculated as 0.02516 nm by multiplying the height of the recess H (85 nm) by a volume change rate of 0.000296. A calculation model for the volume expansion of the embedded region due to heavy doping of B is shown in Figures 13(a) and 13(b). Figure 13(a) is an explanatory diagram illustrating the embedded region without B doping, and Figure 13(b) is an explanatory diagram illustrating the embedded region with B doping.

[0053] The calculated value of 0.02516 nm is relatively close to the measured value of 0.04 ± 0.01 nm, leading to the conclusion that the difference in height is due to fluctuations in the lattice constant caused by the large amount of doping with B. In other words, the result that the surface height position of the embedded region is slightly higher than that of the surrounding region also serves as evidence supporting high-concentration doping of B in the embedded region. In addition, this height difference is much smaller than the typical step height (approximately 0.21 nm) of a single bi-layer (BL) on the {111} plane of a diamond substrate, resulting in these surfaces being atomically flat across the embedded region and its surrounding regions. [Explanation of Symbols]

[0054] 1. n-type diamond semiconductor layer (diamond substrate) 1',2',3' Precursors 2,3 p-type diamond semiconductor layer 4,104 Gate Insulator 5,105 Gate Stop 6,106 source electrodes 7,107 Drain electrode 8,108 Inverted Channel Layer 10,100 Diamond semiconductor devices 10¹ n-type diamond semiconductor layer 102 Source Area 103 Drain area

Claims

1. A diamond semiconductor structure characterized in that a p-type diamond semiconductor layer is embedded in a recess formed on the surface of an n-type diamond semiconductor layer whose surface is a {111} plane, and at least one of the surfaces of the p-type diamond semiconductor layer and the n-type diamond semiconductor layer is an atomically flat surface.

2. The diamond semiconductor structure according to claim 1, wherein the surface of the p-type diamond semiconductor layer is an atomically flat surface.

3. The diamond semiconductor structure according to claim 1 or 2, wherein the surface of the n-type diamond semiconductor layer is an atomically flat surface.

4. The diamond semiconductor structure according to claim 1 or 2, wherein an atomic flat surface is formed between the surface of a p-type diamond semiconductor layer and the surface of an n-type diamond semiconductor layer.

5. The diamond semiconductor structure according to claim 1 or 2, wherein the p-type diamond semiconductor layer is a layer containing boron.

6. The boron concentration in the p-type diamond semiconductor layer is 1 × 10⁻⁶ １９ cm －３ The diamond semiconductor structure according to claim 5, as described above.

7. A p-type diamond semiconductor layer is embedded in each of two recesses formed on the surface of an n-type diamond semiconductor layer, the p-type impurity concentration of the p-type diamond semiconductor layer being 1 × 10 １９ cm －３ to 1 × 10 ２１ cm －３ and the n-type impurity concentration of the n-type diamond semiconductor layer being 1 × 10 １４ cm －３ to 1 × 10 １８ cm －３ The diamond semiconductor structure according to claim 1 or 2, having a structural portion as described above.

8. A recess formation step in which recesses are formed by etching on the surface of an n-type diamond semiconductor layer whose surface is a {111} plane, A p-type diamond semiconductor layer embedding step, in which a p-type diamond semiconductor layer is embedded in the recess by lateral growth of a p-type diamond semiconductor layer precursor along the in-plane direction of the surface from the side surface of the recess, A method for manufacturing a diamond semiconductor structure, characterized by including the following:

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