Semiconductor memory device and test method

Abstract

Even if the number of defective cells decreases due to manufacturing variations, the security of authentication will not be compromised. [Solution] The non-volatile memory 24 stores the address of the first defective cell. The second non-volatile memory 25 stores the address of the second defective cell which is at least partially different from the first defective cell. The decoding circuits 17 and 18 decode the address received from the external device to the physical location of the first memory cell 12. If the address received from the external device matches the address of the first defective cell stored in the non-volatile memory 24, the decoding circuits 17 and 18 decode the address received from the external device to the physical location of the second memory cell 12 which is different from the first memory cell 12. The arithmetic circuit 26 performs a predetermined calculation on the address of the second defective cell stored in the second non-volatile memory 25 and outputs the generated calculation value to the external device.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor memory device and a test method.

Background Art

[0002] In recent years, with the spread of the IoT (Internet of Things), the need for a low-cost and low-load authentication technology for the security of terminal devices has been increasing. Such terminal devices typically include a semiconductor memory device such as a DRAM (Dynamic Random Access Memory). Generally, a semiconductor memory device manufactured using a wafer process or the like has defective cells unique to each individual device. Therefore, for example, it is conceivable to authenticate a semiconductor memory device based on the addresses of defective cells.

[0003] For example, Patent Documents 1 and 2 disclose a semiconductor memory device that is authenticated based on the addresses of defective cells.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] The number and distribution of defective cells cannot be controlled by the manufacturing process and are random for each individual device. Among mass-produced semiconductor memory devices, there is a possibility that some may have a very small number of defective cells due to manufacturing variations. In this case, the size of the confidential data used for authentication (i.e., the address of the defective cell) becomes smaller, which could make the confidential data inferred from the outside, potentially reducing the security of authentication. Therefore, it is necessary to ensure that the security of authentication is not reduced even if the number of defective cells decreases due to manufacturing variations.

[0006] The purpose of this disclosure is to provide a semiconductor memory device that is authenticated based on the address of a defective cell, wherein the authentication security is not compromised even if the number of defective cells decreases due to manufacturing variations. Another purpose of this disclosure is to provide a method for testing such a semiconductor memory device. [Means for solving the problem]

[0007] A semiconductor memory device relating to one aspect of this disclosure is Multiple memory cells arranged two-dimensionally along multiple rows and multiple columns, A first non-volatile memory that stores the addresses of a plurality of first faulty cells among the plurality of memory cells, A second non-volatile memory that stores the addresses of a plurality of second defective cells, which are at least partially different from the plurality of first defective cells among the plurality of memory cells, An input / output circuit that receives addresses and commands from an external device and sends and receives data to and from the external device, A decoding circuit that decodes an address received from the external device to a physical location among the plurality of memory cells, wherein if the address received from the external device does not match the address of the first faulty cell stored in the first non-volatile memory, the decoding circuit decodes the address received from the external device to the physical location of a first memory cell among the plurality of memory cells, and if the address received from the external device matches the address of the first faulty cell stored in the first non-volatile memory, the decoding circuit decodes the address received from the external device to the physical location of a second memory cell different from the first memory cell among the plurality of memory cells, The system includes an arithmetic circuit that performs a predetermined calculation on the address of the second defective cell stored in the second non-volatile memory and outputs the generated calculation value to the external device. [Effects of the Invention]

[0008] According to one aspect of this disclosure, the objective is to provide a semiconductor memory device in which authentication security is not compromised even if the number of defective cells decreases due to manufacturing variations. [Brief explanation of the drawing]

[0009] [Figure 1] This block diagram shows the configuration of a data processing device including a DRAM (Dynamic Random Access Memory) chip 1 according to an embodiment. [Figure 2] This figure shows multiple sub-arrays 11 included in the memory cell array 10. [Figure 3] Figure 2 shows the configuration of the sub-array 11 and the sense amplifier circuit 14. [Figure 4] Figure 3 shows the detailed configuration of the memory cell 12. [Figure 5] Figure 3 shows the detailed configuration of the sense amplifier 32 and its surrounding circuits. [Figure 6] This figure illustrates the address of a faulty cell stored in the non-volatile memory 24 of Figure 1 and how to replace the faulty cell. [Figure 7] It is a diagram for explaining the addresses of defective cells stored in the non-volatile memory 25 of FIG. 1. [Figure 8] It is a block diagram showing a configuration for detecting defective cells in the DRAM chip 1 of FIG. 1. [Figure 9] It is a graph showing the relationship between the number of defective cells and the charge holding time of the capacitor 42 of FIG. 4. [Figure 10] It is a flowchart showing the memory test process executed by the memory tester 4 of FIG. 8. [Figure 11] It is a diagram for explaining the addition of an offset value to the addresses of defective cells detected by executing the memory test process of FIG. 9. [Figure 12] It is a block diagram showing a configuration for authenticating the DRAM chip 1 of FIG. 1. [Figure 13] It is a block diagram showing the detailed configuration of the arithmetic circuit of FIG. 12.

Mode for Carrying Out the Invention

[0010] Hereinafter, referring to the drawings, a semiconductor memory device and a test method thereof according to an embodiment of the present disclosure will be described. In each drawing, the same reference numerals denote the same components.

[0011] [Configuration of Embodiment] FIG. 1 is a block diagram showing the configuration of a data processing device including a DRAM (Dynamic Random Access Memory) chip 1 according to an embodiment. The data processing device of FIG. 1 includes a DRAM chip 1, a memory controller 2, and a processor 3.

[0012] The memory controller 2 transmits a command CMD and an address ADD to the DRAM chip 1 under the control of the processor 3, and transmits and receives a data signal DATA to and from the DRAM chip 1.

[0013] The DRAM chip 1 includes a memory cell array 10, an input / output circuit 21, a memory cell array control circuit 22, a data processing circuit 23, a non-volatile memory 24, a non-volatile memory 25, and an arithmetic circuit 26.

[0014] The memory cell array 10 includes a plurality of memory cells 12, a plurality of bit lines 13, a plurality of sense amplifier circuits 14, a plurality of word lines 15, a plurality of column selection lines 16, a row decoding circuit 17, and a column decoding circuit 18.

[0015] The plurality of memory cells 12 are two-dimensionally arranged along a plurality of word lines 15 and a plurality of column selection lines 16 that are orthogonal to each other, that is, along a plurality of rows and a plurality of columns. Each memory cell 12 arranged along a word line 15 is connected or disconnected to each bit line 13 by a switching element that operates according to the active or inactive state of the word line 15. The plurality of memory cells 12 include normal cells and redundant cells. A normal cell is a memory cell 12 associated with a predetermined row address and column address at the time of designing the DRAM chip 1. A redundant cell is a memory cell 12 that replaces a defective normal cell when any normal cell is defective (also referred to as a "defective cell"). Defective cells are replaced with redundant cells in units of rows or columns. The row of redundant cells, that is, the plurality of redundant cells connected to the same word line 15, is called a "redundant row", and the column of redundant cells, that is, the plurality of redundant cells connected to the same bit line 13, is called a "redundant column". The entire row or column including the defective cell is replaced with a redundant row or redundant column.

[0016] Each of the plurality of sense amplifier circuits 14 includes a plurality of sense amplifiers respectively connected to the plurality of bit lines 13. Each sense amplifier circuit 14 amplifies the data read from the memory cell 12.

[0017] The plurality of column selection lines 16 select one of the plurality of sense amplifiers of each sense amplifier circuit 14.

[0018] The row decoding circuit 17 comprises multiple word line drivers, each connected to a plurality of word lines 15. The row decoding circuit 17 receives a control signal from the memory cell array control circuit 22, which includes the row address ADD_R of a normal cell, and receives the row address DEF_R of a faulty cell from the non-volatile memory 24. If the row address ADD_R sent from the memory cell array control circuit 22 does not match the row address DEF_R sent from the non-volatile memory 24, the row decoding circuit 17 decodes the row address ADD_R sent from the memory cell array control circuit 22 to the physical location of a word line 15 connected to a normal cell and selects one or more of the plurality of word lines 15. If the row address ADD_R sent from the memory cell array control circuit 22 matches the row address DEF_R sent from the non-volatile memory 24, the row decoding circuit 17 decodes the row address ADD_R sent from the memory cell array control circuit 22 to the physical location of a word line 15 connected to a redundant cell and selects one or more of the plurality of word lines 15. This allows defective cells to be replaced with redundant cells, row by row.

[0019] The column decoding circuit 18 comprises multiple column selection line drivers, each connected to a plurality of column selection lines 16. The column decoding circuit 18 receives a control signal from the memory cell array control circuit 22, which includes the column address ADD_C of a normal cell, and receives the column address DEF_C of a faulty cell from the non-volatile memory 24. If the column address ADD_C sent from the memory cell array control circuit 22 does not match the column address DEF_C sent from the non-volatile memory 24, the column decoding circuit 18 decodes the column address ADD_C sent from the memory cell array control circuit 22 to the physical location of a column selection line 16 connected to a normal cell and selects one or more of the plurality of column selection lines 16. If the column address ADD_C sent from the memory cell array control circuit 22 matches the column address DEF_C sent from the non-volatile memory 24, the column decoding circuit 18 decodes the column address ADD_C sent from the memory cell array control circuit 22 to the physical location of a column selection line 16 connected to a redundant cell and selects one or more of the plurality of column selection lines 16. This allows defective cells to be replaced with redundant cells, column by column.

[0020] In Figure 1, for the sake of simplicity, only one memory cell 12, one bit line 13, one word line 15, one column selection line 16, and one sense amplifier circuit 14 are shown.

[0021] The input / output circuit 21 receives the command CMD and address ADD from the memory controller 2 and sends and receives the data signal DATA to and from the memory controller 2. If the command CMD is for reading or writing data, the input / output circuit 21 sends the command CMD and address ADD to the memory cell array control circuit 22, and further sends and receives the data signal DATA to each sense amplifier of the sense amplifier circuit 14 via the data processing circuit 23. Also, as will be described later with reference to Figure 8, the input / output circuit 21 receives the addresses DEF1 and DEF2 of the defective cells detected by executing the memory test process from the memory tester 4, and stores the addresses DEF1 and DEF2 in the non-volatile memories 24 and 25, respectively. Furthermore, as will be described later with reference to Figure 12, the input / output circuit 21 sends the challenge signal CHA received from the authentication device 5 to the arithmetic circuit 26, and sends the response signal RES returned from the arithmetic circuit 26 to the authentication device 5.

[0022] The memory cell array control circuit 22 receives the command CMD and address ADD from the input / output circuit 21 and generates control signals for the row decode circuit 17 and the column decode circuit 18. The control signal for the row decode circuit 17 includes the row address ADD_R of each word line 15 and activates or deactivates each word line 15. The control signal for the column decode circuit 18 includes the column address ADD_C of each column selection line 16 and activates or deactivates each column selection line 16. In this way, the memory cell array control circuit 22 is a control circuit that activates or deactivates each sense amplifier of the sense amplifier circuit 14, each word line 15, and each column selection line 16.

[0023] Furthermore, the memory cell array control circuit 22 recovers the data in the memory cell 12 through a series of operations: activating the word line 15 by row access, amplifying the charge in the memory cell 12 with a sense amplifier, storing the amplified charge in the memory cell 12, and then deactivating the word line 15. This series of operations is called "refresh".

[0024] Non-volatile memory 24 stores the addresses DEF1 of multiple first defective cells among the multiple memory cells 12. Address DEF1 includes the row address DEF_R and the column address DEF_C. Non-volatile memory 25 stores the addresses DEF2 of multiple second defective cells among the multiple memory cells 12 that are at least partially different from the multiple first defective cells. The row address DEF_R and column address DEF_C of the defective cells stored in non-volatile memory 24 are sent to the row decode circuit 17 and the column decode circuit 18, respectively, as described above, and are used to replace the defective cells with redundant cells. The addresses DEF2 of the defective cells stored in non-volatile memory 25 are sent to the arithmetic circuit 26. The arithmetic circuit 26 performs a predetermined operation on the addresses DEF2 of the defective cells stored in non-volatile memory 25, as will be described later with reference to Figure 12, etc. Address DEF2 is not used to replace the defective cells with redundant cells.

[0025] The capacity of the non-volatile memory 24 is set to be equal to, for example, the product of the bit length of the address of each memory cell 12 (e.g., 10 to 20 bits) and the number of redundant cells. The capacity of the non-volatile memory 25 is set to be able to store, for example, a sufficient number of bad cell addresses DEF2 to maintain authentication security. The non-volatile memory 25 may have a larger capacity than the non-volatile memory 24. The non-volatile memory 25 may also store more second bad cell addresses DEF2 than the number of first bad cells.

[0026] The non-volatile memory 25 may store only the row address for multiple defective cells, or only the column address for multiple defective cells, or it may store either the row address or the column address for each of the multiple defective cells.

[0027] The non-volatile memories 24 and 25 may include a dielectric film that can break down dielectrically, for example, a gate oxide film of a transistor that can break down dielectrically by high voltage. In this case, the gate oxide film is broken down dielectrically by a control circuit (not shown) provided on the DRAM chip 1. The gate oxide film that becomes conductive due to dielectric breakdown represents "1", and the gate oxide film that is not broken down and remains non-conductive represents "0". The non-volatile memories 24 and 25 may be equipped with a fuse that can be cut instead of a dielectric film that can break down dielectrically, and may be configured to be rewritable.

[0028] Figure 2 shows a plurality of sub-arrays 11 included in the memory cell array 10 of Figure 1. The memory cell array 10 includes a plurality of sub-arrays 11, each containing a plurality of memory cells 12 arranged in two dimensions. Each of the plurality of sub-arrays 11 is connected to two of the plurality of sense amplifier circuits 14. Two adjacent sub-arrays 11 share one of the plurality of sense amplifier circuits 14.

[0029] Figure 3 shows the configuration of the subarray 11 and sense amplifier circuit 14 in Figure 2. Each subarray 11 comprises at least a plurality of memory cells 12, a plurality of bit lines 13, and a plurality of word lines 15. The plurality of word lines 15 are connected to a plurality of word line drivers 31 of the row decoding circuit 17, respectively. Each word line driver 31 activates the corresponding word line. Each sense amplifier circuit 14 comprises a plurality of sense amplifiers 32 and peripheral circuits (not shown). Each sense amplifier 32 is connected to bit lines 13-1, 13-2, which are included in two adjacent subarrays 11, respectively.

[0030] Figure 4 shows the detailed configuration of the memory cell 12 in Figure 3. Each memory cell 12 comprises a switching element 41 and a capacitor 42. The gate of the switching element 41 is connected to the word line 15, its source is connected to the bit line 13, and its drain is connected to a node with a constant potential (e.g., a ground cell) via the capacitor 42. When the word line 15 is activated, the charge state (high-level or low-level potential) held in the capacitor 42 is read out to the bit line 13.

[0031] Figure 5 shows the detailed configuration of the sense amplifier 32 and peripheral circuits shown in Figure 3. The sense amplifier 32 is connected to bit lines 13-1 and 13-2 (see Figure 3). The sense amplifier 32 includes switching elements 51 to 54. Switching elements 51 and 53 are NMOS transistors, and switching elements 52 and 54 are PMOS transistors, and switching elements 51 to 54 are connected to each other as shown in Figure 5. The sense amplifier circuit 14 further includes switching elements 55 and 56. Bit lines 13-1 and 13-2 are further connected to data lines 58-1 and 58-2 via switching elements 55 and 56. The gates of switching elements 55 and 56 are connected to one of several column selection line drivers 57 of the column decoding circuit 18 via column selection line 16. Data lines 58-1 and 58-2 are connected to the data processing circuit 23 (see Figure 1). The high-level or low-level potential read from the memory cell 12 to the bit line 13-1 or 13-2 is amplified by the sense amplifier 32. When the column selection line 16 is activated by the column selection line driver 57, the switching elements 55 and 56 connect the bit lines 13-1 and 13-2 to the data lines 58-1 and 58-2. As a result, the amplified potential on the bit lines 13-1 and 13-2, i.e., the data stored in the memory cell 12, is read to the data processing circuit 23.

[0032] [Operation of the Embodiment] The operation of the DRAM chip 1 according to the embodiment, namely, the replacement of defective cells, the detection of defective cells, and the authentication of the DRAM chip 1, will be described below.

[0033] [Replacing defective cells] First, please refer to Figure 6 to explain the process of replacing defective cells with redundant cells.

[0034] Figure 6 is a diagram illustrating the addresses of faulty cells stored in the non-volatile memory 24 of Figure 1 and the replacement of faulty cells. The memory cell array 10 includes, for example, faulty cells 12a, 12b, and 12c. Faulty cell 12a exists alone and not consecutively in the row and column directions, and is hereinafter also referred to as a "single-cell fault". Faulty cell 12b exists consecutively along the row direction, and is hereinafter also referred to as an "X-line fault". Faulty cell 12c exists consecutively along the column direction, and is hereinafter also referred to as a "Y-line fault". Causes of faulty cells include hardware failures such as micro-shorts and open circuits, and also include insufficient operating margins for memory cells 12 and sense amplifiers 32, etc.

[0035] The DRAM chip 1 is tested before shipment, thereby detecting defective cells 12a, 12b, and 12c. The row or column addresses of the detected defective cells 12a, 12b, and 12c are stored in the non-volatile memory 24. In the example in Figure 6, the address of column 61 containing the defective cell 12a (single-cell defect), the address of row 62 containing the defective cell 12b (X-line defect), and the address of column 63 containing the defective cell 12c (Y-line defect) are stored in the non-volatile memory 24. As a result, the defective cells 12a, 12b, and 12c are replaced with redundant rows or columns, as shown in Figure 6. Column 61 containing the defective cell 12a (single-cell defect), i.e., multiple memory cells 12 connected to the same bit line 13 as the defective cell 12a, is replaced with a redundant column 61a. Row 62 containing the defective cell 12b (X-line defect), i.e., multiple memory cells 12 connected to the same word line 15 as the defective cell 12b, is replaced with a redundant row 62a. Column 63 containing the defective cell 12c of the Y line failure, i.e., multiple memory cells 12 connected to the same bit line 13 as the defective cell 12c, is replaced by a redundant column 63a. A redundant row 62a replaces all memory cells 12 connected to a certain word line 15 from the top to the bottom of the memory cell array 10. Redundant columns 61a and 63a replace all memory cells 12 connected to a certain bit line 13 from the left to the right of the subarray 11.

[0036] When row 62 or column 61,63 containing a faulty cell is accessed, row 62 or column 61,63 is replaced with redundant row 62a or redundant column 61a,63a. This enables normal writing, reading, and storage of data for all addresses.

[0037] Here, we will explain why the defective cell 12a, which is a single-cell defect, is replaced by a redundant column rather than a redundant row. In recent DRAMs, word lines are formed using a technique called "embedded word lines." Embedded word lines have a structure in which the word lines are embedded in grooves formed in the silicon substrate. Therefore, short circuits between word lines 15 and other wiring, such as short circuits between word lines 15 or between word lines 15 and bit lines 13, are very unlikely to occur. For this reason, defective cells 12b with X-line defects are very rare. On the other hand, the sense amplifier 32 has a complex configuration including two NMOS transistors and two PMOS transistors, as explained with reference to Figure 4. For this reason, the sense amplifier 32 is susceptible to variations in the threshold voltages of these MOS transistors. Also, since the sense amplifier 32 does not have an embedded structure, micro-shorts with adjacent bit lines 13 are likely to occur. For these reasons, defective cells 12c with Y-line defects are relatively likely to occur. Defective cell 12a, which is a single-cell defect, may be a sign of a defect that will develop into a Y-line defect in the future. For these reasons, a single cell that is defective, such as cell 12a, is, in principle, replaced with a redundant column 61a. If no redundant columns remain available, the defective cell is replaced with a redundant row.

[0038] As explained with reference to Figure 6, the addresses of the faulty cells are stored in non-volatile memory 24 and used to replace the faulty cells with redundant cells. On the other hand, as mentioned above, in addition to the addresses of the faulty cells stored in non-volatile memory 24, the addresses of the faulty cells are also stored in non-volatile memory 25.

[0039] Figure 7 is a diagram illustrating the addresses of the defective cells stored in the non-volatile memory 25 of Figure 1. As previously mentioned, the non-volatile memory 25 stores the addresses of defective cells that are at least partially different from the defective cells stored in the non-volatile memory 24. The memory cell array 10 includes a single-cell defective cell 12aa, an X-line defective cell 12bb, and a Y-line defective cell 12cc, as in Figure 6.

[0040] Before shipment, DRAM chip 1 is tested under different conditions than those used to detect the defective cells 12a, 12b, and 12c in Figure 6, thereby detecting the defective cells 12aa, 12bb, and 12cc. The row or column addresses of the detected defective cells 12aa, 12bb, and 12cc are stored in non-volatile memory 25. In the example in Figure 7, the address of row 71 containing the defective cell 12aa (single cell defect), the address of row 72 containing the defective cell 12bb (X-line defect), and the address of column 73 containing the defective cell 12cc (Y-line defect) are stored in non-volatile memory 25. As a result, DRAM chip 1 is authenticated based on the addresses of the defective cells stored in non-volatile memory 25, as will be described later with reference to Figure 12, etc.

[0041] The address of the faulty cell stored in the non-volatile memory 25 is not used to replace the faulty cell, but is used as confidential data to authenticate the DRAM chip 1. Therefore, even if a single faulty cell 12aa is detected, there is no need to consider that this faulty cell 12aa may develop into a Y-line fault in the future, and the non-volatile memory 25 may store either the row address or the column address of the faulty cell 12aa.

[0042] [Detection of defective cells] Next, we will describe the operation for detecting a defective cell in the DRAM chip 1 according to the embodiment.

[0043] Figure 8 is a block diagram showing the configuration for detecting a faulty cell in the DRAM chip 1 shown in Figure 1. To detect a faulty cell, the DRAM chip 1 is connected to a memory tester 4. The memory tester 4 includes, for example, a processor that runs an operating system and a test program, a pattern generator that generates test data, and a timing generator that adjusts the time for applying and judging the test data. The memory tester 4 determines the addresses DEF1 and DEF2 of the faulty cells by executing the memory test process shown in Figure 10 and stores them in non-volatile memories 24 and 25, respectively.

[0044] As mentioned above, if a DRAM chip has a very small number of defective cells, the size of the confidential data used for authentication (i.e., the addresses of the defective cells) becomes small, which may reduce the security of authentication. Therefore, it is necessary to ensure that the security of authentication is not reduced even if the number of defective cells decreases due to manufacturing variations. The DRAM chip 1 according to this embodiment includes two non-volatile memories 24 and 25 for storing the addresses of defective cells. The DRAM chip 1 replaces defective cells with redundant cells based on the address DEF1 of the defective cell stored in the non-volatile memory 24. Furthermore, as will be described later with reference to Figure 12, the DRAM chip 1 is authenticated based on the address DEF2 of the defective cell stored in the non-volatile memory 25. The non-volatile memory 25 stores a sufficient number of addresses DEF2 of defective cells to maintain the security of authentication, independently of the address DEF1 of the defective cell stored in the non-volatile memory 24, that is, regardless of the actual number of defective cells that should be replaced with redundant cells. Therefore, by testing the DRAM chip 1 under the first condition, the address DEF1 stored in the non-volatile memory 24 is determined, and by testing the DRAM chip 1 under the second condition, which is different from the first condition, the address DEF2 stored in the non-volatile memory 25 is determined. The second condition is set so that a larger number of memory cells 12 are detected as faulty cells than in the first condition. In other words, the second condition is a "stricter" condition than the first condition.

[0045] As mentioned above, the causes of defective cells include hardware defects such as micro-shorts and open circuits, as well as insufficient operating margins for memory cells 12 and sense amplifiers 32. The number of defective cells due to insufficient operating margins increases by imposing stricter operating conditions. Methods for tightening operating conditions include, for example, increasing the charge retention time, lowering the power supply voltage, increasing the temperature, and increasing the operating speed. In general, DRAM stores data by accumulating charge in the capacitors of memory cells. Therefore, if the charge of the capacitor decreases due to leakage current flowing through various paths, the memory cell will no longer be able to retain data. In this case, a single cell defect that is not continuous in the row and column directions occurs. To prevent this, DRAM requires refreshing to restore the charge of the capacitor at regular time intervals. The longer the refresh time period, that is, the longer the charge retention time of the capacitor 42, the more defective cells there are. Also, the lower the power supply voltage of the DRAM chip 1, the smaller the acceptable amount of charge reduction becomes, and therefore the more defective cells there are. Furthermore, the leakage current of capacitor 42 is temperature-dependent, with the leakage current increasing as the temperature rises. As a result, the higher the temperature of the memory cell array 10, the worse the charge retention characteristics of capacitor 42 become, and consequently, the number of defective cells increases. Also, as the operating speed of the DRAM chip 1 increases, the operating margin decreases, and consequently, the number of defective cells increases.

[0046] Figure 9 is a graph showing the relationship between the charge retention time of capacitor 42 in Figure 4 and the number of defective cells. As mentioned above, the charge of capacitor 42 gradually decreases over time due to leakage current, and eventually it becomes unable to retain charge. Memory cells 12 that do not meet the specified charge retention time are judged to be defective cells. Generally, the charge retention time T0 required for DRAM memory cells is 32 to 64 milliseconds, according to the JEDEC (Joint Electron Device Engineering Council) specification. If the charge retention time T1 meets the specification, N1 memory cells 12 are judged to be defective cells. By imposing a longer charge retention time T2, a larger number of N2 memory cells 12 are judged to be defective cells.

[0047] Figure 10 is a flowchart showing the memory test process performed by the memory tester 4 in Figure 8. The process in Figure 10 is performed after the manufacturing of the DRAM chip 1 and before shipment.

[0048] In step S1, the memory tester 4 sets first conditions for testing the DRAM chip 1. The first conditions include predetermined charge retention time, power supply voltage, temperature, and operating speed of the DRAM chip 1. The first conditions are set so that normal data can be written to, read from, and stored in the DRAM chip 1. The memory tester 4 also sets the number of redundant rows and columns of the DRAM chip 1 as a threshold for the number of rows and columns containing defective cells.

[0049] In step S2, the memory tester 4 tests the DRAM chip 1 under the first conditions using a predetermined test method and detects a defective cell among the memory cells 12.

[0050] In step S3, the memory tester 4 determines whether the number of rows and columns containing defective cells is less than or equal to a threshold, i.e., the number of redundant rows and columns. If the answer is YES, the tester proceeds to step S4; otherwise, it proceeds to step S9. The memory tester 4 may also proceed to step S9 immediately if it detects a number of defective cells in rows or columns that exceeds the number of redundant rows or columns in step S2.

[0051] In step S4, the memory tester 4 stores the addresses of the row and column containing the defective cell detected in step S2 in the non-volatile memory 24.

[0052] In step S5, the memory tester 4 sets a second condition for testing the DRAM chip 1. The second condition has a stricter charge retention time, power supply voltage, temperature, or operating speed for the DRAM chip 1 than the first condition. The second condition is set so that a larger number of memory cells 12 are detected as faulty cells than in the case of the first condition. The memory tester 4 also sets a threshold for the number of faulty cells to be sufficient to maintain authentication security. This threshold may be set to a value much larger than the number of redundant rows and columns of the DRAM chip 1.

[0053] In step S6, the memory tester 4 tests the DRAM chip 1 under second conditions using a predetermined test method and detects a faulty cell among the memory cells 12.

[0054] In step S7, the memory tester 4 stores the addresses of the row and column containing the defective cell detected in step S6 in the non-volatile memory 25.

[0055] In step S8, the memory tester 4 determines that the DRAM chip 1 has passed the test related to the first condition and is ready for shipment.

[0056] In step S9, the memory tester 4 determines that DRAM chip 1 is defective and cannot be shipped.

[0057] Steps S1 to S4 are performed to obtain the addresses of the faulty cells that will be replaced by redundant cells. Steps S5 to S7 are performed to obtain the secret data used to authenticate DRAM chip 1.

[0058] The defective cells detected in step S6 may include single cell defects that are not consecutive in the row and column directions. In this case, the memory tester 4 may store either the row address or the column address of the single cell defect in the non-volatile memory 25.

[0059] Instead of setting different conditions in steps S1 and S5, or in addition to that, different test methods may be used in steps S2 and S6. As mentioned above, the addresses of the defective cells stored in the non-volatile memory 25 are not used to replace the defective cells with redundant cells, but are used solely to authenticate the DRAM chip 1. Therefore, any test method may be used in steps S2 and S6, as long as a sufficient number of defective cells are detected in step S6 to maintain the security of the authentication.

[0060] By testing the DRAM chip 1 under predetermined conditions, faulty cells can be replaced with redundant cells, ensuring the normal writing, reading, and storage of data to the DRAM chip 1. Depending on the wafer or lot, the quality of the manufactured DRAM chip 1 may be very high, with very few faulty cells. In this case, by testing the DRAM chip 1 under more stringent conditions, it is possible to obtain the addresses of a sufficient number of faulty cells to maintain the security of the authentication. Thus, by performing the process shown in Figure 10, it is possible to prevent a decrease in the security of the authentication even if the number of faulty cells decreases due to manufacturing variations.

[0061] When the DRAM chip 1 is tested under excessively harsh conditions, a large number of defective cells may be detected, exceeding the capacity of the non-volatile memory 25. Generally, the memory tester has a threshold set for the number of rows and columns containing defective cells, and if the number of rows or columns containing the detected defective cells exceeds the threshold, the memory tester determines that the DRAM chip is defective and terminates the test. In this case, the addresses of the defective cells are not stored in the non-volatile memory of the DRAM chip. On the other hand, according to the DRAM chip 1 of this embodiment, the addresses of the defective cells stored in the non-volatile memory 25 are not used to replace the defective cells with redundant cells, but are used as confidential data for authenticating the DRAM chip 1. Therefore, the addresses of all defective cells detected in step S6 do not need to be stored in the non-volatile memory 25. For this reason, as mentioned above, in step S5, the memory tester 4 may set a threshold much larger than the number of redundant rows and columns. In step S6, the memory tester 4 continues testing the DRAM chip 1 even if the number of rows or columns containing the detected faulty cells exceeds the number of redundant rows or columns. In step S7, the memory tester 4 starts writing the addresses of the detected faulty cells to the non-volatile memory 25 and stops writing when the non-volatile memory 25 is fully written. The circuitry of the DRAM chip 1 may be designed to stop writing when the non-volatile memory 25 is fully written. In this case, the memory test process shown in Figure 10 can be performed by an existing (i.e., conventional) memory tester.

[0062] Figure 11 illustrates the addition of offset values ​​to the addresses of faulty cells detected by performing the memory test process shown in Figure 9. When the memory cell array 10 includes multiple sub-arrays 11, a large number of faulty cells may be detected in one sub-array, while only a few or none may be detected in other sub-arrays. Such an imbalance in faulty cells can make confidential data easier to guess from the outside, potentially reducing the security of authentication. For this reason, the addresses of multiple faulty cells may be distributed across the entire memory cell array 10 by adding different offset values ​​to the addresses of multiple faulty cells detected in one sub-array.

[0063] In this case, under the second condition, the memory tester 4 detects multiple second faulty cells in the first subarray of the multiple subarrays 11. In the example in Figure 11, faulty cells 12a-1 to 12a-3 are detected in subarray 11-0. The memory tester 4 then adds one of at least two distinct offset values ​​to each address of the multiple second faulty cells so that the addresses are distributed across at least two of the multiple subarrays 11. In the example in Figure 11, by adding offset values ​​a1 to a3 to their addresses, the faulty cells 12a-11 to 12a-13 are moved to the positions of faulty cells 12a-11 to 12a-13 in subarrays 11-1 to 11-3, respectively. The offset values ​​may be positive or negative. The memory tester 4 then stores the addresses of the multiple second faulty cells with the added offset values ​​in the second non-volatile memory 25.

[0064] For example, the memory tester 4 may add offset values ​​0, 1, 2, ..., N-1, 0, 1, 2, ..., N-1, ... to the part representing the subarray number at the address of multiple faulty cells, where N represents the total number of subarrays.

[0065] As shown in the example in Figure 11, the security of authentication can be improved by distributing the addresses of multiple faulty cells stored in the non-volatile memory 25 across the entire memory cell array 10.

[0066] [DRAM chip certification] Next, the operation for authenticating the DRAM chip 1 according to the embodiment will be described.

[0067] Figure 12 is a block diagram showing the configuration for authenticating the DRAM chip 1 shown in Figure 1.

[0068] The authentication device 5 pre-stores the response signal RES, which is returned from the DRAM chip 1 when it transmits a predetermined challenge signal CHA to the DRAM chip 1, in its internal memory.

[0069] When the DRAM chip 1 to be authenticated is connected to the authentication device 5, the authentication device 5 sends a challenge signal CHA to the DRAM chip 1 as an input value for authentication.

[0070] The input / output circuit 21 sends the challenge signal CHA received from the authentication device 5 to the arithmetic circuit 26. The address DEF2 of the faulty cell stored in the non-volatile memory 25 is also sent to the arithmetic circuit 26.

[0071] Figure 13 is a block diagram showing the detailed configuration of the arithmetic circuit in Figure 12. The arithmetic circuit 26 includes, for example, an XOR (exclusive OR) arithmetic circuit 81 and a hash arithmetic circuit 82. The XOR arithmetic circuit 81 generates a first calculated value by performing an XOR operation between the addresses DEF2 of multiple faulty cells stored in the non-volatile memory 25 and the challenge signal CHA. The addresses of the multiple faulty cells read from the non-volatile memory 25 may be concatenated and input to the XOR arithmetic circuit 81, or they may be input to the XOR arithmetic circuit 81 after some operation has been performed. The challenge signal CHA may be repeated, for example, according to the length of the concatenated addresses of the faulty cells. The hash arithmetic circuit 82 generates a second calculated value by performing a hash operation on the first calculated value. The arithmetic circuit 26 outputs the second calculated value as a response signal RES.

[0072] The input / output circuit 21 transmits the response signal RES, which was returned from the calculation circuit 26, to the authentication device 5.

[0073] The authentication device 5 authenticates whether the DRAM chip 1 is genuine or not based on whether the response signal RES returned from the DRAM chip 1 when the challenge signal CHA is sent to the DRAM chip 1 matches a pre-stored response signal RES. The relationship between the challenge signal CHA and the response signal RES is a random and unpredictable function that reflects the address of the faulty cell, which is unique to each individual DRAM chip 1.

[0074] As mentioned above, by storing the addresses DEF2 of a sufficient number of defective cells in the non-volatile memory 25 to maintain authentication security, the authentication device 5 can properly authenticate the DRAM chip 1 based on the addresses DEF2 of the defective cells stored in the non-volatile memory 25.

[0075] [Effects of the Embodiment] According to the DRAM chip 1 of this embodiment, the addresses of more defective cells than the actual number of defective cells that should be replaced with redundant cells are stored in the non-volatile memory 25, and the DRAM chip 1 is authenticated based on the addresses of the defective cells stored in the non-volatile memory 25. This prevents a decrease in authentication security even if the number of defective cells decreases due to manufacturing variations.

[0076] Assume that the memory cell array 10 contains N rows, of which M rows contain faulty cells. In this case, the possible combinations of row addresses of the faulty cells are C(N,M) = N! / (M! × (NM)!). When N=4192 and M=1, C(N,M)=4192. This is too small a size for the key space used for authentication and is not practical. If N=4192 and M=0, then C(N,M)=1, which is completely unsuitable for authenticating the DRAM chip 1. On the other hand, when N=4192 and M=10, C(N,M) ≈ approximately 4.56 × 10 29 This results in an enormously large number. In this case, the size of the key space is sufficiently large that, in practice, it is unlikely that different DRAM chips 1 will have the same arrangement of row addresses of faulty cells. Furthermore, the addresses of faulty cells stored in the non-volatile memory 25 are virtually impossible to guess from outside the DRAM chip 1. According to the embodiment of the DRAM chip 1, a sufficient number of faulty cell addresses can be stored in the non-volatile memory 25 to maintain authentication security, and the DRAM chip 1 can be properly authenticated based on the faulty cell addresses stored in the non-volatile memory 25.

[0077] According to the embodiment of the DRAM chip 1, even if the DRAM chip 1 is mass-produced with some manufacturing variations, it is possible to guarantee the normal writing, reading, and storage of data to the DRAM chip 1, and to properly authenticate the DRAM chip 1 based on the address of a defective cell.

[0078] The method for authenticating the DRAM chip 1 according to this embodiment involves applying the address of a defective cell in the DRAM chip 1 to the Physical Unclonable Function (PUF), which has attracted attention in recent years.

[0079] [Other embodiments] The arithmetic circuit 26 may include a circuit that performs other calculations for authentication on address DEF2, instead of the XOR arithmetic circuit 81 and the hash arithmetic circuit 82.

[0080] The semiconductor memory device according to this embodiment may be a device other than DRAM that is authenticated based on the address of a defective cell.

[0081] [Summary of Embodiments] A semiconductor memory device and test method relating to an aspect of this disclosure may be described as follows.

[0082] The semiconductor memory device according to the first embodiment is: Multiple memory cells arranged two-dimensionally along multiple rows and multiple columns, A first non-volatile memory that stores the addresses of a plurality of first faulty cells among the plurality of memory cells, A second non-volatile memory that stores the addresses of a plurality of second defective cells, which are at least partially different from the plurality of first defective cells among the plurality of memory cells, An input / output circuit that receives addresses and commands from an external device and sends and receives data to and from the external device, A decoding circuit that decodes an address received from the external device to a physical location among the plurality of memory cells, wherein if the address received from the external device does not match the address of the first faulty cell stored in the first non-volatile memory, the decoding circuit decodes the address received from the external device to the physical location of a first memory cell among the plurality of memory cells, and if the address received from the external device matches the address of the first faulty cell stored in the first non-volatile memory, the decoding circuit decodes the address received from the external device to the physical location of a second memory cell different from the first memory cell among the plurality of memory cells, The system includes an arithmetic circuit that performs a predetermined calculation on the address of the second defective cell stored in the second non-volatile memory and outputs the generated calculation value to the external device.

[0083] According to the semiconductor memory device of the second embodiment, in the semiconductor memory device of the first embodiment, The input / output circuit receives an input value for authentication from the external device. The aforementioned arithmetic circuit is A first calculated value is generated by performing an XOR operation between the address of the second defective cell stored in the second non-volatile memory and the input value for authentication. A hash operation is performed on the first calculated value to generate a second calculated value. The second calculated value is output to the external device.

[0084] According to the semiconductor memory device of the third embodiment, in the semiconductor memory device of the first or second embodiment, The second non-volatile memory has a larger capacity than the first non-volatile memory.

[0085] According to the semiconductor memory device of the fourth embodiment, in a semiconductor memory device of one of the first to third embodiments, The second non-volatile memory stores only the row addresses for the plurality of second defective cells, or only the column addresses for the plurality of second defective cells, or stores either the row address or the column address for each of the plurality of second defective cells.

[0086] According to the semiconductor memory device of the fifth embodiment, in a semiconductor memory device of one of the first to fourth embodiments, The first and second non-volatile memories include dielectric films that can break down dielectrically or fuses that can be cut.

[0087] According to the semiconductor memory device of the sixth embodiment, in a semiconductor memory device of one of the first to sixth embodiments, The aforementioned semiconductor memory device is DRAM (Dynamic Random Access Memory).

[0088] A test method for a semiconductor memory device according to the seventh aspect is: A test method for a semiconductor memory device according to one of the first to sixth embodiments, Under the first condition, a plurality of first defective cells among the plurality of memory cells are detected, The addresses of the plurality of first defective cells are stored in the first non-volatile memory, Under the second condition, a plurality of second defective cells among the plurality of memory cells are detected, This includes storing the addresses of the plurality of second defective cells in the second non-volatile memory, The second condition is set such that a larger number of memory cells are detected as faulty cells than in the case of the first condition.

[0089] The test method for a semiconductor memory device according to the eighth aspect is, in the test method according to the seventh aspect, The first and second conditions described above have different charge retention times, power supply voltages, temperatures, or operating speeds.

[0090] The test method for a semiconductor memory device according to the ninth aspect is a test method according to the seventh or eighth aspect, The second defective cell includes a single defective cell that is not continuous in the row and column directions. The test method includes storing the row address or column address of the single defective cell in the second non-volatile memory.

[0091] The test method for a semiconductor memory device according to the tenth embodiment is a test method according to one of the seventh to ninth embodiments, The aforementioned plurality of memory cells constitute a plurality of subarrays, The aforementioned test method is Under the second condition described above, the plurality of second defective cells are detected in the first subarray among the plurality of subarrays, To distribute the addresses across at least two of the aforementioned subarrays, one of at least two distinct offset values ​​is added to each address of the plurality of second defective cells, This includes storing the addresses of the plurality of second defective cells, to which the offset value has been added, in the second non-volatile memory. [Industrial applicability]

[0092] According to aspects of this disclosure, a semiconductor memory device is provided that is authenticated based on the address of a faulty cell unique to each individual device. [Explanation of Symbols]

[0093] 1 DRAM chip 2 Memory Controller 3 processors 4. Memory Tester 5 Authentication device 10 memory cell arrays 11 subarrays 12 memory cells 12a, 12aa: Defective cell (single cell defect) 12b, 12bb defective cells (X-line defective) 12c, 12cc defective cell (Y-line defect) 13-bit line 14. Sense Amplifier Circuit 15 Word lines 16 Column Selection Lines 17-line decoding circuit 18-column decoding circuit 21 Input / Output Circuits 22 Memory cell array control circuit 23 Data Processing Circuit 24 Non-volatile memory 25 Non-volatile memory 26 Arithmetic circuit 31 Word Line Driver 32 Sense Amplifier 41 Switching elements 42 Capacitors 51-56 Switching elements 58-1, 58-2 data lines 57 Column Selection Line Driver 61 Columns containing defective cells 61a Redundant column 62 rows containing defective cells 62a redundant line 63 Columns containing defective cells 63a Redundant column 71 Rows containing defective cells 72 rows containing defective cells 73 Columns containing defective cells 81 XOR Calculation Circuit 82 Hash Calculation Circuit

Claims

1. Multiple memory cells arranged two-dimensionally along multiple rows and multiple columns, A first non-volatile memory that stores the addresses of a plurality of first defective cells among the plurality of memory cells, A second non-volatile memory that stores the addresses of a plurality of second defective cells, which are at least partially different from the plurality of first defective cells among the plurality of memory cells, An input / output circuit that receives addresses and commands from an external device and sends and receives data to and from the external device, A decoding circuit that decodes an address received from the external device to a physical location among the plurality of memory cells, wherein if the address received from the external device does not match the address of the first faulty cell stored in the first non-volatile memory, the decoding circuit decodes the address received from the external device to the physical location of the first memory cell among the plurality of memory cells, and if the address received from the external device matches the address of the first faulty cell stored in the first non-volatile memory, the decoding circuit decodes the address received from the external device to the physical location of a second memory cell different from the first memory cell among the plurality of memory cells, The system includes an arithmetic circuit that performs a predetermined calculation on the address of the second defective cell stored in the second non-volatile memory and outputs the generated calculation value to the external device. Semiconductor memory device.

2. The input / output circuit receives an input value for authentication from the external device. The aforementioned arithmetic circuit is A first calculated value is generated by performing an XOR operation between the address of the second defective cell stored in the second non-volatile memory and the input value for authentication. A hash operation is performed on the first calculated value to generate a second calculated value. The second calculated value is output to the external device. The semiconductor memory device according to claim 1.

3. The second non-volatile memory has a larger capacity than the first non-volatile memory. The semiconductor memory device according to claim 1.

4. The second non-volatile memory stores only the row addresses for the plurality of second defective cells, or only the column addresses for the plurality of second defective cells, or stores either the row address or the column address for each of the plurality of second defective cells. The semiconductor memory device according to claim 1.

5. The first and second non-volatile memories each include a dielectric film that can break down dielectrically or a fuse that can be cut. The semiconductor memory device according to claim 1.

6. The aforementioned semiconductor memory device is DRAM (Dynamic Random Access Memory). A semiconductor memory device according to one of claims 1 to 5.

7. A method for testing a semiconductor memory device according to claim 1, Under the first condition, a plurality of first defective cells among the plurality of memory cells are detected, The addresses of the plurality of first defective cells are stored in the first non-volatile memory, Under the second condition, a plurality of second defective cells among the plurality of memory cells are detected, This includes storing the addresses of the plurality of second defective cells in the second non-volatile memory, The second condition is set such that a larger number of memory cells are detected as faulty cells than in the case of the first condition. Testing method.

8. The first and second conditions have different charge holding times, power supply voltages, temperatures, or operating speeds. The test method according to claim 7.

9. The second defective cell includes a single defective cell that is not continuous in the row and column directions. The test method includes storing the row address or column address of the single cell defect in the second non-volatile memory. The test method according to claim 7.

10. The aforementioned plurality of memory cells constitute a plurality of subarrays, The aforementioned test method is Under the second condition described above, the plurality of second defective cells are detected in the first subarray among the plurality of subarrays, To distribute the addresses across at least two of the aforementioned subarrays, one of at least two distinct offset values ​​is added to each address of the plurality of second defective cells, This includes storing the addresses of the plurality of second defective cells to which the offset value has been added in the second non-volatile memory, The test method according to claim 7.

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