Polysilicon rod and method for manufacturing a polysilicon rod

Abstract

To improve radial resistivity gradient (RRG) of single crystal silicon that is produced with a large-bore floating zone (FZ) method to enable manufacturing of large-bore high-resistance single crystal silicon with the FZ method.SOLUTION: A polysilicon rod has a diameter of 120 mm or more, a lowest resistivity of 3300 Ωcm or more, and RRG of 100% or less.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a polysilicon rod and a method for manufacturing the polysilicon rod.

Background Art

[0002] The production of polysilicon rods as raw materials for single-crystalline silicon is mainly carried out by the Siemens process. The CVD method is used, in which a silicon rod (silicon core wire) is arranged on an electrode, and the raw material chlorosilane gas is deposited in the air by Joule heat generated when an electric current is passed.

[0003] The silicon core wire used in the CVD method is washed with wet etching (generally nitric acid / hydrofluoric acid) and ultrapure water for the purpose of removing the processing-affected layer (fine scratches and surface cracks) that can occur during shape processing. At the same time as removing the processing-affected layer, surface impurities and natural oxide films are removed.

[0004] After the surface of the silicon core wire is cleaned by wet etching, washing, etc., it is stored in a storage bag, storage case, etc. until it is placed in the reactor. At this time, the surface is contaminated by the contact part of the storage bag or case and airborne particles, and at the same time, a natural oxide film is formed. Therefore, contact with other substances is managed to be short as much as possible. However, it is inevitable that recontamination and the generation of natural oxide films occur from contact, the air, etc. until it is installed in the CVD apparatus.

[0005] The currently mainstream single-crystal manufacturing processes include the FZ (float zone melting) method and the CZ (Chokralski) method. Among these, the FZ method is a method in which the tip of a polysilicon rod is processed into a cone shape and melted by induction coil heating from the tip, and dislocation-free growth is achieved on the seed crystal side, and high-purity and high-resistance single-crystalline silicon can be obtained.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

[0007] Figure 1 shows a schematic diagram of the FZ method. The polysilicon rod 1a is inductively heated by the coil 4, causing melting on the surface of the polysilicon rod 1a, and forming a molten portion 3 as it flows down. The unmolten portion 1b often reaches the single-crystal silicon 2, which can cause problems, and at the same time, the resistivity near the center 1b of the polysilicon rod 1a affects the in-plane resistivity distribution of the single-crystal silicon (Patent Document 1).

[0008] As the diameter of the single crystal increases, due to the characteristics of the coil 4, the unmelted portion 1b may remain in the polysilicon rod 1a with its conical tip pointing toward the single crystal silicon side (lower side in Figure 1). The unmelted portion 1b has a convex shape facing toward the single crystal silicon side, and due to the influence of this unmelted portion 1b, the molten portion 3 does not spread around the single crystal silicon, but solidifies in the central part of the single crystal silicon, resulting in uneven distribution.

[0009] Therefore, as the diameter of the single crystal increases, impurities present near the surface of the silicon core tend to concentrate in the central part of the single crystal silicon, increasing the in-plane resistivity distribution (RRG) of the FZ single crystal silicon.

[0010] As mentioned above, the molten material near the center of the melting zone tends to remain near the center of the single-crystal silicon because the tip of the unmelted portion of the polysilicon rod protrudes. Since the silicon core of a polysilicon rod is usually located in the center, the resistivity near the silicon core greatly affects the in-plane resistivity distribution of the single-crystal silicon. To avoid this, improvements have been made to the FZ apparatus, such as offsetting the rotation axes of the raw material and the single crystal to make the stirring of the molten material asymmetric, as described in Patent Document 2.

[0011] However, as the diameter of the single crystal increased, there was a limit to the thickness of the molten layer on top of it (the thickness of the part indicated by reference numeral 3 in Figure 1), and sufficient stirring effect could not be obtained. [Means for solving the problem]

[0012] Thus, it was found that when growing large-diameter (120 mm or more) single crystals using the FZ method, a commonly used method for producing high-quality single-crystal silicon, the process is strongly affected by the low-resistivity regions of polycrystalline silicon during melting. The inventors diligently investigated why these low-resistivity regions appeared and discovered that the cause lies near the surface of the silicon core wire, which is the central part of the polycrystalline silicon.

[0013] This invention improves the in-plane resistivity distribution (RRG) of single-crystal silicon fabricated by the large-diameter FZ method of 120 mm or more by using polysilicon with an improved in-plane resistivity distribution as a raw material, thereby enabling the production of large-diameter, high-resistivity single-crystal silicon by the FZ method.

[0014] This application relates to a method for producing polycrystalline silicon with an improved in-plane resistivity distribution as a raw material. This method involves surface-treating a silicon core wire placed in the reaction furnace at a temperature not exceeding 1000°C before the CVD reaction, thereby suppressing the elution of impurities from the material in the CVD apparatus, and aims to improve the in-plane resistivity distribution of the large-diameter FZ method. The invention provides a high-purity polysilicon rod and a method for producing the same.

[0015] Patent Document 3 and Patent Document 4 describe that the silicon core wire is heated to a temperature exceeding 1000°C, and the seed rod is etched with silicon tetrachloride or hydrogen chloride to remove impurities. However, at a temperature exceeding 1000°C, the metal surface of the reactor internal structure and the like react with silicon tetrachloride, hydrogen chloride, and the by-produced chloride, and impurities such as dopants are likely to elute together with metal chlorides having a high vapor pressure, and these can cause contamination of the polysilicon rod. Therefore, it is preferable to suppress the elution of impurities from the materials in the CVD apparatus by keeping the silicon core wire below 1000°C.

[0016] Particularly, since the supply amount of the raw material is small from after the silicon core wire is energized to the initial stage of the reaction, the elution amount of impurities such as metal components and dopants becomes high as a ratio to the raw material. For this reason, finally, the resistivity around the silicon core wire near the center of the polysilicon rod decreases, affecting the in-plane resistivity distribution of the polysilicon rod.

[0017] The polysilicon rod for improving the in-plane resistance of the single crystal silicon rod in the present invention is provided by the following aspects.

[0018] (Concept 1) In a polysilicon rod having a diameter of 120 mm or more, the minimum resistivity may be 3300 Ωcm or more and the RRG may be 100% or less.

[0019] (Concept 2) In the polysilicon rod described in Concept 1, the minimum resistivity is within 30 mm from the silicon core wire toward the outer periphery, and the maximum resistivity may be in a portion exceeding 30 mm from the silicon core wire toward the outer periphery.

[0020] (Concept 3) In the polysilicon rod described in Concept 1 or 2, the RRG may be 50% or less.

[0021] (Concept 4) In a polysilicon rod with a diameter of 140 mm or more, the minimum resistivity may be 3300 Ωcm or more and the RRG may be 150% or less.

[0022] (Concept 5) In the polysilicon rod described in Concept 4, the minimum resistivity exists within 30 mm from the silicon core wire toward the outer periphery, and the maximum resistivity may exist in a portion exceeding 30 mm from the silicon core wire toward the outer periphery.

[0023] (Concept 6) In the polysilicon rod described in Concept 4 or 5, the RRG may be 100% or less.

[0024] (Concept 7) A method for manufacturing the polysilicon rod according to any one of Concepts 1 to 6 includes a step of setting a silicon core wire in a reactor, a step of etching the silicon core wire with hydrogen halide in a situation where the temperature of the silicon core wire exceeds 300 °C and is 1000 °C or less, and may include.

[0025] (Concept 8) In the method described in Concept 7, the etching with hydrogen halide may be performed at a temperature of 800 °C or less. (Concept 9) The method described in Concept 7 or 8 may further include a step of removing an oxide film and impurities on the surface of the silicon core wire by wet etching before setting the silicon core wire in the reactor.

[0026] (Concept 10) A method for manufacturing the polysilicon rod according to any one of Concepts 1 to 6 includes a step of removing an oxide film and impurities on the surface of the silicon core wire by wet etching, a step of setting the silicon core wire in a reactor, The process involves etching the silicon core wire with hydrogen halide while the temperature of the silicon core wire is between 300°C and 800°C. A process of precipitating polysilicon by CVD reaction, It may be provided. [Effects of the Invention]

[0027] The present invention provides a high-purity polysilicon rod for use as a raw material for FZ (Fiber-Zon) crystallization, which has an improved in-plane resistivity distribution during single crystallization by the FZ method, and a method for manufacturing the high-purity polysilicon rod. [Brief explanation of the drawing]

[0028] [Figure 1] A diagram illustrating the process of producing single-crystal silicon from polysilicon rods. [Figure 2] A diagram illustrating the process of preparing a sample. [Figure 3] This graph shows the ρMax / ρMi values ​​from the center to the outer surface. The solid line shows the results for polysilicon rods that have undergone the cleaning process according to the embodiment, while the dotted line shows the results for polysilicon rods that have not undergone the cleaning process according to the embodiment. [Figure 4] This figure shows the results of measuring the facet resistivity of single crystals prepared by the FZ method, with white circles indicating the results for the example and black circles indicating the results for the comparative example. [Modes for carrying out the invention]

[0029] This embodiment provides a polysilicon rod and a method for manufacturing the polysilicon rod, which have improved radial in-plane resistivity distribution of single crystal ingots manufactured by the single crystal FZ method. In particular, it provides a high-purity polysilicon rod and a method for manufacturing the same, which have improved internal resistivity distribution of single crystal wafers with a diameter of 6 inches or more.

[0030] One aspect of the present invention One embodiment of a procedure to prevent contamination of the silicon core wire surface and during the initial growth stage in order to obtain a polysilicon rod with improved RRG consists of (1) wet etching before attachment to the reactor, (2) attachment of the silicon core wire to the reactor, (3) dry etching inside the reactor, and (4) temperature control from before the reaction until the polysilicon rod reaches φ30 mm, controlling the temperature of the silicon core wire to less than 1000 degrees. It is preferable to perform at least (3) of these procedures (1) to (4), more preferably to perform both (1) and (3), and particularly preferably to perform all of (1) to (4). The temperature of the silicon core wire in (4) can be observed, for example, by a measuring device using infrared radiation.

[0031] One aspect of the present invention will be described in detail.

[0032] (1) Wet etching before installation in the reactor Wet etching before reactor installation is performed to remove the silicon oxide film and surface contaminants. By using a mixed acid of HF (hydrofluoric acid) and HNO3 (nitric acid) to remove the processed and altered surface layer and make it hydrophobic, the growth rate of the native oxide film after wet etching can be slowed.

[0033] After wet etching, the cleaned silicon core wire is exposed to the atmosphere, where an oxide film gradually forms and it comes into contact with airborne particles. To minimize oxide film formation and contamination by airborne particles, it is preferable to install the core wire in the reactor and start the reaction within 12 hours, more preferably within 8 hours, and particularly preferably within 4 hours. While it is possible to use storage containers to prevent oxidation and contamination, the act of setting the core wire in a storage container may actually cause contamination, so it is best to install it in the reactor as quickly as possible.

[0034] However, if such a method is difficult to implement, contamination of the silicone core wire surface can be prevented by storing it in a clean atmosphere of Class 100 or higher, in a sealed package with a clean surface treatment applied to the surface in contact with the silicone core wire. In this case, a vinyl bag may be used, or a vinyl bag that has been washed with an aqueous acid solution (for example, an aqueous solution in which HF and HNO3 are in a ratio of 1:3 to 1:7) and rinsed, and then air-dried in a clean room. The bag may be made of LDPE (low-density polyethylene), LLDPE (linear low-density polyethylene), PVDF (polyvinylidene fluoride), etc.

[0035] Another way to avoid contamination is to perform ozonated water treatment as soon as possible after wet etching to create an artificially normal oxide film rather than a naturally occurring one. Using such methods can further prevent contamination. It is desirable to perform ozonated water treatment immediately after wet etching.

[0036] Subsequently, by placing the silicone core wire in a clean environment, sealing it in packaging with a clean surface treatment applied to the surface that comes into contact with the silicone core wire, and storing it in this way, contamination of the silicone core wire surface can be prevented more effectively during storage.

[0037] The oxide film applied to the surface of the silicon core wire by ozonated water treatment is difficult to remove by etching with hydrogen halides, and therefore needs to be removed before installation in the reactor. For this reason, etching the oxide film with HF (hydrofluoric acid), washing with ultrapure water, and then promptly installing the wire in the reactor can better prevent contaminants from adhering to the surface of the silicon core wire.

[0038] Alternatively, by directly setting the silicon core wire with an oxide film applied by ozonated water treatment into the reactor, lowering the temperature to below 1000°C, reducing and removing the oxide film in a hydrogen atmosphere, then lowering the temperature of the silicon core wire, and then raising it again to the temperature for etching with hydrogen halide, contaminants on the surface of the silicon core wire can be removed to the greatest extent possible. Alternatively, after the HF (hydrofluoric acid) etching, further reduction treatment of the oxide film using the hydrogen atmosphere can be performed to improve quality and shorten the time required for oxide film removal.

[0039] (2) Attaching the silicon core wire to the reactor When attaching the silicon core wire to the reactor, contact should be limited to only the ends, and the central part should not be touched, thereby preventing contamination by impurities from contact with the jig. Furthermore, the ends that have come into contact with other substances should be cut off during processing of the polycrystalline silicon after its manufacture, so as not to affect the quality of the FZ (Fiber-Zipping Zone). If the diffusion of impurities from both ends becomes a problem, it is preferable to attach the wire using a jig made of "clean silicon" that is unaffected by contamination at the contact points. It is even preferable if the contact points can be replaced with clean silicon each time, as this would prevent impurities from entering the wire each time it is attached. The silicon used for the contact points of the jig should be of a similar quality to the silicon core wire being attached.

[0040] (3) Dry etching in the reactor Even if the silicon core wire is carefully installed inside the reactor, contamination is unavoidable because the work is performed in the atmosphere. Therefore, it is preferable to ultimately treat the silicon core wire installed inside the reactor with etching using a hydrogen halide to remove impurities. Hydrogen halides include hydrogen chloride, hydrogen fluoride, and hydrogen bromide, but hydrogen chloride is preferred due to its ease of handling, low cost, and minimal erosion inside the furnace.

[0041] The etching temperature should be above the temperature at which the reaction between the hydrogen chloride used for etching and silicon occurs, preferably above 300°C, and more preferably above 400°C. However, etching at temperatures above 500°C is preferable because the etching rate decreases, requiring a longer etching time to obtain a sufficient amount of etching, making it unsuitable for operation. Furthermore, the upper limit temperature should not exceed 1000°C, preferably below 900°C, and more preferably below 700°C. As mentioned above, temperatures above 1000°C are prone to leaching from the internal walls and structures of the reactor, which can cause contamination. Therefore, in this embodiment, it is important to etch the silicon core wire at a temperature below 1000°C.

[0042] To obtain the etching effect of hydrogen halides such as hydrogen chloride at such temperatures, it is necessary to remove the oxide film on the silicon. Therefore, wet etching aimed at removing the oxide film is often performed beforehand, and procedure (1) is an example of this. By etching the silicon core wire at a temperature of less than 1000°C, as in procedure (3), the impact on the materials in the reactor can be minimized, and impurities on the surface of the silicon core wire can be removed more effectively.

[0043] (4) Temperature control during initial growth Furthermore, for the same reasons, a temperature of 1000°C or lower is desirable during the initial growth of the polysilicon rod to a diameter of 30 mm, both before and after the reaction. In particular, before the start of the reaction and immediately after the supply of raw materials, it is necessary to keep the gas supply amount low to prevent the collapse of the silicon core wire. As a result, the proportion of impurities leached from the reactor structure into the supply gas increases, and the impurity concentration of the supply gas increases. Consequently, more impurities are introduced during the initial growth of the polysilicon rod, which is a factor that lowers the resistivity.

[0044] Typically, the initial gas supply rate (immediately after raw material supply) should be set to an amount that does not cause cracks in the silicon core wire, taking into account the size of the reactor, the length of the silicon core wire, the position of the core wire and the gas supply nozzle, and the kinetic energy of the gas injected from the nozzle. This prevents the polysilicon rod from collapsing due to cracks during the reaction. In the stable growth region of the CVD reaction (the growth period from the middle to the later stages of the reaction process), the gas supply rate should be approximately 0.5 to 5 kmol / hr / m² relative to the surface area of ​​the silicon core wire. 2 A supply of gas is provided. In contrast, the initial gas supply is approximately 1 / 50 to 1 / 300 of the supply in the stable growth region. The impurity concentration of impurities leached from the reactor structure in the initial stage is 50 to 300 times higher than in the stable growth region. Therefore, the impurity concentration is overwhelmingly higher in the initial stage than in the stable growth region, and the polycrystalline silicon during the reaction is considerably more susceptible to the effects of impurity leaching from the reactor.

[0045] Even during the CVD reaction, the inner walls of the reactor and the metal structures inside the reactor receive radiation from the growing polysilicon rods, causing the metal surface temperature to rise. The metal reacts with the chlorosilanes used as raw materials and reaction by-products, releasing impurities such as dopants along with metal chlorides that have high vapor pressure. Therefore, impurities are introduced during the initial stages of the CVD reaction, lowering the resistance of the polycrystalline silicon. Thus, in order to maintain a constant resistivity distribution on the inner surface of the polycrystalline silicon cross-section, it is preferable to grow the rods at a temperature of 1000°C or lower during the initial stages of the reaction.

[0046] By using this method, and paying attention to the initial growth of the center of the polysilicon rod during manufacturing, it became possible to manufacture the polysilicon rod described in the claim, and the single-crystal silicon rod produced by the FZ method using the polysilicon rod was able to maintain high resistance and good RRG. [Examples]

[0047] Although silicone core wires are stored in bags with few impurities, prolonged storage will result in a large amount of impurities adhering to the surface of the silicone core wires. Since the surface of the silicon core wire used has a native oxide film and impurities, these are removed by wet etching and washing with pure water. A mixed acid of HF (hydrofluoric acid) and HNO3 (nitric acid) (HF:HNO3=1:5) was prepared using 50% hydrofluoric acid (HF) and 70% nitric acid (HNO3). The silicon core wire was etched with this mixture at 25°C for 2 minutes, and then washed with ultrapure water for 30 minutes.

[0048] Afterward, the silicon core was dried in a clean environment (particle count below 100). However, in order to minimize the time until the CVD reaction (a Siemens reaction for the production of polycrystalline silicon) started, immediately after drying, the silicon core was placed in the reaction furnace with the upper and lower ends of the silicon core held in place by a jig to prevent any contact with the linear part of the silicon core. This suppresses natural oxidation and contamination of the silicon core. Furthermore, the silicon core itself used was of high quality, cut from an FZ single crystal, similar to the polysilicon rods being manufactured.

[0049] The silicon core wire should have a resistivity of 3300 Ωcm or higher, more preferably 4000 Ωcm or higher, and particularly preferably 4500 Ωcm or higher. The higher the resistivity of the silicon core wire, the higher the resistance of the polysilicon rod grown by the CVD reaction. In this example, a silicon core wire with a resistivity of 4500 Ωcm was used.

[0050] After setting the silicon core wire (10 mm square, resistivity 4500 Ωcm) in the reactor, the atmosphere was replaced with an inert gas and then with hydrogen gas. At this time, the oxygen concentration was kept below 30 ppm and the dew point below -50°C. When electricity was passed through the silicon core wire and the current was increased, the temperature of the silicon core wire began to rise. When the silicon core wire temperature reached 300°C, hydrogen chloride (hydrogen-based) was introduced and the temperature was raised to a predetermined level. This predetermined temperature is listed as the silicon core wire temperature in Table 1. After reaching the predetermined temperature of 900°C, etching was performed for 5 minutes. To suppress the generation of the aforementioned metal chlorides, anhydrous hydrogen chloride with a purity of 99.999% or higher was used. The etching amount on the surface of the silicon core wire was 15 μm. By going through this process, it is possible to obtain a polysilicon rod with a low in-plane resistivity distribution.

[0051] The etching temperature is set by energizing all silicon core wires and setting them to the desired temperature while the gas inside the reactor is replaced with hydrogen immediately before the CVD reaction. Although rod temperature monitoring during CVD is usually done with an infrared thermometer, the applied voltage and current were adjusted using this infrared thermometer to achieve the desired temperature.

[0052] After etching with 30 mol% hydrogen-based hydrogen chloride (99.999%), a CVD reaction was carried out at a temperature of 900°C on the silicon core wire until it reached a diameter of φ30 mm. A polysilicon rod was then fabricated using a standard manufacturing method, and the position of lowest resistivity was observed. It was confirmed that the lowest resistivity was located within 30 mm of the silicon core wire. This lowest resistivity was defined as the silicon core wire center resistivity. The silicon core wire center resistivity was 3551 Ωcm. When polycrystalline silicon was grown using a standard manufacturing method, the RRG was 66% at a diameter of 120 mm, and 92% at a diameter of 140 mm. When this polysilicon rod was processed into an FZ single crystal using a standard method, the RRG of the FZ single crystal was a good 22% (see Figure 3). Note that the "outer surface" shown on the far right of Figure 3 represents 140 mm. [Examples]

[0053] A silicon core wire similar to that in Example 1 was set in the reaction vessel. After reaching the predetermined temperature of 700°C, etching was performed for 5 minutes. The etching amount was 0.1 μm. Similar to Experiment 1, etching was performed with 30 mol% hydrogen-based hydrogen chloride (99.999%), then the temperature of the silicon core wire was set to 700°C, and the CVD reaction was carried out using the usual method until it reached a diameter of φ30 mm. After that, a polysilicon rod was fabricated using the usual manufacturing method, and the position with the lowest resistivity was observed. As a result, the center resistivity of the silicon core wire was 4329 Ωcm. When polycrystalline silicon was grown using the usual manufacturing method, the RRG was 36% when the diameter reached 120 mm, and the RRG was 77% when the diameter reached 140 mm. Therefore, it was confirmed that Example 2, in which etching was performed at 700°C, was able to keep the RRG value lower than Example 1, in which etching was performed at 900°C, and thus yielded more beneficial results. Comparative Example 1

[0054] A silicon core wire similar to that in Example 1 was set in the reaction vessel. After reaching the predetermined temperature of 1100°C, etching was performed for 3 minutes. The etching amount was 84 μm. Similar to Example 1, etching was performed with hydrogen chloride (99.999%) 30 mol% hydrogen base, and then the silicon core wire was heated to 1100°C and the CVD reaction was carried out until it reached a diameter of φ30 mm. After that, a polysilicon rod was fabricated using a standard manufacturing method, and the position at which the lowest resistivity was obtained was observed to be 2189 Ωcm. When polycrystalline silicon was grown using a standard manufacturing method, the RRG was 97% when the diameter reached 120 mm, and the RRG was 142% when the diameter reached 140 mm. Comparative Example 2

[0055] Unlike Example 1, wet etching was not performed, but a silicon core wire similar to that in Example 1 was set in the reaction furnace. A polysilicon rod was then fabricated using a standard manufacturing method, and the position with the lowest resistivity was observed. The results showed that without wet etching, many impurities present on the surface diffused into the interior of the silicon core wire. Therefore, ρmin was located inside the silicon core wire, and its lowest resistivity was 1697 Ωcm. When polycrystalline silicon was grown using a standard manufacturing method, the RRG was 206% at a diameter of 120 mm, and 258% at a diameter of 140 mm. When this polysilicon rod was processed into an FZ single crystal using a standard method, the RRG of the FZ single crystal was a poor 155% (see Figure 3).

[0056] The results from the examples and comparative examples are shown in Table 1 below. [Table 1]

[0057] Method for measuring the in-plane resistivity distribution of polysilicon rods As shown in Figure 2, the top and bottom edges of a polysilicon rod removed from a CVD reactor were cut, and a core drill was used to extract core material from the outer circumference towards the silicon core, near the cut surface that was outside the effective length for the final product, thereby creating a sample including the outer circumference and the silicon core (JIS H 0615 2021 4.2 Preparation of polycrystalline silicon samples). Using the sample thus prepared, single crystallization was performed from the outer circumference using the FZ method. The resistivity of the resulting single crystal was measured from the outer circumference to the part that touches the silicon core using the four-probe method. This allowed confirmation of the in-plane resistivity distribution of the polysilicon rod. At this time, due to the segregation of impurities by the FZ method, it is not possible to obtain the true value on the polysilicon rod, but by performing FZ from the outer circumference to beyond the silicon core, it is possible to capture the change in resistivity near the silicon core, which is of particular interest. In addition, the RRG index, which represents the internal resistivity distribution, is a relative evaluation and can be used to evaluate the fluctuation of resistivity.

[0058] The Radial Resistivity Gradient (RRG) is used as an index to represent the in-plane resistivity distribution of a silicon single crystal substrate. If the maximum resistivity in the radial direction is ρMax and the minimum value is ρMin, it is expressed by the following equation. RRG=(ρMax -ρMin) / ρMin×100(%) (Formula 1) While it is normally used as an indicator to represent the in-plane resistivity distribution of a silicon single-crystal substrate, in this invention it is adopted as an indicator to represent the radial resistivity distribution of a polysilicon rod.

[0059] In Figure 3, the solid line shows the result of cleaning according to this embodiment. The drop in resistivity near the center, including the silicon core wire, is improved, and the polysilicon rod shows a uniform in-plane resistivity distribution with respect to the rod growth direction. When a single crystal was fabricated using this as raw material by the FZ method and the facet resistivity was measured, the in-plane resistivity became uniform, showing improvement (see Figure 4). For comparison, the FZ method used to fabricate the single crystal was performed without any operation to improve the in-plane resistivity distribution, and was carried out undoped.

[0060] As a result of increasing the resistance near the outer circumference of the silicon core wire, the resistance near the outer circumference of the silicon core wire improved to 3551 Ωcm, resulting in a diameter of 140 mm for the FZ single crystal and an improvement in RRG to 22% (Example 1). Such low-RRG, high-resistance FZ single crystals can be used as substrates for devices using MEMS technology and are also suitable as support substrates for terahertz elements in terahertz devices. Furthermore, because they are homogeneous and high-quality raw materials, even when increased in diameter, it is possible to produce ingots with uniformly dispersed phosphorus using the NTD method, making them suitable for use in high-voltage power semiconductors.

[0061] Furthermore, if the resistivity distribution can be improved in this way and the resistivity can be increased, then by using the manufactured high-resistivity, high-quality FZ single-crystal silicon as a silicon core wire and manufacturing polysilicon rods using the method of this invention, even when manufacturing polysilicon rods with higher resistance, the resistivity at the center of the silicon core wire remains high, thus suppressing RRG (Resistivity Regulatory Growth). This makes it possible to manufacture even higher quality FZ single crystals without reducing production efficiency. [Explanation of Symbols]

[0062] 1a Polysilicon rod 1b Unmelted portion 2 Single-crystal silicon 3. Melting part 4 coils

Claims

1. A method for manufacturing a polysilicon rod used in the FZ method, The process of setting the silicon core wire inside the reactor, The process involves etching the silicon core wire with hydrogen halide while the temperature of the silicon core wire is between 300°C and 1000°C. The process of precipitating polysilicon, Equipped with, A method for manufacturing a polysilicon rod having a diameter of 120 mm or more, wherein the minimum resistivity is 3300 Ωcm or more and the RRG is 100% or less.

2. A method for manufacturing a polysilicon rod used in the FZ method, The process of setting the silicon core wire inside the reactor, The process involves etching the silicon core wire with hydrogen halide while the temperature of the silicon core wire is between 300°C and 1000°C. The process of precipitating polysilicon, Equipped with, A method for manufacturing a polysilicon rod having a diameter of 140 mm or more, wherein the minimum resistivity is 3300 Ωcm or more and the RRG is 150% or less.

3. The method according to claim 1 or 2, wherein the etching with hydrogen halide is performed at a temperature of 800°C or lower.

4. The method according to claim 1 or 2, further comprising the step of removing the oxide film and impurities from the surface of the silicon core wire by wet etching before setting the silicon core wire in the reactor.

5. A method for manufacturing a polysilicon rod used in the FZ method, A process of removing oxide film and impurities from the surface of the silicon core wire by wet etching, The process of setting the aforementioned silicon core wire inside the reactor, The process involves etching the silicon core wire with hydrogen halide while the temperature of the silicon core wire is between 300°C and 800°C. A process of precipitating polysilicon by CVD reaction, Equipped with, A method for manufacturing a polysilicon rod having a diameter of 120 mm or more, wherein the minimum resistivity is 3300 Ωcm or more and the RRG is 100% or less.

6. A method for manufacturing a polysilicon rod used in the FZ method, A process of removing oxide film and impurities from the surface of the silicon core wire by wet etching, The process of setting the aforementioned silicon core wire inside the reactor, The process involves etching the silicon core wire with hydrogen halide while the temperature of the silicon core wire is between 300°C and 800°C. A process of precipitating polysilicon by CVD reaction, Equipped with, A method for manufacturing a polysilicon rod having a diameter of 140 mm or more, wherein the minimum resistivity is 3300 Ωcm or more and the RRG is 150% or less.

7. The minimum resistivity is within 30 mm from the outer circumference of the silicone core wire, The method according to claim 1, 2, 5, or 6, for manufacturing a polysilicon rod having the highest resistivity in the portion exceeding 30 mm from the silicon core wire toward the outer circumference.

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