Photodetector

Abstract

To provide an imaging element with a three-layer structure that does not interrupt the miniaturization of an area per pixel with the same chip size as before.SOLUTION: An imaging element in an embodiment of the present disclosure includes a first substrate, a second substrate, and a third substrate stacked in this order. The first substrate having a sensor pixel performing photoelectric conversion and the second substrate having a readout circuit are electrically connected to each other with a first penetration wire provided in an interlayer insulating film. The second substrate and the third substrate having a logic circuit are electrically connected to each other with a second penetration wire joining pad electrodes together or penetrating a semiconductor substrate.SELECTED DRAWING: Figure 1

Description

Technical Field

[0005] , Photodetector ,

[0004] ,

[0001] The present disclosure relates to Photodetector .

Background Art

[0002] Conventionally, the miniaturization of the area per pixel of an image sensor with a two-dimensional structure has been achieved by introducing a fine process and improving the implementation density. In recent years, in order to realize further miniaturization of the image sensor and higher pixel density, an image sensor with a three-dimensional structure has been developed. In an image sensor with a three-dimensional structure, for example, a semiconductor substrate having a plurality of sensor pixels and a semiconductor substrate having a signal processing circuit for processing signals obtained by each sensor pixel are laminated on each other.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

[0004] By the way, in an image sensor with a three-dimensional structure, when three semiconductor chips are laminated, it is not possible to bond all the semiconductor substrates with their surface sides facing each other. If the semiconductor substrates are laminated haphazardly, due to the structure for electrically connecting the semiconductor substrates, the chip size may increase or the miniaturization of the area per pixel may be inhibited. Therefore, it is desirable to provide a three-layer structure that has the same chip size as before and does not inhibit the miniaturization of the area per pixel. Photodetector

[0005] The first photodetector according to an embodiment of the present disclosure includes a first substrate including a first semiconductor substrate having sensor pixels, a second substrate including a second semiconductor substrate having a first circuit for outputting a pixel signal, a third substrate including a third semiconductor substrate having a second circuit for processing the pixel signal, and an interlayer insulating film. In the interlayer insulating film, a structure for electrically connecting the first substrate and the second substrate Through-wiring A first electrode is provided on the second substrate, and a second electrode is provided on the third substrate. The first electrode and the second electrode are joined to each other, thereby electrically connecting the second substrate and the third substrate. In a cross-sectional view, Through-wiring The width is narrower than the width of at least one of the first electrode and the second electrode. ru. [Brief explanation of the drawing]

[0007] [Figure 1] This figure shows an example of a schematic configuration of an image sensor according to one embodiment of the present disclosure. [Figure 2] This figure shows an example of the sensor pixels and readout circuit shown in Figure 1. [Figure 3] This figure shows an example of the sensor pixels and readout circuit shown in Figure 1. [Figure 4] This figure shows an example of the sensor pixels and readout circuit shown in Figure 1. [Figure 5] This figure shows an example of the sensor pixels and readout circuit shown in Figure 1. [Figure 6] This diagram illustrates an example of a connection configuration between multiple readout circuits and multiple vertical signal lines. [Figure 7] This figure shows an example of the vertical cross-sectional configuration of the image sensor shown in Figure 1. [Figure 8] This figure shows a magnified view of the connection point between the first and second substrates in the image sensor shown in Figure 7. [Figure 9] This figure shows a magnified view of the connection point between the second and third substrates in the image sensor shown in Figure 7. [Figure 10] This figure shows an example of the horizontal cross-sectional configuration of the image sensor shown in Figure 1. [Figure 11] This figure shows an example of the horizontal cross-sectional configuration of the image sensor shown in Figure 1. [Figure 12] This figure shows an example of the wiring layout in the horizontal plane of the image sensor shown in Figure 1. [Figure 13] This figure shows an example of the wiring layout in the horizontal plane of the image sensor shown in Figure 1. [Figure 14] It is a diagram showing an example of the wiring layout in the horizontal plane of the imaging device of FIG. 1. [Figure 15] It is a diagram showing an example of the wiring layout in the horizontal plane of the imaging device of FIG. 1. [Figure 16A] It is a diagram showing an example of the manufacturing process of the imaging device of FIG. 1. [Figure 16B] It is a diagram showing an example of the manufacturing process following FIG. 16A. [Figure 16C] It is a diagram showing an example of the manufacturing process following FIG. 16B. [Figure 16D] It is a diagram showing an example of the manufacturing process following FIG. 16C. [Figure 16E] It is a diagram showing an example of the manufacturing process following FIG. 16D. [Figure 16F] It is a diagram showing an example of the manufacturing process following FIG. 16E. [Figure 17] It is a diagram showing an example of the cross-sectional configuration in the vertical direction of the imaging device of FIG. 1. [Figure 18] It is a diagram showing an example of the cross-sectional configuration in the vertical direction of the imaging device of FIG. 1. [Figure 19] It is a diagram showing an example of the cross-sectional configuration in the vertical direction of the imaging device of FIG. 1. [Figure 20] It is a diagram showing an example of the cross-sectional configuration in the vertical direction of the imaging device of FIG. 1. [Figure 21] It is a diagram showing an example of the cross-sectional configuration in the vertical direction of the imaging device of FIG. 1. [Figure 22] It is a diagram showing an example of the cross-sectional configuration in the vertical direction of the imaging device of FIG. 1. [Figure 23] It is a diagram showing an example of the cross-sectional configuration in the horizontal direction of the imaging device of FIG. 1. [Figure 24] It is a diagram showing an example of the cross-sectional configuration in the horizontal direction of the imaging device of FIG. 1. [Figure 25] It is a diagram showing an example of the wiring layout in the horizontal plane of the imaging device having the cross-sectional configuration of FIG. 24. [Figure 26] It is a diagram showing an example of the wiring layout in the horizontal plane of the imaging device having the cross-sectional configuration of FIG. 24. [Figure 27]This figure shows an example of a wiring layout in the horizontal plane of an image sensor with the cross-sectional configuration shown in Figure 24. [Figure 28] This figure shows an example of the horizontal cross-sectional configuration of the image sensor shown in Figure 1. [Figure 29] This figure shows an example of the horizontal cross-sectional configuration of the image sensor shown in Figure 1. [Figure 30] This figure shows an example of the vertical cross-sectional configuration of the image sensor shown in Figure 1. [Figure 31] This figure shows an example of the horizontal cross-sectional configuration of the image sensor shown in Figure 1. [Figure 32] This figure shows an example of the vertical cross-sectional configuration of the image sensor shown in Figure 1. [Figure 33] This figure shows an example of the horizontal cross-sectional configuration of the image sensor shown in Figure 1. [Figure 34] This figure shows an example of the horizontal cross-sectional configuration of the image sensor shown in Figure 1. [Figure 35] This figure shows an example of the vertical cross-sectional configuration of the image sensor shown in Figure 1. [Figure 36] This figure shows an example of the horizontal cross-sectional configuration of the image sensor shown in Figure 1. [Figure 37] This figure shows an example of the horizontal cross-sectional configuration of the image sensor shown in Figure 1. [Figure 38] This figure shows an example of the horizontal cross-sectional configuration of the image sensor shown in Figure 1. [Figure 39] This figure shows an example of the vertical cross-sectional configuration of the image sensor shown in Figure 1. [Figure 40A] This figure shows a modified example of the manufacturing process for the image sensor shown in Figure 1. [Figure 40B] This figure shows an example of the manufacturing process following Figure 40A. [Figure 40C] This figure shows an example of the manufacturing process, following Figure 40B. [Figure 40D] This figure shows an example of the manufacturing process, following Figure 40C. [Figure 40E] This figure shows an example of the manufacturing process that follows Figure 40D. [Figure 40F] This figure shows an example of the manufacturing process, following Figure 40E. [Figure 41] This figure shows an example of the horizontal cross-sectional configuration of the image sensor shown in Figure 1. [Figure 42] This figure shows an example of the horizontal cross-sectional configuration of the image sensor shown in Figure 1. [Figure 43] This figure shows an example of the horizontal cross-sectional configuration of the image sensor shown in Figure 1. [Figure 44] This figure shows an example of the vertical cross-sectional configuration of the image sensor shown in Figure 1. [Figure 45] This figure shows an example of the vertical cross-sectional configuration of the image sensor shown in Figure 1. [Figure 46] This figure shows an example of the sensor pixels and readout circuit shown in Figure 1. [Figure 47] This figure shows an example of the sensor pixels and readout circuit shown in Figure 1. [Figure 48] This figure shows an example of the sensor pixels and readout circuit shown in Figure 1. [Figure 49] This figure shows an example of the sensor pixels and readout circuit shown in Figure 1. [Figure 50] This figure shows an example of the vertical cross-sectional configuration of the image sensor shown in Figure 1. [Figure 51] This figure shows an example of the horizontal cross-sectional configuration of the image sensor shown in Figure 1. [Figure 52] This figure shows an example of the horizontal cross-sectional configuration of the image sensor shown in Figure 1. [Figure 53] This figure shows an example of the vertical cross-sectional configuration of the image sensor shown in Figure 1. [Figure 54] This figure shows an example of the vertical cross-sectional configuration of the image sensor shown in Figure 1. [Figure 55] This figure shows an example of the vertical cross-sectional configuration of the image sensor shown in Figure 1. [Figure 56] This figure shows an example of the vertical cross-sectional configuration of the image sensor shown in Figure 1. [Figure 57] This figure shows an example of the horizontal cross-sectional configuration of the image sensor shown in Figure 1. [Figure 58] This figure shows an example of the horizontal cross-sectional configuration of the image sensor shown in Figure 1. [Figure 59]This figure shows an example of the vertical cross-sectional configuration of the image sensor shown in Figure 1. [Figure 60] This figure shows an example of the horizontal cross-sectional configuration of the image sensor shown in Figure 1. [Figure 61] This figure shows an example of the horizontal cross-sectional configuration of the image sensor shown in Figure 1. [Figure 62] This figure shows an example of the vertical cross-sectional configuration of the image sensor shown in Figure 1. [Figure 63] This figure shows an example of the vertical cross-sectional configuration of the image sensor shown in Figure 1. [Figure 64] This figure shows an example of the circuit configuration of an image sensor according to the above embodiment and its modified form. [Figure 65] Figure 64 shows an example of an image sensor constructed by stacking three substrates. [Figure 66] This diagram illustrates an example where the logic circuit is formed by separating it into a substrate with sensor pixels and a substrate with a readout circuit. [Figure 67] This diagram shows an example of a logic circuit formed on a third circuit board. [Figure 68] This figure shows an example of a schematic configuration of an imaging device equipped with an image sensor according to the above embodiment and its modified form. [Figure 69] Figure 68 shows an example of the imaging procedure in the imaging device. [Figure 70] This block diagram shows an example of a schematic configuration of a vehicle control system. [Figure 71] This is an explanatory diagram showing an example of the installation location of the external information detection unit and the imaging unit. [Figure 72] This figure shows an example of a schematic configuration of an endoscopic surgical system. [Figure 73] This block diagram shows an example of the functional configuration of a camera head and CCU. [Modes for carrying out the invention]

[0008] The forms for implementing this disclosure will be described in detail below with reference to the drawings. The explanation will be given in the following order. 1. Embodiment (Image Sensor)...Figures 1 to 16 Examples using vertical TG and Cu-Cu bonding. 2. Modified example (image sensor) Modification A: Example using a planar TG…Figure 17 Modification B: Example using TSV...Figures 18, 19 Modification C: An example using Cu-Cu bonding at the outer edge of the panel…Figure 20 Modification D: Example using TSV at the outer edge of the panel…Figures 21 and 22 Modification E: An offset is added between the sensor pixel and the readout circuit. Examples of implementations…Figures 23-27 Modification F: A silicon substrate equipped with a readout circuit An example of an island-like structure: Figure 28 Modification G: A silicon substrate equipped with a readout circuit An example of an island-like structure: Figure 29 Modification H: An example where TG is connected to the wiring inside the lower circuit board...Figures 30 and 31 Modification I: An example where the FD is connected to the wiring inside the lower circuit board...Figures 32-39 Modified form J: After the read circuit is formed, the middle board is attached to the lower board. Examples of combined forms: Figures 40A to 40F Modification K: An example where the FD is shared by four sensor pixels: Figures 41-43 Modified example L: Insulating layer at the point where the lower substrate and the middle substrate are bonded together. In this context, the relative permittivity of one part is different from the relative permittivity of another part. Examples of differences: Figures 44 and 45 Modified form M: Number of shared sensor pixels that share the readout circuit Examples of using two: Figures 46 and 47 Modification N: The readout circuit is limited to only one sensor pixel. Examples of connections: Figures 48 and 49 Variation O: The transistor design conditions for the first and second substrates are Example of a difference: Figure 50 Modified example P: Wiring connecting the first board and the second board Variations: Figures 51-63 Modification Q: Using a general column ADC circuit to process the column signal. Example configuration: Figure 64 Modified example R: An example in which the image sensor is constructed by stacking three substrates: Figure 65 Modified example S: An example in which logic circuits are provided on the first and second boards: Figure 66 Modification T: Example in which the logic circuit is located on the third board: Figure 67 3. Examples of application The image sensor according to the above embodiment and its modified form Examples of application to imaging devices…Figures 68, 69 4. Application Examples Application Example 1... An image sensor according to the above embodiment and its modified form Examples of applications to mobile devices…Figures 70, 71 Application Example 2... An image sensor according to the above embodiment and its modified form Examples of applications in surgical systems…Figures 72, 73

[0009] <1. Embodiment> [composition] Figure 1 shows an example of the schematic configuration of an image sensor 1 according to one embodiment of the present disclosure. The image sensor 1 comprises three substrates (first substrate 10, second substrate 20, and third substrate 30). The image sensor 1 has a three-dimensional structure formed by bonding the three substrates (first substrate 10, second substrate 20, and third substrate 30). The first substrate 10, second substrate 20, and third substrate 30 are stacked in this order.

[0010] The first substrate 10 has a semiconductor substrate 11 with a plurality of sensor pixels 12 that perform photoelectric conversion. The semiconductor substrate 11 corresponds to one specific example of the "first semiconductor substrate" of this disclosure. The plurality of sensor pixels 12 are arranged in a matrix within a pixel region 13 on the first substrate 10. The second substrate 20 has a semiconductor substrate 21 with one readout circuit 22 for every four sensor pixels 12 that outputs a pixel signal based on the charge output from the sensor pixels 12. The semiconductor substrate 21 corresponds to one specific example of the "second semiconductor substrate" of this disclosure. The second substrate 20 has a plurality of pixel drive lines 23 extending in the row direction and a plurality of vertical signal lines 24 extending in the column direction. The third substrate 30 has a semiconductor substrate 31 with a logic circuit 32 that processes pixel signals. The semiconductor substrate 31 corresponds to one specific example of the "third semiconductor substrate" of this disclosure. The logic circuit 32 includes, for example, a vertical drive circuit 33, a column signal processing circuit 34, a horizontal drive circuit 35, and a system control circuit 36. The logic circuit 32 (specifically the horizontal drive circuit 35) outputs an output voltage Vout for each sensor pixel 12 to the outside. In the logic circuit 32, for example, a low-resistance region made of silicide formed using a salicide (Self Aligned Silicide) process such as CoSi2 or NiSi may be formed on the surface of the impurity diffusion region that is in contact with the source electrode and drain electrode.

[0011] The vertical drive circuit 33, for example, sequentially selects multiple sensor pixels 12 row by row. The column signal processing circuit 34, for example, applies correlated double sampling (CDS) processing to the pixel signals output from each sensor pixel 12 in the row selected by the vertical drive circuit 33. The column signal processing circuit 34 extracts the signal level of the pixel signals by applying CDS processing and holds pixel data corresponding to the amount of light received by each sensor pixel 12. The horizontal drive circuit 35, for example, sequentially outputs the pixel data held by the column signal processing circuit 34 to the outside. The system control circuit 36, for example, controls the driving of each block in the logic circuit 32 (vertical drive circuit 33, column signal processing circuit 34, and horizontal drive circuit 35).

[0012] Figure 2 shows an example of a sensor pixel 12 and a readout circuit 22. Below, we will describe the case where four sensor pixels 12 share one readout circuit 22, as shown in Figure 2. Here, "sharing" means that the outputs of the four sensor pixels 12 are input to a common readout circuit 22.

[0013] Each sensor pixel 12 has components that are common to all of them. In Figure 2, identification numbers (1, 2, 3, 4) are added to the end of the codes of the components of each sensor pixel 12 in order to distinguish them from one another. Hereafter, when it is necessary to distinguish the components of each sensor pixel 12 from one another, an identification number will be added to the end of the codes of the components of each sensor pixel 12, but when it is not necessary to distinguish the components of each sensor pixel 12 from one another, the identification number at the end of the codes of the components of each sensor pixel 12 will be omitted.

[0014] Each sensor pixel 12 includes, for example, a photodiode PD, a transfer transistor TR electrically connected to the photodiode PD, and a floating diffusion FD that temporarily holds the charge output from the photodiode PD via the transfer transistor TR. The photodiode PD corresponds to one specific example of the "photoelectric conversion element" of this disclosure. The photodiode PD performs photoelectric conversion to generate a charge corresponding to the amount of light received. The cathode of the photodiode PD is electrically connected to the source of the transfer transistor TR, and the anode of the photodiode PD is electrically connected to a reference potential line (e.g., ground). The drain of the transfer transistor TR is electrically connected to the floating diffusion FD, and the gate of the transfer transistor TR is electrically connected to the pixel drive line 23. The transfer transistor TR is, for example, a CMOS (Complementary Metal Oxide Semiconductor) transistor.

[0015] The floating diffusion FDs of each sensor pixel 12 that share a single readout circuit 22 are electrically connected to each other and are also electrically connected to the input terminal of the common readout circuit 22. The readout circuit 22 includes, for example, a reset transistor RST, a selection transistor SEL, and an amplification transistor AMP. The selection transistor SEL may be omitted if necessary. The source of the reset transistor RST (the input terminal of the readout circuit 22) is electrically connected to the floating diffusion FD, and the drain of the reset transistor RST is electrically connected to the power line VDD and the drain of the amplification transistor AMP. The gate of the reset transistor RST is electrically connected to the pixel drive line 23 (see Figure 1). The source of the amplification transistor AMP is electrically connected to the drain of the selection transistor SEL, and the gate of the amplification transistor AMP is electrically connected to the source of the reset transistor RST. The source of the selection transistor SEL (the output terminal of the readout circuit 22) is electrically connected to the vertical signal line 24, and the gate of the selection transistor SEL is electrically connected to the pixel drive line 23 (see Figure 1).

[0016] When the transfer transistor TR is turned ON, it transfers the charge from the photodiode PD to the floating diffusion FD. The gate of the transfer transistor TR (transfer gate TG) extends from the surface of the semiconductor substrate 11 through the well layer 42 to a depth that reaches the PD 41, as shown in Figure 7 below. The reset transistor RST resets the potential of the floating diffusion FD to a predetermined potential. When the reset transistor RST is turned ON, it resets the potential of the floating diffusion FD to the potential of the power line VDD. The selection transistor SEL controls the output timing of the pixel signal from the readout circuit 22. The amplification transistor AMP generates a signal with a voltage corresponding to the level of charge held in the floating diffusion FD as the pixel signal. The amplification transistor AMP constitutes a source follower type amplifier and outputs a pixel signal with a voltage corresponding to the level of charge generated in the photodiode PD. When the selection transistor SEL is turned on, the amplification transistor AMP amplifies the potential of the floating diffusion FD and outputs a voltage corresponding to that potential to the column signal processing circuit 34 via the vertical signal line 24. The reset transistor RST, amplification transistor AMP, and selection transistor SEL are, for example, CMOS transistors.

[0017] As shown in Figure 3, a selection transistor SEL may be provided between the power line VDD and the amplification transistor AMP. In this case, the drain of the reset transistor RST is electrically connected to the power line VDD and the drain of the selection transistor SEL. The source of the selection transistor SEL is electrically connected to the drain of the amplification transistor AMP, and the gate of the selection transistor SEL is electrically connected to the pixel drive line 23 (see Figure 1). The source of the amplification transistor AMP (the output terminal of the readout circuit 22) is electrically connected to the vertical signal line 24, and the gate of the amplification transistor AMP is electrically connected to the source of the reset transistor RST. Furthermore, as shown in Figures 4 and 5, an FD transfer transistor FDG may be provided between the source of the reset transistor RST and the gate of the amplification transistor AMP.

[0018] The FD transfer transistor FDG is used to switch the conversion efficiency. Generally, when shooting in dark places, the pixel signal is small. Based on Q=CV, when performing charge-to-voltage conversion, if the capacitance of the floating diffusion FD (FD capacitance C) is large, the voltage V when converted by the amplification transistor AMP will be small. On the other hand, in bright places, the pixel signal is large, so if the FD capacitance C is not large enough, the floating diffusion FD cannot accept the charge of the photodiode PD. Furthermore, the FD capacitance C needs to be large so that the voltage V when converted by the amplification transistor AMP does not become too large (in other words, to keep it small). Considering these points, when the FD transfer transistor FDG is turned on, the gate capacitance of the FD transfer transistor FDG increases, so the overall FD capacitance C becomes large. On the other hand, when the FD transfer transistor FDG is turned off, the overall FD capacitance C becomes small. In this way, by switching the FD transfer transistor FDG on and off, the FD capacitance C can be varied and the conversion efficiency can be switched.

[0019] Figure 6 shows an example of a connection configuration between multiple readout circuits 22 and multiple vertical signal lines 24. When multiple readout circuits 22 are arranged in the direction of extension of the vertical signal lines 24 (e.g., in the column direction), one vertical signal line 24 may be assigned to each readout circuit 22. For example, as shown in Figure 6, when four readout circuits 22 are arranged in the direction of extension of the vertical signal lines 24 (e.g., in the column direction), one vertical signal line 24 may be assigned to each readout circuit 22. In Figure 6, an identification number (1, 2, 3, 4) is added to the end of the code of each vertical signal line 24 to distinguish them.

[0020] Figure 7 shows an example of the vertical cross-sectional configuration of the image sensor 1. Figure 7 illustrates the cross-sectional configuration of the area of ​​the image sensor 1 facing the sensor pixels 12. Figure 8 is a magnified view of the connection point between the first substrate 10 and the second substrate 20 in the image sensor 1 (circled in Figure 7). Figure 9 is a magnified view of the connection point between the second substrate 20 and the third substrate 30 in the image sensor 1 (circled in Figure 7). The image sensor 1 is constructed by stacking the first substrate 10, the second substrate 20, and the third substrate 30 in this order, and furthermore, a color filter 40 and a light-receiving lens 50 are provided on the back side (light incident surface side) of the first substrate 10. One color filter 40 and one light-receiving lens 50 are provided for each sensor pixel 12, for example. In other words, the image sensor 1 is a back-illuminated type.

[0021] The first substrate 10 is constructed by laminating an insulating layer 46 on a semiconductor substrate 11. The insulating layer 46 corresponds to a specific example of the "first insulating layer" of this disclosure. The first substrate 10 has the insulating layer 46 as part of an interlayer insulating film 51. The insulating layer 46 is provided in the gap between the semiconductor substrate 11 and the semiconductor substrate 21 described later. The semiconductor substrate 11 is made of a silicon substrate. The semiconductor substrate 11 has, for example, a p-well layer 42 on a part of its surface and its vicinity, and a PD 41 with a different conductivity type than the p-well layer 42 in the remaining region (a region deeper than the p-well layer 42). The p-well layer 42 is made up of a p-type semiconductor region. The PD 41 is made up of a semiconductor region with a different conductivity type (specifically n-type) than the p-well layer 42. The semiconductor substrate 11 has a floating diffusion FD within the p-well layer 42 as a semiconductor region with a different conductivity type (specifically n-type) than the p-well layer 42.

[0022] The first substrate 10 has a photodiode PD, a transfer transistor TR, and a floating diffusion FD for each sensor pixel 12. The first substrate 10 is configured such that the transfer transistor TR and floating diffusion FD are provided on the surface side (opposite to the light incident surface, on the second substrate 20 side) of the semiconductor substrate 11. The first substrate 10 has an element isolation section 43 that separates each sensor pixel 12. The element isolation section 43 is formed extending in the direction normal to the semiconductor substrate 11 (a direction perpendicular to the surface of the semiconductor substrate 11). The element isolation section 43 is provided between two adjacent sensor pixels 12. The element isolation section 43 electrically isolates adjacent sensor pixels 12 from each other. The element isolation section 43 is made of, for example, silicon oxide. The element isolation section 43 penetrates, for example, the semiconductor substrate 11. The first substrate 10 further has, for example, a p-well layer 44 that is on the side surface of the element isolation section 43 and in contact with the photodiode PD side. The p-well layer 44 is composed of a semiconductor region with a different conductivity type (specifically, p-type) than the photodiode PD. The first substrate 10 further has, for example, a fixed charge film 45 in contact with the back surface of the semiconductor substrate 11. The fixed charge film 45 is negatively charged to suppress the generation of dark current caused by the interface state on the light-receiving surface side of the semiconductor substrate 11. The fixed charge film 45 is formed, for example, of an insulating film having a negative fixed charge. Examples of materials for such an insulating film include hafnium oxide, zircon oxide, aluminum oxide, titanium oxide, or tantalum oxide. The electric field induced by the fixed charge film 45 forms a hole accumulation layer at the interface on the light-receiving surface side of the semiconductor substrate 11. This hole accumulation layer suppresses the generation of electrons from the interface. The color filter 40 is provided on the back surface side of the semiconductor substrate 11. The color filter 40 is provided, for example, in contact with the fixed charge film 45 and is positioned opposite the sensor pixel 12 via the fixed charge film 45. The light-receiving lens 50 is, for example, provided in contact with the color filter 40 and positioned opposite the sensor pixel 12 via the color filter 40 and the fixed charge film 45.

[0023] The second substrate 20 is constructed by laminating an insulating layer 52 on a semiconductor substrate 21. The insulating layer 52 corresponds to a specific example of the "third insulating layer" of this disclosure. The second substrate 20 has the insulating layer 52 as part of the interlayer insulating film 51. The insulating layer 52 is provided in the gap between the semiconductor substrate 21 and the semiconductor substrate 31. The semiconductor substrate 21 is made of silicon. The second substrate 20 has one readout circuit 22 for every four sensor pixels 12. The second substrate 20 is configured such that the readout circuit 22 is provided on the surface side (third substrate 30 side) of the semiconductor substrate 21. The second substrate 20 is bonded to the first substrate 10 with the back side of the semiconductor substrate 21 facing the surface side of the semiconductor substrate 11. In other words, the second substrate 20 is bonded to the first substrate 10 face to back. The second substrate 20 further has an insulating layer 53 that penetrates the semiconductor substrate 21 within the same layer as the semiconductor substrate 21. The insulating layer 53 corresponds to a specific example of the "second insulating layer" of this disclosure. The second substrate 20 has the insulating layer 53 as part of the interlayer insulating film 51. The insulating layer 53 is provided so as to cover the side surface of the through wiring 54, which will be described later.

[0024] The laminate, consisting of a first substrate 10 and a second substrate 20, has an interlayer insulating film 51 and through-wiring 54 provided within the interlayer insulating film 51. The through-wiring 54 corresponds to a specific example of the "first through-wiring" of this disclosure. The laminate has one through-wiring 54 for each sensor pixel 12. The through-wiring 54 extends in the direction normal to the semiconductor substrate 21 and is provided penetrating the portion of the interlayer insulating film 51 that includes the insulating layer 53. The first substrate 10 and the second substrate 20 are electrically connected to each other by the through-wiring 54. Specifically, the through-wiring 54 is electrically connected to the floating diffusion FD and the connection wiring 55 described later.

[0025] The laminate, consisting of a first substrate 10 and a second substrate 20, further has through-wirings 47 and 48 (see Figure 10 below) provided within the interlayer insulating film 51. Through-wiring 48 corresponds to a specific example of the "first through-wiring" of this disclosure. The laminate has one through-wiring 47 and one through-wiring 48 for each sensor pixel 12. Through-wirings 47 and 48 each extend in the direction normal to the semiconductor substrate 21 and are provided through portions of the interlayer insulating film 51 that include the insulating layer 53. The first substrate 10 and the second substrate 20 are electrically connected to each other by through-wirings 47 and 48. Specifically, through-wiring 47 is electrically connected to the p-well layer 42 of the semiconductor substrate 11 and to the wiring in the second substrate 20. Through-wiring 48 is electrically connected to the transfer gate TG and the pixel drive line 23.

[0026] The second substrate 20 has, for example, a plurality of connection parts 59 within an insulating layer 52 that are electrically connected to the readout circuit 22 and the semiconductor substrate 21. The second substrate 20 further has, for example, a wiring layer 56 on the insulating layer 52. The wiring layer 56 has, for example, an insulating layer 57 and a plurality of pixel drive lines 23 and a plurality of vertical signal lines 24 provided within the insulating layer 57. The wiring layer 56 further has, for example, a plurality of connection wirings 55 within the insulating layer 57, one for every four sensor pixels 12. The connection wirings 55 electrically connect each through-wiring 54 that is electrically connected to the floating diffusion FD included in the four sensor pixels 12 that share the readout circuit 22. Here, the total number of through-wirings 54,48 is greater than the total number of sensor pixels 12 included in the first substrate 10, and is twice the total number of sensor pixels 12 included in the first substrate 10. Furthermore, the total number of through-wirings 54, 48, and 47 is greater than the total number of sensor pixels 12 contained in the first substrate 10, and is three times the total number of sensor pixels 12 contained in the first substrate 10.

[0027] The wiring layer 56 further has, for example, a plurality of pad electrodes 58 within the insulating layer 57. Each pad electrode 58 is made of a metal such as Cu (copper) or Al (aluminum). Each pad electrode 58 is exposed on the surface of the wiring layer 56. Each pad electrode 58 is used for electrical connection between the second substrate 20 and the third substrate 30, and for bonding the second substrate 20 and the third substrate 30. The plurality of pad electrodes 58 are provided, for example, one for each pixel drive line 23 and vertical signal line 24. Here, the total number of pad electrodes 58 (or the total number of connections between pad electrodes 58 and pad electrodes 64 (described later)) is less than the total number of sensor pixels 12 included in the first substrate 10.

[0028] The third substrate 30 is constructed, for example, by laminating an interlayer insulating film 61 on a semiconductor substrate 31. As will be described later, the third substrate 30 is bonded to the second substrate 20 with their surface sides facing each other, so when describing the internal structure of the third substrate 30, the top and bottom directions are reversed compared to the top and bottom directions in the drawings. The semiconductor substrate 31 is made of a silicon substrate. The third substrate 30 has a configuration in which a logic circuit 32 is provided on the surface side of the semiconductor substrate 31. The third substrate 30 further has, for example, a wiring layer 62 on the interlayer insulating film 61. The wiring layer 62 has, for example, an insulating layer 63 and a plurality of pad electrodes 64 provided within the insulating layer 63. The plurality of pad electrodes 64 are electrically connected to the logic circuit 32. Each pad electrode 64 is made of, for example, Cu (copper). Each pad electrode 64 is exposed on the surface of the wiring layer 62. Each pad electrode 64 is used for electrical connection between the second substrate 20 and the third substrate 30, and for bonding the second substrate 20 and the third substrate 30 together. Furthermore, there does not necessarily need to be multiple pad electrodes 64; even one can be electrically connected to the logic circuit 32. The second substrate 20 and the third substrate 30 are electrically connected to each other by the junctions of the pad electrodes 58 and 64. In other words, the gate of the transfer transistor TR (transfer gate TG) is electrically connected to the logic circuit 32 via the through-wiring 54 and the pad electrodes 58 and 64. The third substrate 30 is bonded to the second substrate 20 with its surface facing the surface of the semiconductor substrate 21. That is, the third substrate 30 is bonded to the second substrate 20 face-to-face.

[0029] As shown in Figure 8, the first substrate 10 and the second substrate 20 are electrically connected to each other by through-wiring 54. Also, as shown in Figure 9, the second substrate 20 and the third substrate 30 are electrically connected to each other by the joining of pad electrodes 58 and 64. Here, the width D1 of the through-wiring 54 is narrower than the width D3 of the joining point between the pad electrodes 58 and 64. In other words, the cross-sectional area of ​​the through-wiring 54 is smaller than the cross-sectional area of ​​the joining point between the pad electrodes 58 and 64. Therefore, the through-wiring 54 does not hinder the miniaturization of the area per pixel on the first substrate 10. Furthermore, since the readout circuit 22 is formed on the second substrate 20 and the logic circuit 32 is formed on the third substrate 30, the structure for electrically connecting the second substrate 20 and the third substrate 30 can be formed with a more flexible layout in terms of arrangement and the number of contacts for connection compared to the structure for electrically connecting the first substrate 10 and the second substrate 20. Therefore, a connection between the pad electrodes 58 and 64 can be used as a structure for electrically connecting the second substrate 20 and the third substrate 30 to each other.

[0030] Figures 10 and 11 show examples of the horizontal cross-sectional configuration of the image sensor 1. The upper diagrams in Figures 10 and 11 show an example of the cross-sectional configuration in section Sec1 of Figure 7, and the lower diagrams in Figures 10 and 11 show an example of the cross-sectional configuration in section Sec2 of Figure 7. Figure 10 illustrates a configuration in which two sets of four 2x2 sensor pixels 12 are arranged in the second direction H, and Figure 11 illustrates a configuration in which four sets of four 2x2 sensor pixels 12 are arranged in the first direction V and the second direction H. In the upper cross-sectional diagrams in Figures 10 and 11, an example of the surface configuration of the semiconductor substrate 11 is superimposed on the diagram showing an example of the cross-sectional configuration in section Sec1 of Figure 7, and the insulating layer 46 is omitted. In the lower cross-sectional diagrams in Figures 10 and 11, an example of the surface configuration of the semiconductor substrate 21 is superimposed on the diagram showing an example of the cross-sectional configuration in section Sec2 of Figure 7.

[0031] As shown in Figures 10 and 11, the multiple through-wires 54, 48, and 47 are arranged in a strip-like pattern in the first direction V (up and down direction in Figure 10, left and right direction in Figure 11) within the plane of the first substrate 10. Figures 10 and 11 illustrate the case where the multiple through-wires 54, 48, and 47 are arranged in two columns in the first direction V. The first direction V is parallel to one of the two arrangement directions (e.g., row direction and column direction) of the matrix-arranged multiple sensor pixels 12 (e.g., column direction). In the four sensor pixels 12 that share the readout circuit 22, the four floating diffusion FDs are arranged in close proximity to each other, for example, via an element isolation section 43. In the four sensor pixels 12 that share the readout circuit 22, the four transfer gates TG are arranged to surround the four floating diffusion FDs, and for example, the four transfer gates TG form a ring shape.

[0032] The insulating layer 53 is composed of a plurality of blocks extending in a first direction V. The semiconductor substrate 21 is composed of a plurality of island-shaped blocks 21A that extend in the first direction V and are arranged in a second direction H perpendicular to the first direction V via the insulating layer 53. Each block 21A is provided with, for example, a plurality of sets of reset transistors RST, amplification transistors AMP, and selection transistors SEL. One readout circuit 22 shared by the four sensor pixels 12 is composed of, for example, a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL located in a region facing the four sensor pixels 12. One readout circuit 22 shared by the four sensor pixels 12 is composed of, for example, an amplification transistor AMP in the block 21A to the left of the insulating layer 53, and a reset transistor RST and a selection transistor SEL in the block 21A to the right of the insulating layer 53.

[0033] Figures 12, 13, 14, and 15 show examples of wiring layouts in the horizontal plane of the image sensor 1. Figures 12 to 15 illustrate a case where one readout circuit 22 shared by four sensor pixels 12 is provided in an area facing the four sensor pixels 12. The wiring shown in Figures 12 to 15 is provided, for example, in different layers of the wiring layer 56.

[0034] The four adjacent through-wirings 54 are electrically connected to the connecting wiring 55, for example, as shown in Figure 12. The four adjacent through-wirings 54 are further electrically connected, for example, to the gate of the amplification transistor AMP included in the block 21A to the left of the insulating layer 53 and to the gate of the reset transistor RST included in the block 21A to the right of the insulating layer 53, via the connecting wiring 55 and the connecting portion 59, as shown in Figure 12.

[0035] The power line VDD is positioned opposite each readout circuit 22, which are arranged in a row in the second direction H, as shown in Figure 13, for example. The power line VDD is electrically connected via a connector 59 to the drain of the amplification transistor AMP and the drain of the reset transistor RST of each readout circuit 22, which are arranged in a row in the second direction H, as shown in Figure 13, for example. Two pixel drive lines 23 are positioned opposite each readout circuit 22, which are arranged in a row in the second direction H, as shown in Figure 13, for example. One pixel drive line 23 (second control line) is wiring RSTG, which is electrically connected to the gate of the reset transistor RST of each readout circuit 22, which are arranged in a row in the second direction H, as shown in Figure 13, for example. The other pixel drive line 23 (third control line) is wiring SELG, which is electrically connected to the gate of the selection transistor SEL of each readout circuit 22, which are arranged in a row in the second direction H, as shown in Figure 13, for example. In each readout circuit 22, the source of the amplification transistor AMP and the drain of the selection transistor SEL are electrically connected to each other via wiring 25, for example, as shown in Figure 13.

[0036] Two power lines VSS are positioned opposite each readout circuit 22, which are arranged in a row in the second direction H, as shown in Figure 14, for example. Each power line VSS is electrically connected to a plurality of through-wirings 47 at a position opposite each sensor pixel 12, which are arranged in a row in the second direction H, as shown in Figure 14, for example. Four pixel drive lines 23 are positioned opposite each readout circuit 22, which are arranged in a row in the second direction H, as shown in Figure 14, for example. Each of the four pixel drive lines 23 is a wiring TRG electrically connected to a through-wiring 48 of one of the four sensor pixels 12 corresponding to each readout circuit 22, which are arranged in a row in the second direction H, as shown in Figure 14, for example. In other words, the four pixel drive lines 23 (first control lines) are electrically connected to the gate (transfer gate TG) of the transfer transistor TR of each sensor pixel 12, which are arranged in a row in the second direction H. In Figure 14, identifiers (1, 2, 3, 4) are added to the end of each wiring TRG to distinguish them.

[0037] The vertical signal line 24 is positioned opposite each readout circuit 22, which is arranged in a line in the first direction V, as shown in Figure 15, for example. The vertical signal line 24 (output line) is electrically connected to the output terminal (source of the amplification transistor AMP) of each readout circuit 22, which is arranged in a line in the first direction V, as shown in Figure 15, for example.

[0038] [Manufacturing method] Next, the manufacturing method of the image sensor 1 will be described. Figures 16A to 16F show an example of the manufacturing process of the image sensor 1.

[0039] First, a p-well layer 42, an element isolation layer 43, and another p-well layer 44 are formed on the semiconductor substrate 11. Next, a photodiode PD, a transfer transistor TR, and a floating diffusion FD are formed on the semiconductor substrate 11 (Figure 16A). This forms a sensor pixel 12 on the semiconductor substrate 11. At this time, it is preferable not to use materials with low heat resistance, such as CoSi2 or NiSi produced by the salicide process, as the electrode material for the sensor pixel 12. Rather, it is preferable to use a material with high heat resistance as the electrode material for the sensor pixel 12. Polysilicon is an example of a material with high heat resistance. After that, an insulating layer 46 is formed on the semiconductor substrate 11 (Figure 16A). In this way, the first substrate 10 is formed.

[0040] Next, the semiconductor substrate 21 is bonded onto the first substrate 10 (insulating layer 46) (Figure 16B). At this time, the semiconductor substrate 21 is thinned as needed. In this case, the thickness of the semiconductor substrate 21 is set to the thickness required for forming the readout circuit 22. The thickness of the semiconductor substrate 21 is generally around several hundred nanometers. However, depending on the concept of the readout circuit 22, an FD (Fully Depletion) type is also possible, in which case the thickness of the semiconductor substrate 21 can be in the range of several nanometers to several micrometers.

[0041] Next, an insulating layer 53 is formed in the same layer as the semiconductor substrate 21 (Figure 16C). The insulating layer 53 is formed, for example, in a location opposite to the floating diffusion FD. For example, a slit is formed through the semiconductor substrate 21 to separate the semiconductor substrate 21 into multiple blocks 21A. Then, the insulating layer 53 is formed to fill the slit. Subsequently, a readout circuit 22 including an amplifying transistor AMP is formed in each block 21A of the semiconductor substrate 21 (Figure 16C). At this time, if a highly heat-resistant metal material is used as the electrode material for the sensor pixel 12, the gate insulating film of the readout circuit 22 can be formed by thermal oxidation.

[0042] Next, an insulating layer 52 is formed on the semiconductor substrate 21. In this way, an interlayer insulating film 51 consisting of insulating layers 46, 52, and 53 is formed. Subsequently, through holes 51A and 51B are formed in the interlayer insulating film 51 (Figure 16D). Specifically, a through hole 51B is formed in the insulating layer 52 at a location facing the read circuit 22. Also, a through hole 51A is formed in the interlayer insulating film 51 at a location facing the floating diffusion FD (i.e., facing the insulating layer 53).

[0043] Next, conductive material is embedded in the through holes 51A and 51B to form through-wiring 54 in through-hole 51A and connection portion 59 in through-hole 51B (Figure 16E). Furthermore, connection wiring 55 is formed on the insulating layer 52 to electrically connect the through-wiring 54 and the connection portion 59 to each other (Figure 16E). After that, a wiring layer 56 including pad electrodes 58 is formed on the insulating layer 52. In this way, the second substrate 20 is formed.

[0044] Next, the second substrate 20 is attached to the third substrate 30, on which the logic circuit 32 and wiring layer 62 are formed, with the surface of the second substrate 20 facing the surface of the semiconductor substrate 31 (Figure 16F). At this time, the pad electrodes 58 of the second substrate 20 and the pad electrodes 64 of the third substrate 30 are joined to each other, thereby electrically connecting the second substrate 20 and the third substrate 30. In this way, the image sensor 1 is manufactured.

[0045] [effect] Traditionally, miniaturization of the area per pixel in two-dimensional image sensors has been achieved through the introduction of finer processes and improved mounting density. In recent years, three-dimensional image sensors have been developed to further miniaturize image sensors and reduce the area per pixel. In a three-dimensional image sensor, for example, a semiconductor substrate having multiple sensor pixels and a semiconductor substrate having a signal processing circuit that processes the signals obtained from each sensor pixel are stacked on top of each other. This makes it possible to increase the integration density of sensor pixels or increase the size of the signal processing circuit while maintaining the same chip size as before.

[0046] Incidentally, when stacking three semiconductor chips in a three-dimensional image sensor, it is not possible to bond all the semiconductor substrates face to face. If three semiconductor substrates are simply stacked without careful consideration, the structure that electrically connects the semiconductor substrates may result in an increased chip size or hinder the miniaturization of the area per pixel.

[0047] On the other hand, in this embodiment, the sensor pixels 12 and the readout circuit 22 are formed on different substrates (first substrate 10 and second substrate 20). This allows for an increase in the area of ​​the sensor pixels 12 and the readout circuit 22 compared to when they are formed on the same substrate. As a result, photoelectric conversion efficiency can be improved and transistor noise can be reduced. Furthermore, the first substrate 10 having the sensor pixels 12 and the second substrate 20 having the readout circuit 22 are electrically connected to each other by through-wiring 54 provided in the interlayer insulating film 51. This allows for a smaller chip size compared to when the first substrate 10 and the second substrate 20 are electrically connected to each other by bonding pad electrodes or through-wiring (e.g., TSV (Thorough Si Via)) that penetrates the semiconductor substrate. Furthermore, the resolution can be increased by further miniaturizing the area per pixel. Also, if the chip size is the same as before, the area for forming the sensor pixels 12 can be expanded. Furthermore, in this embodiment, the read circuit 22 and the logic circuit 32 are formed on different substrates (the second substrate 20 and the third substrate 30). This allows for an increase in the area of ​​the read circuit 22 and the logic circuit 32 compared to when they are formed on the same substrate. Also, since the area of ​​the read circuit 22 and the logic circuit 32 is not constrained by the element isolation section 43, the noise characteristics can be improved. In addition, in this embodiment, the second substrate 20 and the third substrate 30 are electrically connected to each other by the joining of the pad electrodes 58 and 64. Here, since the read circuit 22 is formed on the second substrate 20 and the logic circuit 32 is formed on the third substrate 30, the structure for electrically connecting the second substrate 20 and the third substrate 30 can be formed with a more flexible layout in terms of arrangement and the number of contacts for connection compared to the structure for electrically connecting the first substrate 10 and the second substrate 20. Therefore, the bonding of the pad electrodes 58 and 64 can be used for the electrical connection between the second substrate 20 and the third substrate 30. In this way, in this embodiment, the electrical connection between the substrates is made according to the integration density of the substrates.This prevents the chip size from increasing or the miniaturization of the area per pixel from being hindered by the structure that electrically connects the substrates. As a result, it is possible to provide a three-layer image sensor 1 with the same chip size as before, without hindering the miniaturization of the area per pixel.

[0048] Furthermore, in this embodiment, a sensor pixel 12 having a photodiode PD, a transfer transistor TR, and a floating diffusion FD is formed on the first substrate 10, and a readout circuit 22 having a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL is formed on the second substrate 20. This allows for an increase in the area of ​​the sensor pixel 12 and the readout circuit 22 compared to when the sensor pixel 12 and the readout circuit 22 are formed on the same substrate. As a result, even when the electrical connection between the second substrate 20 and the third substrate 30 is made using junctions between the pad electrodes 58 and 64, the chip size does not increase, nor does it hinder the miniaturization of the area per pixel. As a result, it is possible to provide a three-layer image sensor 1 with the same chip size as before, without hindering the miniaturization of the area per pixel. Specifically, by reducing the number of transistors provided on the first substrate 10, the area of ​​the photodiode PD of the sensor pixel 12 can be increased in particular. This increases the saturation signal charge amount in photoelectric conversion, thereby improving the photoelectric conversion efficiency. The second substrate 20 allows for greater flexibility in the layout of each transistor in the readout circuit 22. Furthermore, the area of ​​each transistor can be increased; in particular, increasing the area of ​​the amplification transistor AMP reduces noise affecting the pixel signal. Even when using junctions between the pad electrodes 58 and 64 for the electrical connection between the second substrate 20 and the third substrate 30, the chip size does not increase, nor does it hinder the miniaturization of the area per pixel. As a result, a three-layer image sensor 1 can be provided with the same chip size as before, without hindering the miniaturization of the area per pixel.

[0049] Furthermore, in this embodiment, the second substrate 20 is bonded to the first substrate 10 with the back surface of the semiconductor substrate 21 facing the front surface of the semiconductor substrate 11, and the third substrate 30 is bonded to the second substrate 20 with the front surface of the semiconductor substrate 31 facing the front surface of the semiconductor substrate 21. As a result, by using through-wiring 54 for the electrical connection between the first substrate 10 and the second substrate 20, and by using bonding between pad electrodes 58 and 64 for the electrical connection between the second substrate 20 and the third substrate 30, it is possible to provide a three-layer image sensor 1 with the same chip size as before, without hindering the miniaturization of the area per pixel.

[0050] Furthermore, in this embodiment, the cross-sectional area of ​​the through-wiring 54 is smaller than the cross-sectional area of ​​the junction between the pad electrodes 58 and 64. This makes it possible to provide a three-layer image sensor 1 with the same chip size as before, without hindering the miniaturization of the area per pixel.

[0051] Furthermore, in the logic circuit 32 of this embodiment, a low-resistance region made of silicide formed using a salicide (Self-Aligned Silicide) process, such as CoSi2 or NiSi, is formed on the surface of the impurity diffusion region that contacts the source electrode and drain electrode. The low-resistance region made of silicide is formed from a compound of the semiconductor substrate material and a metal. Here, the logic circuit 32 is provided on the third substrate 30. Therefore, the logic circuit 32 can be formed using a process different from the process used to form the sensor pixels 12 and the readout circuit 22. As a result, high-temperature processes such as thermal oxidation can be used when forming the sensor pixels 12 and the readout circuit 22. In addition, silicide, which is a material with low heat resistance, can be used for the logic circuit 32. Accordingly, when a low-resistance region made of silicide is provided on the surface of the impurity diffusion region that contacts the source electrode and drain electrode of the logic circuit 32, contact resistance can be reduced, and as a result, the calculation speed of the logic circuit 32 can be increased.

[0052] Furthermore, in this embodiment, the first substrate 10 is provided with an element isolation section 43 that separates each sensor pixel 12. However, in this embodiment, the sensor pixels 12 having a photodiode PD, a transfer transistor TR, and a floating diffusion FD are formed on the first substrate 10, and the readout circuit 22 having a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL is formed on the second substrate 20. As a result, even if the area surrounded by the element isolation section 43 becomes smaller due to the miniaturization of the area per pixel, the area of ​​the sensor pixels 12 and the readout circuit 22 can be enlarged. Consequently, even when using the element isolation section 43, the chip size does not increase, nor does it hinder the miniaturization of the area per pixel. Therefore, it is possible to provide a three-layer image sensor 1 with the same chip size as before, without hindering the miniaturization of the area per pixel.

[0053] Furthermore, in this embodiment, the element isolation section 43 penetrates the semiconductor substrate 11. This allows for suppression of signal crosstalk between adjacent sensor pixels 12, even when the distance between them decreases due to miniaturization of the area per pixel, thereby suppressing a decrease in resolution and image quality degradation due to color mixing in the reproduced image.

[0054] Furthermore, in this embodiment, the laminate consisting of the first substrate 10 and the second substrate 20 has three through-wirings 54, 47, and 48 for each sensor pixel 12. Through-wiring 48 is electrically connected to the gate (transfer gate TG) of the transfer transistor TR, through-wiring 47 is electrically connected to the p-well layer 42 of the semiconductor substrate 11, and through-wiring 54 is electrically connected to the floating diffusion FD. In other words, the number of through-wirings 54, 47, and 48 is greater than the number of sensor pixels 12 contained in the first substrate 10. However, in this embodiment, through-wirings 54 with a small cross-sectional area are used for the electrical connection between the first substrate 10 and the second substrate 20. This makes it possible to further reduce the chip size and further miniaturize the area per pixel on the first substrate 10. As a result, it is possible to provide a three-layer image sensor 1 with the same chip size as before, without hindering the miniaturization of the area per pixel.

[0055] <2. Variant> A modified example of the image sensor 1 according to the above embodiment is described below. In the following modified examples, components common to the above embodiment are given the same reference numerals.

[0056] [Differentiation A] Figure 17 shows a modified example of the vertical cross-sectional configuration of the image sensor 1 according to the above embodiment. Figure 17 shows a modified example of the cross-sectional configuration described in Figure 7. In this modified example, the transfer transistor TR has a planar transfer gate TG. Therefore, the transfer gate TG does not penetrate the well layer 42 and is formed only on the surface of the semiconductor substrate 11. Even when a planar transfer gate TG is used for the transfer transistor TR, the image sensor 1 has the same effects as in the above embodiment.

[0057] [Variation B] Figures 18 and 19 show a modified example of the vertical cross-sectional configuration of the image sensor 1 according to the above embodiment and its modified examples. Figure 18 shows a modified example of the cross-sectional configuration described in Figure 7. Figure 19 shows a modified example of the cross-sectional configuration described in Figure 17. In this modified example, instead of joining the pad electrodes 58 and 64 together, through-wiring 65 that penetrates the semiconductor substrate 31 is used as a structure to electrically connect the second substrate 20 and the third substrate 30. That is, the third substrate 30 has through-wiring 65 used for the electrical connection between the second substrate 20 and the third substrate 30, and the second substrate 20 and the third substrate 30 are electrically connected to each other by through-wiring 65. In other words, the gate of the transfer transistor TR (transfer gate TG) is electrically connected to the logic circuit 32 via through-wiring 48, pad electrodes 58, and through-wiring 65. Here, the total number of through-wirings 65 is less than the total number of sensor pixels 12 included in the first substrate 10. The through-wiring 65 corresponds to one specific example of the "second through-wiring" in this disclosure.

[0058] The through-hole wiring 65 is composed of, for example, so-called TSVs (Thorough Silicon Vias). The width D1 of the through-hole wiring 54 is narrower than the width D3 of the through-hole wiring 65. In other words, the cross-sectional area of ​​the through-hole wiring 54 is smaller than the cross-sectional area of ​​the through-hole wiring 65. As a result, the through-hole wiring 54 does not hinder the miniaturization of the area per pixel on the first substrate 10. Furthermore, since the read circuit 22 is formed on the second substrate 20 and the logic circuit 32 is formed on the third substrate 30, the structure for electrically connecting the second substrate 20 and the third substrate 30 can be formed with a more flexible layout in terms of arrangement and the number of contacts for connection compared to the structure for electrically connecting the first substrate 10 and the second substrate 20. As a result, even when through-hole wiring 65 is used as the structure for electrically connecting the second substrate 20 and the third substrate 30, the chip size does not increase, nor does it hinder the miniaturization of the area per pixel. As a result, it is possible to provide a three-layer image sensor 1 with the same chip size as before, without hindering the miniaturization of the area per pixel.

[0059] [Differentiation C] Figure 20 shows a modified example of the vertical cross-sectional configuration of the image sensor 1 according to the above embodiment. In this modified example, the electrical connection between the second substrate 20 and the third substrate 30 is made in the region of the first substrate 10 that faces the peripheral region 14. The peripheral region 14 corresponds to the frame region of the first substrate 10 and is provided at the periphery of the pixel region 13. In this modified example, the second substrate 20 has a plurality of pad electrodes 58 in the region facing the peripheral region 14, and the third substrate 30 has a plurality of pad electrodes 64 in the region facing the peripheral region 14. The second substrate 20 and the third substrate 30 are electrically connected to each other by the joining of the pad electrodes 58 and 64 provided in the region facing the peripheral region 14.

[0060] Thus, in this modified example, the second substrate 20 and the third substrate 30 are electrically connected to each other by bonding the pad electrodes 58 and 64, which are provided in the region facing the peripheral region 14. This reduces the risk of hindering the miniaturization of the area per pixel compared to the case where the pad electrodes 58 and 64 are bonded in the region facing the pixel region 13. Therefore, it is possible to provide a three-layer image sensor 1 with the same chip size as before, without hindering the miniaturization of the area per pixel.

[0061] [Differentiation D] Figures 21 and 22 show one modified example of the vertical cross-sectional configuration of the image sensor 1 according to the modified example C described above. In this modified example, the electrical connection between the second substrate 20 and the third substrate 30 is made in the region facing the peripheral region 14.

[0062] In this modified example, the image sensor 1 is provided with through-wiring 66 in a region facing the peripheral region 14, as shown in Figure 21, for example. The through-wiring 66 electrically connects the second substrate 20 and the third substrate 30 to each other. The through-wiring 66 extends in the direction normal to the semiconductor substrates 11 and 21, penetrates the first substrate 10 and the second substrate 20, and reaches into the wiring layer 62 of the third substrate 30. The through-wiring 66 electrically connects the wiring in the wiring layer 56 of the second substrate 20 to the wiring in the wiring layer 62 of the third substrate 30 to each other.

[0063] In this modified example, the image sensor 1 may, for example, be provided with through-wirings 67, 68 and connecting wiring 69 in a region facing the peripheral region 14, as shown in Figure 22. The wiring consisting of through-wirings 67, 68 and connecting wiring 69 electrically connects the second substrate 20 and the third substrate 30 to each other. Through-wiring 67 extends in the direction normal to the semiconductor substrates 11, 21, penetrates the first substrate 10 and the second substrate 20, and reaches into the wiring layer 62 of the third substrate 30. Through-wiring 68 extends in the direction normal to the semiconductor substrates 11, 21, penetrates the first substrate 10, and reaches into the wiring layer 56 of the second substrate 20. Connecting wiring 69 is provided in contact with the back surface of the semiconductor substrate 11 and is provided in contact with through-wirings 67 and 68. The through-wirings 67 and 68 electrically connect the wiring in the wiring layer 56 of the second substrate 20 and the wiring in the wiring layer 62 of the third substrate 30 to each other via the connecting wiring 69.

[0064] As described above, in this modified example, the second substrate 20 and the third substrate 30 are electrically connected to each other by through-wiring 66, or through-wiring 67, 68 and connecting wiring 69, which are provided in the region facing the peripheral region 14. This reduces the risk of hindering the miniaturization of the area per pixel compared to the case where the second substrate 20 and the third substrate 30 are electrically connected to each other in the region facing the pixel region 13. Therefore, it is possible to provide a three-layer image sensor 1 with the same chip size as before, without hindering the miniaturization of the area per pixel.

[0065] [Differentiation Example E] Figures 23 and 24 show a modified example of the horizontal cross-sectional configuration of the image sensor 1 according to the above embodiment. The upper diagrams in Figures 23 and 24 show a modified example of the cross-sectional configuration at cross-section Sec1 of Figure 7, and the lower diagram in Figure 23 shows a modified example of the cross-sectional configuration at cross-section Sec2 of Figure 7. In the upper cross-sectional diagrams in Figures 23 and 24, a diagram showing a modified example of the surface configuration of the semiconductor substrate 11 in Figure 7 is superimposed on a diagram showing a modified example of the cross-sectional configuration at cross-section Sec1 of Figure 7, and the insulating layer 46 is omitted. In the lower cross-sectional diagrams in Figures 23 and 24, a diagram showing a modified example of the surface configuration of the semiconductor substrate 21 is superimposed on a diagram showing a modified example of the cross-sectional configuration at cross-section Sec2 of Figure 7.

[0066] As shown in Figures 23 and 24, the multiple through-wires 54, 48, and 47 (multiple dots arranged in a matrix in the figures) are arranged in a strip-like pattern in the first direction V (left-right direction in Figures 23 and 24) within the plane of the first substrate 10. Figures 23 and 24 illustrate the case where the multiple through-wires 54, 48, and 47 are arranged in two columns in the first direction V. In the four sensor pixels 12 that share the readout circuit 22, the four floating diffusion FDs are arranged in close proximity to each other, for example, via an element isolation section 43. In the four sensor pixels 12 that share the readout circuit 22, the four transfer gates TG (TG1, TG2, TG3, TG4) are arranged to surround the four floating diffusion FDs, and for example, the four transfer gates TG form a ring shape.

[0067] The insulating layer 53 is composed of a plurality of blocks extending in the first direction V. The semiconductor substrate 21 is composed of a plurality of island-shaped blocks 21A that extend in the first direction V and are arranged in a second direction H perpendicular to the first direction V via the insulating layer 53. Each block 21A is provided with, for example, a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL. A single readout circuit 22 shared by the four sensor pixels 12 is, for example, not positioned directly opposite the four sensor pixels 12, but offset in the second direction H.

[0068] In Figure 23, a single readout circuit 22 shared by four sensor pixels 12 is composed of a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL located in a region on the second substrate 20 that is shifted in the second direction H from the region facing the four sensor pixels 12. The single readout circuit 22 shared by four sensor pixels 12 is composed of, for example, an amplification transistor AMP, a reset transistor RST, and a selection transistor SEL in a single block 21A.

[0069] In Figure 24, a single readout circuit 22 shared by four sensor pixels 12 is composed of a reset transistor RST, an amplification transistor AMP, a selection transistor SEL, and an FD transfer transistor FDG, located in a region on the second substrate 20 that is shifted in the second direction H from the region facing the four sensor pixels 12. The single readout circuit 22 shared by four sensor pixels 12 is composed of, for example, an amplification transistor AMP, a reset transistor RST, a selection transistor SEL, and an FD transfer transistor FDG within a single block 21A.

[0070] In this modified example, the single readout circuit 22 shared by the four sensor pixels 12 is not positioned directly facing the four sensor pixels 12, but rather offset in the second direction H from the position directly facing the four sensor pixels 12. In this case, the wiring 25 can be shortened, or the wiring 25 can be omitted, and the source of the amplification transistor AMP and the drain of the selection transistor SEL can be configured in a common impurity region. As a result, the size of the readout circuit 22 can be reduced, or the size of other parts of the readout circuit 22 can be increased.

[0071] Figures 25, 26, and 27 show an example of the wiring layout in the horizontal plane of the image sensor 1 described in Figure 24. Figures 25 to 27 illustrate a case in which one readout circuit 22 shared by four sensor pixels 12 is provided in a region shifted in the second direction H from the region facing the four sensor pixels 12. The wiring shown in Figures 25 to 27 is provided, for example, in different layers of the wiring layer 56.

[0072] The four adjacent through-wirings 54 are electrically connected to the connecting wiring 55, for example, as shown in Figure 25. The four adjacent through-wirings 54 are further electrically connected, for example, to the gate of the amplification transistor AMP contained in the block 21A below the insulating layer 53 and to the source of the FD transfer transistor FDG contained in the block 21A below the insulating layer 53, via the connecting wiring 55 and the connection 59.

[0073] For example, as shown in Figure 26, wiring SELG, wiring Vout, wiring RSTG, wiring FDG, and power line VSS are arranged in the region opposite each block 21A. Also, as shown in Figure 26, for example, wiring TRG1, TRG2, TRG3, and TRG4 are arranged in the region opposite each insulating layer 53.

[0074] Furthermore, as shown in Figure 27, for example, a power line VDDx is provided that is electrically connected to the power line VDD. Power line VDDx extends in a second direction H that is perpendicular to the power line VDD which extends in a first direction V. Also, as shown in Figure 27, for example, a power line VSSx is provided that is electrically connected to the power line VSS. Power line VSSx extends in a second direction H that is perpendicular to the power line VSS which extends in a first direction V.

[0075] Furthermore, for example, as shown in Figure 27, there is a wiring VOUT1x that is electrically connected to wiring VOUT1. Wiring VOUT1x extends in a second direction H that is perpendicular to wiring VOUT1 which extends in a first direction V. Also, for example, as shown in Figure 27, there is a wiring VOUT2x that is electrically connected to wiring VOUT2. Wiring VOUT2x extends in a second direction H that is perpendicular to wiring VOUT2 which extends in a first direction V. Also, for example, as shown in Figure 27, there is a wiring VOUT3x that is electrically connected to wiring VOUT3. Wiring VOUT3x extends in a second direction H that is perpendicular to wiring VOUT3 which extends in a first direction V. Also, for example, as shown in Figure 27, there is a wiring VOUT4x that is electrically connected to wiring VOUT4. Wiring VOUT4x extends in a second direction H that is perpendicular to wiring VOUT4 which extends in a first direction V.

[0076] In this modified example, power lines VDDx, VSSx and wiring VOUT1x to VOUT4x are provided within the wiring layer 56. This allows for flexible configuration of the wiring exit direction.

[0077] [Modification F] Figure 28 shows a modified example of the horizontal cross-sectional configuration of the image sensor 1 according to the above embodiment. Figure 28 shows a modified example of the cross-sectional configuration of Figure 10.

[0078] In this modified example, the semiconductor substrate 21 is composed of a plurality of island-shaped blocks 21A arranged side by side in a first direction V and a second direction H, separated by an insulating layer 53. Each block 21A is provided, for example, with a set of reset transistors RST, amplification transistors AMP and selection transistors SEL. In this configuration, crosstalk between adjacent readout circuits 22 can be suppressed by the insulating layer 53, thereby suppressing a decrease in resolution and image quality degradation due to color mixing in the reproduced image.

[0079] [Differentiation G] Figure 29 shows a modified example of the horizontal cross-sectional configuration of the image sensor 1 according to the above embodiment. Figure 29 shows a modified example of the cross-sectional configuration of Figure 28.

[0080] In this modified example, one readout circuit 22 shared by four sensor pixels 12 is not, for example, positioned directly opposite the four sensor pixels 12, but is offset in the first direction V. In this modified example, similar to modified example F, the semiconductor substrate 21 is further composed of a plurality of island-shaped blocks 21A arranged in the first direction V and the second direction H via an insulating layer 53. Each block 21A is provided with, for example, a set of reset transistors RST, amplification transistors AMP and selection transistors SEL. In this modified example, a plurality of through-wirings 47 and a plurality of through-wirings 54 are also arranged in the second direction H. Specifically, the plurality of through-wirings 47 are arranged between four through-wirings 54 that share a certain readout circuit 22 and four through-wirings 54 that share other readout circuits 22 adjacent to that readout circuit 22 in the second direction H. In this case, crosstalk between adjacent readout circuits 22 can be suppressed by the insulating layer 53 and the through-wirings 47, thereby suppressing a decrease in resolution and image quality degradation due to color mixing on the reproduced image.

[0081] [Modification H] Figure 30 shows one modified example of the vertical cross-sectional configuration of the image sensor 1 according to the above embodiment and its modified form. Figure 30 shows an enlarged view of one modified example of the cross-sectional configuration of the connection point between the first substrate 10 and the second substrate 20 in Figures 7, 17 to 24, 28, and 29.

[0082] In this modified example, the transfer gate TG is not connected to the through-wiring 48, but is electrically connected to a gate wiring 49 that extends in a direction parallel to the surface of the first substrate 10 and is provided within the interlayer insulating film 51 (specifically, the insulating layer 46). In other words, in this modified example, the first substrate 10 has a gate wiring 49 provided within the interlayer insulating film 51 (specifically, the insulating layer 46). The gate wiring 49 is electrically connected to the logic circuit 32 via through-wiring provided in a region (frame region) not facing the pixel region 13 in a laminate consisting of the first substrate 10 and the second substrate 20. In other words, the gate of the transfer transistor TR (transfer gate TG) is electrically connected to the logic circuit 32 via the gate wiring 49. As a result, there is no need to provide through-wiring 48, and the area of ​​the readout circuit 22 can be made larger compared to the case where through-wiring 48 is provided.

[0083] The gate wiring 49 may be formed from, for example, a highly heat-resistant metal material. Examples of highly heat-resistant metal materials include W (tungsten) or Ru (ruthenium). When the gate wiring 49 is formed from a highly heat-resistant metal material, for example, when forming the readout circuit 22 after bonding the semiconductor substrate 21 to the first substrate 10, a thermal oxide film can be used as the gate insulating film.

[0084] Figure 31 shows one modified example of the horizontal cross-sectional configuration of the image sensor 1 according to this modification. Figure 31 shows an example of the cross-sectional configuration of the image sensor 1 having the cross-sectional configuration of Figure 30. Each gate wiring 49 extends in a direction parallel to the first direction V, for example. In this case, each gate wiring 49 is arranged at a location facing each block 21A of the semiconductor substrate 21, for example.

[0085] In this modified example, the through-wiring 48 is omitted, and the transfer gate TG is electrically connected to a gate wiring 49 that extends in a direction parallel to the surface of the first substrate 10 and is provided within the interlayer insulating film 51 (specifically, the insulating layer 46). As a result, the multiple gate wirings 49 are connected to different readout circuits 22 and are positioned between two through-wirings 54 that are adjacent to each other in the second direction H. Consequently, the electric field line density between two through-wirings 54 that are connected to different readout circuits 22 and adjacent to each other in the second direction H can be reduced by the multiple gate wirings 49. As a result, signal crosstalk between adjacent sensor pixels 12 can be suppressed, and image quality degradation due to resolution reduction and color mixing on the reproduced image can be suppressed.

[0086] [Modification I] Figure 32 shows one modified example of the vertical cross-sectional configuration of the image sensor 1 according to the modified example H described above. Figure 32 shows one modified example of the cross-sectional configuration of Figure 30.

[0087] In this modified example, the transfer gate TG is electrically connected to a gate wiring 49 provided within the interlayer insulating film 51 (specifically, the insulating layer 46). In this modified example, four floating diffusion FDs that share the readout circuit 22 are further electrically connected to a connection portion 71 and a connection wiring 72 provided within the interlayer insulating film 51 (specifically, the insulating layer 46). The connection wiring 72 is electrically connected to a through-wiring 54. In other words, in this modified example, there is no through-wiring 54 for each sensor pixel 12, and one through-wiring 54 is provided for each of the four sensor pixels 12 that share the readout circuit 22 (connection wiring 72). Note that in Figure 32, the connection portion 71 and the connection wiring 72 may be formed integrally.

[0088] Figures 33 and 34 show an example of the horizontal cross-sectional configuration of the image sensor 1 according to this modified example. Figures 33 and 34 show an example of the cross-sectional configuration of the image sensor 1 having the cross-sectional configuration of Figure 32.

[0089] In this modified example, as described above, one through-wiring 54 is provided for each of the four floating diffusion FDs that share the readout circuit 22. In this modified example, the through-wiring 47 is also omitted in the same way as the through-wiring 54. Specifically, instead of four adjacent through-wirings 47, for example, as shown in Figure 35, four connection points 73 provided within the interlayer insulating film 51 (specifically the insulating layer 46) are each electrically connected to the p-well layer 42 of the semiconductor substrate 11 of each sensor pixel 12. These four connection points 73 are electrically connected to a connection wiring 74 provided within the interlayer insulating film 51 (specifically the insulating layer 46). The connection wiring 74 is electrically connected to the through-wiring 47 and the power line VSS. In other words, in this modified example, there is no through-wiring 47 for each sensor pixel 12, and one through-wiring 47 is provided for each of the four sensor pixels 12 that share the connection wiring 74.

[0090] The four sensor pixels 12 that share the connection wiring 74 do not perfectly coincide with the four sensor pixels 12 that share the readout circuit 22 (connection wiring 72). Here, in a matrix arrangement of multiple sensor pixels 12, the four sensor pixels 12 that correspond to a region obtained by shifting the unit region corresponding to four sensor pixels 12 that share one floating diffusion FD in the first direction V by the amount of one sensor pixel 12 are conveniently referred to as four sensor pixels 12A. In this modified example, the first substrate 10 shares a through-wiring 47 for every four sensor pixels 12A. Therefore, in this modified example, one through-wiring 47 is provided for every four sensor pixels 12A.

[0091] Furthermore, for convenience, two adjacent readout circuits 22 in the first direction V are referred to as the first readout circuit 22A and the second readout circuit 22B. Of the four sensor pixels 12 that share the first readout circuit 22A, the two sensor pixels 12 adjacent to the second readout circuit 22B, and of the four sensor pixels 12 that share the second readout circuit 22B, the two sensor pixels 12 adjacent to the first readout circuit 22A, share one connection wire 74. In other words, the four sensor pixels 12 that share the connection wire 74 and the four sensor pixels 12 that share the readout circuit 22 (connection wire 72) are shifted by the width of one sensor pixel 12 in the first direction V.

[0092] As a result, for example, as shown in Figure 34, it becomes possible to arrange through-wirings 54, 47 in a single row on the insulating layer 53 extending in the first direction V. In this case, the width of the insulating layer 53 in the second direction H can be narrowed compared to when the through-wirings 54, 47, 48 are arranged in two rows. Furthermore, by the amount by which the width of the insulating layer 53 in the second direction H is narrowed, the width of each block 21A of the semiconductor substrate 21 extending in the first direction V can be widened in the second direction H. When each block 21A of the semiconductor substrate 21 is enlarged, the size of the readout circuit 22 within each block 21A can also be enlarged. As a result, even when the electrical connection between the second substrate 20 and the third substrate 30 is made using the bonding of pad electrodes 58, 64, the chip size does not increase, nor is the miniaturization of the area per pixel hindered. As a result, it is possible to provide a three-layer image sensor 1 with the same chip size as before, without hindering the miniaturization of the area per pixel.

[0093] Figure 36 shows an example of the horizontal cross-sectional configuration of the image sensor 1 according to this modified example. Figure 36 shows a modified example of the cross-sectional configuration of Figure 34. In the image sensor 1 shown in Figure 36, one through-wiring 54 is provided for every four sensor pixels 12 that share the readout circuit 22 (connection wiring 72), and one through-wiring 47 is provided for every four sensor pixels 12 that share the connection wiring 74.

[0094] As a result, for example, as shown in Figure 36, it becomes possible to arrange through-wirings 54 and 47 in a single row in the portion of the insulating layer 53 that extends in the first direction V. In this case, compared to the case where the through-wirings 54, 47, and 48 are arranged in two rows, the width in the second direction H of the portion of the insulating layer 53 that extends in the first direction V can be narrowed. Furthermore, by the amount by which the width in the second direction H of the portion of the insulating layer 53 that extends in the first direction V has been narrowed, the width in the second direction H of each block 21A of the semiconductor substrate 21 can be widened. If each block 21A of the semiconductor substrate 21 is enlarged, the size of the readout circuit 22 within each block 21A can also be enlarged. As a result, even when the electrical connection between the second substrate 20 and the third substrate 30 is made using the junction of pad electrodes 58 and 64, the chip size does not increase, nor is the miniaturization of the area per pixel hindered. As a result, it is possible to provide a three-layer image sensor 1 with the same chip size as before, without hindering the miniaturization of the area per pixel.

[0095] Figures 37 and 38 show an example of the horizontal cross-sectional configuration of the image sensor 1 according to this modified example. Figures 37 and 38 show an example of the horizontal cross-sectional configuration of the image sensor 1 having the cross-sectional configuration of Figure 32, and also show a modified example of the cross-sectional configuration of Figures 33 and 34.

[0096] In this modified example, as described above, one through-wiring 54 is provided for each of the four floating diffusion FDs that share the readout circuit 22. In this modified example, the through-wiring 47 is also omitted in a similar manner to the through-wiring 54. Specifically, instead of two adjacent through-wirings 47, for example, as shown in Figure 39, two connection parts 73 provided within the interlayer insulating film 51 (specifically the insulating layer 46) are each electrically connected to the p-well layer 42 of the semiconductor substrate 11 of each sensor pixel 12. These two connection parts 73 are electrically connected to a connection wiring 74 provided within the interlayer insulating film 51 (specifically the insulating layer 46). The connection wiring 74 is electrically connected to the through-wiring 47 and the power line VSS. In other words, in this modified example, there is no through-wiring 47 for each sensor pixel 12, and one through-wiring 47 is provided for each of the two sensor pixels 12 that share the connection wiring 74.

[0097] As a result, for example, as shown in Figure 38, it becomes possible to arrange the through-wirings 54 and 47 in a single row in the portion of the insulating layer 53 that extends in the first direction V. Furthermore, as shown in Figure 38, for example, it becomes possible to arrange the through-wirings 54 and 47 in a single row in the portion of the insulating layer 53 that extends in the second direction H. In this case, compared to the case where the through-wirings 54, 47, and 48 are arranged in two rows, the width in the second direction H of the portion of the insulating layer 53 that extends in the first direction V can be narrowed, and the width in the first direction V of the portion of the insulating layer 53 that extends in the second direction H can be narrowed. Furthermore, by narrowing the width in the second direction H of the portion of the insulating layer 53 that extends in the first direction V, the width in the second direction H of each block 21A of the semiconductor substrate 21 can be widened, and by narrowing the width in the first direction V of the portion of the insulating layer 53 that extends in the second direction H, the width in the first direction V of each block 21A of the semiconductor substrate 21 can be widened. When each block 21A of the semiconductor substrate 21 is enlarged, the size of the readout circuit 22 within each block 21A can also be enlarged. As a result, even when the electrical connection between the second substrate 20 and the third substrate 30 is made using the bonding of the pad electrodes 58 and 64, the chip size does not increase, nor does it hinder the miniaturization of the area per pixel. As a result, it is possible to provide a three-layer image sensor 1 with the same chip size as before, without hindering the miniaturization of the area per pixel.

[0098] [Modification J] Figures 40A to 40F show a modified example of the manufacturing process of the image sensor 1 according to the above embodiment and its modified form.

[0099] First, a readout circuit 22, including an amplification transistor AMP, is formed on the semiconductor substrate 21 (Figure 40A). Next, a depression is formed in a predetermined location on the surface of the semiconductor substrate 21, and an insulating layer 53 is formed to fill the depression (Figure 40A). Next, an insulating layer 52 is formed on the semiconductor substrate 21 (Figure 40A). In this way, the substrate 110 is formed. Next, a support substrate 120 is bonded to the substrate 110 so as to be in contact with the insulating layer 52 (Figure 40B). Subsequently, the thickness of the semiconductor substrate 21 is reduced by polishing the back surface of the semiconductor substrate 21 (Figure 40C). At this time, the back surface of the semiconductor substrate 21 is polished until the depression of the semiconductor substrate 21 is reached. After that, a bonding layer 130 is formed on the polished surface (Figure 40D).

[0100] Next, the bonding layer 130 is oriented towards the surface side of the semiconductor substrate 11 of the first substrate 10, and the substrate 110 is bonded to the first substrate 10 (Figure 40E). Subsequently, with the substrate 110 bonded to the first substrate 10, the support substrate 120 is peeled off from the substrate 110 (Figure 40F). After that, the procedure described in Figures 16D to 16F above is carried out. The image sensor 1 can also be manufactured in this way.

[0101] Thus, in this modified example, a readout circuit 22 including an amplification transistor AMP is formed on the semiconductor substrate 21, and then the semiconductor substrate 21 is bonded to the first substrate 10. Even in this case, the configuration of the image sensor 1 according to the above embodiment and its modified example can be realized.

[0102] [Differentiation K] Figure 41 shows an example of the horizontal cross-sectional configuration of the image sensor 1 according to the above embodiment and its modified form. Figure 41 shows one modified form of the cross-sectional configuration of Figure 10.

[0103] In this modified example, the first substrate 10 has a photodiode PD and a transfer transistor TR for each sensor pixel 12, and a floating diffusion FD is shared for every four sensor pixels 12. Therefore, in this modified example, one through-wiring 54 is provided for every four sensor pixels 12.

[0104] In a matrix arrangement of multiple sensor pixels 12, the four sensor pixels 12 corresponding to a unit region obtained by shifting a unit region corresponding to four sensor pixels 12 that share one floating diffusion FD in the first direction V by the amount of one sensor pixel 12 are conveniently referred to as four sensor pixels 12A. In this modified example, the first substrate 10 shares a through-wiring 47 for every four sensor pixels 12A. Therefore, in this modified example, one through-wiring 47 is provided for every four sensor pixels 12A.

[0105] In this modified example, the first substrate 10 has an element isolation section 43 that separates the photodiode PD and transfer transistor TR for each sensor pixel 12. The element isolation section 43 does not completely enclose the sensor pixels 12 when viewed from the direction normal to the semiconductor substrate 11, and has gaps (unformed regions) near the floating diffusion FD (through-wiring 54) and near the through-wiring 47. These gaps allow four sensor pixels 12 to share one through-wiring 54 and four sensor pixels 12A to share one through-wiring 47. In this modified example, the second substrate 20 has a readout circuit 22 for each of the four sensor pixels 12 that share the floating diffusion FD.

[0106] Figure 42 shows an example of the horizontal cross-sectional configuration of the image sensor 1 according to this modified example. Figure 42 shows a modified example of the cross-sectional configuration of Figure 28. In this modified example, the first substrate 10 has a photodiode PD and a transfer transistor TR for each sensor pixel 12, and a floating diffusion FD is shared for every four sensor pixels 12. Furthermore, the first substrate 10 has an element isolation section 43 that separates the photodiode PD and transfer transistor TR for each sensor pixel 12.

[0107] Figure 43 shows an example of the horizontal cross-sectional configuration of the image sensor 1 according to this modified example. Figure 43 shows a modified example of the cross-sectional configuration of Figure 29. In this modified example, the first substrate 10 has a photodiode PD and a transfer transistor TR for each sensor pixel 12, and a floating diffusion FD is shared for every four sensor pixels 12. Furthermore, the first substrate 10 has an element isolation section 43 that separates the photodiode PD and transfer transistor TR for each sensor pixel 12.

[0108] [Modified version L] Figure 44 shows an example of the vertical cross-sectional configuration of the image sensor 1 according to the above embodiment and its modified form. Figure 44 shows an enlarged view of the connection point between the first substrate 10 and the second substrate 20 in the image sensor 1 according to the above embodiment and its modified form.

[0109] In two adjacent sensor pixels 12 connected to different readout circuits 22, two transfer gates TG are provided in the gap between the floating diffusion FD of one sensor pixel 12 and the floating diffusion FD of the other sensor pixel 12. In this case, let t1 be the thickness of each transfer gate TG, and t2 be the thickness of the insulating layer 46 in the gap between the floating diffusion FD of one sensor pixel 12 and the floating diffusion FD of the other sensor pixel 12, and it is preferable that the relationship between t1 and t2 satisfies t2 > t1 > t2 / 3.5.

[0110] By doing so, the electric field line density between two through-wirings 54 that are connected to different readout circuits 22 and adjacent to each other can be reduced. As a result, signal crosstalk between adjacent sensor pixels 12 can be suppressed, and image quality degradation due to resolution reduction and color mixing on the reproduced image can be suppressed.

[0111] In the interlayer insulating film 51 shown in Figure 44, the insulating layer 53 may be formed of a material with a relative permittivity smaller than that of the insulating layers 46 and 52. In this case, the insulating layer 53 may be formed of, for example, SiOC (relative permittivity of about 2.9), and the insulating layers 46 and 52 may be formed of SiO2 (relative permittivity of about 4.1). Furthermore, in the interlayer insulating film 51 shown in Figure 44, the insulating layers 53 and 52 may be formed of materials with a relative permittivity smaller than that of the insulating layer 46. In this case, the insulating layers 53 and 52 may be formed of, for example, SiOC (relative permittivity of about 2.9), and the insulating layer 46 may be formed of SiO2 (relative permittivity of about 4.1). Furthermore, in the interlayer insulating film 51 shown in Figure 44, the insulating layers 46 and 53 may be formed of materials with a relative permittivity smaller than that of the insulating layer 52. In this case, insulating layers 46 and 53 may be formed of, for example, SiOC (relative permittivity of about 2.9), and insulating layer 52 may be formed of SiO2 (relative permittivity of about 4.1). Also, in the interlayer insulating film 51 shown in Figure 44, insulating layer 46 may be formed of a material with a relative permittivity lower than that of insulating layers 52 and 53. In this case, insulating layer 46 may be formed of, for example, SiOC (relative permittivity of about 2.9), and insulating layers 52 and 53 may be formed of SiO2 (relative permittivity of about 4.1). Also, in the interlayer insulating film 51 shown in Figure 44, insulating layers 46, 52, and 53 may be formed of materials with low relative permittivity. In this case, insulating layers 46, 52, and 53 may be formed of, for example, SiOC (relative permittivity of about 2.9). Furthermore, in the interlayer insulating film 51 shown in Figure 44, the insulating layer 52 may be formed of a material with a relative permittivity smaller than that of the insulating layers 46 and 53. In this case, the insulating layer 52 may be formed of, for example, SiOC (relative permittivity of about 2.9), and the insulating layers 46 and 53 may be formed of SiO2 (relative permittivity of about 4.1).

[0112] In this configuration, capacitance between two through-wirings 54 that are connected to different readout circuits 22 and adjacent to each other can be reduced. As a result, signal crosstalk between adjacent sensor pixels 12 can be suppressed, thereby reducing resolution and image quality degradation due to color mixing in the reproduced image.

[0113] In this modified example, the insulating layer 53 provided to cover the side surface of the through-wiring 54 may be made of a material with a relative permittivity smaller than that of the insulating layers 46 and 52. The insulating layers 46 and 52 are formed of, for example, SiO2 (relative permittivity of about 4.1). The insulating layers 46 and 52 may be formed of a silicon oxide film including, for example, TEOS (Tetraethylorthosilicate), NSG, HDP (High Density Plasma), BSG (Boro Silicate Glass), PSG (Phospho Silicate Glass), BPSG (Boro Phospho Silicate Glass), etc. The insulating layer 53 is formed of, for example, SiOC (relative permittivity of about 2.9). In this case, the capacitance between two through-wirings 54 that are connected to different readout circuits 22 and adjacent to each other can be reduced. As a result, the conversion efficiency can be improved.

[0114] In this modified example, the insulating layer 46 may be composed of a laminate of at least two insulating layers. The insulating layer 46 may be composed of, for example, an insulating layer 46A in contact with the semiconductor substrate 11 and an insulating layer 46B in contact with both the insulating layer 46A and the semiconductor substrate 21, as shown in Figure 45. Here, the insulating layer 46A is the uppermost layer of the insulating layer 46 and is composed of, for example, a material with a relative permittivity greater than that of other parts of the interlayer insulating film 51. In this case, the insulating layer 46A may be formed of, for example, SiN (relative permittivity of about 7.0). The insulating layers 46B and 52 may be formed of, for example, SiO2 (relative permittivity of about 4.1). The insulating layers 46B and 52 may be formed of, for example, silicon oxide films including TEOS, NSG, HDP, BSG, PSG, BPSG, etc. The insulating layer 53 may be formed of, for example, SiOC (relative permittivity of about 2.9).

[0115] Furthermore, in the interlayer insulating film 51 shown in Figure 45, the insulating layer 53 may be formed of, for example, SiOC (relative permittivity of about 2.9), and the insulating layers 46B and 52 may be formed of SiO2 (relative permittivity of about 4.1). Furthermore, in the interlayer insulating film 51 shown in Figure 45, the insulating layers 53 and 52 may be formed of, for example, SiOC (relative permittivity of about 2.9), and the insulating layer 46B may be formed of SiO2 (relative permittivity of about 4.1). Furthermore, in the interlayer insulating film 51 shown in Figure 45, the insulating layers 46B and 53 may be formed of materials with a relative permittivity smaller than that of the insulating layer 52. In this case, the insulating layers 46B and 53 may be formed of, for example, SiOC (relative permittivity of about 2.9), and the insulating layer 52 may be formed of SiO2 (relative permittivity of about 4.1). Furthermore, in the interlayer insulating film 51 shown in Figure 45, the insulating layer 46B may be formed of a material with a relative permittivity smaller than that of the insulating layers 52 and 53. In this case, the insulating layer 46B may be formed of, for example, SiOC (relative permittivity of about 2.9), and the insulating layers 52 and 53 may be formed of SiO2 (relative permittivity of about 4.1). Furthermore, in the interlayer insulating film 51 shown in Figure 45, the insulating layers 46B, 52, and 53 may be formed of materials with low relative permittivity. In this case, the insulating layers 46B, 52, and 53 may be formed of, for example, SiOC (relative permittivity of about 2.9).

[0116] In this configuration, capacitance between two through-wirings 54 that are connected to different readout circuits 22 and adjacent to each other can be reduced. As a result, signal crosstalk between adjacent sensor pixels 12 can be suppressed, thereby reducing resolution and image quality degradation due to color mixing in the reproduced image.

[0117] In some cases, the insulating layers 46B, 52, and 53 may be formed from a common material. In this case, the insulating layers 46B, 52, and 53 may be formed from, for example, SiO2 (with a relative permittivity of about 4.1).

[0118] [Differentiation M] Figures 46 and 47 show a modified example of the sensor pixel 12 and readout circuit 22 in the image sensor 1 according to the above embodiment and its modified examples. Figure 46 shows a modified example of the sensor pixel 12 and readout circuit 22 described in Figure 2. Figure 47 shows a modified example of the sensor pixel 12 and readout circuit 22 described in Figure 3. In this modified example, the second substrate 20 has a readout circuit 22 for every two sensor pixels 12. Even with this configuration, the image sensor 1 has the effects described in the above embodiment and its modified examples.

[0119] [Differentiation N] Figures 48 and 49 show a modified example of the sensor pixel 12 and readout circuit 22 in the image sensor 1 according to the above embodiment and its modified examples. Figure 48 shows a modified example of the sensor pixel 12 and readout circuit 22 described in Figure 2. Figure 49 shows a modified example of the sensor pixel 12 and readout circuit 22 described in Figure 3. In this modified example, the second substrate 20 has a readout circuit 22 for each sensor pixel 12. Even with this configuration, the image sensor 1 has the effects described in the above embodiment and its modified examples.

[0120] In addition, in the image sensor 1 according to the above embodiment and its modified form, the second substrate 20 may have a readout circuit 22 for every three sensor pixels 12. Furthermore, in the image sensor 1 according to the above embodiment and its modified form, the second substrate 20 may have a readout circuit 22 for every eight sensor pixels 12. Furthermore, in the image sensor 1 according to the above embodiment and its modified form, the second substrate 20 may have a readout circuit 22 for every five or more sensor pixels 12. Even with these configurations, the image sensor 1 will have the effects described in the above embodiment and its modified form.

[0121] [Modification O] Figure 50 shows an example of a cross-sectional configuration of a part of the image sensor 1 according to the above embodiment and its modified form. In this modified form, the transistors in the first substrate 10 (e.g., transfer transistors TR) and the transistors in the second substrate 20 (e.g., amplification transistors AMP) are formed under different design conditions. Specifically, the thickness of the gate insulating film 81 of the transistor in the first substrate 10 and the thickness of the gate insulating film 83 of the transistor in the second substrate 20 are different. Also, the sidewall width of the transistor in the first substrate 10 and the sidewall width of the transistor in the second substrate 20 are different. Furthermore, the source / drain concentration (e.g., floating diffusion FD concentration) of the transistor in the first substrate 10 and the source / drain concentration of the transistor in the second substrate 20 are different. Also, the thickness of the layer 82 covering the transistor in the first substrate 10 and the thickness of the layer 84 covering the transistor in the second substrate 20 are different.

[0122] In other words, in this modified example, the design conditions for the transistors in the sensor pixel 12 and the transistors in the readout circuit 22 can be made different from each other. This makes it possible to set design conditions suitable for the transistors in the sensor pixel 12, and further, to set design conditions suitable for the transistors in the readout circuit 22.

[0123] [Modified Version P] Figures 51 and 52 show a modified example of the horizontal cross-sectional configuration of the image sensor 1 according to the above modification I. Figure 51 shows a modified example of the cross-sectional configuration of Figure 33. Figure 52 shows a modified example of the cross-sectional configuration of Figure 34.

[0124] In this modified example, the gate wiring 49 is omitted, and multiple through-wirings 48 are provided, one for each transfer gate TG. Each through-wiring 48 is electrically connected to the corresponding transfer gate TG and also electrically connected to the pixel drive line 23. As shown in Figures 51 and 52, the multiple through-wirings 54, 48, and 47 are arranged in a strip in the first direction V (left-right direction in Figures 51 and 52). The multiple through-wirings 54 and 47 are arranged in a single row in the first direction V (left-right direction in Figures 51 and 52), and the multiple through-wirings 48 are arranged in two rows in the first direction V (left-right direction in Figures 51 and 52).

[0125] Figure 53 shows an example of the vertical cross-sectional configuration of the image sensor 1 according to this modified example. In this modified example, one connection wiring 76 is provided for each of the four floating diffusion FDs that share the readout circuit 22. In modified example I shown in Figure 32, as an example of the embodiment, the portion of the connection wiring 72 that extends horizontally across the substrate was formed above the transfer gate TG (closer to the second substrate 20). When forming this structure, for example, a manufacturing method can be adopted in which an insulating film reaching the height of the transfer gate TG is formed after the transfer gate TG is formed, and then the connection wiring 72 is formed. On the other hand, in modified example P shown in Figure 53, as an example of the embodiment, the lower surface (the surface on the first substrate 10 side) of the portion of the connection wiring 76 that extends horizontally across the substrate is formed below (closer to the first substrate 10 side) the upper surface (the surface on the second substrate 20 side) of the transfer gate TG. As an example, the portion of the connection wiring 76 that extends horizontally across the substrate may be formed on the gate insulating film of the transistor of the readout circuit 22. Alternatively, an insulating film with a thickness less than the height of the transfer gate TG may be formed on the top and side surfaces of the transfer gate TG and on the top surface of the first substrate 10 where the transfer gate TG is not placed, and the portion of the connecting wiring 76 that extends horizontally across the substrate may be placed on top of it.

[0126] The connecting wire 76 is connected to the four floating diffusion FDs via an opening in the gate insulating film of the transistors of the read circuit 22 (e.g., the gate insulating film 75 of the transfer transistor TR) or an insulating film with a thickness less than the height of the transfer gate TG. The connecting wire 76 is formed in contact with the surface of the gate insulating film of the transistors of the read circuit 22 (e.g., the gate insulating film 75 of the transfer transistor TR). It is preferable to use a heat-resistant material for the electrode material used in the connecting wire 76. Examples of heat-resistant materials include polysilicon. The connecting wire 76 may be made of a metal such as tungsten or copper.

[0127] In this modified example, the provision of connecting wiring 76 reduces the area occupied by the insulating layer 53 through which the through-wiring 54 passes. As a result, the area of ​​the semiconductor substrate 21 (block 21A) can be increased by the amount by which the area occupied by the insulating layer 53 is reduced, and thus the area of ​​the readout circuit 22 (especially the amplification transistor AMP) can be enlarged. Consequently, random noise can be improved.

[0128] Comparing the length a of the connection portion 71 shown in Figure 32 in the direction perpendicular to the substrate with the length b of the connection wiring 76 shown in Figure 53 in the direction perpendicular to the substrate up to the common wiring, b is shorter than a. Similarly, comparing the length c of the connection portion 73 shown in Figure 35 of Modification I in the direction perpendicular to the substrate with the length d of the connection wiring 77 shown in Figure 54, which will be described later in Modification P, d is shorter than c. Furthermore, comparing the thickness e of the portion of the connection wiring 76 and 77 that extends horizontally to the substrate (the height of the common wiring in the direction perpendicular to the substrate) with the thickness f (=b) of the portion that extends vertically to the substrate, f is smaller than e.

[0129] Here, we consider a case where ion implantation is used in a manufacturing method for doping the connecting wiring 76 connected to the floating diffusion FD, which is an N-type impurity region, with N-type impurities, and a manufacturing method for doping the connecting wiring 77 connected to the p-well layer 42 with P-type impurities. If the length of the portion of the connecting wiring 76 and 77 that penetrates the insulating film and extends in the direction perpendicular to the substrate is long, it may be necessary to perform ion implantation separately on the portion of the connecting wiring 76 and 77 that extends horizontally to the substrate and on the portion of the connecting wiring 76 and 77 that extends vertically to the substrate, in order to dope the entire connecting wiring 76 and 77 with a sufficient concentration of impurities. On the other hand, if the length of the portion that penetrates the insulating film and extends vertically to the substrate is short, it may be possible to dope the portion that extends vertically to the substrate with a sufficient concentration of impurities by performing ion implantation on the portion that extends horizontally to the substrate. This may simplify the manufacturing method. Furthermore, it may be possible to uniformly dope the portion extending vertically to the substrate without any difference in impurity doping concentration in the vertical direction of the substrate. In addition, it may be possible to dope the portion extending vertically and the portion extending horizontally to the substrate to the same concentration.

[0130] Figure 54 shows an example of the vertical cross-sectional configuration of the image sensor 1 according to this modified example. In this modified example, one connecting wire 77 is provided for each well layer 42 of four adjacent sensor pixels 12. In the modified example P shown in Figure 54, as an example of the embodiment, the lower surface of the connecting wire 77 (the surface on the first substrate 10 side) is formed lower (closer to the first substrate 10) than the upper surface of the transfer gate TG (the surface on the second substrate 20 side) shown in Figure 53. As an example, the portion of the connecting wire 77 that extends horizontally across the substrate may be formed on the gate insulating film of the transistor of the readout circuit 22. Alternatively, an insulating film with a thickness less than the height of the transfer gate TG may be formed on the upper and side surfaces of the transfer gate TG and on the upper surface of the first substrate 10 where the transfer gate TG is not placed, and the portion of the connecting wire 77 that extends horizontally across the substrate may be placed on top of it.

[0131] The connecting wire 77 is connected to the four well layers 42 via an opening provided in the gate insulating film 75 of the transistor (e.g., transfer transistor TR) of the read circuit 22, or in an insulating film with a thickness less than the height of the transfer gate TG. The connecting wire 76 is formed in contact with the surface of the gate insulating film of the transistor (e.g., the gate insulating film 75 of the transfer transistor TR) of the read circuit 22. It is preferable to use a heat-resistant material as the electrode material for the connecting wire 77. Examples of heat-resistant materials include polysilicon. The connecting wire 77 is made of polysilicon doped with P-type impurities, for example. The connecting wire 77 may also be made of a metal such as tungsten or copper.

[0132] Comparing the connection portion 73 and connection wiring 74 shown in Figure 35 of Modification I with the connection wiring 77 shown in Figure 54 of Modification P, the length g of the portion of the connection wiring 77 that penetrates the insulating film and extends in a direction perpendicular to the substrates 10 and 20 is shorter than the length h of the portion of the connection portion 73 and connection wiring 74 that penetrates the insulating film and extends in a direction perpendicular to the substrates 10 and 20. Furthermore, comparing the thickness i (height in the vertical direction of the substrate) of the portion of the connection wiring 77 that extends in the horizontal direction of the substrate with the thickness g (height in the vertical direction of the substrate) of the portion that extends in the vertical direction of the substrate, g is smaller than i.

[0133] In this modified example, the provision of connecting wiring 77 reduces the area occupied by the insulating layer 53 through which the through-wiring 47 penetrates. As a result, the area of ​​the semiconductor substrate 21 (block 21A) can be increased by the amount by which the area occupied by the insulating layer 53 is reduced, and thus the area of ​​the readout circuit 22 (especially the amplification transistor AMP) can be enlarged. Consequently, random noise can be improved.

[0134] The thickness of the connecting wires 76 and 77 does not necessarily have to be the same as the thickness of the gate electrodes of the transistors in the readout circuit 22 (for example, the transfer gate TG of the transfer transistor TR). The thickness of the connecting wires 76 and 77 is, for example, thinner than the thickness of the gate electrodes of the transistors in the readout circuit 22 (for example, the transfer gate TG of the transfer transistor TR). In addition, the thickness of the connecting wires 76 and 77 may be the same as or thicker than the thickness of the gate electrodes of the transistors in the readout circuit 22 (for example, the transfer gate TG of the transfer transistor TR), as shown in Figures 55 and 56.

[0135] As the thickness of the connecting wires 76 and 77 is reduced to less than the thickness of the transfer gate TG, it may be possible to reduce the coupling capacitance between the connecting wire 76 connected to the floating diffusion FD and the transfer gate TG. This may allow for a larger signal voltage to be generated when a certain amount of charge is converted to voltage in the floating diffusion FD.

[0136] On the other hand, when impurity doping of connecting wires 76 and 77 is performed by ion implantation, the ion implantation range does not become a single range distance, but rather spreads in the range direction as a distribution of range distances called the projection range. Considering this spread of impurities in the range direction, when impurity doping of connecting wires 76 and 77 is performed by ion implantation, it is possible to control the impurity doping of connecting wires 76 and 77 with good control as the thickness of connecting wires 76 and 77 increases.

[0137] In this modified example, for example, as shown in Figures 57, 58, and 59, instead of providing one through-wiring 48 for each transfer gate TG, one through-wiring 48 may be provided for each of multiple transfer gates TG. In this case, connection parts 79 and connection wiring 78 may be provided to electrically connect each of the multiple transfer gates TG that share the through-wiring 48. One connection part 79 is provided for each transfer gate TG, and each connection part 79 is connected to the transfer gate TG and the connection wiring 78. One connection wiring 78 is provided for each of the multiple transfer gates TG that share the through-wiring 48. The connection parts 79 and connection wiring 78 are made of, for example, polysilicon doped with N-type impurities and are connected to the transfer gates TG. The connection parts 73 and connection wiring 74 are made of, for example, polysilicon doped with N-type impurities and are connected to the floating diffusion FD, which is the N-type impurity region.

[0138] In this way, when one through-wiring 48 is provided for each of the multiple transfer gates TG, the area occupied by the insulating layer 53 through which the through-wiring 48 penetrates can be reduced, for example, as shown in Figure 58. As a result, the area of ​​the semiconductor substrate 21 (block 21A) can be increased by the amount by which the area occupied by the insulating layer 53 is reduced, and thus the area of ​​the readout circuit 22 (especially the amplification transistor AMP) can be enlarged. Note that in Figure 59, the connection part 71 and the connection wiring 72 may be formed integrally. Furthermore, the through-wiring 48 may be formed on the first substrate 10, connected to the wiring formed on the insulating layer 46, and configured to receive the drive signal of the transfer gate.

[0139] Furthermore, in this modified example, the height j of the connection portion 71 is greater than the height k of the transfer gate TG. That is, an insulating film is formed above the upper surface of the transfer gate TG, and the connection wiring 72 is formed with the substrate surface flattened by this insulating film. This makes it easier to process the connection wiring 72.

[0140] Furthermore, in this modified example, as shown in Figures 60, 61, and 62, for example, instead of a set of connection parts 73, connection wiring 74, and through wiring 47, a through wiring 80 spanning four adjacent sensor pixels 12 may be provided. The through wiring 80 is formed by penetrating the insulating layer 53 and is electrically connected to the well layer 42 of the four adjacent sensor pixels 12 and the power line VSS. Although not shown, a configuration in which polysilicon is doped to the pwell can be used for contact with the pwell, similar to the configurations in Figures 54 and 56.

[0141] In this modified example, when through-wiring 80 is provided, the area occupied by the insulating layer 53 through which the through-wiring 80 penetrates can be reduced. As a result, the area of ​​the semiconductor substrate 21 (block 21A) can be increased by the amount by which the area occupied by the insulating layer 53 is reduced, and thus the area of ​​the readout circuit 22 (especially the amplification transistor AMP) can be increased. Consequently, random noise can be improved.

[0142] Furthermore, in this modified example, in addition to providing through-wiring 80, connecting wiring 76 may also be provided, for example, as shown in Figure 63. In this case, the area occupied by the insulating layer 53 through which the through-wiring 54 and 80 pass can be reduced. As a result, the area of ​​the semiconductor substrate 21 (block 21A) can be increased by the amount by which the area occupied by the insulating layer 53 has been reduced, and the area of ​​the readout circuit 22 (especially the amplification transistor AMP) can be increased. As a result, random noise can be improved.

[0143] [Differentiation Example Q] Figure 64 shows an example of the circuit configuration of the image sensor 1 according to the above embodiment and its modified form. The image sensor 1 according to this modified form is a CMOS image sensor equipped with a column-parallel ADC.

[0144] As shown in Figure 64, the image sensor 1 according to this modified example has a pixel region 13 in which a plurality of sensor pixels 12 including photoelectric conversion elements are arranged in a matrix in two dimensions, as well as a vertical drive circuit 33, a column signal processing circuit 34, a reference voltage supply unit 38, a horizontal drive circuit 35, a horizontal output line 37, and a system control circuit 36.

[0145] In this system configuration, the system control circuit 36 ​​generates clock signals and control signals that serve as a reference for the operation of the vertical drive circuit 33, column signal processing circuit 34, reference voltage supply unit 38, and horizontal drive circuit 35, etc., based on the master clock MCK, and provides them to the vertical drive circuit 33, column signal processing circuit 34, reference voltage supply unit 38, and horizontal drive circuit 35, etc.

[0146] Furthermore, the vertical drive circuit 33 is formed on the first substrate 10 together with each sensor pixel 12 of the pixel region 13, and is also formed on the second substrate 20 on which the readout circuit 22 is formed. The column signal processing circuit 34, reference voltage supply unit 38, horizontal drive circuit 35, horizontal output line 37, and system control circuit 36 ​​are formed on the third substrate 30.

[0147] As the sensor pixel 12, although not shown in the diagram here, for example, a configuration can be used that includes a photodiode PD and a transfer transistor TR that transfers the charge obtained by photoelectric conversion in the photodiode PD to the floating diffusion FD. Also, as the readout circuit 22, although not shown in the diagram here, for example, a three-transistor configuration can be used that includes a reset transistor RST that controls the potential of the floating diffusion FD, an amplification transistor AMP that outputs a signal corresponding to the potential of the floating diffusion FD, and a selection transistor SEL for pixel selection.

[0148] In the pixel region 13, sensor pixels 12 are arranged in two dimensions, and pixel drive lines 23 are wired for each row and vertical signal lines 24 are wired for each column of this m x n pixel arrangement. One end of each of the multiple pixel drive lines 23 is connected to the output terminals of the vertical drive circuit 33 corresponding to each row. The vertical drive circuit 33 is composed of a shift register and the like, and controls the row address and row scanning of the pixel region 13 via the multiple pixel drive lines 23.

[0149] The column signal processing circuit 34 has, for example, ADCs (analog-to-digital converters) 34-1 to 34-m provided for each pixel row of the pixel region 13, i.e., for each vertical signal line 24, and converts the analog signals output from each sensor pixel 12 of the pixel region 13 for each row into digital signals and outputs them.

[0150] The reference voltage supply unit 38 includes, for example, a DAC (digital-to-analog converter) 38A as a means for generating a reference voltage Vref of a so-called ramp waveform, whose level changes in a sloping manner as time progresses. However, the means for generating the reference voltage Vref of a ramp waveform is not limited to the DAC 38A.

[0151] Under the control of the control signal CS1 provided by the system control circuit 36, DAC38A generates a reference voltage Vref of the ramp waveform based on the clock CK provided by the system control circuit 36 ​​and supplies it to the ADC34-1~34-m of the column processing unit 15.

[0152] Each of the ADCs 34-1 to 34-m is configured to selectively perform AD conversion operations corresponding to two operating modes: a normal frame rate mode using a progressive scanning method that reads information from all sensor pixels 12, and a high-speed frame rate mode that increases the frame rate by N times, for example, 2 times, by setting the exposure time of the sensor pixels 12 to 1 / N compared to the normal frame rate mode. This switching of operating modes is performed by control signals CS2 and CS3 provided by the system control circuit 36. Furthermore, the system control circuit 36 ​​is provided with instruction information from an external system controller (not shown) to switch between the normal frame rate mode and the high-speed frame rate mode.

[0153] All ADC34-1 to 34-m have the same configuration, and here we will use ADC34-m as an example for explanation. ADC34-m consists of a comparator 34A, a counting means such as an up / down counter (labeled U / DCNT in the figure) 34B, a transfer switch 34C, and a memory device 34D.

[0154] The comparator 34A compares the signal voltage Vx of the vertical signal line 24 corresponding to the signal output from each sensor pixel 12 in the nth column of the pixel area 13 with the reference voltage Vref of the ramp waveform supplied by the reference voltage supply unit 38. For example, when the reference voltage Vref is greater than the signal voltage Vx, the output Vco becomes "H" level, and when the reference voltage Vref is less than or equal to the signal voltage Vx, the output Vco becomes "L" level.

[0155] The up / down counter 34B is an asynchronous counter. Under the control of the control signal CS2 provided by the system control circuit 36, the system control circuit 36 ​​simultaneously provides a clock CK to the DAC 18A. By performing down (DOWN) counting or up (UP) counting in synchronization with the clock CK, the counter measures the comparison period from the start to the end of the comparison operation in the comparator 34A.

[0156] Specifically, in normal frame rate mode, during the signal readout operation from one sensor pixel 12, the comparison time for the first readout is measured by downcounting during the first readout operation, and the comparison time for the second readout is measured by upcounting during the second readout operation.

[0157] On the other hand, in high-speed frame rate mode, the count result for a given row of sensor pixels 12 is retained, and then, for the next row of sensor pixels 12, a downcount is performed during the first read operation based on the previous count result to measure the comparison time for the first read operation, and an upcount is performed during the second read operation to measure the comparison time for the second read operation.

[0158] Under the control of the control signal CS3 provided by the system control circuit 36, the transfer switch 34C is turned ON (closed) in the normal frame rate mode when the counting operation of the up / down counter 34B for a certain row of sensor pixels 12 is completed, and the count result of the up / down counter 34B is transferred to the memory device 34D.

[0159] On the other hand, at a high frame rate of, for example, N=2, the up / down counter 34B remains in the off (open) state when the counting operation of the sensor pixel 12 in a given row is completed, and then turns on when the counting operation of the up / down counter 34B for the next row of sensor pixel 12 is completed, transferring the counting result for the vertical 2 pixels of the up / down counter 34B to the memory device 34D.

[0160] In this way, the analog signals supplied row by row from each sensor pixel 12 in the pixel region 13 via the vertical signal line 24 are converted into N-bit digital signals by the operation of the comparator 34A and up / down counter 34B in the ADCs 34-1 to 34-m and stored in the memory device 34D.

[0161] The horizontal drive circuit 35 is composed of a shift register and other components, and controls the column address and column scanning of the ADCs 34-1 to 34-m in the column signal processing circuit 34. Under the control of this horizontal drive circuit 35, the N-bit digital signals converted by each of the ADCs 34-1 to 34-m are sequentially read out to the horizontal output line 37 and output as imaging data via the horizontal output line 37.

[0162] Although not specifically illustrated as it is not directly related to this disclosure, it is also possible to provide circuits and the like for performing various signal processing on the imaging data output via the horizontal output line 37, in addition to the above-mentioned components.

[0163] In the image sensor 1 equipped with a column-parallel ADC according to this modified configuration described above, the count result of the up / down counter 34B can be selectively transferred to the memory device 34D via the transfer switch 34C. Therefore, the counting operation of the up / down counter 34B and the reading operation of the count result of the up / down counter 34B to the horizontal output line 37 can be controlled independently.

[0164] [Modification R] Figure 65 shows an example in which the image sensor 1 of Figure 64 is constructed by stacking three substrates (first substrate 10, second substrate 20, and third substrate 30). In this modified example, on the first substrate 10, a pixel region 13 containing multiple sensor pixels 12 is formed in the central part, and a vertical drive circuit 33 is formed around the pixel region 13. On the second substrate 20, a readout circuit region 15 containing multiple readout circuits 22 is formed in the central part, and a vertical drive circuit 33 is formed around the readout circuit region 15. On the third substrate 30, a column signal processing circuit 34, a horizontal drive circuit 35, a system control circuit 36, a horizontal output line 37, and a reference voltage supply unit 38 are formed. As a result, similar to the above embodiment and its modified examples, the structure that electrically connects the substrates does not increase the chip size or hinder the miniaturization of the area per pixel. As a result, it is possible to provide a three-layer image sensor 1 with the same chip size as before, without hindering the miniaturization of the area per pixel. The vertical drive circuit 33 may be formed only on the first substrate 10 or only on the second substrate 20.

[0165] [Differentiation S] Figure 66 shows a modified cross-sectional configuration of the image sensor 1 according to the above embodiment and its modified form. In the above embodiment and its modified form, the image sensor 1 was constructed by stacking three substrates (first substrate 10, second substrate 20, third substrate 30). However, in the above embodiment and its modified form, the image sensor 1 may be constructed by stacking two substrates (first substrate 10, second substrate 20). In this case, the logic circuit 32 is formed separately on the first substrate 10 and the second substrate 20, for example, as shown in Figure 66. Here, in the logic circuit 32, circuit 32A provided on the first substrate 10 side is provided with a transistor having a gate structure in which a high dielectric constant film made of a material that can withstand high-temperature processes (e.g., high-k) and a metal gate electrode are stacked. On the other hand, in circuit 32B provided on the second substrate 20 side, a low-resistance region 26 is formed on the surface of the impurity diffusion region that is in contact with the source electrode and drain electrode, consisting of silicide formed using a salicide (Self-Aligned Silicide) process such as CoSi2 or NiSi. The low-resistance region, made of silicide, is formed from a compound of the semiconductor substrate material and a metal. This allows for the use of high-temperature processes such as thermal oxidation when forming the sensor pixels 12. Furthermore, in the logic circuit 32B located on the second substrate 20 side, if a low-resistance region 26 made of silicide is provided on the surface of the impurity diffusion region that contacts the source electrode and drain electrode, contact resistance can be reduced. As a result, the calculation speed in the logic circuit 32 can be increased.

[0166] Figure 67 shows a modified cross-sectional configuration of the image sensor 1 according to the above embodiment and its modified form. In the logic circuit 32 of the third substrate 30 according to the above embodiment and its modified form, a low-resistance region 37 made of silicide formed using a salicide (Self-Aligned Silicide) process such as CoSi2 or NiSi may be formed on the surface of the impurity diffusion region that is in contact with the source electrode and the drain electrode. This allows the use of high-temperature processes such as thermal oxidation when forming the sensor pixels 12. Furthermore, if a low-resistance region 37 made of silicide is provided on the surface of the impurity diffusion region that is in contact with the source electrode and the drain electrode in the logic circuit 32, the contact resistance can be reduced. As a result, the calculation speed in the logic circuit 32 can be increased.

[0167] [Modified version T] In the above embodiment and its modified form, the conductivity type may be reversed. For example, in the description of the above embodiment and its modified form, p-type may be read as n-type, and n-type as p-type. Even in this case, the same effects as in the above embodiment and its modified form can be obtained.

[0168] Furthermore, this disclosure can be applied not only to visible light receiving elements, but also to elements capable of detecting various types of radiation, such as infrared, ultraviolet, X-rays, and electromagnetic waves. In terms of applications, it can be used for a variety of purposes, including not only image output, but also distance measurement, detection of changes in light intensity, and detection of physical properties.

[0169] <3. Application Examples> Figure 68 shows an example of the schematic configuration of an imaging device 2 equipped with an image sensor 1 (hereinafter simply referred to as "image sensor 1") according to the above embodiment and its modified form.

[0170] The imaging device 2 is, for example, an imaging device such as a digital still camera or a video camera, or an electronic device such as a mobile terminal device such as a smartphone or a tablet. The imaging device 2 includes, for example, an image sensor 1, an optical system 141, a shutter device 142, a control circuit 143, a DSP circuit 144, a frame memory 145, a display unit 146, a storage unit 147, an operation unit 148, and a power supply unit 149. In the imaging device 2, the image sensor 1, the shutter device 142, the control circuit 143, the DSP circuit 144, the frame memory 145, the display unit 146, the storage unit 147, the operation unit 148, and the power supply unit 149 are interconnected via a bus line 150.

[0171] The image sensor 1 outputs image data corresponding to the incident light. The optical system 141 is composed of one or more lenses and guides light from the subject (incident light) to the image sensor 1, forming an image on the light-receiving surface of the image sensor 1. The shutter device 142 is positioned between the optical system 141 and the image sensor 1 and controls the light illumination period and light shielding period to the image sensor 1 according to the control circuit 143. The image sensor 1 accumulates signal charge for a certain period of time according to the light formed on the light-receiving surface via the optical system 141 and the shutter device 142. The signal charge accumulated in the image sensor 1 is transferred as image data according to the drive signal (timing signal) supplied from the control circuit 143. The control circuit 143 drives the image sensor 1 and the shutter device 142 by outputting drive signals that control the transfer operation of the image sensor 1 and the shutter operation of the shutter device 142.

[0172] The DSP circuit 144 is a signal processing circuit that processes the signals (image data) output from the image sensor 1. The frame memory 145 temporarily holds the image data processed by the DSP circuit 144 in frame units. The display unit 146 consists of a panel-type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and displays the video or still images captured by the image sensor 1. The storage unit 147 records the image data of the video or still images captured by the image sensor 1 onto a recording medium such as a semiconductor memory or a hard disk. The operation unit 148 issues operation commands for various functions of the imaging device 2 according to user operations. The power supply unit 149 appropriately supplies various power supplies to the image sensor 1, shutter device 142, control circuit 143, DSP circuit 144, frame memory 145, display unit 146, storage unit 147, and operation unit 148, which serve as power sources for these devices.

[0173] The image sensor of this disclosure is also applicable to the image sensor of an imaging module equipped with a lens, an IRCF (Infrared Cut Filter), etc., as described in the prior art of Japanese Patent Application Publication No. 2015-99262, or as described in this disclosure. An imaging module using this image sensor is also applicable to imaging device 2.

[0174] Next, the imaging procedure in imaging device 2 will be described.

[0175] Figure 69 shows an example flowchart of the imaging operation in the imaging device 2. The user instructs the start of imaging by operating the operation unit 148 (step S101). The operation unit 148 then transmits the imaging command to the control circuit 143 (step S102). Upon receiving the imaging command, the control circuit 143 starts controlling the shutter device 142 and the image sensor 1. The image sensor 1 (specifically the system control circuit 32d) performs imaging in a predetermined imaging method under the control of the control circuit 143 (step S103). The shutter device 142 controls the light irradiation period and the light shielding period for the image sensor 1 under the control of the control circuit 143.

[0176] The image sensor 1 outputs the image data obtained by imaging to the DSP circuit 144. Here, the image data is the data for all pixels of the pixel signal generated based on the charge temporarily held in the floating diffusion FD. The DSP circuit 144 performs predetermined signal processing (for example, noise reduction processing) based on the image data input from the image sensor 1 (step S104). The DSP circuit 144 stores the image data that has undergone predetermined signal processing in the frame memory 145, and the frame memory 145 stores the image data in the storage unit 147 (step S105). In this way, imaging is performed in the imaging device 2.

[0177] In this application example, the image sensor 1 according to the above embodiment and its modified form is applied to the imaging device 2. This makes it possible to miniaturize or increase the resolution of the image sensor 1, thereby providing a compact or high-resolution imaging device 2.

[0178] <4. Application Examples> [Application Example 1] The technology disclosed herein (the Technology) can be applied to a variety of products. For example, the Technology disclosed herein may be implemented as a device mounted on any type of mobile vehicle, such as an automobile, electric vehicle, hybrid electric vehicle, motorcycle, bicycle, personal mobility device, airplane, drone, ship, or robot.

[0179] Figure 70 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology described herein may be applied.

[0180] The vehicle control system 12000 comprises multiple electronic control units connected via a communication network 12001. In the example shown in Figure 70, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 is also shown, consisting of a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface 12053.

[0181] The drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 12010 functions as a control device for a drivetrain generating device that generates driving force for the vehicle, such as an internal combustion engine or a drive motor; a drivetrain transmission mechanism that transmits driving force to the wheels; a steering mechanism that adjusts the steering angle of the vehicle; and a braking device that generates braking force for the vehicle.

[0182] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 12020 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc.

[0183] The external information detection unit 12030 detects information from outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the external information detection unit 12030. The external information detection unit 12030 causes the imaging unit 12031 to capture images of the outside of the vehicle and receives the captured images. Based on the received images, the external information detection unit 12030 may perform object detection processing such as detecting people, cars, obstacles, signs, or characters on the road surface, or distance detection processing.

[0184] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0185] The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver status detection unit 12041 that detects the driver's state. The driver status detection unit 12041 includes, for example, a camera that images the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration, or determine whether the driver is drowsy, based on the detection information input from the driver status detection unit 12041.

[0186] The microcomputer 12051 can calculate control target values ​​for the drive force generator, steering mechanism, or braking system based on information from inside and outside the vehicle acquired by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including collision avoidance or impact mitigation, following based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

[0187] Furthermore, the microcomputer 12051 can perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on information about the vehicle's surroundings acquired by the external information detection unit 12030 or the internal information detection unit 12040.

[0188] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on external information acquired by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of a preceding or oncoming vehicle detected by the external information detection unit 12030, and perform coordinated control aimed at reducing glare, such as switching from high beams to low beams.

[0189] The audio-image output unit 12052 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying information to the vehicle's occupants or to those outside the vehicle. In the example shown in Figure 70, the output devices include an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

[0190] Figure 71 shows an example of the installation position of the imaging unit 12031.

[0191] In Figure 71, the vehicle 12100 has imaging units 12101, 12102, 12103, 12104, and 12105 as the imaging unit 12031.

[0192] The imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle 12100. The imaging unit 12101 installed on the front nose and the imaging unit 12105 installed on the upper part of the windshield inside the vehicle mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 installed on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The forward images acquired by imaging units 12101 and 12105 are mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0193] Figure 71 shows an example of the imaging range of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 located on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 12101 to 12104, an overhead view image of the vehicle 12100 can be obtained.

[0194] At least one of the imaging units 12101 to 12104 may have a function for acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple image sensors, or an image sensor having pixels for phase difference detection.

[0195] For example, the microcomputer 12051, based on distance information obtained from imaging units 12101 to 12104, can determine the distance to each object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed to vehicle 12100). In particular, it can extract the nearest object on the vehicle 12100's path that is traveling in approximately the same direction as vehicle 12100 at a predetermined speed (e.g., 0 km / h or more) as the preceding vehicle. Furthermore, the microcomputer 12051 can set a predetermined distance to be maintained before the preceding vehicle and perform automatic braking control (including follow-and-stop control) and automatic acceleration control (including follow-and-start control), etc. In this way, cooperative control aimed at autonomous driving, where the vehicle drives autonomously without driver intervention, can be performed.

[0196] For example, the microcomputer 12051 can use distance information obtained from imaging units 12101 to 12104 to classify and extract three-dimensional object data related to three-dimensional objects, such as motorcycles, passenger cars, heavy vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle. If the collision risk is above a set value and there is a possibility of collision, the microcomputer 12051 can provide driving assistance to avoid collisions by outputting a warning to the driver via the audio speaker 12061 or display unit 12062, or by performing forced deceleration or evasive steering via the drive system control unit 12010.

[0197] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not pedestrians are present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, by a procedure to extract feature points from the images captured by the imaging units 12101 to 12104 as infrared cameras, and a procedure to perform pattern matching on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes a pedestrian, the audio-image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio-image output unit 12052 may also control the display unit 12062 to display an icon indicating a pedestrian at a desired position.

[0198] The above describes an example of a mobile object control system to which the technology of this disclosure may be applied. The technology of this disclosure can be applied to the imaging unit 12031 of the configuration described above. Specifically, the image sensor 1 according to the above embodiment and its modified form can be applied to the imaging unit 12031. By applying the technology of this disclosure to the imaging unit 12031, high-definition captured images with low noise can be obtained, so that high-precision control using captured images can be performed in the mobile object control system.

[0199] [Application Example 2] Figure 72 is a diagram showing an example of a schematic configuration of an endoscopic surgical system to which the technology described herein (the technology) may be applied.

[0200] Figure 72 illustrates a surgeon (physician) 11131 performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgical system 11000. As shown in the figure, the endoscopic surgical system 11000 consists of an endoscope 11100, other surgical instruments 11110 such as an insufflation tube 11111 and an energy treatment device 11112, a support arm device 11120 for supporting the endoscope 11100, and a cart 11200 equipped with various devices for endoscopic surgery.

[0201] The endoscope 11100 consists of a barrel 11101, the tip of which is inserted into the body cavity of the patient 11132 for a predetermined length, and a camera head 11102 connected to the base end of the barrel 11101. In the illustrated example, the endoscope 11100 is shown as a so-called rigid endoscope having a rigid barrel 11101, but the endoscope 11100 may also be configured as a so-called flexible endoscope having a flexible barrel.

[0202] An opening into which an objective lens is fitted is provided at the tip of the endoscope tube 11101. A light source device 11203 is connected to the endoscope 11100, and the light generated by the light source device 11203 is guided to the tip of the endoscope tube by a light guide extending inside the endoscope tube 11101, and is irradiated through the objective lens towards the object to be observed inside the body cavity of the patient 11132. The endoscope 11100 may be a straight-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0203] The camera head 11102 contains an optical system and an image sensor. Reflected light from the object being observed (observation light) is focused onto the image sensor by the optical system. The image sensor converts the observation light into electrical signals, generating an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. This image signal is transmitted as RAW data to the camera control unit (CCU) 11201.

[0204] The CCU11201 consists of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), and other components, and comprehensively controls the operation of the endoscope 11100 and the display device 11202. Furthermore, the CCU11201 receives image signals from the camera head 11102 and performs various image processing operations on these image signals, such as development processing (demosaic processing), to display the image based on those image signals.

[0205] The display device 11202 displays an image based on an image signal that has been processed by the CCU 11201, under control from the CCU 11201.

[0206] The light source device 11203 consists of a light source such as an LED (Light Emitting Diode) and supplies illumination light to the endoscope 11100 when photographing the surgical area, etc.

[0207] The input device 11204 is an input interface for the endoscopic surgical system 11000. The user can input various information and instructions to the endoscopic surgical system 11000 via the input device 11204. For example, the user can input instructions to change the imaging conditions (type of light, magnification, focal length, etc.) of the endoscope 11100.

[0208] The treatment instrument control device 11205 controls the drive of the energy treatment instrument 11112 for purposes such as tissue cauterization, incision, or vascular sealing. The insufflation device 11206 delivers gas into the patient's body cavity via the insufflation tube 11111 to inflate the body cavity of the patient 11132 for the purpose of securing a field of view by the endoscope 11100 and securing the operator's working space. The recorder 11207 is a device capable of recording various information related to the surgery. The printer 11208 is a device capable of printing various information related to the surgery in various formats such as text, images, or graphs.

[0209] The light source device 11203, which supplies illumination light to the endoscope 11100 when photographing the surgical area, can be configured as a white light source consisting of, for example, an LED, a laser light source, or a combination thereof. When the white light source is configured as a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, so the white balance of the captured image can be adjusted in the light source device 11203. In this case, it is also possible to time-divisionally capture images corresponding to each of the RGB light sources by irradiating the observation target with laser light from each RGB laser light source and controlling the drive of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, a color image can be obtained without providing a color filter on the image sensor.

[0210] Furthermore, the light source device 11203 may be controlled to change the intensity of the light it outputs at predetermined time intervals. By controlling the drive of the image sensor of the camera head 11102 in synchronization with the timing of the change in light intensity, images can be acquired in time-division order, and these images can be combined to generate high dynamic range images without so-called black crushing and white clipping.

[0211] In addition, the light source device 11203 may be configured to supply light in a predetermined wavelength band corresponding to special light observation. In special light observation, for example, by utilizing the wavelength dependence of light absorption in body tissues, a narrow-band light is irradiated as compared with the irradiation light (i.e., white light) during normal observation, so that a so-called narrow-band light observation (Narrow Band Imaging) is performed to photograph a predetermined tissue such as blood vessels in the mucosal surface layer with high contrast. Alternatively, in special light observation, fluorescence observation may be performed to obtain an image by fluorescence generated by irradiating excitation light. In fluorescence observation, excitation light is irradiated to body tissues and fluorescence from the body tissues is observed (autofluorescence observation), or a reagent such as indocyanine green (ICG) is locally injected into the body tissues and excitation light corresponding to the fluorescence wavelength of the reagent is irradiated to the body tissues to obtain a fluorescence image. The light source device 11203 can be configured to supply such narrow-band light and / or excitation light corresponding to special light observation.

[0212] FIG. 73 is a block diagram showing an example of the functional configuration of the camera head 11102 and the CCU 11201 shown in FIG. 72.

[0213] The camera head 11102 includes a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are communicably connected to each other by a transmission cable 11400.

[0214] The lens unit 11401 is an optical system provided at a connection portion with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and enters the lens unit 11401. The lens unit 11401 is configured by combining a plurality of lenses including a zoom lens and a focus lens.

[0215] The imaging unit 11402 is composed of an imaging device. The imaging device constituting the imaging unit 11402 may be one (so-called single-plate type) or a plurality (so-called multi-plate type). When the imaging unit 11402 is configured in a multi-plate type, for example, image signals corresponding to RGB respectively may be generated by each imaging device, and a color image may be obtained by synthesizing them. Alternatively, the imaging unit 11402 may be configured to have a pair of imaging devices for respectively acquiring image signals for the right eye and the left eye corresponding to 3D (Dimensional) display. By performing 3D display, the surgeon 11131 can more accurately grasp the depth of the biological tissue in the surgical site. When the imaging unit 11402 is configured in a multi-plate type, a plurality of lens units 11401 may be provided corresponding to each imaging device.

[0216] Also, the imaging unit 11402 does not necessarily have to be provided in the camera head 11102. For example, the imaging unit 11402 may be provided immediately behind the objective lens inside the lens barrel 11101.

[0217] The drive unit 11403 is composed of an actuator, and under the control from the camera head control unit 11405, it moves the zoom lens and the focus lens of the lens unit 11401 along the optical axis by a predetermined distance. Thereby, the magnification and focus of the captured image by the imaging unit 11402 can be appropriately adjusted.

[0218] The communication unit 11404 is composed of a communication device for transmitting and receiving various information with the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 as RAW data to the CCU 11201 via the transmission cable 11400.

[0219] Furthermore, the communication unit 11404 receives control signals from the CCU 11201 to control the drive of the camera head 11102 and supplies them to the camera head control unit 11405. These control signals include information regarding imaging conditions, such as information to specify the frame rate of the captured image, information to specify the exposure value at the time of imaging, and / or information to specify the magnification and focus of the captured image.

[0220] The imaging conditions such as frame rate, exposure value, magnification, and focus may be specified by the user as appropriate, or they may be automatically set by the control unit 11413 of the CCU11201 based on the acquired image signal. In the latter case, the endoscope 11100 will be equipped with so-called AE (Auto Exposure), AF (Auto Focus), and AWB (Auto White Balance) functions.

[0221] The camera head control unit 11405 controls the drive of the camera head 11102 based on the control signal received from the CCU 11201 via the communication unit 11404.

[0222] The communication unit 11411 consists of a communication device for sending and receiving various types of information with the camera head 11102. The communication unit 11411 receives image signals transmitted from the camera head 11102 via the transmission cable 11400.

[0223] Furthermore, the communication unit 11411 transmits control signals to the camera head 11102 to control the driving of the camera head 11102. Image signals and control signals can be transmitted by telecommunications, optical communications, etc.

[0224] The image processing unit 11412 performs various image processing operations on the image signal, which is RAW data transmitted from the camera head 11102.

[0225] The control unit 11413 performs various controls related to imaging the surgical area, etc., by the endoscope 11100, and the display of the images obtained from imaging the surgical area, etc. For example, the control unit 11413 generates control signals to control the driving of the camera head 11102.

[0226] Furthermore, the control unit 11413 displays the captured image showing the surgical area on the display device 11202 based on the image signal processed by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition technologies. For example, the control unit 11413 can recognize surgical instruments such as forceps, specific biological sites, bleeding, mist when using the energy treatment device 11112, etc., by detecting the shape and color of the edges of objects included in the captured image. When displaying the captured image on the display device 11202, the control unit 11413 may use the recognition results to superimpose various surgical support information onto the image of the surgical area. By superimposing the surgical support information and presenting it to the surgeon 11131, the burden on the surgeon 11131 can be reduced, and the surgeon 11131 can proceed with the surgery with confidence.

[0227] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable compatible with electrical signal communication, an optical fiber compatible with optical communication, or a composite cable thereof.

[0228] In the illustrated example, communication was performed via a wired connection using the transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may be performed wirelessly.

[0229] The above describes an example of an endoscopic surgical system to which the technology described herein can be applied. The technology described herein can be suitably applied to the imaging unit 11402 provided on the camera head 11102 of the endoscope 11100, among the configurations described above. By applying the technology described herein to the imaging unit 11402, the imaging unit 11402 can be miniaturized or made higher resolution, thereby providing a small or high-resolution endoscope 11100.

[0230] The present disclosure has been described above with reference to embodiments, their modifications, application examples, and application examples. However, the present disclosure is not limited to the above embodiments, and various modifications are possible. The effects described herein are merely illustrative. The effects of the present disclosure are not limited to those described herein. The present disclosure may have effects other than those described herein.

[0231] Furthermore, for example, this disclosure can take the following configuration. (1) The first semiconductor substrate has a sensor pixel that performs photoelectric conversion, The second semiconductor substrate has a readout circuit that outputs a pixel signal based on the charge output from the sensor pixel, The third semiconductor substrate has a logic circuit for processing the pixel signal and Equipped with, The first substrate, the second substrate, and the third substrate are stacked in this order. The laminate comprising the first substrate and the second substrate has an interlayer insulating film and a first through-wiring provided within the interlayer insulating film. The first substrate and the second substrate are electrically connected to each other by the first through-wiring. The second substrate and the third substrate are electrically connected to each other by bonding of the pad electrodes if the second substrate and the third substrate each have pad electrodes, and by the second through-wiring if the third substrate has a second through-wiring that penetrates the third semiconductor substrate. Image sensor. (2) The sensor pixel has a photoelectric conversion element, a transfer transistor electrically connected to the photoelectric conversion element, and a floating diffusion that temporarily holds the charge output from the photoelectric conversion element through the transfer transistor. The readout circuit has a reset transistor that resets the potential of the floating diffusion to a predetermined potential, an amplification transistor that generates a voltage signal corresponding to the level of the charge held in the floating diffusion as the pixel signal, and a selection transistor that controls the output timing of the pixel signal from the amplification transistor. The imaging device according to (1). (3) The first substrate has a configuration in which the photoelectric conversion element, the transfer transistor, and the floating diffusion are provided on a surface side portion of the first semiconductor substrate. The second substrate has a configuration in which the readout circuit is provided on a surface side portion of the second semiconductor substrate, and the second substrate is bonded to the first substrate with the back surface of the second semiconductor substrate facing the surface side of the first semiconductor substrate. The third substrate has a configuration in which the logic circuit is provided on a surface side portion of the third semiconductor substrate, and the third substrate is bonded to the second substrate with the surface side of the third semiconductor substrate facing the surface side of the second semiconductor substrate. The imaging device according to (1) or (2). (4) The second substrate and the third substrate each have the pad electrode. The cross-sectional area of the first through-wiring is smaller than the cross-sectional area of the connection portion between the pad electrodes. The imaging device according to any one of (1) to (3). (5) The third substrate has the first through-wiring. The cross-sectional area of the first through-wiring is smaller than the cross-sectional area of the second through-wiring. The imaging device according to any one of (1) to (3). (6) The logic circuit is configured to include silicide on the surface of the impurity diffusion region that is in contact with the source electrode or drain electrode. The image sensor described in any one of (1) to (5). (7) The first substrate has the photoelectric conversion element, the transfer transistor, and the floating diffusion for each sensor pixel, and further has an element isolation section that separates each sensor pixel. The second substrate has the readout circuit for each of the sensor pixels. The image sensor described in any one of (2) to (6). (8) The first substrate has the photoelectric conversion element, the transfer transistor, and the floating diffusion for each sensor pixel, and further has an element isolation section that separates each sensor pixel. The second substrate has the readout circuit for each of the plurality of sensor pixels. The image sensor described in any one of (2) to (6). (9) The first substrate has the photoelectric conversion element and the transfer transistor for each sensor pixel, the floating diffusion is shared for each of the multiple sensor pixels, and further has an element isolation section that separates the photoelectric conversion element and the transfer transistor for each sensor pixel. The second substrate has the readout circuit for each of the multiple sensor pixels that share the floating diffusion. The image sensor described in any one of (2) to (6). (10) The element isolation portion penetrates the first semiconductor substrate. The image sensor described in any one of (7) to (9). (11) The laminate has at least two of the first through-wirings for each of the sensor pixels, The first through-wiring is electrically connected to the gate of the transfer transistor, The second through-wiring is electrically connected to the floating diffusion. The image sensor described in (8) or (9). (12) The second substrate further has connecting wirings that electrically connect each of the first through-wirings, which are electrically connected to each of the floating diffusions that share the read circuit, to each other. The image sensor described in (11). (13) The number of the first through-wirings is greater than the number of the sensor pixels included in the first substrate. The number of connections between the pad electrodes, or the number of the second through-wirings, is less than the number of sensor pixels included in the first substrate. The image sensor described in (12). (14) The gate of the transfer transistor is electrically connected to the logic circuit via the first through-hole wiring and the pad electrode or the second through-hole wiring. The image sensor described in any one of (11) to (13). (15) The first substrate further has gate wiring extending in a direction parallel to the first substrate within the interlayer insulating film, The gate of the transfer transistor is electrically connected to the logic circuit via the gate wiring. The image sensor described in (8) or (9). (16) The interlayer insulating film is A first insulating layer provided in the gap between the first semiconductor substrate and the second semiconductor substrate, A second insulating layer is provided to cover the side surface of the first through-wiring, A third insulating layer provided in the gap between the second semiconductor substrate and the third semiconductor substrate, Includes, The second insulating layer is made of a material having a relative permittivity smaller than that of the first insulating layer and the third insulating layer. The image sensor described in any one of (1) to (15). (17) The first insulating layer is composed of a laminate of at least two insulating layers. The insulating layer, which is the uppermost layer of the laminate, is made of a material with a relative permittivity greater than that of the other parts of the interlayer insulating film. The image sensor described in (16). (18) The second substrate has the readout circuit for each of the four sensor pixels, Multiple first through-wirings are arranged in a strip-like pattern in a first direction within the plane of the first substrate. The image sensor described in any one of (11) to (13). (19) The readout circuit is not positioned directly in front of the four sensor pixels that share the readout circuit, but is offset in a second direction perpendicular to the first direction. The image sensor described in (18). (20) Each of the sensor pixels is arranged in a matrix in the first direction and in a second direction orthogonal to the first direction. The second substrate is A first control line electrically connected to the gate of the transfer transistor of each of the sensor pixels arranged in the second direction, A second control line electrically connected to the gate of each of the reset transistors arranged in the second direction, A third control line electrically connected to the gate of each of the selected transistors arranged in the second direction, Output lines electrically connected to the output terminals of each of the readout circuits arranged in the first direction and It further possesses The image sensor described in (18) or (19).

[0232] According to one embodiment of the image sensor of this disclosure, the electrical connections between substrates are made according to the integration density of the substrates, so that the structure of electrically connecting the substrates does not increase the chip size or hinder the miniaturization of the area per pixel. As a result, it is possible to provide a three-layer image sensor with the same chip size as before, without hindering the miniaturization of the area per pixel. The effects of this disclosure are not necessarily limited to those described herein, and may be any of the effects described herein.

[0233] This application claims priority based on U.S. Patent Application No. 62 / 610806, filed with the U.S. Patent and Trademark Office on 27 December 2017, and International Application PCT / JP2018 / 036417, filed with the Japan Patent Office on 28 September 2018, all contents of the former application are incorporated herein by reference.

[0234] Those skilled in the art will understand that various modifications, combinations, subcombinations, and changes can be conceived depending on design requirements and other factors, and that these fall within the scope of the attached claims and their equivalents.

Claims

1. A first substrate including a first semiconductor substrate having sensor pixels, A second substrate including a second semiconductor substrate having a first circuit for outputting pixel signals, A third substrate including a third semiconductor substrate having a second circuit for processing the aforementioned pixel signals, Interlayer insulating film and Equipped with, The interlayer insulating film is A first insulating layer is provided between the first semiconductor substrate and the second semiconductor substrate, A second insulating layer penetrating the second semiconductor substrate, A third insulating layer provided between the second semiconductor substrate and the third semiconductor substrate and Includes, The interlayer insulating film is provided with at least two through-wirings. The interlayer insulating film is provided with at least one first through-wiring of the at least two through-wirings for each sensor pixel, and further, one second through-wiring of the at least two through-wirings is provided for each group having multiple sensor pixels. The at least two through-wirings are provided to penetrate the portion of the interlayer insulating film that includes the second insulating layer, and electrically connect the first substrate and the second substrate. The first semiconductor substrate is provided with an insulating portion that does not completely enclose the plurality of sensor pixels belonging to the same group, and has a gap in the vicinity of the floating diffusion. The at least one first through-wiring and the one second through-wiring are provided at a location facing the area enclosed by the insulating portion. The second substrate is provided with a first electrode, The third substrate is provided with a second electrode, The first electrode and the second electrode are joined to each other, thereby electrically connecting the second substrate and the third substrate to each other. In a cross-sectional view, the width of the through-wiring is narrower than the width of at least one of the first electrode and the second electrode. The sensor pixel includes a photoelectric conversion element and a transfer transistor electrically connected to the photoelectric conversion element. One of the at least one first through-wiring is electrically connected to the gate of the transfer transistor. In the aforementioned group, the multiple sensor pixels share the floating diffusion, and the one second through-wiring is electrically connected to the floating diffusion. Light detection element.

2. The total number of through-wirings is greater than the total number of sensor pixels included in the first substrate. The photodetector according to claim 1.

3. The gate of the transfer transistor is electrically connected to the second circuit via the first through-wiring, the first electrode, and the second electrode. The photodetector according to claim 1.

4. The floating diffusion is electrically connected to the first circuit via the second through-wiring. The photodetector according to claim 1.

5. The first circuit includes an amplifying transistor. The photodetector according to claim 1.

6. The floating diffusion is electrically connected to the gate of the amplification transistor via the second through-wiring. The photodetector according to claim 5.

7. The first circuit is electrically connected to the second circuit via the first electrode and the second electrode. The photodetector according to claim 1.

8. The second insulating layer is formed of a material having a relative permittivity lower than that of the first insulating layer and the third insulating layer. The photodetector according to claim 1.

9. The first insulating layer is composed of a laminate of at least two insulating layers. In the laminate, the insulating layer in contact with the first semiconductor substrate is made of a material with a relative permittivity greater than that of other parts of the laminate. The photodetector according to claim 8.

10. The first electrode and the second electrode are formed of Cu or Al. The photodetector according to claim 1.

Images