High-speed multiport memory that supports collisions

Abstract

A multi-port memory is provided that supports collisions between read and write ports to the same multi-port bitcell. A sense amplifier reads a data bit from a multi-port bitcell when a write port to the multi-port bitcell is addressed during a system clock signal. A multiplexer selects an output bit from the sense amplifier when a read port to the multi-port bitcell is addressed during the same system clock signal.

Description

Technical Field

[0001] Cross - reference to Related Applications This application claims the benefit of priority of U.S. Application No. 17 / 210,230, filed on March 23, 2021, the entire content of which is incorporated herein by reference.

[0002] This application relates to memory, and more particularly to high - speed multi - port memory that supports collisions.

Background Art

[0003] A static random - access memory (SRAM) bit cell includes a pair of cross - coupled inverters for storing a bit. Each inverter requires two transistors, and thus four transistors are required to implement two cross - coupled inverters. In a conventional single - port SRAM bit cell, two additional access transistors complete the bit - cell implementation, thereby requiring a total of six transistors. The two access transistors are controlled by a shared word line, whereby the two access transistors form a single read / write port to the bit cell. However, the single - port architecture has problems for multiple - processor applications because competition occurs between multiple processors at the single access port. By adding additional access transistors, a multi - port SRAM bit cell may have an access (read) port for each processor.

[0004] While multi-port SRAM offers advantages for multiple processor architectures, conflicts can occur if write operations occur simultaneously with read operations on the same multi-port SRAM bit cell. To avoid these conflicts, multi-port SRAM bit cells are traditionally accessed using a "double-pump" method in response to the system clock signal that controls memory access. In response to a transition in the system clock signal (e.g., a rising edge), a read operation may be performed on one or more access ports during the first part of the system clock signal period. After the read operation is complete, a write operation may then be performed during the second part of the system clock signal period. However, the double-pump operation reduces memory speed because write and read operations must be performed consecutively during the system clock signal period. [Overview of the project] [Means for solving the problem]

[0005] According to one aspect of the present disclosure, a multiport memory is provided, comprising a multiport bit cell including a first read port having a first read port bit line, further comprising a pair of write port bit lines, a sense amplifier coupled to the pair of write port bit lines, a first inverter coupled to the first read port bit line, and a first multiplexer configured to select either a data output bit from the sense amplifier or a data output bit from the first inverter and provide the selected data output bit.

[0006] Another aspect of the present disclosure provides a method for operating a multiport memory, comprising the steps of: comparing a first read port address with a write port address to detect a first collision in response that the first read port address matches a write port address; detecting that no first collision has occurred in response that the first read port address does not match a write port address; in a first multiplexer, selecting data output bits obtained from a single-ended read through the first read port to a multiport bit cell in response to the detection of no first collision; and in a first multiplexer, selecting data output bits obtained from a differential read through the write port to a multiport bit cell in response to the detection of a first collision.

[0007] A further aspect of the present disclosure provides a multiport memory comprising a multiport bit cell including a first read port having a first read port bit line and a first read port word line, the multiport bit cell further including a pair of write bit lines or a write port; an address comparator configured to detect collisions in response that a write port address points to a write port and a read port address points to a first read port; and a read port word line controller configured to assert the first read port word line in response to a collision being detected and not assert the first read port word line in response to no collision being detected.

[0008] A further aspect of the present disclosure provides a multiport memory comprising: an address comparator configured to detect collisions in response to both a read port address and a write port address pointing to a first multiport bit cell; a sense amplifier configured to read a first data bit from the first multiport bit cell through a write port; a write driver configured to write a second data bit to the first multiport bit cell through a write port after the reading of the first data bit is complete; and a multiplexer coupled to the sense amplifier and configured to select a first data bit in response to the detection of a collision.

[0009] These and additional advantages may be better understood through the following embodiments for carrying out the invention. [Brief explanation of the drawing]

[0010] [Figure 1] This figure shows an exemplary multiport bit cell for a multiport memory that implements the collision support disclosed herein. [Figure 2] This flowchart shows an example of a collision support implementation according to one aspect of this disclosure. [Figure 3] This is a circuit diagram of a multiport memory configured to provide collision support, according to one aspect of the present disclosure. [Figure 4] This is a flowchart showing how collision support operates according to one aspect of this disclosure. [Figure 5] This figure shows several exemplary electronic systems, each incorporating collision support in a multiport memory, according to one aspect of the present disclosure. [Modes for carrying out the invention]

[0011] The embodiments of this disclosure and their advantages are best understood by referring to the detailed description below. Please note that similar reference numerals are used to identify similar elements shown in one or more of the figures.

[0012] A multi-port SRAM is disclosed that supports collisions rather than avoiding them through double-pump operation or similar means. To support collisions, the memory includes an address comparator for each read port. Each address comparator compares the read port address with the write port address. If the comparison indicates that the read port address points to a first multi-port bit cell and the write port address points to a second multi-port bit cell, a single-ended read operation is performed to the first multi-port bit cell through the read port. Simultaneously, a write operation is performed to the second multi-port bit cell through the write port. Therefore, high-speed operation is improved due to the simultaneous operation of the read and write ports (even though the operations are performed on different multi-port bit cells).

[0013] However, if the address comparison indicates that the read port address and the write port address point to the same multiport bit cell, the read port is not accessed. To perform a read, the multiport SRAM utilizes the speed difference between single-ended and differential read operations. To do this, the write operation is delayed until a differential read is performed through the write port. Therefore, this differential read operation may be performed each time the write port is accessed. Although the write operation is delayed so that the differential read is performed first, the memory operation speed is not affected because single-ended reads through the read port are not as fast as differential reads. Therefore, differential read and write operations (which are also differential operations) may be completed in approximately the same amount of time as a single-ended read operation. Note the following advantage: If the multiport bit cell does not have collisions, the single-ended read operation may proceed. Differential reads, on the other hand, are performed on multiport bit cells that do have collisions. Therefore, the delays that occur in the double-pump technique do not occur.

[0014] Next, an exemplary multiport bit cell will be described, but it will be understood that any SRAM having any suitable multiport bit cell architecture may implement the collision support disclosed herein. Furthermore, although the exemplary multiport bit cell below has a pair of read ports, an alternative implementation may include only one read port in the multiport bit cell. Thus, a multiport SRAM bit cell includes at least one read port in addition to a write port. The write port and read port will be better understood by considering the exemplary 3-port SRAM bit cell 100 shown in Figure 1. The write port includes a write port access n-type metal oxide semiconductor (NMOS) transistor M3 and another write port access NMOS transistor M4. A write word line (WWL) is connected to the gates of the write port access transistors M3 and M4, thereby switching the write port access transistors ON when the write word line is charged to the power supply voltage. The write port also includes a pair of write bit lines formed by the true write bit line (WBL) and the complementary write bit line (WBLB). For brevity, the true write bit line may simply be referred to as the write bit line in the following description. The write bit line WBL is connected to the drain / source terminal of the write port access transistor M3. The remaining drain / source terminal of the write port access transistor M3 is connected to the Q data output node of bit cell 100. The terminals are called "drain / source" terminals in that which terminal is the source and which is the drain is determined by the binary state of the SRAM bit cell 100 before the write operation, and by the binary state of the bits being written to the SRAM bit cell 100 during the write operation. The complementary write bit line WBLB is similarly positioned as it is connected to the drain / source terminal of the write port access transistor M4. The remaining drain / source terminal of the write port access transistor M4 is connected to the complementary data output node QB of the SRAM bit cell 100.

[0015] Prior to the write operation, the write bit lines WBL and WBLB are precharged to the supply voltage. The write operation is performed in response to an edge (e.g., rising edge) of the system clock signal. The word line generator or controller (not shown in Figure 1, but described further below) responds to the clock edge by charging the write word line WWL to the supply voltage so that the write port access transistor can be switched on. With the write word lines asserted, the write driver (also not shown in Figure 1, but described further below) then drives the write bit line pair with the data bits to be written to the multiport bit cell. If the binary value of the data bits is true, the write driver discharges the complementary write bit line WBLB while keeping the true write bit line WBL charged. Conversely, in response to a data bit being false, the write driver discharges the true write bit line WBL while keeping the complementary write bit line WBLB charged.

[0016] Depending on which bit lines are charged and which write bit lines are discharged to ground, the write driver determines which output nodes of the SRAM bit cell 100 are charged to the power supply voltage or discharged to ground. For example, if the write bit lines remain charged during a write operation, the Q output node is charged, while the auxiliary QB output node is discharged. The Q output node is the output node of a first inverter cross-coupled to a second inverter in the SRAM bit cell 100. The first inverter includes a p-type metal oxide semiconductor (PMOS) transistor P1, whose source is connected to a power supply node for the power supply voltage. The drain of transistor P1 is connected to the drain of an NMOS transistor M1. The source of transistor M1 is connected to ground. The drains of transistors P1 and M1 form the output node of the first inverter and also form the Q output node for the bit cell 100.

[0017] The second inverter is similarly arranged and therefore includes a PMOS transistor P2. The source of the PMOS transistor P2 is connected to the power node, and its drain is connected to the drain of an NMOS transistor M2, whose source is connected to ground. The drains of transistors P2 and M2 form the output node of the second inverter and also form the QB output node. To complete the cross coupling between the inverters, the Q output node is connected to the gates of transistors P2 and M2. Similarly, the QB output node is connected to the gates of transistors P1 and M2. Thus, the two inverters reinforce each other and latch the bits to be written to the SRAM bit cell 100.

[0018] The first read port A of the SRAM bit cell 100 includes an NMOS transistor M5, an NMOS access transistor M6, a read port A bit line (RBLA), and a read port A word (RWLA). The read port A bit line RBLA is connected to the drain of the access transistor M6. The source of the access transistor M6 is connected to the drain of transistor M5. The source of transistor M5 is connected to ground. The Q output node is connected to the gate of transistor M5. The read port A word line RWLA is connected to the gate of access transistor M6. Prior to a read operation to read port A, the read port A bit line RBLA is precharged to the supply voltage. The read port A bit line RBLA then floats during a single-ended read operation to read port A, thereby the bit line voltage may be affected by the single-ended read operation to the SRAM bit cell 100 through read port A. During a single-ended read operation to read port A, the read port A word line RWLA is charged to the supply voltage, and access transistor M6 is switched on. If the Q output node is charged to the supply voltage before the read operation to port A, transistor M5 is switched on, and the source of transistor M6 is discharged. When access transistor M6 is switched on by asserting the read port A word line RWLA, the read port A bit line RBLA discharges through transistors M5 and M6. If the read operation to read port A is single-ended (involving only one read bit line), the sense amplifier that senses the binary content of the SRAM bit cell 100 through read port A may be formed by a simple inverter (not shown in Figure 1, but described further below). When the read port A bit line RBLA discharges to the trip point of the sense amplifier inverter, the sense amplifier inverter asserts its output signal to the supply voltage, successfully representing the binary 1 that was read from the SRAM bit cell 100.Since each of the sense amplifier inverters disclosed herein is formed by an inverter that acts as a sense amplifier, a sense amplifier inverter may be referred to simply as an inverter herein.

[0019] Instead, if SRAM bit cell 100 stores binary 0, the Q output node is discharged before the read operation. In this case, transistor M5 is switched off, thereby causing the read port A bit line RBLA to remain pre-charged during the read operation to read port A. Thus, the sense amplifier inverter continues to discharge an output signal indicating that binary 0 has been read from SRAM bit cell 100.

[0020] The remaining read port B is similarly configured to include NMOS transistors M7 and M8, as well as the read port B word line (RWLB) and read port B bit line (RBLB). The read port B bit line RBLB is connected to the drain of access transistor M8. The source of access transistor M8 is connected to the drain of transistor M7. The source of transistor M7 is connected to ground. The QB output node is connected to the gate of transistor M7. The read port B word line RWLB is connected to the gate of access transistor M8. Before a single-ended read operation to read port B, the read port B bit line RBLB is precharged to the supply voltage. The read port B bit line RBLB then floats, and thereby the voltage of the read port B bit line RBLB may be affected by the read operation to SRAM bit cell 100 through read port B. During a single-ended read operation through read port B, the read port B word line RWLB is charged to the supply voltage and access transistor M8 is switched on. If the QB output node is charged to the supply voltage before a read operation on port B, transistor M7 is switched on and the source of access transistor M8 is discharged. When access transistor M8 is switched on by asserting the read port B word line RWLB, the read port B bit line RBLB discharges through transistors M7 and M8. Conversely, the read port B bit line RBLB remains precharged during read port B access if the QB node is discharged.

[0021] Single-ended read operations to read ports A and B are performed only when there are no collisions. A collision occurs if a write operation to the multi-port bit cell 100 via the write port is performed in the same system clock cycle as a read operation to read port A and / or read port B. The read operation attempts to read the binary state of the bits stored in the SRAM bit cell 100, and in some cases, while the write operation is modifying this binary state. The resulting collision disrupts the read operation. As mentioned above, collision mitigation has traditionally been performed via a double-pump operation that divides the system clock period into two parts. In the first part, read operations are performed to either (or both) read ports A and B. The write port is not accessed during this first part. Write operations are performed during the second part of the system clock period. If the double-pump operation is performed correctly, no write operations will occur between read operations, so collisions cannot occur. However, dividing the system clock period in this way in the double-pump operation reduces the memory operation speed.

[0022] To eliminate the timing penalty of double pump operation, a multi-port memory is provided where the system clock cycle is not divided into separate parts for read and write operations. Instead, address comparison is performed for each active read port, and it is determined whether the write port of the SRAM bit cell is also addressed by the write operation. If the address comparison indicates that a write operation is not being performed on the addressed SRAM bit cell, a single-ended read operation is performed via the corresponding read port. This single-ended read operation is performed as described for SRAM bit cell 100. Thus, the corresponding read port bit line is precharged and then floats while the corresponding read word line is being charged, whereby the resulting voltage of the read port bit line is sensed by the sense amplifier inverter, and a read port data output bit or a complementary read port data output bit is generated depending on whether the addressed read port is read port A or read port B. However, if the address comparison indicates that the write port of the SRAM bit cell is also being accessed, no read operation is performed via the read port. Since the read port is not being used, the corresponding read port bit line is not floated and the corresponding read word line voltage is not asserted. Instead, if the write port of the multi-port SRAM bit cell is accessed during the same system clock cycle as the system clock cycle in which one (or both) of the read ports is being accessed, a read operation is performed through the write port.

[0023] Read operations through write ports utilize the differences between read and write ports. In particular, note that write operations to write ports involve a pair of write port bit lines, while read operations to either read port A or B are single-ended and performed through only one read port bit line. Assuming differential characteristics for write port access, differential reading of bits stored in a multi-port SRAM bit cell can be performed relatively quickly through the write ports compared to single-ended reads on the read ports. In this regard, the threshold voltage for a sense amplifier inverter performing a single-ended read is approximately half the supply voltage. For example, assuming a supply voltage of 0.8V, the threshold voltage for the sense amplifier inverter to perform a single-ended read through the read port is approximately 400mV. In this case, the precharge read port bit line must be discharged from 800mV to the 400mV trigger point before the sense amplifier inverter can make its bit determination. However, differential reading via the write port bit line does not require such a relatively large voltage change before the differential sense amplifier coupled to the write port bit line can make a bit determination.

[0024] When a write port is addressed during a given system clock cycle, driving of the write bit lines using the data bits written during the write operation is delayed until a differential read operation can be performed. Prior to write port access, the write bit lines may be precharged to a default state. During differential read through the write port, depending on the binary value of the bit stored in the multi-port SRAM bit cell, one of the write bit lines starts discharging from the default precharged state. Subsequently, a voltage difference occurs between the write port bit lines sensed by the differential sense amplifier. Comparing with the threshold voltage of the sense amplifier inverter, the differential sense amplifier may make a bit decision when the voltage difference is only a small fraction of the supply voltage (e.g., 100 mV or 80 mV or even lower voltage). The voltage difference across the write port bit lines for making a differential bit decision in the differential sense amplifier is quite small compared with the threshold voltage for which the sense amplifier inverter makes a single-ended bit decision. Therefore, a sufficient voltage difference across the write port bit lines for performing differential read occurs more rapidly compared with the single-ended read operation.

[0025] Assuming such a relative speed for differential read, the differential read and driving of the write bit lines to complete the write operation may still be performed in substantially the same time as that taken for a single-ended read operation. Thus, the operation performed is that the write operation (including the initial differential read) can start at substantially the same time as the time when the single-ended read operation is being performed, but in terms of address comparison, it is shown that the write port was also addressed, so it is quite fast compared with the double-pump operation.

[0026] Generally, it is more common for read ports to be accessed without collisions for multiport SRAM bit cells. In such cases, single-ended reads are performed through the addressed read port. The write port is not accessed, and therefore the write bit line remains in its default pre-charged state. However, for a given multiport SRAM bit cell in the same system clock period, both the read and write ports may be addressed. In this case, single-ended read operations are not performed through the addressed read port; instead, differential read operations are performed through the write port before the write operation begins and completes. Differential read operations sense both the stored data bits and their complements in the multiport SRAM bit cell. Therefore, the multiplexer may choose to select the bit determination from the sense amplifier inverter for the addressed read port if the write port is not addressed (no collision occurs), or to select the bit determination from the differential sense amplifier if the write port is addressed (a collision exists). A latch may then latch the bit determination selection from the multiplexer.

[0027] A flowchart 200 for collision mitigation performed on a multiport SRAM is shown in Figure 2. With respect to this multiport SRAM, the multiplexed bit cell 100 is an example of a suitable multiport bit cell, but it will be understood that the collision mitigation disclosed herein can be performed using any suitable multiport bit cell architecture. Flowchart 200 begins in response to the triggering edge of the clock signal 205 initiating a read and / or write operation. With respect to flowchart 200, the write port is shown as port C to distinguish it from read ports A and B. The write port may be addressed following the triggering edge of the clock signal 205; however, this is not necessarily true for every cycle of the clock signal 205. If the write port is addressed, the write word line (port C word line) is asserted in step 220. After the write word line is asserted, the stored bits in the multiport bit cell corresponding to write port C are retrieved to write port C through the pair of write bit lines via the differential read 240. Next, the differential sense amplifier senses the binary value of the extracted bit. After the differential read is complete, the write driver then drives the data bit to be written to the corresponding bit cell through the write port C in step 265. Once the write operation is complete, the write word line is discharged (closed) and step 265 is completed.

[0028] To determine whether a collision has occurred to read port A in the same clock cycle, the addresses of read port A and write port C are compared in step 210. If the addresses point to the same multiport bit cell (for example, the addresses may be equal), a collision has occurred, as indicated by the "yes" decision in flowchart 200. Conversely, if the addresses of read port A and write port C each point to different multiport bit cells, no collision has occurred with respect to read port A (as indicated by the "no" decision in flowchart 200). If no collision has occurred at read port A, the read port A word line may be charged in step 225, thereby allowing a single-ended read operation to be performed through read port A in step 235. The multiplexer 250 then selects the single-ended read result (assuming no collision has occurred), thereby allowing the output bits to be latched in step 260. However, if a collision occurs between port A and port C, the read port A word line is not asserted, and the multiplexer 250 selects the output bits by differential read operation in step 240. Thus, the selection by the multiplexer 250 may be controlled by whether the yes decision for the collision between port A and port C in step 210 is true or false.

[0029] In step 215, a similar address comparison is performed for read port B. If the addresses of port B and port C point to the same multiport bit cell, a collision has occurred (yes, determined). Conversely, if the addresses of read port A and write port C each point to different multiport bit cells, there is no collision with respect to read port B (no, determined). If there is no collision at read port B, the read port B word line may be charged in step 230, thereby allowing a single-ended read operation to be performed through read port B in step 245. The multiplexer 255 then selects the port B single-ended read result (assuming no collision has occurred), thereby latching the complement bit in step 270. However, if a collision occurs between port B and port C, the read port B word line is not asserted, and the multiplexer 255 selects the complement bit by differential read operation in step 240. Therefore, the selection by the multiplexer 255 may be controlled by whether the yes decision regarding the collision between port B and port C in step 215 is true or false.

[0030] Next, the SRAM 300 configured for collision avoidance will be described with reference to Figure 3. The address comparator 305 performs an address comparison between the address of port A and the address of port C in response to the triggering edge of the system clock signal (CLK). If the comparison indicates that no collision has occurred between port A and port C, the address comparator 305 sends the system clock signal as the clock A signal (CLKA) to the precharge and port A word line controller 310, and in response to the assertion of the precharge A signal, triggers the assertion (charging) of the port A word line and the precharge float of the port A bit line. The state (true or false) of the precharge signal A may control the selection by the multiplexer 250 as further described herein.

[0031] The address comparator 315 performs an address comparison between the address of port B and the address of port C in response to the triggering edge of the system clock signal (CLK). If the comparison indicates that there is no collision between port B and port C, the address comparator 315 sends the system clock signal as the clock B signal (CLKB) to the precharge and port B word line controller 311, and in response to the assertion of the precharge B signal, triggers the assertion (charging) of the port B word line and the precharge float of the port B bit line. The state (true or false) of the precharge signal A may control the selection by the multiplexer 255 as further described herein.

[0032] The write port in the multiport bit cell 100 includes a write word line WWL and write bit lines WBL and WBLB, as described above. The differential sense amplifier 320 is coupled to the write bit lines WBL and WBLB, so that when the write word line WWL is asserted and the write port is opened, the differential sense amplifier 320 can sense both the data bits and their complements stored in the multiport bit cell 100. The sensed data bits are represented as Sout, while the sensed complementary data bits are represented as SoutB. Sensing by the sense amplifier 320 is performed in response to the assertion of the sense enable signal. The sense amplifier 320 is also integrated with a write driver (Din driver), which can then drive the write bit lines WBL and WBLB with the data bits Din, which are written after the differential read operation is complete.

[0033] The precharge A signal drives the gate of PMOS transistor P4, whose source is coupled to the power supply voltage node and whose drain is connected to the read port A bit line. The precharge A signal controls whether the read port A bit line floats or remains in its default precharged state. When the precharge A signal is deasserted, the read port A bit line is precharged due to conduction by transistor P4. As used herein, signals are considered "asserted" when they are true, regardless of whether a logical high or logical low convention is used. The precharge A signal is active high and is thereby asserted by being charged to the power supply voltage. The precharge A signal also controls the float of the global read port A bit line (GRBLA). To do so, the precharge A signal also drives the gate of PMOS transistor P5, whose drain is connected to the global read port A bit line and whose source is connected to the power supply node. Therefore, when the precharge A signal is deasserted, transistor P5 conducts again, precharging the global read bit line A to the power supply voltage. Inverter INV C inverts the binary state of the read port A bit line, driving the gate of NMOS transistor M9, whose source is connected to ground and whose drain is connected to the global read port A bit line. Thus, transistor M9 is turned off while the read port A bit line is precharging. When read port A is addressed, the precharge A signal is asserted, switching both transistors P4 and P5 off, thereby causing both the read port A bit line RBLA and the global read port A bit line GRBLA to float. If the data bit stored in the multiport bit cell 100 is binary 0 (assuming the logic high convention), the precharge state of the RBLA and GRBLA lines is unaffected despite the RBLA and GRBLA lines floating. The read port A sense amplifier inverter (INV A) inverts the binary state of the GRBLA line to provide the sensed data output bits.The sensed data output bit is selected by the multiplexer 250 due to the assertion of the precharge A signal. However, in the event of a collision, the precharge A signal is not asserted, and thereby the multiplexer 250 selects the Sout data bit from the differential sense amplifier 320. The data output latch 325 may then latch the sensed bit (DoutA), regardless of whether the sensed bit (DoutA) was generated by read port A or write port C.

[0034] Read port B is similar. The precharge B signal drives the gate of PMOS transistor P6, whose source is coupled to the power supply voltage node and whose drain is connected to read port B bit line B (RBLB). The precharge B signal controls whether read port B bit line floats or remains in its default precharged state. When the precharge B signal is deasserted, precharging of read port B bit line occurs due to conduction by transistor P6. The precharge B signal also controls the float of global read port B bit line (GRBLB). To do so, the precharge B signal also drives the gate of PMOS transistor P7, whose drain is connected to global read port B bit line and whose source is connected to the power supply node. Therefore, when the precharge B signal is deasserted, transistor P7 also conducts, precharging global read port B bit line to the power supply voltage. Inverter INV D inverts the binary state of the read port B bit line to drive the gate of NMOS transistor M10, whose source is connected to ground and whose drain is connected to the global read port B bit line. Thus, transistor M10 is turned off while the read port B bit line is precharged. When read port B is addressed, the precharge B signal is asserted, switching both transistors P6 and P7 off, thereby causing both the read port B bit line RBLB and the global read port B bit line GRBLB to float. If the data bit stored in the multiport bit cell 100 is binary 0 (assuming the logic high convention in this case as well), the precharge states of the RBLB and GRBLB lines are unaffected despite the RBLB and GRBLB lines being floated. The read port B sense amplifier inverter (INV B) inverts the binary state of the GRBLB line to provide the sensed data output bit. The sensed data output bit is selected by the multiplexer 255 due to the assertion of the precharge B signal.However, in the event of a collision, the precharge B signal is not asserted, and the multiplexer 255 instead selects the SoutB supplemental data bit from the differential sense amplifier 320. The data output latch 325 may then latch the sensed bit (DoutB), regardless of whether the sensed bit (DoutB) was generated by the read port B or the write port C.

[0035] Next, the collision support method will be described with reference to the flowchart shown in Figure 4. This method includes an action 400 which compares a first read port address with a write port address to detect a first collision in response to the first read port address matching the write port address, and detects the absence of a first collision in response to the first read port address not matching the write port address. A comparison in either address comparator 305 or 315 is an example of action 400. The method further includes an action 405 which is performed in a first multiplexer and, in response to the detection of the absence of a first collision, includes selecting data output bits obtained from a single-ended read to a multiport bit cell through the first read port. A selection in either multiplexer 250 or 255 with the absence of a collision is an example of action 405. Finally, the method includes an action 410 which is also performed in the first multiplexer and, in response to the detection of a first collision, includes selecting data output bits obtained from a differential read to a multiport bit cell through the write port. A choice in either the multiplexer 250 or 255 involving collision is an example of act 410.

[0036] The multiport memory including collision support disclosed herein may be incorporated into a variety of electronic systems. For example, as shown in Figure 5, a mobile phone 500, a laptop computer 505, and a tablet PC 510 may all include multiport memory including collision support as disclosed herein. Other exemplary electronic systems such as music players, video players, communication devices, and personal computers may also be configured using multiport memory built according to this disclosure.

[0037] Next, this disclosure is summarized in the following series of clauses. Clause 1. Multiport memory, A multiport bit cell including a first read port having a first read port bit line, further including a pair of write port bit lines, A sense amplifier coupled to a pair of write port bit lines, A first inverter coupled to the first read port bit line, A multiport memory comprising a first multiplexer configured to select either data output bits from a sense amplifier or data output bits from a first inverter and provide the selected data output bits. Clause 2. A multiport bit cell further includes a second read port having a second read port bit line, and the multiport memory is A second inverter coupled to the second read port bit line, The multiport memory according to Clause 1, further comprising a second multiplexer configured to select either a supplemental data output bit from a sense amplifier or a supplemental data output bit from a second inverter and provide the selected supplemental data output bit. Clause 3. The multiport memory described in Clause 2, further comprising a data latch configured to latch selected data output bits and selected complementary data output bits. Clause 4. An address comparator configured to detect a collision in response that the read port address is the same as the write port address, and to detect no collision in response that the read port address is different from the write port address, A multiport memory according to any one of claims 1 to 3, further comprising a read word line controller configured to assert a read port word line to a first read port in response to the detection of no collision, and not to assert a read port word line in response to the detection of a collision. Clause 5. The multiport memory described in Clause 4, further configured, to assert a precharge signal in response to the detection of no collision and not assert a precharge signal in response to the detection of a collision. Clause 6. The multiport memory described in Clause 5, further comprising a transistor coupled between a first read port bit line and a power node for a power supply voltage, wherein the transistor is configured to switch on in response to an assertion of a precharge signal and to switch off in response to the failure to assert a precharge signal. Clause 7. The multiport memory described in Clause 6 comprises p-type metal-oxide-semiconductor (PMOS) transistors. Clause 8. A multiport memory according to any one of Clauses 1 to 7, further comprising a write driver configured to drive a pair of write bit lines in response to a bit being written to a multiport bit cell after a sense operation by a sense amplifier has completed. Clause 9. The multiport memory according to Clause 4, comprising a pair of cross-coupled inverters configured to drive a data output node and a complementary data output node, and further comprising an access transistor configured to be controlled by a read port word line for the first read port. Clause 10. The multiport memory described in Clause 9, wherein the first read port further includes a second transistor coupled between ground and the terminal of the access transistor, the gate of the second transistor coupled to a data output node, and the multiport memory is incorporated into a mobile phone. Clause 11. A method for operating a multiport memory, The steps include: comparing a first read port address with a write port address; detecting a first collision in response to the first read port address matching the write port address; and detecting the absence of a first collision in response to the first read port address not matching the write port address; In the first multiplexer, in response to the detection of the absence of a first collision, the steps include selecting data output bits obtained from single-ended reads to a multi-port bit cell through a first read port, A method comprising the step of selecting a data output bit obtained from a differential read to a multiport bit cell through a write port in a first multiplexer in response to the detection of a first collision. Clause 12. The method according to Clause 11, further comprising the step of triggering a comparison of a first read port address and a write port address in response to the edge of a clock signal. Clause 13. The steps of comparing a second read port address with a write port address, detecting a second collision in response that the second read port address matches the write port address, and detecting the absence of a second collision in response that the second read port address does not match the write port address, In the second multiplexer, in response to the detection of the absence of a second collision, the steps include selecting a supplemental data output bit obtained from a single-ended read to a multi-port bit cell through the second read port, The method according to either of clauses 11 and 12, further comprising the step of selecting a complementary data output bit obtained from a differential read to a multiport bit cell through a write port in a second multiplexer in response to the detection of a second collision. Clause 14. Before comparing the first read port address with the write port address, the first bit line is precharged at the first read port, Steps include: floating a first bit line in response to the detection of a first collision; The method according to any one of the clauses 11 to 13, further comprising the step of maintaining a precharge on a first bit line in response to the detection of the absence of a first collision. Clause 15. The method of Clause 14, further comprising the step of asserting a precharge signal in response to detection of the absence of a first collision, wherein the float of a first bit line is performed in response to the assertion of the precharge signal. Clause 16. The method of Clause 15, further comprising the step of switching off a transistor coupled between a first bit line and a power node for a power supply voltage in response to an assertion of a precharge signal. Clause 17. The method according to Clause 16, further comprising the step of maintaining the ON state of the transistor by maintaining the deassertion of the precharge signal in response to the detection of a first collision. Clause 18. The method according to any one of Clauses 11 to 17, further comprising the step of latching data output bits from a first multiplexer. Clause 19. Multiport memory, A multiport bit cell comprising a first read port having a first read port bit line and a first read port word line, further comprising a write port having a pair of write port bit lines, An address comparator configured to detect collisions in response to a write port address pointing to a write port and a read port address pointing to a first read port, A multiport memory comprising a read port word line controller configured to assert a first read port word line in response to no collision being detected, and configured not to assert the first read port word line in response to collision detection. Clause 20. The multiport memory as described in Clause 19, wherein the read port word line controller is further configured to assert a precharge signal for a first read port in response to no collision being detected, and the first read port is further configured to float the first read port bit line in response to the assertion of the precharge signal. Clause 21. A multiport memory according to either of Clauses 19 and 20, further comprising a sense amplifier configured to perform differential reads through a write port in response to a write port address pointing to a write port. Clause 22. The multiport memory according to Clause 21, further comprising a data driver configured to drive a pair of write bit lines such that data bits are written to a multiport bit cell after differential reading is complete. Article 23. An inverter coupled to the first read port bit line, A multiport memory according to either of clauses 21 and 22, further comprising a multiplexer configured to select either the output of an inverter or a sense amplifier. Clause 24. Multiport memory, An address comparator configured to detect collisions in response to both the read port address and the write port address pointing to a first multiport bit cell, A sense amplifier configured to read a first data bit from a first multiport bit cell through a write port, A write driver configured to write the second data bit to the first multiport bit cell via the write port after the first data bit has been read, A multiport memory comprising a sense amplifier and a multiplexer configured to select a first data bit in response to collision detection. Clause 25. The multiport memory according to Clause 24, further comprising an inverter coupled to a read port bit line in a first read port in a first multiport bit cell, wherein the multiplexer is further configured to select the output of the inverter in response to detection of the absence of a collision. Clause 26. The multiport memory described in Clause 25, further comprising a data latch configured to latch output bits from a multiplexer. Clause 27. The first multiport bit cell is a multiport memory as described in either Clause 25 or 26, including a second read port. Clause 28. A multiport memory according to any one of Clauses 25 to 27, further comprising a read port word line controller configured to assert a word line to a first read port in response to the detection of the absence of a collision. Clause 29. The multiport memory described in Clause 28, further configured to assert a precharge signal to the first read port in response to detection of the absence of a collision. Clause 30. A multiport memory as described in any of Clauses 24 to 29, wherein the address comparator is configured to be triggered to detect collisions in response to the edges of a clock signal.

[0038] As those skilled in the art will now understand, depending on the specific applications present, many modifications, substitutions, and variations can be made to the materials, apparatus, configuration and method of use of the devices of this disclosure, and to them, without departing from their scope. In light of this, the specific embodiments illustrated and described herein are only a few examples, and therefore the scope of this disclosure should not be limited to the scope of such specific embodiments, but rather should be exactly the same as the scope of the claims and their functional equivalents appended below. [Explanation of Symbols]

[0039] 100 SRAM bit cells 200 flowcharts 205 Clock signal 240 Differential Readout 250, 255 Multiplexer 300 SRAM 305 Address Comparator 310 Port A Word Line Controller 311 Port B Word Line Controller 315 Address Comparator 320 Differential Sense Amplifier 325 Data output latch 500 mobile phones 505 Laptop Computer 510 Tablet PC M1, M2, M3, M4, M5, M6, M7, M8, M9, M10 NMOS transistors P1, P2, P4, P5, P6, P7 PMOS transistors RBLA Read Port A Bit Line RBLB Read Port B Bit Line RWLA Read Port A Word Line RWLB Read Port B Word Line WBL True Write Bit Line WBLB Compensation Bitline WWL writing word line

Claims

1. A multiport memory which is static random access memory (SRAM), A multiport bit cell comprising a first single-ended read port having a first read port bit line, further comprising a differential write port with a pair of write port bit lines, A differential sense amplifier coupled to the pair of write port bit lines, A first inverter coupled to the first read port bit line, The system includes a first multiplexer configured to select and provide selected data output bits from either the data output bits from the differential sense amplifier or the data output bits from the first inverter, A multiport memory in which the first multiplexer selects a data output bit from the differential sense amplifier in response to the read port address being the same as the write port address.

2. The multiport bit cell further includes a second read port having a second read port bit line, and the multiport memory is A second inverter coupled to the second read port bit line, The multiport memory according to claim 1, further comprising a second multiplexer configured to select and provide a selected complementary data output bit from either a complementary data output bit from the differential sense amplifier or a complementary data output bit from the second inverter.

3. The multiport memory according to claim 2, further comprising a data latch configured to latch the selected data output bits and the selected complementary data output bits.

4. An address comparator configured to detect a collision in response to the read port address being the same as the write port address, and to detect no collision in response to the read port address being different from the write port address, The multiport memory according to claim 1, further comprising: a read word line controller configured to assert a read port word line to the first read port in response to the detection of the absence of a collision, and not to assert the read port word line in response to the detection of a collision.

5. The multiport memory according to claim 4, wherein the read word line controller is further configured to assert a precharge signal in response to the detection of the absence of a collision, and not to assert the precharge signal in response to the detection of a collision.

6. The multiport memory according to claim 5, further comprising a transistor coupled between the first read port bit line and a power node for a power supply voltage, wherein the transistor is configured to switch on in response to the assertion of the precharge signal and to switch off in response to the failure to assert the precharge signal.

7. The multiport memory according to claim 6, wherein the transistor comprises a p-type metal-oxide-semiconductor (PMOS) transistor.

8. The multiport memory according to claim 1, further comprising a write driver configured to drive a pair of write port bit lines in response to a bit being written to the multiport bit cell after the completion of a sense operation by the differential sense amplifier.

9. The multiport memory according to claim 4, wherein the multiport bit cell comprises a pair of cross-coupled inverters configured to drive a data output node and a complementary data output node, and the first read port further comprises an access transistor configured to be controlled by the read port word line.

10. The multiport memory according to claim 9, wherein the first read port further includes a second transistor coupled between ground and the terminal of the access transistor, the gate of the second transistor is coupled to the data output node, and the multiport memory is incorporated into a mobile phone.

11. A method for operating a multiport memory which is a static random access memory (SRAM), The steps include: comparing a first read port address with a write port address, detecting a first collision in response to the first read port address matching the write port address, and detecting the absence of a first collision in response to the first read port address not matching the write port address; The inverter inverts the data output bits obtained from a single-ended read to a multi-port bit cell through a first read port, and the first multiplexer selects the output of the inverter in response to the detection of the absence of the first collision. A method comprising the step of selecting a data output bit obtained from a differential read to the multiport bit cell through a write port in the first multiplexer in response to the detection of the first collision.

12. The method according to claim 11, further comprising the step of triggering the comparison between the first read port address and the write port address in response to the edge of a clock signal.

13. The steps include: comparing a second read port address with the write port address, detecting a second collision in response to the second read port address matching the write port address, and detecting the absence of a second collision in response to the second read port address not matching the write port address; In the second multiplexer, in response to the detection of the absence of the second collision, the steps include selecting a supplemental data output bit obtained from a single-ended read to the multiport bit cell through the second read port, The method according to claim 11, further comprising the step of selecting, in the second multiplexer, an auxiliary data output bit obtained from the differential read to the multiport bit cell through the write port in response to the detection of the second collision.

14. Before comparing the first read port address with the write port address, the first bit line is precharged at the first read port; In response to the detection that there is no first collision, the first bit line is floated, The further step includes maintaining the precharge of the first bit line in response to the detection of the first collision, The step of asserting a precharge signal in response to the detection of the absence of a first collision, further comprising the step of the float of the first bit line being performed in response to the assertion of the precharge signal, The step further includes switching off a transistor coupled between the first bit line and a power supply node for the power supply voltage in response to the assertion of the precharge signal, The method according to claim 11, further comprising the step of maintaining the ON state of the transistor by maintaining the deassertion of the precharge signal in response to the detection of the first collision.

15. The method according to claim 11, further comprising the step of latching data output bits from the first multiplexer.

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