Power control IC, diagnostic method for power control IC

Abstract

Provided is a power supply control IC that is mounted on an ECU, that has a function capable of reactivating through a process of an internal circuit or an external circuit, and that can perform highly accurate failure predictive diagnosis. This power supply control IC is characterized by comprising: a power supply circuit that generates at least one voltage from a power supply voltage; an activation pin for activating the power supply circuit; and an activation circuit that performs a reactivation process for the power supply circuit on the basis of a reactivation signal when a prescribed voltage is applied to the activation pin.

Description

Technical Field

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[0003]

[0001] The present invention relates to the configuration and control of a semiconductor device, and particularly to a technique effective when applied to a power control IC mounted on an in-vehicle ECU that requires high reliability.

Background Art

[0002] In car-sharing and fully autonomous driving, the operating time of automobiles per day increases, and accordingly, the operating time of in-vehicle semiconductor components also increases. Further, when the autonomous driving level 4 or higher is put into practical use, an autonomous driving system mounted on the automobile will be responsible for all driving operations, and an increase in the processing amount in the CPU (Central Processing Unit) mounted in the ECU (Electronic Control Unit) responsible for the control of autonomous driving and an accompanying increase in losses in the power control IC (Integrated Circuit) are expected.

[0003] As background art in this technical field, for example, there is a technique such as Patent Document 1. Patent Document 1 discloses a technique for cooling an electronic device by flowing a refrigerant that circulates inside an automobile through an ECU housing for the purpose of suppressing heat generation of the electronic device.

[0004] Further, Patent Document proposes a power control IC provided with a diagnostic function for performing diagnosis at the time of starting the power control IC which is in a stopped state of the automobile.

[0005] Further, Patent Document discloses a diagnostic method for determining a failure only when an abnormality is continuously detected a plurality of times in a power control IC for the purpose of avoiding misdiagnosis due to environmental causes such as electromagnetic noise during the operation of an automobile.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Patent Document 2

[0007] Generally, the higher the junction temperature (operating temperature) of a semiconductor component, the sooner it will wear out and fail (reach its lifespan). Depending on the characteristics, the phenomenon of characteristics changing from their initial values ​​in relation to operating time (hereinafter referred to as "time-dependent characteristic change") may be accelerated. As mentioned above, if the operating time of the power control IC mounted on the ECU increases, and the junction temperature of the power control IC rises due to increased losses, the lifespan of the power control IC, i.e., the time it reaches failure, will be shortened.

[0008] In such cases, when the power control IC approaches the end of its lifespan, the vehicle can be continued to be used by replacing the ECU that houses the power control IC. When using a vehicle, including ECU replacement, it is desirable to reduce the frequency of replacements, and to achieve this, it is necessary to extend the operating time of the power control IC itself.

[0009] By using the technology described in Patent Document 1, the rise in junction temperature of the power control IC can be suppressed, and by slowing down the variation in characteristics over time, the operating time of the power control IC can be extended compared to when it is not cooled. However, it is necessary to provide a path for circulating refrigerant in the ECU housing, and an ECU housing with high heat dissipation becomes costly.

[0010] On the other hand, if the power control IC fails, the ECU equipped with the power control IC may cease to function, and if the ECU ceases to function while the vehicle is in motion, it could lead to an accident. Therefore, it is desirable to be able to detect and notify of signs of failure when the power control IC is started up while the vehicle is stopped. In particular, failures caused by changes in characteristics over time are characterized in that abnormalities begin to be detected as the time of failure approaches, and the probability of the abnormality occurring increases as the time of failure approaches. When detecting signs of failure, it is necessary to detect them when the probability of detecting abnormalities is low, before the failure occurs.

[0011] The technology described in Patent Document 2 above has the drawback that, because the probability of an abnormality occurring is low at the point when a failure is predicted, it is difficult to detect signs of failure with a single diagnosis at startup. Furthermore, there is a possibility of misdiagnosis due to environmental factors, and if a misdiagnosis occurs, the vehicle will not start. In order to start again, the user must turn the ignition switch (hereinafter referred to as IG-SW) off and then on again. Moreover, since the detected abnormality is cleared with the user's operation, it is not possible to identify the startup failure even after restarting. If there is a startup failure of unknown cause, the ECU may be replaced even though there is sufficient operating time before the power control IC fails.

[0012] The technology described in Patent Document 3 above can distinguish between a malfunction and a misdiagnosis caused by environmental factors based on whether or not abnormalities are detected consecutively. However, since the probability of malfunction precursors occurring is low and they cannot be detected, there is a possibility that the ECU will not be replaced until a malfunction occurs.

[0013] Therefore, it is important to provide a low-cost method for extending the operating time of power control ICs, which are subject to demanding operating conditions in terms of IC lifespan within the ECU, and to provide a method for detecting signs of failure.

[0014] Therefore, the object of the present invention is to provide a power control IC mounted on an ECU that has a function to restart in response to processing by an internal or external circuit, and that enables more accurate fault prediction diagnosis. [Means for solving the problem]

[0015] To solve the above problems, the present invention provides a power supply circuit that generates at least one voltage from a power supply voltage, a start pin for starting the power supply circuit, and a start circuit that performs a restart process of the power supply circuit based on a restart signal when a predetermined voltage is input to the start pin. A diagnostic circuit that performs a self-diagnosis of the power control IC when the power supply circuit is started, and a counter circuit that counts the number of diagnoses and the number of abnormalities detected by the diagnostic circuit, Equipped with The power control IC, when it detects a startup abnormality of the power supply circuit or an abnormality detected by the diagnostic circuit, sends a restart signal to the startup circuit, the counter circuit calculates an abnormality detection frequency which is the ratio of the number of abnormality detections to the number of diagnostics, maintains the number of diagnostics and the number of abnormality detections regardless of the operation of the power supply circuit, and determines that there is a precursor to a failure or that a failure has occurred if the abnormality detection frequency is greater than a predetermined value. It is characterized by the following:

[0016] Furthermore, the present invention includes (a) the step of inputting a startup signal for a power control IC, and (b) In step (a) above, when a startup signal is input, a diagnostic signal is output; and in step (b) above, when a diagnostic signal is output, the diagnostic circuit The steps include: incrementing the number of diagnoses by one and storing it in memory; (d) The steps include performing a startup diagnosis of the power control IC, (e) The aforementioned (d) If an anomaly is detected during the step, In the aforementioned diagnostic circuit The steps include: incrementing the number of anomaly detections by one and storing it in the memory; (f) From the aforementioned memory The aforementioned Number of diagnoses and The aforementioned The steps include reading the number of anomaly detections and calculating the anomaly detection frequency, (g) The aforementioned (f) The step includes comparing the anomaly detection frequency calculated in the step with a predetermined threshold, (g) In the step, if the frequency of abnormality detection is less than the predetermined threshold, it is determined to be normal and a restart signal for the power control IC is output; if the frequency of abnormality detection is equal to or greater than the predetermined threshold, it is determined to be a sign of failure and a notification of the sign of failure is output. [Effects of the Invention]

[0017] According to the present invention, a power control IC mounted on an ECU can have a function that allows it to restart in response to processing by an internal or external circuit, thereby enabling a more accurate fault prediction diagnosis.

[0018] As a result, it is possible to extend the operating time of the power control IC and the ECU equipped with the same while suppressing cost increases.

[0019] Problems, configurations, and effects other than those described above will be clarified by the description of the following embodiments.

Brief Description of the Drawings

[0020] [Figure 1] It is a diagram showing a schematic configuration of an ECU according to Embodiment 1 of the present invention. [Figure 2] It is a block diagram showing a configuration example of the power control IC 100 in FIG. 1. [Figure 3] It is a diagram showing a configuration example of the startup circuit 20 in FIG. 2. [Figure 4] It is a diagram showing a configuration example of the power supply circuit 10 in FIG. 2. [Figure 5] It is a diagram showing a configuration example of the startup diagnostic circuit 31 in FIG. 2. [Figure 6] It is a flowchart schematically showing the startup process of the power control IC 100 in FIG. 2. [Figure 7] It is a block diagram showing the configuration of the power control IC 100 according to Embodiment 2 of the present invention. [Figure 8] It is a diagram showing a configuration example of the counter circuit 40 in FIG. 7. [Figure 9] It is a flowchart schematically showing the startup process of the power control IC 100 in FIG. 7. [Figure 10] It is a flowchart schematically showing the startup process of the power control IC according to Embodiment 3 of the present invention. [[ID=4L]] [Figure 11] It is a block diagram showing the configuration of the power control IC 100 according to Embodiment 4 of the present invention. [Figure 12] It is a block diagram showing a configuration example of the characteristic control circuit 60 in FIG. 11. [Figure 13] It is a timing chart schematically showing the correction operation of the characteristic control circuit 60 in FIG. 11. [Figure 14] It is a flowchart schematically showing the startup process of the power control IC 100 in FIG. 11. [Figure 15] This is a block diagram showing the configuration of the power control IC 100 according to Embodiment 5 of the present invention. [Figure 16] Figure 15 is a flowchart illustrating the startup process of the power control IC 100. [Figure 17] This is a block diagram showing the configuration of the power control IC 100 according to Embodiment 6 of the present invention. [Figure 18] Figure 17 is a flowchart illustrating the startup process of the power control IC 100. [Figure 19] This is a block diagram showing the configuration of the power control IC 100 according to Embodiment 7 of the present invention. [Figure 20] Figure 19 is a block diagram showing an example configuration of the restart setting circuit 50. [Figure 21] Figure 19 is a flowchart illustrating the startup process of the power control IC 100. [Modes for carrying out the invention]

[0021] Embodiments of the present invention will be described below with reference to the drawings. Note that the drawings are simplified, and the technical scope of the present invention should not be narrowly interpreted based on their depiction. Furthermore, the same reference numerals are used for identical elements, and redundant explanations are omitted. [Examples]

[0022] A power control IC and its diagnostic method according to Embodiment 1 of the present invention will be described with reference to Figures 1 to 6.

[0023] This embodiment is characterized by performing a process to stop the power control IC in accordance with a predetermined process performed inside the power control IC (hereinafter referred to as the internal process), and then performing a process to restart the power control IC (hereinafter referred to as the restart process). The configuration and operation of the power control IC that can restart the power control IC by performing the restart process if a temporary abnormality occurs in the power control IC due to noise or the like will be described.

[0024] Figure 1 shows an example of the configuration of ECU1 equipped with a power control IC 100. ECU1 comprises a CPU 200 responsible for control and a power control IC 100 that supplies power to the CPU 200. When the IG-SW2 is turned on by user operation, the power control IC 100 performs a startup process and supplies power to the CPU 200 by generating an output voltage Voutput from the power supply voltage Vpower.

[0025] Figure 2 is a block diagram showing an example configuration of the power control IC 100 shown in Figure 1. The power control IC 100 shown in Figure 2 consists of a power supply circuit 10 that generates at least one voltage from the power supply voltage Vpower, an internal processing unit 30 that performs internal processing and outputs a restart signal Srepup as needed, and a startup circuit 20 that performs a restart process for the power control IC 100 when the restart signal Srepup is input.

[0026] The startup circuit 20 performs the startup process for the power control IC 100 when the startup signal Spup is input, and performs the shutdown process for the power control IC 100 when the stop signal Spdown is input. Furthermore, when a High signal is input to the startup signal line 102 and a restart signal Srepup is input, the startup circuit 20 performs the restart process.

[0027] The power supply circuit 10 is equipped with a start pin (not shown) for starting the power supply circuit 10, and when a predetermined voltage is input to the start pin, the start circuit 20 performs a restart process for the power supply circuit 10 based on a restart signal.

[0028] An example of the startup circuit 20 in this embodiment is the circuit configuration shown in Figure 3. The startup circuit 20 shown in Figure 3 consists of a startup signal detection unit 21 that detects the startup signal Spup, a diagnostic signal generation unit 22 that outputs a diagnostic signal Sdiag for a diagnostic time Tdiag after detecting the startup signal Spup, a control signal generation unit 23 that outputs a logical high level (hereinafter referred to as High) to the control signal line 104 if the restart signal Srepup is not input after the diagnostic time Tdiag, and a switch element 24 that, when the restart signal Srepup is input, interrupts the startup signal Spup for a certain period of time and then reconnects it to return the startup circuit 20 to its initial state. Furthermore, the delay circuits 26a and 26b are configured to be initialized when the restart signal Srepup is input.

[0029] The initial state of the startup circuit 20 is that it outputs a logical Low level (hereinafter referred to as Low) to the diagnostic signal line 105 and the control signal line 104. Also, since the restart signal line 101 is Low, the switch element 24 is connected, and when High is input to the startup signal line 102 as the startup signal Spup, the startup signal detection unit 21 compares it with the startup signal determination threshold voltage Vth_pup, and if it is greater than the startup signal determination threshold voltage Vth_pup, it determines that it is a startup signal Spup and outputs High to the diagnostic signal generation unit 22.

[0030] When the diagnostic signal generation unit 22 receives a High signal from the startup signal detection unit 21, it outputs a High signal to the diagnostic signal line 105 as a diagnostic signal Sdiag. The delay time of the delay circuit 26a becomes the diagnostic time Tdiag, and it outputs a Low signal after Tdiag has elapsed and the diagnosis is complete. By setting the delay time of the delay circuit 26b in the control signal generation unit 23 to be longer than Tdiag, it is possible to determine whether to disable or enable the power supply circuit 10 depending on whether or not there is a restart signal Srepup after Tdiag. Since it is known that the delay circuit can be easily implemented with multiple NOT gates, the description of its configuration and operation is omitted.

[0031] If there is no restart signal Srepup after the diagnostic time Tdiag, the power supply circuit 10 outputs High to the control signal line 104 and starts operating. If there is a restart signal Srepup after Tdiag, the switch element 24 is disconnected while the control signal line 104 remains output Low, and the startup circuit 20 is initialized. Also, when Low is input to the startup signal line 102, the startup signal detection unit 21 determines that it is a stop signal Spdown because it is smaller than the startup signal determination threshold voltage Vth_pup, and outputs Low to the diagnostic signal generation unit 22. As a stop process, the startup circuit 20 returns to its initial state where it outputs Low to the diagnostic signal line 105 and the control signal line 104.

[0032] The power supply circuit 10 has two functions: (function A) which supplies the power required for startup to the internal circuit when the power supply voltage Vpower is input to the power supply line 103, and (function B) which generates at least one output voltage from the power supply voltage Vpower and supplies the power required for ECU operation to the internal or external circuit when the power supply voltage Vpower is input and the control signal Spower_en which changes the voltage level of the control signal line 104 from Low to High is input.

[0033] Circuits that can realize these functions include switching regulators, linear regulators, and bandgap references. A configuration incorporating one or more of these, or a combination thereof, is also possible.

[0034] As an example of the power supply circuit 10 in this embodiment, the circuit configuration shown in Figure 4 can be considered. The former function (function A) is configured by the linear regulator 12b, and the latter function (function B) is configured by the linear regulator 12a, and the power supply line 103 and the linear regulator 12a are connected by a switch element 11 that disconnects or connects them.

[0035] One example of the configuration of the linear regulator 12a is that it consists of a feedback resistor 16 and a feedback resistor 17 that divide the output voltage Voutput to generate a feedback voltage Vfb, a reference voltage generation unit 13 that generates a reference voltage Vref which serves as the reference for the output voltage Voutput, an error amplifier 15 that outputs the difference in voltage values ​​between the feedback voltage Vfb and the reference voltage Vref as a difference signal Sdiff, and a MOSFET 14 that generates the output voltage Voutput from the power supply voltage Vpower by controlling the resistance value according to the difference signal Sdiff.

[0036] The switch element 11 electrically connects the power supply voltage Vpower and the MOSFET 14 when a High signal is input to the control signal line 104, and electrically disconnects the power supply voltage Vpower and the MOSFET 14 when a Low signal is input to the control signal line 104.

[0037] The reference voltage generation unit 13 is known to be easily implemented using a bandgap reference circuit or the like, and outputs a reference voltage Vref whose voltage value does not fluctuate with respect to changes in the surrounding environment such as input voltage and temperature.

[0038] By controlling the linear regulator 12a so that the difference between the feedback voltage Vfb and the reference voltage Vref is small in response to changes in the output voltage Voutput, a stable output voltage Voutput, determined by the reference voltage Vref and the feedback resistance values ​​Rfbu and Rfbd as shown in equation (1), is output to the output voltage line 108 of the linear regulator 12a.

[0039] Voutput=Vref×(Rfbu+Rfbd)÷Rfbd (1) Since linear regulator 12b is the same as linear regulator 12a, the explanation of its configuration and operation will be omitted.

[0040] The internal processing unit 30 outputs a restart signal Srepup when predetermined characteristics (hereinafter referred to as internal characteristics) within the power control IC 100 satisfy predetermined conditions. Here, internal characteristics refer to the physical quantities of the waveform (voltage value, current value, frequency, etc.).

[0041] An example of a circuit mounted within the internal processing unit 30 in this embodiment is the circuit configuration shown in Figure 5. The startup diagnostic circuit 31 shown in Figure 5 compares the internal characteristics with the abnormality detection threshold voltage Vth_diag and outputs a restart signal Srepup. The startup diagnostic circuit 31 can detect abnormalities in the internal characteristics by allowing the internal characteristics to be monitored on the diagnostic signal line 111.

[0042] As shown in Figure 5, the startup diagnostic circuit 31 consists of an abnormality determination unit 32 that compares the internal characteristics monitored on the diagnostic signal line 111 with the abnormality determination threshold voltage Vth_diag, a diagnostic control unit 33 that outputs the diagnostic results for the period during which High is input to the diagnostic signal line 105, and a filter circuit 34 that determines an abnormality only if High is output during the abnormality determination filter time Tfilter. The delay amount of the delay circuit 26c determines the filter time Tfilter.

[0043] The startup diagnostic circuit 31 diagnoses whether there is an abnormality in the internal characteristics by comparing the internal characteristics with the abnormality detection threshold voltage Vth_diag when a High signal is input to the diagnostic signal line 105 from the startup circuit 20. If the internal characteristics are greater than the abnormality detection threshold voltage Vth_diag, it is determined to be normal and outputs Low to the restart signal line 101. On the other hand, if the internal characteristics are less than or equal to the abnormality detection threshold voltage Vth_diag, it is determined that there is an abnormality in the internal characteristics and outputs High to the restart signal line 101.

[0044] As an example of a startup process in which the power control IC 100 in this embodiment is restarted by internal processing, the flow of the process in which the system restarts when a temporary abnormality occurs due to noise or the like during startup diagnosis will be explained using the flowchart in Figure 6.

[0045] First, when the power supply voltage Vpower is applied to the power supply line 103 (START), in step S1, a voltage level High is input to the start signal line 102 as a start signal Spup. The start circuit 20 outputs High to the diagnostic signal line 105 as a diagnostic signal and proceeds to step S2.

[0046] Next, in step S2, the startup diagnostic circuit 31 compares the internal characteristics with the abnormality detection threshold voltage Vth_diag. If the internal characteristics are greater than the abnormality detection threshold voltage Vth_diag, it is determined that the internal characteristics are normal (OK), and the process proceeds to step S3. If the internal characteristics are less than or equal to the abnormality detection threshold voltage Vth_diag, it is determined that the internal characteristics are abnormal (NG), and the process proceeds to step S5.

[0047] In step S3, the startup circuit 20 outputs a High signal to the control signal line 104. The power supply circuit 10 starts operating, and the process proceeds to step S4.

[0048] Next, in step S4, the power supply circuit 10 generates an output voltage Voutput from the power supply voltage Vpower. The output voltage Voutput is supplied to the load, the load starts operating, and the startup process ends (END).

[0049] Meanwhile, in step S5, the startup diagnostic circuit 31 outputs a High signal to the restart signal line 101 as a restart signal Srepup, and the process proceeds to step S6.

[0050] In step S6, the startup circuit 20 returns to its initial state as a shutdown process, and the process returns to step S2. Then, if an abnormality occurs after the last startup, the system restarts repeatedly until no abnormalities are detected. The restart process may also be configured to be performed a predetermined number of times.

[0051] Here, the startup process refers to the process from the state in which the power supply voltage Vpower is applied to the power line 103 (START) to the state in which the power supply circuit of the power control IC 100 is operating (END). The restart process refers to the process of restarting the startup process midway through, and refers to the process from step S5 to step S6.

[0052] In this embodiment, a configuration example is shown in which the restart process is performed by the internal processing of the power control IC 100. However, by electrically connecting the startup circuit 20 of the power control IC 100 to the external elements of the power control IC 100, the restart process of the power control IC 100 can also be performed by processing at the external elements (hereinafter referred to as external processing).

[0053] The diagnosis performed by the startup diagnostic circuit 31 in this embodiment is merely one example described from the perspective of comparing voltage values, and similar diagnoses can be achieved in a variety of other forms. For example, the abnormality determination unit 32, which is a comparison circuit, may be a current-input type comparator circuit for comparing current values, or a digital counter or phase comparator for comparing frequencies.

[0054] As described above, the power control IC 100 of this embodiment is characterized by executing a restart process according to internal processing, and if a temporary abnormality occurs in the power control IC 100 due to noise or the like, it can be restarted by the restart process. [Examples]

[0055] Referring to Figures 7 to 9, a power supply control IC according to Embodiment 2 of the present invention and its diagnostic method will be described.

[0056] In this embodiment, in addition to the configuration of Embodiment 1, the configuration and operation of a power control IC that determines the abnormality detection frequency by detecting the number of diagnostics and the number of abnormality detections, and determines that a failure is likely when the abnormality detection frequency is above a predetermined threshold, will be described. The following description will focus on the differences from Embodiment 1.

[0057] Figure 7 is a block diagram showing the configuration of the power control IC 100 in this embodiment. Focusing on the differences from Embodiment 1 (Figure 2), the power control IC 100 in this embodiment has a counter circuit 40 that counts the number of diagnostics performed at startup, Ndiag and the number of abnormality detections, Ndet_err, and the startup circuit 20 is equipped with a stop signal line 110 connected to the counter circuit 40.

[0058] When the voltage level of the stop signal line 110 changes from Low to High, the start circuit 20 returns to its initial state as a stop process. The counter circuit 40 is connected to the diagnostic signal line 105 and the diagnostic result signal line 106. Each time a High signal is input to the diagnostic signal line 105 as a diagnostic signal, the diagnostic count Ndiag is incremented, and each time a High signal is input to the diagnostic result signal line 106 as an abnormality detection, the abnormality detection count Ndet_err is incremented.

[0059] The abnormal detection frequency Rdet_err, obtained from the number of diagnostics Ndiag and the number of abnormal detections Ndet_err, is compared with the predictive detection threshold Rth_preerr. If the abnormal detection frequency Rdet_err is less than the predictive detection threshold Rth_preerr, the voltage level of the restart signal line 101 is changed from Low to High. If the abnormal detection frequency Rdet_err is equal to or greater than the predictive detection threshold Rth_preerr, the number of diagnostics Ndiag and the number of abnormal detections Ndet_err in the counter circuit memory 47 of the counter circuit 40 (described later in Figure 8) are cleared to their initial values, and the voltage level of the stop signal line 110 is changed from Low to High.

[0060] Furthermore, the counter circuit 40 has a configuration or means that allows it to retain the number of diagnostics Ndiag and the number of abnormality detections Ndet_err even when the power supply circuit 10 is stopped.

[0061] The anomaly detection frequency Rdet_err can be calculated using the following equation (2).

[0062] Rdet_err = Ndet_err / Ndiag (2) For accuracy, it is desirable to calculate the anomaly detection frequency Rdet_err from three or more execution counts.

[0063] An example of the counter circuit 40 in this embodiment is the configuration shown in Figure 8. The counter circuit 40 shown in Figure 8 includes a diagnostic result edge detection unit 41 that detects the rising edge of the voltage level of the diagnostic result signal line 106 from Low to High, a diagnostic signal edge detection unit 42 that detects the rising edge of the voltage level of the diagnostic signal line 105 from Low to High, an abnormality detection counter circuit 44 that counts up the number of abnormality detections Ndet_err each time a rising edge is detected by the diagnostic result edge detection unit 41, a diagnostic counter circuit 45 that counts up the number of diagnoses Ndiag each time a rising edge is detected by the diagnostic signal edge detection unit 42, a counter circuit memory 47 that stores the number of abnormality detections Ndet_err, and an abnormality detection frequency determination unit 46 that calculates the abnormality detection frequency Rdet_err and determines whether or not to activate by comparing the abnormality detection frequency Rdet_err with the predictive judgment threshold Rth_preerr.

[0064] The abnormality detection frequency determination unit 46 calculates the abnormality detection frequency Rdet_err, which is the ratio of the number of abnormality detections Ndet_err to the number of diagnoses Ndiag. It compares the abnormality detection frequency Rdet_err with the predictive detection threshold Rth_preerr. If the abnormality detection frequency Rdet_err is less than the predictive detection threshold Rth_preerr, it determines that the system is normal and changes the voltage level of the restart signal line 101 from Low to High. On the other hand, if the abnormality detection frequency Rdet_err is greater than or equal to the predictive detection threshold Rth_preerr, it determines that the system is in the process of failing, clears the number of abnormality detections Ndet_err in the counter circuit memory 47 to its initial value, and changes the voltage level of the stop signal line 110 from Low to High.

[0065] Furthermore, the abnormality detection frequency determination unit 46 can also notify the user via an external element by outputting a High signal to the communication signal line 109 when a sign of failure is detected.

[0066] Using the flowchart in Figure 9, an example of the startup process that determines signs of failure using the Rdet_err anomaly detection frequency at startup in this embodiment will be explained.

[0067] The flowchart shown in Figure 9 describes a process in which, if an abnormality is detected during startup diagnosis of the power control IC 100, it restarts to restart, calculates the abnormality detection frequency Rdet_err each time an abnormality is detected during startup diagnosis, determines that a failure is imminent if the abnormality detection frequency Rdet_err is equal to or greater than the predictive threshold Rth_preerr, notifies the load of the impending failure, and then does not start the power control IC 100.

[0068] The following explanation will focus on the differences from the process in Example 1 (Figure 6).

[0069] First, when the power supply voltage Vpower is applied to the power supply line 103 (START), in step S1, a voltage level High is input to the start signal line 102 as a start signal Spup, similar to Example 1 (Figure 6). The start circuit 20 outputs High to the diagnostic signal line 105 as a diagnostic signal and proceeds to step S2.

[0070] In step S2, the diagnostic count Ndiag is incremented by 1 and stored in the counter circuit memory 47, and the process proceeds to step S3.

[0071] In step S3, the startup diagnostic circuit 31 compares the internal characteristics with the abnormality detection threshold voltage Vth_diag. If the internal characteristics are greater than the abnormality detection threshold voltage Vth_diag and the internal characteristics are determined to be normal (OK), the process of steps S4 and S5, which correspond to steps S3 and S4 in Example 1 (Figure 6), is executed, and the startup process is terminated (END).

[0072] On the other hand, in step S3, if the internal characteristics are below the abnormality detection threshold voltage Vth_diag, it is determined that the internal characteristics are abnormal (NG), and the process proceeds to step S6.

[0073] In step S6, the diagnostic result edge detection unit 41 detects the rising edge of the voltage level of the diagnostic result signal line 106 from Low to High, incrementing the abnormality detection count Ndet_err by 1, storing it in the counter circuit memory 47, and proceeding to step S7.

[0074] Next, in step S7, the diagnosis count Ndiag and the abnormal detection count Ndet_err are read from the memory 47 for the counter circuit, and the abnormal detection frequency Rdet_err is calculated. If the abnormal detection frequency Rdet_err is less than the omen determination threshold Rth_preerr (<Rth_preerr), it is determined as normal, and the process proceeds to step S8. If the abnormal detection frequency Rdet_err is greater than or equal to the omen determination threshold Rth_preerr (≧Rth_preerr), it is determined as a sign of failure, and the process proceeds to step S10.

[0075] In step S10, the power supply circuit 10 is temporarily activated, and the process proceeds to step S11.

[0076] Subsequently, in step S11, power is temporarily supplied to the load, and the load is notified that there is a sign of failure.

[0077] Next, in step S12, the diagnosis count Ndiag and the abnormal detection count Ndet_err (i.e., the abnormal detection frequency Rdet_err) in the memory 47 for the counter circuit are cleared to the initial values, and the process proceeds to step S13.

[0078] In step S13, after performing the stop process of the power control IC 100, the process returns to step S1, and the processes after step S1 are repeated.

[0079] On the other hand, in step S7, if the abnormal detection frequency Rdet_err is less than the omen determination threshold Rth_preerr (<Rth_preerr) and it is determined as normal, the processes of steps S8 and S9 corresponding to steps S5 and S6 in Example 1 (Fig. 6) are executed, the process returns to step S2, and the processes after step S2 are repeated.

[0080] In this embodiment, the abnormal detection frequency is cleared each time a stop signal is input. However, the abnormal detection frequency obtained by inputting a plurality of start signals may also be used. In that case, it is possible to make a determination based on the abnormal detection frequency obtained over a longer period than making a determination with a single start signal.

[0081] Furthermore, in this embodiment, the flow shown is one in which, when a malfunction is detected, only a notification of the malfunction is issued and normal operation is not performed. However, it is also possible to have a flow in which a malfunction is detected and then normal operation is performed.

[0082] As described above, the power control IC 100 in this embodiment determines the abnormality detection frequency by detecting the number of diagnostic tests and the number of abnormality detections, and can determine that a malfunction is imminent if the abnormality detection frequency is above a predetermined threshold. [Examples]

[0083] Referring to Figures 8 to 10, a power control IC according to Embodiment 3 of the present invention and its diagnostic method will be described.

[0084] In this embodiment, a modified version of the power control IC 100 from Embodiment 2 is described, including a configuration and operation example that performs a fixed number of restarts at startup. The following description will focus on the differences from Embodiment 2.

[0085] Focusing on the difference from the counter circuit 40 of Example 2, in this embodiment, the counter circuit memory 47 within the counter circuit 40 is characterized in that it further stores the number of startups Npup, which is the number of times the system has been started, including restarts, after the input of the startup signal Spup, and the maximum number of startups Nmax_pup, which is the number of times the system is started in response to a single input of the startup signal Spup.

[0086] Furthermore, when the number of startups Npup reaches the maximum number of startups Nmax_pup, the counter circuit 40 compares the abnormality detection frequency Rdet_err, which is the ratio of the number of abnormality detections Ndet_err to the number of diagnostics Ndiag, with the predictive detection threshold Rth_preerr. If the abnormality detection frequency Rdet_err is less than the predictive detection threshold Rth_preerr, it is determined to be normal and the voltage level of the restart signal line 101 is changed from Low to High. If the abnormality detection frequency Rdet_err is equal to or greater than the predictive detection threshold Rth_preerr, it is determined to be a precursor to failure, and the load is notified of this precursor to failure. The abnormality detection count Ndet_err in the counter circuit memory 47 is then cleared to its initial value and the voltage level of the stop signal line 110 is changed from Low to High.

[0087] In this case, even if the power control IC 100 stops, the counter circuit 40 retains the startup count Npup, the maximum restart count Nmax_pup, and the warning threshold Rth_preerr stored in the counter circuit memory 47. In particular, the maximum restart count Nmax_pup and the warning threshold Rth_preerr can be modified as needed by external processing if they are made rewritable by an external element via a communication signal line or the like.

[0088] Furthermore, since the maximum restart count Nmax_pup and the warning threshold Rth_preerr only need to retain their values ​​even if the power control IC 100 stops, it is acceptable to store these values ​​in a circuit other than the counter circuit 40 (for example, another circuit within the power control IC 100 or memory outside the power control IC 100).

[0089] Furthermore, the maximum number of reboots Nmax_pup and the warning threshold Rth_preerr can be stored in non-volatile memory, allowing the values ​​to be pre-written during manufacturing and fixed during use.

[0090] Using the flowchart in Figure 10, we will explain an example of a startup process that divides processing according to the frequency of anomaly detection in this embodiment.

[0091] The flowchart shown in FIG. 10 is a flow of startup processing that performs a restart a predetermined number of times at startup and can determine a sign of a failure from the abnormal detection frequency.

[0092] Note that, hereinafter, the description will focus on the points different from the processing of Example 2 (FIG. 9).

[0093] The processing from START to step S3 is the same as that of Example 2 (FIG. 9).

[0094] In step S3, when it is determined that the internal characteristic is greater than the abnormal determination threshold voltage Vth_diag and the internal characteristic is normal (OK), the process proceeds to step S4.

[0095] In step S4, the startup count Npup stored in the counter circuit memory 47 is read out and compared with the maximum startup count Nmax_pup. If the startup count Npup is less than the maximum startup count Nmax_pup (<Nmax_pup), the process proceeds to step S5. If the startup count Npup has reached the maximum startup count Nmax_pup (=Nmax_pup), the process proceeds to step S9.

[0096] In step S5, the diagnosis count Ndiag and the abnormal detection count Ndet_err stored in the counter circuit memory 47 are read out, and the abnormal detection frequency Rdet_err is calculated. If the abnormal detection frequency Rdet_err is less than the sign determination threshold value Rth_preerr (<Rth_preerr), the process proceeds to step S6. The processing from step S6 to END is the same as the processing from step S4 to END of Example 2 (FIG. 9).

[0097] If the abnormal detection frequency Rdet_err is greater than or equal to the sign determination threshold value Rth_preerr (≧Rth_preerr), the process proceeds to step S8. The processing from step S8 to step S13 is the same as the processing from step S10 to step S11 of Example 2 (FIG. 9).

[0098] In step S14, the startup count Npup, the number of anomaly detections Ndet_err, and the number of diagnoses Ndiag stored in the counter circuit memory 47 are cleared to their initial values, and the process proceeds to step S15.

[0099] In step S15, after stopping the power control IC 100, the process returns to step S1 and repeats the process from step S1 onward.

[0100] In step S3, if the internal characteristics are below the abnormality detection threshold voltage Vth_diag, it is determined that the internal characteristics are abnormal (NG), and the process proceeds to step S10.

[0101] In step S10, the diagnostic result edge detection unit 41 detects the rising edge of the voltage level of the diagnostic result signal line 106 from Low to High, incrementing the abnormality detection count Ndet_err by 1, storing it in the counter circuit memory 47, and proceeding to step S4.

[0102] In step S9, the startup count Npup stored in the counter circuit memory 47 is counted up, and the process proceeds to step S11. The processing in steps S11 and S12 is the same as the processing in steps S8 and S9 of Example 2 (Figure 9).

[0103] As explained above, the power control IC 100 in this embodiment determines the abnormality detection frequency by performing a fixed number of restarts at startup, and if the abnormality detection frequency is above the predictive threshold, it can be determined that there is a precursor to failure. [Examples]

[0104] Referring to Figures 11 to 14, a power supply control IC according to Embodiment 4 of the present invention and its diagnostic method will be described.

[0105] This embodiment describes a configuration and operation example that allows for correction of the characteristics in which abnormalities are detected according to the frequency of abnormality detection, detection of whether the corrected characteristics have improved based on the frequency of abnormality detection, and setting a flag when the amount of characteristic variation over time exceeds a predetermined value. The following description will focus on the differences from Embodiment 2.

[0106] Figure 11 is a block diagram showing the configuration of the power control IC 100 in this embodiment. Focusing on the differences from Embodiment 2 (Figure 7), the power control IC 100 in this embodiment further includes a characteristic control circuit 60 that controls the characteristic values ​​of the internal characteristics based on the abnormality detection frequency Rdet_err.

[0107] An example of the characteristic control circuit 60 in this embodiment is the configuration shown in Figure 12. The characteristic control circuit 60 shown in Figure 12 includes a characteristic adjustment circuit 61 that determines the amount of correction of the internal characteristics based on the abnormality detection frequency Rdet_err, a correction circuit 63 that can correct the characteristic value of the internal characteristics with a fixed correction resolution based on the correction signal output by the characteristic adjustment circuit 61, and a characteristic control circuit memory 62 that stores the correction signal calculated by the characteristic adjustment circuit 61. An example of a circuit mounted on the characteristic adjustment circuit 61 is an up / down counter circuit.

[0108] The up / down counter circuit counts up when the voltage level of the correction request signal line 116 transitions from Low to High while a High signal is input to the correction polarity signal line 117, and counts down when the voltage level of the correction request signal line 116 transitions from Low to High while a Low signal is input to the correction polarity signal line 117. The count value is output as the correction amount to the characteristic control circuit memory 62. The correction circuit 63 reads the correction amount stored in the characteristic control circuit memory 62 at startup and performs correction according to the correction amount.

[0109] Figure 13 shows the operation of correcting the characteristic value of the output voltage of the power supply circuit 10 based on the abnormality detection frequency Rdet_err. The correction circuit 63 is assumed to be capable of correction with a correction resolution Dcomp.

[0110] At time t1, as the voltage value approaches the low voltage threshold due to temporal characteristic fluctuations, the anomaly detection frequency Rdet_err increases, and when it exceeds the predictive threshold, the counter circuit 40 determines it to be a precursor to a failure.

[0111] When the abnormality diagnosed as a precursor to a malfunction is a low voltage anomaly in the output voltage, the counter circuit 40 outputs High to the correction polarity signal line 117 and High to the correction request signal line 116. The characteristic adjustment circuit 61 counts up the correction amount and stores the correction amount as 1 in the characteristic control circuit memory 62. The correction circuit 63 reads the correction amount of 1 from the characteristic control circuit memory 62 and applies the correction resolution Dcomp.

[0112] At time t2, if the counter circuit 40 detects a potential fault, the characteristic adjustment circuit 61 increments the correction amount and stores it as 2 in the characteristic control circuit memory 62. The correction circuit 63 reads the correction amount of 2 from the characteristic control circuit memory 62 and applies 2 (correction amount) × correction resolution Dcomp.

[0113] Furthermore, if the already corrected amount reaches the maximum corrected value Dmax_comp, the characteristic control circuit 60 sets the voltage level of the maximum corrected signal line 112 to High, and the counter circuit memory 47 stores the voltage level (High or Low) of the maximum corrected signal line 112.

[0114] Furthermore, by providing a mechanism that detects when a High signal is output to the maximum correction signal line 112 using one of the components within the ECU, it is possible to notify the vehicle user or others that the power control IC 100 or the component in the vehicle that houses the power control IC 100 needs to be replaced.

[0115] Figure 13 shows an example of a low voltage anomaly. If the anomaly diagnosed as a precursor to a fault is an overvoltage anomaly, the counter circuit 40 outputs Low to the correction polarity signal line 117 and High to the correction request signal line 116. The characteristic adjustment circuit 61 then counts down the correction amount and performs a correction to lower the output voltage.

[0116] An example of the startup process for the power control IC 100 in this embodiment (Figure 11) will be explained using the flowchart in Figure 14.

[0117] The flowchart shown in Figure 14 describes the startup process, which involves correcting internal characteristics identified as signs of failure during the startup process, restarting the system, not enabling the power supply circuit 10 unless the abnormality detection frequency Rdet_err improves to less than the sign detection threshold Rth_preerr, and setting the maximum correction signal to High if the correction amount Dcomp reaches the maximum correction value Dmax_comp.

[0118] The following explanation will focus on the differences from the process in Example 3 (Figure 10).

[0119] In step S2, the correction amount Dcomp of the characteristic control circuit memory 62 is applied, and the process proceeds to step S3.

[0120] Steps S3, S5, and S7 through to the END are the same as the steps S3 through to the END in Example 3 (Figure 10).

[0121] Furthermore, the processes in steps S6, S4, S16, and S17 are the same as the processes in steps S9 to S12 of Example 3 (Figure 10).

[0122] In step S10, the correction amount Dcomp to be applied during the next restart is calculated for the characteristics in which an abnormality was detected during the startup diagnosis, and the process proceeds to step S11.

[0123] In step S11, the correction amount Dcomp is stored in the characteristic control circuit memory 62, and the process proceeds to step S12.

[0124] In step S12, the correction amount Dcomp is compared with the maximum correction value Dmax_comp. If the correction amount Dcomp has reached the maximum correction value Dmax_comp (= Dmax_comp), the process proceeds to step S13. If the correction amount Dcomp has not reached the maximum correction value Dmax_comp (< Dmax_comp), the process proceeds to step S16.

[0125] In step S13, the voltage level of the maximum correction signal line 112 is switched from Low to High. The counter circuit memory 47 stores the maximum correction signal with the rising of the voltage level of the maximum correction signal line 112, and the process proceeds to step S14.

[0126] In step S14, the power supply circuit 10 is enabled, and the process proceeds to step S15.

[0127] In step S15, the maximum correction signal and the indication of a potential failure are notified to the user, and the process proceeds to step S18.

[0128] In step S18, after performing the stop process of the power control IC 100, the process returns to step S1, and the processes after step S1 are repeated.

[0129] As described above, the power control IC 100 of this embodiment applies correction to the characteristics in which an abnormality is detected according to the abnormality detection frequency, detects whether the characteristics after correction are improved by the abnormality detection frequency, and further sets a flag when the amount of characteristic variation over time becomes a predetermined value or more.

Embodiment

[0130] Referring to FIGS. 15 and 16, a power control IC and its diagnostic method according to Embodiment 5 of the present invention will be described.

[0131] In this embodiment, we describe a configuration and operation example in which the internal characteristics of the power supply control IC are controlled during startup diagnosis, and then the internal characteristics are returned to their state before startup diagnosis after startup diagnosis. This makes it easier to detect abnormalities before a failure occurs in the power supply control IC compared to when it is not controlled during startup diagnosis. The following description will focus on the differences from Embodiment 4.

[0132] Figure 15 is a block diagram showing the configuration of the power control IC 100 in this embodiment. Focusing on the differences from Embodiment 4 (Figure 11), the characteristic control circuit 60 is configured to connect the correction request signal line 116 to the diagnostic signal line 105, and further includes a characteristic control circuit 60 that controls the internal characteristics to approach the diagnostic threshold during the diagnostic period.

[0133] As an example of the configuration of the characteristic control circuit 60 in this embodiment, in a configuration conforming to Figure 12, a possible configuration is one that includes a correction circuit 63 that controls the internal characteristics to approach a diagnostic threshold according to a control amount in the characteristic control circuit memory 62 during the period when the voltage level of the diagnostic signal line 105 of the startup diagnostic circuit 31 is High, and a characteristic control circuit memory 62 that stores the control amount.

[0134] An example of the startup process for the power control IC 100 in this embodiment (Figure 15) will be explained using the flowchart in Figure 16.

[0135] The flowchart shown in Figure 16 represents a startup process flow that makes it easier to detect abnormalities compared to a case where there is no control, by controlling the internal characteristics to be close to the diagnostic threshold only during the startup diagnostic period.

[0136] The following explanation will focus on the differences from the process in Example 4 (Figure 14).

[0137] In step S2, the internal characteristics of the power control IC 100 are controlled to approach the diagnostic threshold before the startup diagnosis, and then the process proceeds to step S3.

[0138] In step S3, the startup diagnostic circuit 31 compares the internal characteristics with the abnormality detection threshold voltage Vth_diag. If the internal characteristics are greater than the abnormality detection threshold voltage Vth_diag and the internal characteristics are determined to be normal (OK), the circuit proceeds to step S4.

[0139] In step S4, the characteristics that were controlled after the startup diagnosis are returned to their characteristics before control, and the process proceeds to step S5.

[0140] The process from step S5 to END is the same as the process from step S7 to END in Example 4 (Figure 14).

[0141] On the other hand, in step S3, if the internal characteristics are below the abnormality detection threshold voltage Vth_diag, it is determined that the internal characteristics are abnormal (NG), and the process proceeds to step S8.

[0142] In step S8, the characteristics that were controlled after the startup diagnosis are returned to their characteristics before control, and the process proceeds to step S9.

[0143] In step S9, the diagnostic result edge detection unit 41 detects the rising edge of the voltage level of the diagnostic result signal line 106 from Low to High, incrementing the abnormality detection count Ndet_err by 1, storing it in the counter circuit memory 47, and proceeding to step S10.

[0144] The processing in steps S10 and S11 is the same as the processing in steps S16 and S17 of Example 4 (Figure 14).

[0145] In step S5, if the anomaly detection frequency Rdet_err is greater than or equal to the warning threshold Rth_preerr (≧Rth_preerr), proceed to step S12.

[0146] In step S12, after stopping the power control IC 100, the process returns to step S1 and repeats the process from step S1 onward.

[0147] As described above, the power supply control IC 100 in this embodiment controls its internal characteristics to approach the diagnostic threshold only during the startup diagnostic period, and then performs the startup diagnostic. This makes it easier to detect abnormalities before a failure occurs in the power supply control IC during the startup diagnostic. Furthermore, after the startup diagnostic, the internal characteristics are returned to their pre-control state, ensuring a margin of safety relative to the diagnostic threshold. [Examples]

[0148] Referring to Figures 17 and 18, a power control IC according to Embodiment 6 of the present invention and its diagnostic method will be described.

[0149] In this embodiment, the setting information of previously configured terminals is stored in memory, and the validity of the terminal setting detected at startup is determined by comparing it with the previously configured terminal setting. If the determination result does not match, the setting information is reread through a restart process, thereby enabling the distinction between misdiagnosis due to accidental abnormalities caused by the environment and settings that have been intentionally changed. This configuration and operation example will be described below. The following description will focus on the differences from Embodiment 2 (Figure 7).

[0150] Figure 17 is a block diagram showing the configuration of the power control IC 100 in this embodiment. Focusing on the differences from Embodiment 2 (Figure 7), the power control IC 100 in this embodiment further includes a setting terminal 115 that sets a predetermined setting (hereinafter referred to as internal setting) within the power control IC 100 according to the voltage level (High or Low) input at startup, and a memory 70 that stores past terminal setting Dpre_set set at past startups, and the comparison circuit 32 in the startup diagnostic circuit 31 compares the terminal setting Dset detected at startup with the past terminal setting Dpre_set.

[0151] The comparison circuit 32 compares the past terminal setting Dpre_set with the setting terminal Dset read out in the startup process. If they match, the content of the terminal setting Dset is reflected in the internal setting. If they do not match, the abnormal detection count Ndet_err is incremented, and the startup diagnosis circuit 31 outputs High to the restart signal line 101. When the abnormal detection count Ndet_err reaches the startup determination threshold count Nth_pup, it is determined that it is not a misdiagnosis due to environmental factors, and the terminal setting Dset is reflected in the power control IC 100.

[0152] Using the flowchart of FIG. 18, an example of the startup process of the power control IC 100 of this embodiment (FIG. 17) will be described.

[0153] The flowchart shown in FIG. 18 is a flowchart of the startup process for detecting an abnormality in the terminal setting Dset during startup diagnosis and performing restart.

[0154] Note that hereinafter, the description will focus on the points different from the process of Embodiment 2 (FIG. 9).

[0155] In step S2, the terminal setting Dset is detected from the potential of the setting terminal 115, and the process proceeds to step S3.

[0156] In step S3, the abnormal detection count Ndet_err is read from the memory 70. If the abnormal detection count Ndet_err is less than the startup determination threshold count Nth_pup (<Nth_pup), the process proceeds to step S4. If the abnormal detection count Ndet_err reaches the startup determination threshold count Nth_pup (=Nth_pup), the process proceeds to step S5.

[0157] In step S4, the terminal setting Dset and the past terminal setting Dpre_set are compared by the comparison circuit 32. If they match, the process proceeds to step S5. If they do not match, the process proceeds to step S7.

[0158] The processing from step S5 to END is the same as the processing from step S4 to END of Embodiment 2 (FIG. 9).

[0159] In step S7, the number of anomaly detections, Ndet_err, is counted up and stored in memory 70, and the process proceeds to step S8.

[0160] The processing in steps S8 and S9 is the same as the processing in steps S8 and S9 of Example 2 (Figure 9).

[0161] In this embodiment, we have shown an example in which the validity of the detected terminal setting can be determined by storing the past terminal setting Dpre_set in memory 70 and comparing the terminal setting Dset detected at startup with the past terminal setting Dpre_set in memory 70. However, other configurations are also possible. For example, a configuration in which the value of non-volatile memory is used as the comparison target can be considered, and the validity of the detected terminal setting can be determined by comparing it with the expected value of the terminal setting that was prewritten during manufacturing.

[0162] As described above, the power control IC 100 in this embodiment stores previously set terminals in memory, and determines the validity of the terminal settings by comparing the terminal settings detected at startup with the previously set terminal settings. If the determination results do not match, the setting information can be reread by restarting the system. Furthermore, if the number of startup determination thresholds does not match, it can be determined that the terminal settings have been intentionally changed, and the terminal settings can be reflected in the power control IC. [Examples]

[0163] Referring to Figures 19 to 21, a power control IC according to Embodiment 7 of the present invention and its diagnostic method will be described.

[0164] This embodiment describes a configuration and operation example that allows for optimal restart while suppressing the restart process time by enabling the selection of the process to be executed and the number of times it is executed during the restart process. The following description will focus on the differences from Embodiment 6 (Figure 17).

[0165] Figure 19 is a block diagram showing the configuration of the power control IC 100 in this embodiment. Focusing on the differences from Embodiment 6 (Figure 17), the power control IC 100 in this embodiment further includes a restart setting circuit 50 that can set the reading process and diagnostic process of setting pins performed in the restart process, as well as the number of times each process is performed.

[0166] The restart setting circuit 50 is connected to the diagnostic result signal line 106 of the startup diagnostic circuit 31 and sets the startup and shutdown processes to be performed during restart according to the diagnostic result. Furthermore, by connecting the restart setting circuit 50 to the startup circuit 20 with the re-diagnosis signal line 113 and the reset pin read signal line 114, it is possible to control the process of repeating the process.

[0167] The counter circuit 40 stores the number of times the setting terminal has been read and the number of diagnostic tests in memory, respectively, and outputs them to the restart setting circuit 50 when the system starts up. Note that setting the number of executions to 0 will disable the process.

[0168] An example of the restart setting circuit 50 in this embodiment is the configuration shown in Figure 20. The restart setting circuit 50 shown in Figure 20 consists of a restart setting circuit memory 51 in which the target diagnostic count Ndiag_target and the target terminal setting read count Npinread_target are stored, a comparison circuit 52a that compares the diagnostic count Ndiag output from the counter circuit 40 with the target diagnostic count Ndiag_target stored in the counter circuit memory 47, and a comparison circuit 52b that compares the terminal setting read count Npinread output from the counter circuit 40 with the target terminal setting read count Npinread_target stored in the counter circuit memory 47.

[0169] An example of the restart process of the power control IC 100 in this embodiment (Figure 19) will be explained using the flowchart in Figure 21.

[0170] The flowchart shown in Figure 21 represents the startup process, in which only the steps where an abnormality is detected during the reading of the setting terminal 115 and the startup diagnosis are repeated.

[0171] Hereinafter, the description will focus on the points different from the process of Example 6 (FIG. 18).

[0172] In step S4, the terminal setting read count Npinread is incremented. The terminal setting Dset is compared with the past terminal setting Dpre_set. If they match, the process proceeds to step S6. If they do not match, the process proceeds to step S5.

[0173] In step S5, the abnormality detection count Ndet_err is incremented, stored in the memory 70, and the process proceeds to step S6.<于 (原文中此标签似乎有误,推测为 ,按原文保留)

[0174] In step S6, the diagnosis count Ndiag and the target diagnosis count Ndiag_target are read and compared. If the diagnosis count Ndiag is less than the target diagnosis count Ndiag_target (<Ndiag_target), the process proceeds to step S7. If the diagnosis count Ndiag has reached the target diagnosis count Ndiag_target (=Ndiag_target), the process proceeds to step S9.

[0175] In step S7, the startup diagnosis circuit 31 compares the internal characteristics with the abnormality determination threshold voltage Vth_diag. If the internal characteristics are greater than the abnormality determination threshold voltage Vth_diag and it is determined that the internal characteristics are normal (OK), the process proceeds to step S9. If the internal characteristics are below the abnormality determination threshold voltage Vth_diag, it is determined that the internal characteristics are abnormal (NG), and the process proceeds to step S8.

[0176] In step S8, by detecting the rising edge from Low to High of the voltage level of the diagnosis result signal line 106 by the diagnosis result edge detection unit 41, the abnormality detection count Ndet_err is incremented by one, stored in the counter circuit memory 47, and the process proceeds to step S9.

[0177] In step S9, if the number of diagnoses Ndiag is less than the target number of diagnoses Ndiag_target, output High to the re-diagnosis signal line 113. If the number of terminal setting readings Npinread is less than the target number of terminal setting readings Npinread_target, output High to the re-setting pin read signal line 114, and proceed to step S14. On the other hand, if the number of diagnoses Ndiag has reached the target number of diagnoses Ndiag_target and the number of terminal setting readings Npinread has reached the target number of terminal setting readings Npinread_target, proceed to step S10.

[0178] In step S14, read and compare the number of terminal setting readings Npinread and the target number of terminal setting readings Npinread_target. If the number of terminal setting readings Npinread is less than the target number of terminal setting readings Npinread_target (<Npinread_target), proceed to step S3. On the other hand, if the number of terminal setting readings Npinread has reached the target number of terminal setting readings Npinread_target (=Npinread_target), proceed to step S6.

[0179] In step S10, if the number of anomaly detections Ndet_err is less than the activation determination threshold number Nth_pup (<Nth_pup), proceed to step S11. If the number of anomaly detections Ndet_err has reached the activation determination threshold number Nth_pup (=Nth_pup), proceed to step S15.

[0180] The processing from step S11 to END is the same as the processing from step S5 to END in Example 6 (Fig. 18).

[0181] The processing in step S15 is the same as the processing in step S9 in Example 6 (Fig. 18).

[0182] In this embodiment, a restart setting circuit is mounted inside the power control IC 100, and the diagnostic results of the diagnostic circuit are used as input to set the startup and shutdown processes to be performed during restart according to the startup diagnostic results. However, other configurations are also possible.

[0183] For example, by configuring the system to input restart settings via a communication interface circuit, subsequent restart processes can be set in response to abnormalities detected during the operation of circuits outside the power control IC 100 (e.g., the CPU). Alternatively, the restart settings can be pre-configured during manufacturing by storing the process to be executed during the restart process and the number of times that process has been executed in non-volatile memory.

[0184] As described above, the power control IC 100 in this embodiment allows the user to select the process to be executed and the number of times it is executed during the restart process, thereby enabling optimal restart while suppressing the restart process time.

[0185] As described in each embodiment, using the power control IC according to the present invention makes it possible to notify the user of component replacement before the power control IC fails, allowing it to be used closer to the end of its lifespan compared to power control ICs that do not have predictive detection capabilities. Furthermore, since the power control IC can be used for a longer period through predictive detection without using an ECU housing with high heat dissipation, such as the one described in Patent Document 1, the operating time of the ECU housing can be extended while also reducing costs. Moreover, by combining an ECU housing with high heat dissipation with predictive detection, the operating time can be extended even further. In addition, by incorporating a mechanism to correct for characteristics where the frequency of abnormality detection increases, the period until component replacement can be extended even further, and costs can be reduced by reducing the number of replacements and inspections.

[0186] It should be noted that the present invention is not limited to the embodiments described above, and various modifications are included. For example, the embodiments described above are described in detail to make the present invention easier to understand, and are not necessarily limited to those having all the configurations described. Furthermore, it is possible to replace parts of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add configurations from other embodiments to the configuration of one embodiment. In addition, it is possible to add, delete, or replace parts of the configuration of each embodiment with other configurations. [Explanation of Symbols]

[0187] 1…ECU, 2…Ignition switch (IG-SW), 10…Power supply circuit, 11,24…Switching element, 12a,12b…Linear regulator, 13…Reference voltage generation unit, 14…MOSFET, 15…Error amplifier, 16,17…Feedback resistor, 20…Startup circuit, 21…Startup signal detection unit, 22…Diagnostic signal generation unit, 23…Control signal generation unit, 25a,25b,25c…NOT circuit, 26a,26b,26c…Delay circuit, 27 a, 27b...AND circuit, 30...Internal processing unit, 31...Startup diagnostic circuit, 32...Anomaly determination unit (comparison circuit), 33...Diagnostic control unit, 34...Filter circuit, 40...Counter circuit, 41...Diagnostic result edge detection unit, 42...Diagnostic signal edge detection unit, 44...Anomaly detection counter circuit, 45...Diagnostic counter circuit, 46...Anomaly detection frequency determination unit, 47...Memory for counter circuit, 50...Restart setting circuit, 51...Memory for restart setting circuit, 52a,52b...Comparison circuit, 60...Characteristic control circuit, 61...Characteristic adjustment circuit, 62...Memory for characteristic control circuit, 63...Correction circuit, 70...Memory, 100...Power supply control IC, 101...Restart signal line, 102...Start signal line, 103...Power line, 104...Control signal line, 105...Diagnostic signal line, 106...Diagnostic result signal line, 107...Internal voltage line, 108...Output voltage line, 109...Communication signal line, 110...Stop signal line, 111...Signal under diagnosis line, 112...Maximum correction Signal line, 113... Re-diagnosis signal line, 114... Reset pin read signal line, 115... Setting terminal, 116... Correction request signal line, 117... Correction polarity signal line, 118... Diagnosis count signal line, 119... Terminal setting read count signal line, 200... CPU, Vpower... Power supply voltage, Vth_pup... Start signal judgment threshold voltage, Voperate_min... Minimum operating voltage, Voutput... Output voltage, Vref... Reference voltage, Vfb... Feedback voltage, Vinterna l…Internal voltage, Vth_diag…Low voltage anomaly detection threshold voltage, Srepup…Restart signal, Spup…Start signal, Spdown…Stop signal, Spower_en…Control signal, Sdiff…Differential signal, Sdiag…Diagnostic signal, Smax_comp…Maximum correction signal, Ndiag…Number of diagnoses, Ndet_err…Number of anomaly detections, Nth_pup…Number of start-up determination threshold counts, Npup…Number of starts, Nmax_pup…Maximum number of starts, Nerr_set…Number of terminal setting anomalies, Npinread…Number of terminal setting reads, Ndiag_target…Target diagnosis count, Npinread_target…Target terminal setting read count, Rdet_err…Anomaly detection frequency, Rth_pup…Start-up determination threshold frequency, Rth_preerr…Predictive judgment threshold, Dset…Terminal setting, Dpre_set…Past terminal setting, Dcomp…Correction resolution (correction amount), Dmax_comp…Maximum correction value.

Claims

1. A power supply circuit that generates at least one voltage from the power supply voltage, A start pin for starting the aforementioned power supply circuit, A startup circuit that performs a restart process for the power supply circuit based on a restart signal when a predetermined voltage is input to the startup pin, A diagnostic circuit that performs a self-diagnosis of the power control IC when the power supply circuit is started, A counter circuit that counts the number of diagnoses and the number of abnormalities detected in the diagnostic circuit, The power control IC comprising, When a startup abnormality in the power supply circuit or an abnormality detected by the diagnostic circuit is detected, a restart signal is sent to the startup circuit. The counter circuit calculates the anomaly detection frequency, which is the ratio of the number of anomaly detections to the number of diagnostics. Regardless of the operation of the power supply circuit, the number of diagnostics and the number of abnormality detections are maintained. A power control IC that determines a malfunction to be a precursor or a malfunction when the frequency of abnormality detection is greater than a predetermined value.

2. A power control IC according to claim 1, A power control IC that repeatedly restarts the system until no abnormalities are detected after the last boot-up if an abnormality occurs.

3. A power control IC according to claim 1, A power control IC that performs the aforementioned restart process a predetermined number of times.

4. A power control IC according to claim 1, The counter circuit is a power control IC that calculates the abnormality detection frequency from the number of startups, three or more times.

5. A power control IC according to claim 1, A power control IC equipped with a notification function that notifies an external party when any of the following is detected: the restart signal, the startup abnormality, the abnormality detected by the diagnostic circuit, the precursor of the failure, or the failure.

6. A power control IC according to claim 1, A characteristic control circuit that calculates a correction amount when the frequency of abnormality detection exceeds the predetermined value, A storage unit for storing the correction amount, The system includes a correction circuit that corrects the characteristic value in which an abnormality has been detected according to the aforementioned correction amount, The counter circuit is a power control IC that determines that the characteristic value in which an abnormality was detected has been corrected when the frequency of abnormality detection after applying the correction amount is lower than the frequency of abnormality detection before applying the correction amount.

7. A power control IC according to claim 1, It is equipped with a control circuit that controls predetermined characteristic values, The control circuit is a power control IC that controls the predetermined characteristic value during the startup diagnostic period to make it more likely for an abnormality to occur.

8. A power control IC according to claim 1, A setting terminal that determines a predetermined setting value according to the voltage value input at startup, A memory that stores past setting values ​​of the aforementioned setting terminal, The system includes a comparison circuit that compares the predetermined set value with the past set value, The memory retains the stored values ​​regardless of the operation of the power supply circuit. The diagnostic circuit is a power control IC that sends a restart signal to the startup circuit according to the comparison result in the comparison circuit.

9. A power control IC according to claim 1, The system includes a restart setting circuit that allows setting the number of executions for each process of the restart process, A power control IC that, when executing the aforementioned restart process, executes the process set for each process a predetermined number of times.

10. (a) A step of inputting a startup signal for the power control IC, (b) In step (a), when a start signal is input, the step of outputting a diagnostic signal, (c) In step (b), when a diagnostic signal is output, the diagnostic count of the diagnostic circuit is incremented by one and stored in memory. (d) A step of performing a startup diagnosis of the power control IC, (e) If an abnormality is detected in step (d) above, the number of abnormality detections in the diagnostic circuit is incremented by one and stored in the memory, (f) A step of reading the number of diagnostics and the number of anomaly detections from the memory and calculating the frequency of anomaly detection, (g) A step of comparing the anomaly detection frequency calculated in step (f) above with a predetermined threshold, It has, A method for diagnosing a power control IC, wherein in step (g), if the frequency of abnormality detection is less than the predetermined threshold, it is determined to be normal and a restart signal for the power control IC is output, and if the frequency of abnormality detection is equal to or greater than the predetermined threshold, it is determined to be a sign of failure and a notification of the sign of failure is output.

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