Paste for manufacturing multilayer ceramic capacitors and bumps for multilayer ceramic capacitors

Abstract

Provided are: a layered ceramic capacitor with improved adhesion between a capacitor body and bumps; and a paste for manufacturing bumps. This layered ceramic capacitor 1 comprises: a layered body 2 in which a dielectric layer 14 and an inner electrode layer 15 are layered in alternation; an outer electrode layer 3 that is disposed on each of two end surfaces at both longitudinal ends of the layered body 2, that covers the end-surface side of two principal surfaces at both layering-direction ends of the layered body and the end-surface side of two side surfaces at both width-direction ends thereof, and that connects to the inner electrode layer; and a bump 4 that is disposed on each of the two end-surface sides of one of the two principal surfaces of the layered body 2 so as to sandwich the outer electrode layer covering the principal-surface side therebetween. The bump includes copper Cu that accounts for 50-96% of an area of a cross-section passing through the width-direction center of the bump 4 and extending in the layering direction and the longitudinal direction.

Description

Technical Field

[0001] The present invention relates to a multilayer ceramic capacitor and a paste for manufacturing bumps.

Background Art

[0002] A multilayer ceramic capacitor has an inner layer portion in which dielectric layers and internal electrodes are alternately stacked. Then, dielectric layers as outer layer portions are disposed above and below the inner layer portion to form a rectangular parallelepiped laminate, and external electrodes are provided on both end faces in the longitudinal direction of the laminate to form a capacitor body. Furthermore, in order to suppress the occurrence of so-called "whining", a multilayer ceramic capacitor provided with bumps formed so as to cover a part of an external electrode on the side of the capacitor body mounted on a substrate is known (see Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, conventionally, the adhesive force between the capacitor body and the bumps was weak, and the bumps might peel off from the capacitor body.

[0005] An object of the present invention is to provide a multilayer ceramic capacitor and a paste for manufacturing bumps in which the adhesive force between the capacitor body and the bumps is improved.

Means for Solving the Problems

[0006] To solve the above problems, the present invention provides a multilayer ceramic capacitor comprising: a laminate in which dielectric layers and internal electrode layers are alternately stacked; an external electrode layer disposed on each of two end faces provided at both ends in the longitudinal direction intersecting the stacking direction of the laminate, covering the end face sides of the two main faces provided at both ends in the stacking direction of the laminate, and the end face sides of the two side surfaces provided at both ends in the width direction intersecting the stacking direction and the longitudinal direction, and connecting to the internal electrode layer; and a bump disposed on each of the two end face sides of one of the two main faces of the laminate, sandwiching the external electrode layer that covers the main face side, wherein the bump contains copper that occupies 50% to 96% of the area in a cross-section that passes through the center of the bump in the width direction and extends in the stacking direction and the longitudinal direction.

[0007] Furthermore, in order to solve the above problems, the present invention provides a paste for manufacturing bumps for multilayer ceramic capacitors, comprising copper powder, epoxy resin, and solvent, and not containing curing agents such as phenolic resin or imidazole. [Effects of the Invention]

[0008] According to the present invention, it is possible to provide a multilayer ceramic capacitor and a bump manufacturing paste in which the adhesive strength between the capacitor body and the bump is improved. [Brief explanation of the drawing]

[0009] [Figure 1] This is a schematic perspective view of the multilayer ceramic capacitor 1 of the embodiment. [Figure 2] This is a cross-sectional view of the multilayer ceramic capacitor 1 of the embodiment along the line II-II in Figure 1. [Figure 3] This is a cross-sectional view of the multilayer ceramic capacitor 1 of the embodiment along the line III-III in Figure 1. [Figure 4] This is a flowchart illustrating the manufacturing method of the multilayer ceramic capacitor 1. [Figure 5]This diagram illustrates the laminate manufacturing process S1 and the base electrode layer formation process S2. [Figure 6] This diagram illustrates the bump placement process S3 and the plating layer formation process S4. [Modes for carrying out the invention]

[0010] A multilayer ceramic capacitor 1 according to an embodiment of the present invention will now be described. Figure 1 is a schematic perspective view of the multilayer ceramic capacitor 1 according to the embodiment. Figure 2 is a cross-sectional view of the multilayer ceramic capacitor 1 according to the embodiment along the line II-II in Figure 1. Figure 3 is a cross-sectional view of the multilayer ceramic capacitor 1 according to the embodiment along the line III-III in Figure 1.

[0011] The multilayer ceramic capacitor 1 has a substantially rectangular parallelepiped shape and comprises a capacitor body 1A having a laminate 2 and a pair of external electrode layers 3 provided at both ends of the laminate 2, and a bump 4 attached to the capacitor body 1A. The laminate 2 also includes an inner layer portion 11 which includes multiple sets of dielectric layers 14 and internal electrode layers 15.

[0012] In the following description, the orientation of the multilayer ceramic capacitor 1 is described as follows: The direction in which the pair of external electrode layers 3 are provided in the multilayer ceramic capacitor 1 is defined as the length direction L. The direction in which the dielectric layer 14 and the internal electrode layer 15 are stacked is defined as the stacking direction T. The direction that intersects both the length direction L and the stacking direction T is defined as the width direction W. In this embodiment, the width direction W is perpendicular to both the length direction L and the stacking direction T. Figure 2 shows a cross-section of the multilayer ceramic capacitor 1 that passes through the center in the width direction W and extends in the length direction L and the stacking direction T.

[0013] (Outer surface of laminate 2) Among the six outer surfaces of the laminate 2, a pair of outer surfaces facing each other in the lamination direction T are defined as the first main surface A1 and the second main surface A2, a pair of outer surfaces facing each other in the width direction W are defined as the first side surface B1 and the second side surface B2, and a pair of outer surfaces facing each other in the length direction L are defined as the first end surface C1 and the second end surface C2. When there is no need to particularly distinguish and explain the first main surface A1 and the second main surface A2, they are collectively referred to as the main surface A. When there is no need to particularly distinguish and explain the first side surface B1 and the second side surface B2, they are collectively referred to as the side surface B. When there is no need to particularly distinguish and explain the first end surface C1 and the second end surface C2, they are collectively referred to as the end surface C for explanation.

[0014] The laminate 2 preferably has rounded edges at the ridge line portion R1 including the corners. The ridge line portion R1 is the portion where two surfaces of the laminate 2, that is, the main surface A and the side surface B, the main surface A and the end surface C, or the side surface B and the end surface C intersect.

[0015] (Laminate 2) The laminate 2 includes a laminate body 10 including an inner layer portion 11 and outer layer portions 12 respectively disposed on both sides of the inner layer portion 11 in the lamination direction T, and side gap portions 16 provided on both sides of the laminate body 10 in the width direction W.

[0016] (Inner layer portion 11) The inner layer portion 11 includes a plurality of sets of dielectric layers 14 and internal electrode layers 15 laminated alternately along the lamination direction T.

[0017] The dielectric layer 14 is made of a ceramic material. As the ceramic material, for example, a dielectric ceramic mainly composed of BaTiO3 is used.

[0018] The internal electrode layer 15 includes a plurality of first internal electrode layers 15a and a plurality of second internal electrode layers 15b. The first internal electrode layers 15a and the second internal electrode layers 15b are arranged alternately. The first internal electrode layer 15a includes a first opposing portion 152a that faces the second internal electrode layer 15b, and a first lead-out portion 151a that is drawn out from the first opposing portion 152a toward the first end face C1. The end of the first lead-out portion 151a is exposed on the first end face C1 and is electrically connected to the first external electrode layer 3a described later. The second internal electrode layer 15b includes a second opposing portion 152b that faces the first internal electrode layer 15a, and a second lead-out portion 151b that is drawn out from the second opposing portion 152b toward the second end face C2. The end of the second lead-out portion 151b is electrically connected to the second external electrode layer 3b described later. Electric charges are accumulated in the first opposing portion 152a of the first internal electrode layer 15a and the second opposing portion 152b of the second internal electrode layer 15b.

[0019] The internal electrode layer 15 is preferably formed of a metal material typified by, for example, nickel (Ni), copper (Cu), silver (Ag), palladium (Pd), silver-palladium (Ag-Pd) alloy, gold (Au), and the like.

[0020] (Outer layer portion 12) The outer layer portion 12 is manufactured from the same material as the dielectric layer 14 of the inner layer portion 11.

[0021] (Side gap portion 16) The side gap portion 16 includes a first side gap portion 16a provided on the side B side of the laminate body 10, and a second side gap portion 16b provided on the second side B2 side of the laminate body 10. The side gap portion 16 is manufactured from the same material as the dielectric layer 14.

[0022] (External electrode layer 3) The external electrode layer 3 includes a first external electrode layer 3a provided on the first end face C1 and a second external electrode layer 3b provided on the second end face C2. The external electrode layer 3 covers not only the end face C but also a part of the main face A and the end face C side of the side face B.

[0023] As described above, the end of the first lead portion 151a of the first internal electrode layer 15a is exposed to the first end face C1 and electrically connected to the first external electrode layer 3a. Similarly, the end of the second lead portion 151b of the second internal electrode layer 15b is exposed to the second end face C2 and electrically connected to the second external electrode layer 3b. As a result, the structure between the first external electrode layer 3a and the second external electrode layer 3b is such that multiple capacitor elements are electrically connected in parallel.

[0024] Furthermore, the external electrode layer 3 includes the base electrode layer 30 and the plating layer 32.

[0025] The base electrode layer 30 includes, for example, a conductive metal and glass G. In this embodiment, copper Cu is used as the conductive metal in the base electrode layer 30.

[0026] The plating layer 32 includes a nickel plating layer 32a arranged on the outer periphery of the base electrode layer 30, and a tin plating layer 32b arranged on the outer periphery of the nickel plating layer 32a. However, in the portion where the bump 4 described below is located, the plating layer 32 is arranged on the outer periphery of the bump 4.

[0027] (Bump 4) The bump 4 comprises a pair of first bumps 4a and second bumps 4b. The first bump 4a is located on one end face C1 in the length direction L on the second main surface A2 side, which is the substrate mounting surface of the capacitor body 1A, and the second bump 4b is located on the other end face C2 side. As shown in Figure 2, the first bump 4a and the second bump 4b are positioned approximately symmetrically across a center line that passes through the center in the length direction L and extends in the width direction W, and are spaced a certain distance apart in the length direction L.

[0028] Bump 4 wraps around to the second main surface A2 and is positioned on the outside of the capacitor body 1A, with the underlying electrode layer 30 of the external electrode layer 3 in between. In addition, on the second main surface A2, bump 4 has a portion that is in direct contact not only with the underlying electrode layer 30 but also with the outer layer portion 12 of the laminate 2.

[0029] Bump 4 contains copper (Cu) as the base metal and gaps 52 within the copper (Cu). The copper (Cu) occupies between 50% and 96% of the area in a cross-section that passes through the center of the bump in the width direction W shown in Figure 2 and extends in the stacking direction T and the length direction L. This area is calculated by exposing the cross-section, imaging it, and binarizing it, then dividing the area of ​​copper (Cu) by the total area. Confirmation that it is copper (Cu) is performed using various methods such as WDX and EDX. In this embodiment, the bump 4 does not contain glass G. The bump 4 may contain a small amount of glass G, but even in that case, the amount of glass contained in the bump 4 is trace compared to the underlying electrode layer 30.

[0030] The outer surface of bump 4, although not shown in the diagram, has a rough surface due to undissolved copper (Cu) particles remaining. Furthermore, nickel (Ni) is present within at least 10 μm of the surface of bump 4. Nickel (Ni) may also be present more than 10 μm from the surface of bump 4.

[0031] (Method for manufacturing a multilayer ceramic capacitor 1) Figure 4 is a flowchart illustrating the manufacturing method of the multilayer ceramic capacitor 1. The manufacturing method of the multilayer ceramic capacitor 1 includes a laminate manufacturing process S1, a base electrode layer formation process S2, a bump placement process S3, and a plating layer formation process S4. Figure 5 is a diagram illustrating the laminate manufacturing process S1 and the base electrode layer formation process S2. Figure 6 is a diagram illustrating the bump placement process S3 and the plating layer formation process S4.

[0032] (Laminate manufacturing process S1) A ceramic slurry containing ceramic powder, a binder, and a solvent is formed into a sheet on the outer circumference of a carrier film using a die coater, gravure coater, microgravure coater, etc. to produce a laminated ceramic green sheet 101 that will become the dielectric layer 14. Next, a conductive paste is printed in strips onto the laminated ceramic green sheet 101 by screen printing, inkjet printing, gravure printing, etc., and a conductive pattern 102 that will become the internal electrode layer 15 is printed on the surface of the laminated ceramic green sheet 101 to produce a printed material sheet 103.

[0033] Next, as shown in Figure 5(a), multiple material sheets 103 are stacked so that the conductive patterns 102 face the same direction and are offset by half a pitch in the width direction between adjacent material sheets 103. Furthermore, outer layer ceramic green sheets 112, which will form the outer layer 12, are stacked on both sides of the multiple stacked material sheets 103.

[0034] Multiple stacked material sheets 103 and the outer layer ceramic green sheet 112 are heat-pressed together to create the mother block 110 shown in Figure 5(b).

[0035] Next, the mother block 110 is cut along the cutting line X and the cutting line Y that intersects cutting line X shown in Figure 5(b) to produce multiple laminates 2 as shown in Figure 5(c).

[0036] (Base electrode layer formation step S2) Next, a conductive paste containing copper Cu, a conductive metal, and glass G is applied to the end face C of the laminate 2 and baked to form a base electrode layer 30. The base electrode layer 30 extends not only to the end faces C on both sides of the laminate 2, but also to the main surface A and side surface B of the laminate 2, and is formed to cover a part of the end face C side of the main surface A.

[0037] (Bump placement process S3) Prepare a bump-making paste 44 for use in bump manufacturing. The bump-making paste is a conductive paste. The bump-making paste 44 contains copper powder (Cu), epoxy resin, and a solvent. The bump-making paste 44 does not contain curing agents such as phenolic resin or imidazole.

[0038] The volume ratio of copper to epoxy resin is between 70% and 90%. The epoxy resin is bisphenol A type epoxy resin.

[0039] The conductive paste Cu contains copper powder with a median diameter d50 of 5 μm to 10 μm in a volume ratio of 55% to 95% relative to copper powder with a median diameter d50 of 0.5 μm to 1.5 μm.

[0040] The solvent is, for example, diethylene glycol monobutyl ether, diethylene glycol monoethyl ether, or diethylene glycol monomethyl ether.

[0041] For forming the bumps 4, a retaining substrate 40, such as the one shown in Figure 6, is used. As shown in Figure 6(a), a bump manufacturing paste 44 is placed on the retaining substrate 40 by screen printing or dispensing. The retaining substrate 40 is preferably made of a material that can withstand the curing temperature of Cu.

[0042] Next, the capacitor body 1A is mounted on the outer circumference of the retaining substrate 40 in the orientation shown in Figure 6(b), with the second main surface A2 facing the retaining substrate 40. At this time, the external electrode layer 3 of the capacitor body 1A and the bump manufacturing paste 44 are aligned, and the bump manufacturing paste 44 adheres to the capacitor body 1A.

[0043] In this state, a heating process is carried out in which the paste is heated to a temperature at which the copper Cu sintersects. This causes the metal in the paste to form intermetallic compounds and harden, creating bumps 4 that are bonded to the capacitor body 1A and the external electrode layer 3. If multiple metals are included, alloys may be formed within the sintered body. Examples of multiple metals include copper Cu and nickel Ni.

[0044] Subsequently, the capacitor body 1A, along with the bump 4, is separated from the retaining substrate 40, resulting in the state shown in Figure 6(c).

[0045] (Plating layer formation process S4) Next, a nickel plating layer 32a is formed on the exposed portion of the base electrode layer 30 of the capacitor body 1A and on the outer circumference of the bump 4, and then a tin plating layer 32b is formed on the outer circumference of the nickel plating layer 32a. A multilayer ceramic capacitor 1 is manufactured through the above process.

[0046] (Effects of the embodiment) Bump 4 contains copper (Cu), and the copper (Cu) occupies 50% to 96% of the area in a cross-section that passes through the center of the width direction W of bump 4 and extends in the lamination direction T and the length direction L. The outer electrode layer 3 includes a base electrode layer 30 containing copper (Cu) and glass (G). Since both the base electrode layer 30 and bump 4 are formed by sintering a conductive paste containing copper (Cu), the bond between the base electrode layer 30 and bump 4 becomes stronger and the adhesive strength is improved.

[0047] Since the outer periphery of the outer electrode layer 3 and bump 4 is provided with nickel plating 32a and tin plating 32b arranged on the outer periphery of the nickel plating 32, the multilayer ceramic capacitor 1 can be firmly attached to the mounting substrate using solder.

[0048] The bump-making paste 44 contains copper powder (Cu), epoxy resin, and a solvent, but does not contain curing agents such as phenolic resin or imidazole. Because the bump-making paste 44 does not contain curing agents, the bonding between the copper powder particles can be strengthened. This improves the strength of the bump 4.

[0049] The volume ratio of copper (Cu) to epoxy resin in the bump manufacturing paste 44 is between 70% and 90%. Because of the high volume ratio of copper (Cu), it exhibits good electrical conductivity.

[0050] (Transformed form) Although embodiments of the present invention have been described above, the present invention is not limited thereto, and various modifications are possible within the scope of the invention.

[0051] For example, the metal contained in the base electrode layer 30 does not have to be copper (Cu). For example, the base electrode layer 30 may be formed by sintering a conductive paste containing a metal such as nickel (Ni). When the metal contained in the outer electrode layer 3 is nickel (Ni), the Ni contained in the base electrode layer 30 and the Cu contained in the bump 4 alloy together to form the sintered portion 51. Furthermore, even if the sintered portion 51 is not formed, if both the base electrode layer 30 and the bump 4 are made of a conductive paste containing metal that has been sintered, the bond between the base electrode layer 30 and the bump 4 will become stronger and the adhesive strength will improve. [Explanation of symbols]

[0052] Cu copper G Glass Ni (nickel) 1. Multilayer ceramic capacitor 1A Capacitor Body 2 Laminate 3 External electrode layer 4 Bump 10 Laminate body 11 Inner layer 12 Outer layer 14 Dielectric layer 15 Internal electrode layer 30 Base electrode layer 32 Plating layer 32a Nickel plating layer 32b Tin plating layer 44 Bump manufacturing paste 51 Sintered part

Claims

1. A laminate in which dielectric layers and internal electrode layers are stacked alternately, An external electrode layer is provided on each of the two end faces provided at both ends in the longitudinal direction intersecting the stacking direction of the laminate, covering the end face sides of the two main faces provided at both ends in the stacking direction of the laminate, and the end face sides of the two side surfaces provided at both ends in the width direction intersecting the stacking direction and the longitudinal direction, and connecting to the internal electrode layer. The laminate comprises, on one of the two main surfaces, each of the two end face sides, with a bump positioned between the external electrode layer covering the main surface side, The bump contains copper that occupies 50% to 96% of the area in a cross-section that passes through the center of the bump in the width direction and extends in the stacking direction and the length direction. The external electrode layer includes a base electrode layer, and the base electrode layer and the bump are sintered. Multilayer ceramic capacitor.

2. Nickel is contained within at least 10 μm of the surface of the bump. The multilayer ceramic capacitor according to claim 1.

3. The external electrode layer includes a base electrode layer containing copper and glass. The underlying electrode layer and the copper contained in the bump are electrically connected. The multilayer ceramic capacitor according to claim 1.

4. The bump has a lower glass content than the underlying electrode layer. The multilayer ceramic capacitor according to claim 3.

5. The outer electrode layer and the outer circumference of the bump, Nickel plating and The system comprises a tin plating arranged on the outer circumference of the nickel plating, A multilayer ceramic capacitor according to any one of claims 1 to 4.

6. The bump has a portion that is directly attached to the laminate. A multilayer ceramic capacitor according to any one of claims 1 to 4.

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