Multilayer ceramic capacitor

Abstract

The present invention addresses the problem of providing an LW reversal type multilayer ceramic capacitor which is capable of suppressing deterioration of a self-alignment effect and achieving a stable mounting.　The present invention provides a multilayer ceramic capacitor 1 wherein if l is the length in the longitudinal direction connecting a first end surface LS1 and a second end surface LS2 of a multilayer body 10, w is the length in the width direction connecting a first lateral surface WS1 and a second lateral surface WS2 of the multilayer body 10, and t is the length in the height direction connecting a first main surface TS1 and a second main surface TS2 of the multilayer body 10, the dimensional relationship w > l > t is satisfied. With respect to this multilayer ceramic capacitor 1, the dimensions in the longitudinal direction L of a fourth surface part 40A4 and a fifth surface part 40A5 of a first external electrode 40A are larger than the dimensions in the longitudinal direction of a second surface part 40A2 and a third surface part of the first external electrode 40A; and the dimensions in the longitudinal direction L of a ninth surface part 40B4 and a tenth surface part 40B5 of a second external electrode 40B are larger than the dimensions in the longitudinal direction L of a seventh surface part 40B2 and an eighth surface part 40B3 of the second external electrode 40B.

Description

Technical Field

[0001] The present invention relates to a multilayer ceramic capacitor.

Background Art

[0002] Conventionally, multilayer ceramic capacitors have been known. A general multilayer ceramic capacitor has a substantially rectangular parallelepiped-shaped laminate whose dimension in the length direction L is longer than the dimension in the width direction W, and external electrodes are provided at both ends in the length direction L of this laminate. On the other hand, in order to reduce ESL, a so-called LW inversion type multilayer ceramic capacitor in which the magnitude relationship between the dimension in the length direction L and the dimension in the width direction W of the laminate is reversed is also known (see Patent Document 1 and Patent Document 2).

[0003] Furthermore, in recent years, as the mounting density of the substrate has increased, the mounting area of the multilayer ceramic capacitor has been decreasing. Therefore, a PoP (Package on Package) mounting form is adopted, and the demand for multilayer ceramic capacitors mounted in an LSC (Land side Capacitor) type at the lower end of the substrate is increasing. As such a multilayer ceramic capacitor mounted in an LSC (Land side Capacitor) type, a multilayer ceramic capacitor with a reduced height and a thin thickness in the height direction is required.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] Patent Document 2 discloses an LW reverse type multilayer ceramic electronic component in which at least one edge of the fourth and fifth surfaces of the external electrode is provided with a recess extending inward from that edge toward the first surface, and both sides of the recess in the third direction form a covering portion that covers the edges of two surfaces of the component body in the second direction.

[0006] However, in the multilayer ceramic electronic component disclosed in Patent Document 2, variations in the formation position and thickness of the underlying conductor layer and the covering conductor layer provided on top of it may cause variations in the area and shape of the covering portion that covers the edges of the two faces in the second direction of the component body. When mounting an LW reverse type multilayer ceramic electronic component to a mounting substrate using solder, differences in the area and shape of the covering portion between the left and right sides may cause the way the solder wets the covering portion to change on each side, potentially resulting in differences in how the tensile stress of the solder is applied. This may worsen the self-alignment effect. As a result, the multilayer ceramic electronic component may become more prone to rotation or tilting, potentially reducing its mountability. Furthermore, because the distance between lands on a substrate on which an LW reverse type multilayer ceramic electronic component is mounted is short, if the self-alignment effect worsens and the multilayer ceramic electronic component rotates significantly, one external electrode may be mounted so as to straddle lands with different polarities, potentially causing a short circuit.

[0007] The objective of the present invention is to provide an LW reverse type multilayer ceramic capacitor that suppresses deterioration of the self-alignment effect and enables stable mounting. [Means for solving the problem]

[0008] The multilayer ceramic capacitor according to the present invention includes a plurality of dielectric layers and a plurality of internal electrode layers stacked alternately in the height direction, and a laminate having a first main surface and a second main surface facing each other in the height direction, a first end surface and a second end surface facing each other in the length direction perpendicular to the height direction, and a first side surface and a second side surface facing each other in the width direction perpendicular to the height direction and the length direction, and a first external electrode having a first surface portion located on the first end surface, at least one of a second surface portion located on a part of the first main surface and a third surface portion located on a part of the second main surface, a fourth surface portion located on a part of the first side surface and a fifth surface portion located on a part of the second side surface, and a sixth surface portion located on the second end surface, a seventh surface portion located on a part of the first main surface and a part of the second main surface A multilayer ceramic capacitor having a second external electrode having at least one of the eighth face portions located thereon, a ninth face portion located on a part of the first side surface, and a tenth face portion located on a part of the second side surface, wherein when the length in the longitudinal direction connecting the first end face and the second end face of the laminate is l, the length in the width direction connecting the first side surface and the second side surface is w, and the length in the height direction connecting the first main surface and the second main surface is t, the dimensional relationship is w>l>t, the length in the longitudinal direction of the fourth and fifth face portions of the first external electrode is larger than the length in the longitudinal direction of the second and third face portions, and the length in the longitudinal direction of the ninth and tenth face portions of the second external electrode is larger than the length in the longitudinal direction of the seventh and eighth face portions. [Effects of the Invention]

[0009] According to the present invention, it is possible to provide an LW reverse type multilayer ceramic capacitor that can suppress deterioration of the self-alignment effect and enable stable mounting. [Brief explanation of the drawing]

[0010] [Figure 1] This is an external perspective view of the multilayer ceramic capacitor of the embodiment. [Figure 2] Figure 1 is a view of the multilayer ceramic capacitor shown, looking at the first side along the direction of arrow II. [Figure 3] Figure 1 is a view of the multilayer ceramic capacitor shown, looking at the second side along the direction of arrow III. [Figure 4] Figure 2 is a view of the multilayer ceramic capacitor shown, looking at the first main surface side along the direction of arrow IV. [Figure 5] Figure 2 is a view of the multilayer ceramic capacitor shown, looking at the second main surface side along the direction of arrow V. [Figure 6] Figure 4 is a cross-sectional view of the multilayer ceramic capacitor along the VI-VI line. [Figure 7] Figure 6 is a cross-sectional view of the multilayer ceramic capacitor along the line VII-VII. [Figure 8A] Figure 6 is a cross-sectional view of the multilayer ceramic capacitor along the line VIIIA-VIIIA, showing the first internal electrode layer. [Figure 8B] Figure 6 is a cross-sectional view of the multilayer ceramic capacitor along the VIIIB-VIIIB line, showing the second internal electrode layer. [Figure 9] Figure 4 is a cross-sectional view of the multilayer ceramic capacitor along the line IX-IX, showing the first side view of the laminate. [Figure 10A] This is an enlarged view of section XA in Figure 6, showing a cross-section of the first external electrode. [Figure 10B] This is an enlarged view of section XB in Figure 6, showing a cross-section of the second external electrode. [Figure 11A] This is a cross-sectional view showing a modified example of the layer configuration of the external electrodes of the multilayer ceramic capacitor of the above embodiment, and corresponds to Figure 10A. [Figure 11B] This is a cross-sectional view showing a modified example of the layer configuration of the external electrodes of the multilayer ceramic capacitor of the above embodiment, and corresponds to Figure 10B. [Figure 12]It is a diagram showing an intermediate state in the manufacturing process of the multilayer ceramic capacitor of the above embodiment. [Figure 13] It is a diagram showing an intermediate state in the manufacturing process of the multilayer ceramic capacitor of the above embodiment. [Figure 14] It is a diagram showing an intermediate state in the manufacturing process of the multilayer ceramic capacitor of the above embodiment. [Figure 15] It is a cross-sectional view showing a modified example of the arrangement position of the external electrodes of the multilayer ceramic capacitor of the above embodiment, and is a diagram corresponding to FIG. 1. [Figure 16A] It is an external perspective view of the multilayer ceramic capacitor of Comparative Example 1, and is a diagram corresponding to FIG. 1. [Figure 16B] It is a diagram showing the first internal electrode layer of the multilayer ceramic capacitor of the above comparative example, and is a diagram corresponding to FIG. 8A. [Figure 16C] It is a diagram showing the second internal electrode layer of the multilayer ceramic capacitor of the above comparative example, and is a diagram corresponding to FIG. 8B. [Figure 17A] It is an external perspective view of the multilayer ceramic capacitor of Comparative Example 2, and is a diagram corresponding to FIG. 1. [Figure 17B] It is a diagram showing the first internal electrode layer of the multilayer ceramic capacitor of the above comparative example, and is a diagram corresponding to FIG. 8A. [Figure 17C] It is a diagram showing the second internal electrode layer of the multilayer ceramic capacitor of the above comparative example, and is a diagram corresponding to FIG. 8B. [Figure 18A] It is a diagram for explaining the evaluation method of mountability in the experimental example. [Figure 18B] It is a diagram for explaining the evaluation method of mountability in the experimental example. [Figure 18C] It is a diagram for explaining the evaluation method of mountability in the experimental example. [Figure 18D] It is a diagram for explaining the evaluation method of mountability in the experimental example.

Mode for Carrying Out the Invention

[0011] The following describes a multilayer ceramic capacitor 1 according to an embodiment of this disclosure. Figure 1 is an external perspective view of the multilayer ceramic capacitor 1 of this embodiment. Figure 2 is a view of the multilayer ceramic capacitor 1 shown in Figure 1, looking at the first side surface WS1 side along the direction of arrow II. Figure 3 is a view of the multilayer ceramic capacitor 1 shown in Figure 1, looking at the second side surface WS2 side along the direction of arrow III. Figure 4 is a view of the multilayer ceramic capacitor 1 shown in Figure 2, looking at the first main surface TS1 side along the direction of arrow IV. Figure 5 is a view of the multilayer ceramic capacitor 1 shown in Figure 2, looking at the second main surface TS2 side along the direction of arrow V. Figure 6 is a cross-sectional view of the multilayer ceramic capacitor 1 shown in Figure 4 along the line VI-VI. Figure 7 is a cross-sectional view of the multilayer ceramic capacitor 1 shown in Figure 6 along the line VII-VII. Figure 8A is a cross-sectional view of the multilayer ceramic capacitor 1 shown in Figure 6 along the line VIIIA-VIIIA. Figure 8B is a cross-sectional view of the multilayer ceramic capacitor 1 shown in Figure 6 along the line VIIIB-VIIIB. Figure 9 is a cross-sectional view of the multilayer ceramic capacitor 1 shown in Figure 4 along the line IX-IX, showing the first side surface WS1 of the laminate 10. Figure 10A is an enlarged view of section XA in Figure 6, showing a cross-section of the first external electrode 40A. Figure 10B is an enlarged view of section XB in Figure 6, showing a cross-section of the second external electrode 40B.

[0012] The multilayer ceramic capacitor 1 comprises a laminated body 10 and external electrodes 40.

[0013] Figures 1 to 9 show the XYZ Cartesian coordinate system. The length direction L of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Y direction. The width direction W of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the X direction. The height direction T of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Z direction. Here, the cross section shown in Figure 6 is also called the LT cross section. The cross section shown in Figure 7 is also called the WT cross section. The cross sections shown in Figures 8A and 8B are also called the LW cross section.

[0014] As shown in Figures 1 to 5, the laminate 10 includes a first main surface TS1 and a second main surface TS2 that are opposite to the height direction T, a first end surface LS1 and a second end surface LS2 that are opposite to the length direction L which is perpendicular to the height direction T, and a first side surface WS1 and a second side surface WS2 that are opposite to the width direction W which is perpendicular to the height direction T and the length direction L.

[0015] The laminate 10 has a substantially rectangular parallelepiped shape. Preferably, the corners and edges of the laminate 10 are rounded. The corners are the parts where three faces of the laminate intersect, and the edges are the parts where two faces of the laminate intersect. In addition, some or all of the surfaces constituting the laminate 10 may have irregularities or other features formed on them.

[0016] As shown in Figures 6 and 7, the laminate 10 has an inner layer 11 and a first main surface-side outer layer 12 and a second main surface-side outer layer 13 arranged to sandwich the inner layer 11 in the height direction T.

[0017] The inner layer 11 includes a plurality of dielectric layers 20 and a plurality of internal electrode layers 30. In the height direction T, the inner layer 11 includes the internal electrode layer 30 located closest to the first main surface TS1 to the internal electrode layer 30 located closest to the second main surface TS2. In the inner layer 11, the plurality of internal electrode layers 30 are arranged facing each other via the dielectric layers 20. The inner layer 11 is the part that generates capacitance and functions substantially as a capacitor. The inner layer 11 is also called the effective layer.

[0018] Multiple dielectric layers 20 are composed of a dielectric material. The dielectric material is, for example, a ceramic material. The dielectric material may be a dielectric ceramic containing components such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3. When these components are the main components, depending on the desired properties of the laminate, minor components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds may be added in lower amounts than the main components.

[0019] The thickness of the dielectric layer 20 is preferably 0.5 μm or more and 10 μm or less. The number of dielectric layers 20 to be stacked is preferably 15 or more and 700 or less. This number of dielectric layers 20 is the sum of the number of dielectric layers in the inner layer portion 11 and the number of dielectric layers in the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13.

[0020] The multiple internal electrode layers 30 have multiple first internal electrode layers 31 and multiple second internal electrode layers 32. The first internal electrode layers 31 are arranged on multiple dielectric layers 20 and are led out to a first end face LS1. The second internal electrode layers 32 are arranged on multiple dielectric layers 20 and are led out to a second end face LS2. The multiple first internal electrode layers 31 and the multiple second internal electrode layers 32 are arranged alternately in the height direction T of the laminate 10 via the dielectric layers 20. The first internal electrode layers 31 and the second internal electrode layers 32 are arranged so as to sandwich the dielectric layers 20.

[0021] As shown in Figure 8A, the first internal electrode layer 31 has a first opposing electrode portion 31A facing the second internal electrode layer 32, and a first lead-out portion 31B that extends from the first opposing electrode portion 31A to a first end face LS1, a part of the first side surface WS1, and a part of the second side surface WS2. The first opposing electrode portion 31A is located inside the laminate 10. The first lead-out portion 31B is connected to the first opposing electrode portion 31A and is exposed to the first end face LS1, a part of the first side surface WS1, and a part of the second side surface WS2.

[0022] This ensures the width of the first lead-out portion 31B of the first internal electrode layer 31, thereby increasing the connection area between the first lead-out portion 31B and the first external electrode 40A, and thus increasing the current path. As a result, ESL can be reduced. Furthermore, since the first lead-out portion 31B of the first internal electrode layer 31 is positioned to a part of the first side surface WS1 and the second side surface WS2 of the laminate 10, the distance between the first lead-out portion 31B and the second lead-out portion 32B of the second internal electrode layer 32 (described later) can be shortened, further reducing ESL.

[0023] As shown in Figure 8B, the second internal electrode layer 32 has a second opposing electrode portion 32A facing the first internal electrode layer 31, and a second lead-out portion 32B that extends from the second opposing electrode portion 32A to a second end face LS2, a part of the first side surface WS1, and a part of the second side surface WS2. The second opposing electrode portion 32A is located inside the laminate 10. The second lead-out portion 32B is connected to the second opposing electrode portion 32A and is exposed to the second end face LS2, a part of the first side surface WS1, and a part of the second side surface WS2.

[0024] This ensures the width of the second lead portion 32B of the second internal electrode layer 32, thereby increasing the connection area between the second lead portion 32B and the second external electrode 40B, and thus increasing the current path. As a result, ESL can be reduced. Furthermore, since the second lead portion 32B of the second internal electrode layer 32 is positioned to a portion of the first side surface WS1 and the second side surface WS2 of the laminate 10, the distance between the second lead portion 32B and the first lead portion 31B of the first internal electrode layer 31 can be shortened, further reducing ESL.

[0025] Figure 9 is a cross-sectional view of the multilayer ceramic capacitor 1 shown in Figure 4 along the line IX-IX, and shows the first side surface WS1 of the laminate 10. Note that the line IX-IX, which indicates the position of the cross-sectional view in Figure 9, is also shown in Figures 8A and 8B. As shown in Figure 9, the first lead-out portion 31B of the first internal electrode layer 31 and the second lead-out portion 32B of the second internal electrode layer 32 are exposed on the first side surface WS1 of the laminate 10.

[0026] As shown in Figure 9, the lengthwise dimension L of the multiple first pull-out portions 31B arranged in the height direction T is all larger than the lengthwise dimension L of the second surface portion 40A2 and the third surface portion 40A3 of the first external electrode 40A, which will be described later.

[0027] On the other hand, the same applies to the plurality of second pull-out portions 32B of the second internal electrode layer 32, which are arranged in the height direction T. The length L dimension of these plurality of second pull-out portions 32B is larger than the length L dimension of the seventh surface portion 40B2 and the eighth surface portion 40B3 of the second external electrode 40B, which will be described later.

[0028] Although not shown in the diagram, similar to the first side surface WS1, the first lead-out portion 31B of the first internal electrode layer 31 and the second lead-out portion 32B of the second internal electrode layer 32 are exposed on the second side surface WS2. On the second side surface WS2, similar to the first side surface WS1, the length L dimension of the multiple first lead-out portions 31B is larger than the length L dimension of the second surface portion 40A2 and the third surface portion 40A3 of the first external electrode 40A. Similarly, the length L dimension of the multiple second lead-out portions 31B is larger than the length L dimension of the seventh surface portion 40B2 and the eighth surface portion 40B3 of the second external electrode 40B.

[0029] The length L dimension of the portion of the first pull-out section 31B and the second pull-out section 32B that is exposed to a part of the first side surface WS1 is preferably 30 μm or more and 230 μm or less. The length L dimension of the portion of the first pull-out section 31B and the second pull-out section 32B that is exposed to a part of the second side surface WS2 is preferably 30 μm or more and 230 μm or less. The dimensions of each pull-out section exposed to the side surface of these laminates 10 may be approximately equal.

[0030] This makes it possible to realize the shapes of the first external electrode 40A and 9th external electrode 40B4 having the fourth and fifth surfaces 40A4 and 40A5 respectively, and the shape of the second external electrode 40B having the tenth surface 40B5, as described later. Furthermore, since the distance between the first lead-out portion 31B of the first internal electrode layer 31 and the second lead-out portion 32B of the second internal electrode layer 32 can be shortened, the path through which the current flows can be shortened. Thus, the ESL can be reduced.

[0031] In this embodiment, capacitance is formed when the first counter electrode portion 31A and the second counter electrode portion 32A face each other via the dielectric layer 20, and the characteristics of a capacitor are exhibited.

[0032] The shapes of the first counter electrode portion 31A and the second counter electrode portion 32A are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded, or the corners of the rectangular shape may be formed at an angle.

[0033] The shape of the first drawer section 31B and the second drawer section 32B is not particularly limited, but it is preferably rectangular. However, the corners of the rectangular shape may be rounded, or the corners of the rectangular shape may be formed at an angle. In this embodiment, the shape of the first drawer section 31B and the second drawer section 32B is substantially T-shaped, with a portion of the corners of the rectangular shape removed.

[0034] Furthermore, the widthwise dimension W of the portion of the first extension portion 31B exposed to the first end face LS1 is greater than the widthwise dimension of the first opposing electrode portion 31A. The widthwise dimension W of the portion of the second extension portion 32B exposed to the second end face LS2 is greater than the widthwise dimension of the second opposing electrode portion 32A.

[0035] The first internal electrode layer 31 and the second internal electrode layer 32 are made of a suitable conductive material such as metals like Ni, Cu, Ag, Pd, and Au, or alloys containing at least one of these metals. When using an alloy, the first internal electrode layer 31 and the second internal electrode layer 32 may be made of, for example, an Ag-Pd alloy.

[0036] The thickness of the first internal electrode layer 31 and the second internal electrode layer 32 is preferably, for example, 0.2 μm or more and 2.0 μm or less. The total number of the first internal electrode layer 31 and the second internal electrode layer 32 is preferably 15 or more and 200 or less.

[0037] The first main surface-side outer layer 12 is located on the first main surface TS1 side of the laminate 10. The first main surface-side outer layer 12 is an assembly of multiple dielectric layers 20 located between the first main surface TS1 and the internal electrode layer 30 closest to the first main surface TS1. That is, the first main surface-side outer layer 12 is formed from multiple dielectric layers 20 located between the first main surface TS1 and the internal electrode layer 30 located closest to the first main surface TS1 among the multiple internal electrode layers 30. The dielectric layers 20 used in the first main surface-side outer layer 12 may be the same as the dielectric layers 20 used in the inner layer 11.

[0038] The second main surface-side outer layer 13 is located on the second main surface TS2 side of the laminate 10. The second main surface-side outer layer 13 is an assembly of multiple dielectric layers 20 located between the second main surface TS2 and the internal electrode layer 30 closest to the second main surface TS2. That is, the second main surface-side outer layer 13 is formed from multiple dielectric layers 20 located between the second main surface TS2 and the internal electrode layer 30 located closest to the second main surface TS2 among the multiple internal electrode layers 30. The dielectric layers 20 used in the second main surface-side outer layer 13 may be the same as the dielectric layers 20 used in the inner layer 11.

[0039] As described above, the laminate 10 has a plurality of stacked dielectric layers 20 and a plurality of internal electrode layers 30 stacked on the dielectric layers 20. In other words, the multilayer ceramic capacitor 1 has a laminate 10 in which the dielectric layers 20 and internal electrode layers 30 are stacked alternately.

[0040] The laminate 10 has a counter electrode portion 11E. The counter electrode portion 11E is the portion where the first counter electrode portion 31A of the first internal electrode layer 31 and the second counter electrode portion 32A of the second internal electrode layer 32 face each other. The counter electrode portion 11E is configured as part of the inner layer portion 11. Figures 8A and 8B show the width W and length L ranges of the counter electrode portion 11E. The counter electrode portion 11E is also called the capacitor effective portion.

[0041] The laminate 10 has an end-face side outer layer. The end-face side outer layer includes a first end-face side outer layer LG1 located on the first end face LS1 side and a second end-face side outer layer LG2 located on the second end face LS2 side. The first end-face side outer layer LG1 is a portion that includes a dielectric layer 20 and a first lead-out portion 31B located between the opposing electrode portion 11E and the first end face LS1. That is, the first end-face side outer layer LG1 is an assembly of the portions of multiple dielectric layers 20 on the first end face LS1 side and multiple first lead-out portions 31B. The second end-face side outer layer LG2 is a portion that includes a dielectric layer 20 and a second lead-out portion 32B located between the opposing electrode portion 11E and the second end face LS2. In other words, the second end-face outer layer LG2 is an assembly of the portions of the second end faces LS2 of the multiple dielectric layers 20 and the multiple second lead-out portions 32B. Figures 6, 8A, and 8B show the range L in the longitudinal direction of the first end-face outer layer LG1 and the second end-face outer layer LG2. The first end-face outer layer LG1 and the second end-face outer layer LG2 are also called the L gap or end gap.

[0042] The laminate 10 has a side outer layer. The side outer layer includes a first side outer layer WG1 located on the first side WS1 side and a second side outer layer WG2 located on the second side WS2 side. The first side outer layer WG1 is a portion that includes a dielectric layer 20 located between the opposing electrode portion 11E and the first side WS1. That is, the first side outer layer WG1 is an aggregate of portions of multiple dielectric layers 20 on the first side WS1 side. The second side outer layer WG2 is a portion that includes a dielectric layer 20 located between the opposing electrode portion 11E and the second side WS2. That is, the second side outer layer WG2 is an aggregate of portions of multiple dielectric layers 20 on the second side WS2 side. Figures 7, 8A, and 8B show the width range W of the first side outer layer WG1 and the second side outer layer WG2. The first side outer layer WG1 and the second side outer layer WG2 are also referred to as the W gap or side gap.

[0043] As shown in Figures 6 to 8B, when the length L in the longitudinal direction connecting the first end face LS1 and the second end face LS2 of the laminate 10 is l, the length W in the width direction connecting the first side face WS1 and the second side face WS2 is w, and the length T in the height direction connecting the first main face TS1 and the second main face TS2 is t, the dimensional relationship is w > l > t. This makes it possible to widen the width of the pull-out portion at the end face of the internal electrode layer 30. In addition, since the distance between the first external electrode 40A and the second external electrode 40B can be shortened, the ESL of the multilayer ceramic capacitor 1 can be reduced.

[0044] The length l in the longitudinal direction L connecting the first end face LS1 and the second end face LS2 of the laminate 10 is preferably 0.05 mm or more and 0.7 mm or less. The length w in the width direction W connecting the first side face WS1 and the second side face WS2 of the laminate 10 is preferably 0.15 mm or more and 1.5 mm or less. The length t in the height direction T connecting the first main surface TS1 and the second main surface TS2 of the laminate 10 is preferably 150 μm or less. This enables high-density mounting. Furthermore, the length t in the height direction T connecting the first main surface TS1 and the second main surface TS2 of the laminate 10 is preferably 100 μm or less, and more preferably 50 μm or less. This enables even higher density mounting.

[0045] The dimensions l, w, and t of the laminate 10 are measured by the following method.

[0046] First, the w dimension of the laminate 10 is measured. Specifically, the w dimension of the laminate 10 is measured using a micrometer at the midpoint in the length L of the multilayer ceramic capacitor 1, that is, at the L / 2 position of the multilayer ceramic capacitor 1.

[0047] Next, the l and t dimensions of the laminate 10 are measured. First, the same multilayer ceramic capacitor 1 whose w dimension was measured is polished so that it is parallel to the LT surface up to the middle position in the width direction W of the multilayer ceramic capacitor 1, i.e., the W / 2 position of the multilayer ceramic capacitor 1. Then, the LT cross section exposed by polishing is observed with a microscope. The l dimension of the laminate 10 is measured with a microscope at the middle position in the height direction T of the laminate 10 in the LT cross section, i.e., the t / 2 position of the laminate 10. The t dimension of the laminate 10 is measured with a microscope at the middle position in the length direction L of the laminate 10 in the LT cross section, i.e., the l / 2 position of the laminate 10.

[0048] The external electrode 40 includes a first external electrode 40A positioned on the first end face LS1 side and a second external electrode 40B positioned on the second end face LS2 side.

[0049] The first external electrode 40A is connected to the first internal electrode layer 31. The first external electrode 40A in this embodiment has a first surface portion 40A1 located on the first end face LS1, a second surface portion 40A2 located on a part of the first main surface TS1, a third surface portion 40A3 located on a part of the second main surface TS2, a fourth surface portion 40A4 located on a part of the first side surface WS1, and a fifth surface portion 40A5 located on a part of the second side surface WS2. Preferably, the first external electrode 40A has at least one of the second surface portion 40A2 located on a part of the first main surface TS1 and the third surface portion 40A3 located on a part of the second main surface TS2, a first surface portion 40A1 located on the first end face LS1, a fourth surface portion 40A4 located on a part of the first side surface WS1, and a fifth surface portion 40A5 located on a part of the second side surface WS2.

[0050] The first surface portion 40A1 covers the entire first end face LS1 and is the portion connected to the first internal electrode layer 31. Either the second surface portion 40A2 or the third surface portion 40A3 is the portion connected to the land of the mounting substrate.

[0051] The fourth face portion 40A4 is the portion connected to the first pull-out portion 31B that is exposed on the first side surface WS1. As shown in Figures 2, 4, and 5, the lengthwise dimension L4 of the fourth face portion 40A4 is larger than the lengthwise dimension L2 of the second face portion 40A2. Also, the lengthwise dimension L4 of the fourth face portion 40A4 is larger than the lengthwise dimension L3 of the third face portion 40A3. That is, the lengthwise center side of the fourth face portion 40A4 protrudes further towards the lengthwise center than the end portion 40A2a of the second face portion 40A2, and also protrudes further towards the lengthwise center than the end portion 40A3a of the third face portion 40A3.

[0052] The fifth face portion 40A5 is the portion connected to the first pull-out portion 31B that is exposed on the second side surface WS2. As shown in Figures 3 to 5, the lengthwise dimension L5 of the fifth face portion 40A5 is larger than the lengthwise dimension L2 of the second face portion 40A2. Also, the lengthwise dimension L5 of the fifth face portion 40A5 is larger than the lengthwise dimension L3 of the third face portion 40A3. In other words, the lengthwise center side of the fifth face portion 40A5 protrudes lengthwise towards the center beyond the end portion 40A2a of the second face portion 40A2, and also protrudes lengthwise towards the center beyond the end portion 40A3a of the third face portion 40A3.

[0053] The dimensions L4 in the longitudinal direction L of the fourth surface portion 40A4 and L5 in the longitudinal direction L of the fifth surface portion 40A5 of the first external electrode 40A are preferably 110% or more and 245% or less of the dimensions L2 in the longitudinal direction L of the second surface portion 40A2 and L3 in the longitudinal direction L of the third surface portion 40A3.

[0054] The second external electrode 40B is connected to the second internal electrode layer 32. The second external electrode 40B in this embodiment has a sixth face portion 40B1 located on the second end face LS2, a seventh face portion 40B2 located on a part of the first main face TS1, an eighth face portion 40B3 located on a part of the second main face TS2, a ninth face portion 40B4 located on a part of the first side surface WS1, and a tenth face portion 40B5 located on a part of the second side surface WS2. Preferably, the second external electrode 40B includes at least one of the seventh face portion 40B2 located on a part of the first main surface TS1 and the eighth face portion 40B3 located on a part of the second main surface TS2, the first external electrode 40A, the sixth face portion 40B1 located on the second end surface LS2, the ninth face portion 40B4 located on a part of the first side surface WS1, and the tenth face portion 40B5 located on a part of the second side surface WS2.

[0055] The sixth face portion 40B1 covers the entire second end face LS2 and is the portion connected to the second internal electrode layer 32. Either the seventh face portion 40B2 or the eighth face portion 40B3 is the portion connected to the land of the mounting substrate.

[0056] The ninth face portion 40B4 is the portion connected to the second pull-out portion 32B that is exposed on the first side surface WS1. As shown in Figures 2, 4, and 5, the lengthwise dimension L9 of the ninth face portion 40B4 is larger than the lengthwise dimension L7 of the seventh face portion 40B2. Also, the lengthwise dimension L9 of the ninth face portion 40B4 is larger than the lengthwise dimension L8 of the eighth face portion 40B3. That is, the lengthwise center side of the ninth face portion 40B4 protrudes further towards the lengthwise center than the end portion 40B2a of the seventh face portion 40B2, and also protrudes further towards the lengthwise center than the end portion 40B3a of the eighth face portion 40B3.

[0057] The tenth face portion 40B5 is the portion connected to the second pull-out portion 32B that is exposed on the second side surface WS2. As shown in Figures 3 to 5, the lengthwise dimension L10 of the tenth face portion 40B5 is larger than the lengthwise dimension L7 of the seventh face portion 40B2. Also, the lengthwise dimension L10 of the tenth face portion 40B5 is larger than the lengthwise dimension L8 of the eighth face portion 40B3. In other words, the lengthwise center side of the tenth face portion 40B5 protrudes further towards the lengthwise center than the end portion 40B2a of the seventh face portion 40B2, and also protrudes further towards the lengthwise center than the end portion 40B3a of the eighth face portion 40B3.

[0058] The dimensions L9 in the longitudinal direction L of the ninth face portion 40B4 and L10 in the longitudinal direction L of the tenth face portion 40B5 of the second external electrode 40B are preferably 110% or more and 245% or less of the dimensions L7 in the longitudinal direction L of the seventh face portion 40B2 and L8 in the longitudinal direction L of the eighth face portion 40B3.

[0059] The dimensions in the length direction L of the second and third surfaces 40A2 and 40A3 of the first external electrode 40A, which are the main surface surfaces, and the seventh and eighth surfaces 40B2 and 40B3 of the second external electrode 40B, as well as the dimensions in the length direction L of the fourth and fifth surfaces 40A4 and 40A5 of the first external electrode 40A, which are the side surfaces, and the ninth and tenth surfaces 40B4 and 40B5 of the second external electrode 40B, are measured by the following method.

[0060] The dimensions L in the longitudinal direction of the second surface 40A2 and the seventh surface 40B2 are measured by a microscope at a position halfway across the width W when observed from the first main surface TS1 of the laminate 10. Similarly, the dimensions L in the longitudinal direction of the third surface 40A3 and the eighth surface 40B3 are measured by a microscope at a position halfway across the width W when observed from the second main surface TS2 of the laminate 10.

[0061] The lengthwise dimension L of the fourth face 40A4 and the ninth face 40B4 is measured by a microscope at a position halfway through the height T when observed from the first side surface WS1 of the laminate 10. Similarly, the lengthwise dimension L of the fifth face 40A5 and the tenth face 40B5 is measured by a microscope at a position halfway through the height T when observed from the second side surface WS2 of the laminate 10.

[0062] From the dimensions L in the longitudinal direction of the main surface and the dimensions L in the longitudinal direction of the side surface measured in this way, the ratio of the dimension L in the longitudinal direction of the side surface to the dimension L in the longitudinal direction of the main surface can be determined.

[0063] As shown in Figure 10A, the first external electrode 40A has a first base electrode layer 50A and a first plating layer 60A disposed on the first base electrode layer 50A. The first base electrode layer 50A is disposed on the surface of the laminate 10. The first plating layer 60A is disposed to cover the first base electrode layer 50A.

[0064] As shown in Figure 10B, the second external electrode 40B has a second base electrode layer 50B and a second plating layer 60B disposed on the second base electrode layer 50B. The second base electrode layer 50B is disposed on the surface of the laminate 10. The second plating layer 60B is disposed to cover the second base electrode layer 50B.

[0065] The first base electrode layer 50A and the second base electrode layer 50B each include at least one selected from a baked layer, a thin film layer, and the like.

[0066] In this embodiment, the first base electrode layer 50A and the second base electrode layer 50B are thin film layers. A thin film layer is a layer on which metal particles are deposited.

[0067] When the first base electrode layer 50A and the second base electrode layer 50B are formed as thin film layers, it is preferable that they be formed by a thin film formation method such as sputtering or vapor deposition. Here, we will describe a sputtered electrode formed by the sputtering method.

[0068] In this embodiment, the first base electrode layer 50A is composed of a first thin film layer 51A formed by a sputtering electrode. The second base electrode layer 50B is composed of a second thin film layer 51B formed by a sputtering electrode. When forming the base electrode layer with a sputtering electrode, it is preferable to form the sputtering electrode directly on the first main surface TS1 and the second main surface TS2 of the laminate 10.

[0069] As shown in Figures 6 and 10A, the first thin film layer 51A formed by the sputtering electrode is located on a portion of the first end face LS1 side of the first main surface TS1 and on a portion of the first end face LS1 side of the second main surface TS2. Specifically, it is preferable that the first thin film layer 51A is located on the portion of the first main surface TS1 that is covered by the first external electrode 40A shown in Figure 4. It is also preferable that the first thin film layer 51A is located on the portion of the second main surface TS2 that is covered by the first external electrode 40A shown in Figure 5.

[0070] Furthermore, as shown in Figure 9, it is preferable that the first thin film layer 51A is arranged so as to slightly wrap around a portion of the first main surface TS1 and a portion of the first side surface WS1, which is continuous with the portion of the first main surface TS1. It is also preferable that the first thin film layer 51A is arranged so as to slightly wrap around a portion of the second main surface TS2 and a portion of the first side surface WS1, which is continuous with the portion of the second main surface TS2.

[0071] Furthermore, although not shown in the diagram, it is preferable that, similar to the first side surface WS1, the first thin film layer 51A is arranged on the second side surface WS2 so as to be on a portion of the first main surface TS1 and slightly wraps around a portion of the second side surface WS2, continuing from the portion of the first main surface TS1.

[0072] For example, if a chamfered portion such as a rounded edge is formed on the edge of the laminate 10, it is preferable that the first thin film layer 51A is arranged on a part of the first end face LS1 side of the first main surface TS1, and on the chamfered portion on the first side surface WS1 and the chamfered portion on the second side surface WS2 that are continuous with that portion. It is also preferable that the first thin film layer 51A is arranged on a part of the first end face LS1 side of the second main surface TS2, and on the chamfered portion on the first side surface WS1 and the chamfered portion on the second side surface WS2 that are continuous with that portion. In this case, the formation of the thin film layer by sputtering or the like is easy.

[0073] The longitudinal center side of the first pull-out portion 31B protrudes longitudinally further towards the center than the longitudinal center end of the first thin film layer 51A located on the first main surface TS1 and the longitudinal center end of the first thin film layer 51A located on the second main surface TS2. Similarly, the longitudinal center side of the second pull-out portion 32B protrudes longitudinally further towards the center than the longitudinal center end of the second thin film layer 51B located on the first main surface TS1 and the longitudinal center end of the second thin film layer 51B located on the second main surface TS2.

[0074] By the above method, when forming the plating layer, the distance between the first thin film layer 51A, which is positioned on a portion of the first side surface WS1 and a portion of the second side surface WS2, and the internal electrode layer 30, which is exposed on the first side surface WS1 and the second side surface WS2, can be controlled. Therefore, it becomes easy to deposit the plating layer even on the surface of the laminate 10 between the first thin film layer 51A, which is positioned on a portion of the first side surface WS1 and a portion of the second side surface WS2, and the internal electrode layer 30, which is exposed on the first side surface WS1 and the second side surface WS2.

[0075] As shown in Figures 6 and 10B, the second thin film layer 51B formed by the sputtering electrode is located on a portion of the second end face LS2 side of the first main surface TS1 and on a portion of the second end face LS2 side of the second main surface TS2. Specifically, it is preferable that the second thin film layer 51B is located on the portion of the first main surface TS1 that is covered by the second external electrode 40B shown in Figure 4. It is also preferable that the second thin film layer 51B is located on the portion of the second main surface TS2 that is covered by the second external electrode 40B shown in Figure 5.

[0076] Furthermore, as shown in Figure 9, it is preferable that the second thin film layer 51B is arranged so as to extend slightly around a portion of the first main surface TS1 and a portion of the first side surface WS1, continuous with the portion of the first main surface TS1. It is also preferable that the second thin film layer 51B is arranged so as to extend slightly around a portion of the second main surface TS2 and a portion of the first side surface WS1, continuous with the portion of the second main surface TS2.

[0077] Furthermore, although not shown in the diagram, it is preferable that, similar to the first side surface WS1, the second thin film layer 51B on the second side surface WS2 is arranged such that it covers a portion of the first main surface TS1 and extends slightly around a portion of the second side surface WS2, continuing from the portion of the first main surface TS1.

[0078] For example, if a chamfered portion such as a rounded edge is formed on the edge of the laminate 10, it is preferable that the second thin film layer 51B is arranged on a part of the second end face LS2 side of the first main surface TS1, and on the chamfered portion on the first side surface WS1 and the chamfered portion on the second side surface WS2 that are continuous with that portion. It is preferable that the second thin film layer 51B is arranged on a part of the second end face LS2 side of the second main surface TS2, and on the chamfered portion on the first side surface WS1 and the chamfered portion on the second side surface WS2 that are continuous with that portion. In this case, the formation of the thin film layer by sputtering or the like is easy.

[0079] By the above method, when forming the plating layer, the distance between the second thin film layer 51B, which is positioned on a portion of the first side surface WS1 and a portion of the second side surface WS2, and the internal electrode layer 30, which is exposed on the first side surface WS1 and the second side surface WS2, can be controlled. Therefore, it becomes easy to deposit the plating layer even on the surface of the laminate 10 between the second thin film layer 51B, which is positioned on a portion of the first side surface WS1 and a portion of the second side surface WS2, and the internal electrode layer 30, which is exposed on the first side surface WS1 and the second side surface WS2.

[0080] The thin film layer formed by the sputtering electrode preferably contains at least one metal selected from the group consisting of Mg, Al, Ti, W, Cr, Cu, Ni, Ag, Co, Mo, and V. This increases the adhesion force of the external electrode 40 to the laminate 10. The thin film layer may be a single layer or formed by multiple layers. For example, it may be formed by a two-layer structure consisting of a Ni-Cr alloy layer and a Ni-Cu alloy layer.

[0081] The thickness of the sputtering electrode in the stacking direction connecting the first main surface TS1 and the second main surface TS2 is preferably 50 nm to 400 nm, and more preferably 50 nm to 130 nm.

[0082] When sputter electrodes are directly formed on the first main surface TS1 and the second main surface TS2 of the laminate 10 to form a base electrode layer, it is preferable to either form a base electrode layer for the baking layer on the first end surface LS1 and the second end surface LS2, or to directly form the plating layer described later without forming a base electrode layer. In this embodiment, the plating layer described later is directly formed on the first end surface LS1 and the second end surface LS2 without forming a base electrode layer.

[0083] As will be described later in the modified examples, the first base electrode layer 50A and the second base electrode layer 50B may be baked layers. The baked layers preferably contain a metal component and either a glass component or a ceramic component, or both. The metal component includes at least one selected from, for example, Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. The glass component includes at least one selected from, for example, B, Si, Ba, Mg, Al, Li, etc. The ceramic component may be the same type of ceramic material as the dielectric layer 20, or a different type of ceramic material may be used. The ceramic component includes at least one selected from, for example, BaTiO3, CaTiO3, (Ba,Ca)TiO3, SrTiO3, CaZrO3, etc.

[0084] The baked layer is, for example, formed by applying a conductive paste containing glass and metal to the laminate 10 and baking it. The baked layer may be formed by simultaneously firing the laminate chip having an internal electrode layer and a dielectric layer and the conductive paste applied to the laminate chip, or by firing the laminate chip having an internal electrode layer and a dielectric layer to obtain the laminate 10, and then applying the conductive paste to the laminate 10 and baking it. When simultaneously firing the laminate chip having an internal electrode layer and a dielectric layer and the conductive paste applied to the laminate chip, it is preferable to form the baked layer by baking a material with a ceramic material added instead of a glass component. In this case, it is particularly preferable to use the same type of ceramic material as the dielectric layer 20 as the added ceramic material. The baked layer may consist of multiple layers.

[0085] Alternatively, the first and second base electrode layers 50A and 50B may be omitted, and the first and second plating layers 60A and 50B described later may be directly placed on the laminate 10.

[0086] The first plating layer 60A is positioned to cover the first underlay electrode layer 50A.

[0087] The second plating layer 60B is positioned to cover the second under electrode layer 50B.

[0088] The first plating layer 60A and the second plating layer 60B may each contain at least one selected from, for example, Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, etc. The first plating layer 60A and the second plating layer 60B may each be formed by multiple layers.

[0089] When the underlying electrode layer is formed as a thin film layer, the plating layer is preferably formed as a three-layer structure: a Cu plating layer as the lower plating layer, a Ni plating layer as the middle plating layer, and a Sn plating layer as the upper plating layer. Specifically, the first plating layer 60A preferably has a first Cu plating layer 61A, a first Ni plating layer 62A, and a first Sn plating layer 63A. The second plating layer 60B preferably has a second Cu plating layer 61B, a second Ni plating layer 62B, and a second Sn plating layer 63B. However, the first plating layer 60A and the second plating layer 60B are not limited to a three-layer structure and may have other layer configurations.

[0090] The first Cu plating layer 61A is positioned to cover the first end face LS1 of the laminate 10 and the first thin film layer 51A, which serves as the first underlay electrode layer 50A, located on the first main surface TS1 and the second main surface TS2 of the laminate 10. In this embodiment, the first Cu plating layer 61A is further positioned to cover the portion of the internal electrode layer 30 that is exposed on the first side surface WS1 and the second side surface WS2 of the laminate 10. At this time, the gap between the first thin film layer 51A and the internal electrode layer 30 exposed on the surface of the laminate 10, and the gaps between the multiple internal electrode layers 30 exposed on the surface of the laminate 10 are formed to be narrow, so the plating layer is deposited in these gap regions as well.

[0091] The first Ni plating layer 62A is positioned to cover the first Cu plating layer 61A. The first Sn plating layer 63A is positioned to cover the first Ni plating layer 62A. In this embodiment, the first plating layer 60A is directly electrically connected to the first internal electrode layer 31.

[0092] The second Cu plating layer 61B is positioned to cover the second end face LS2 of the laminate 10 and the second thin film layer 51B, which serves as the second underlay electrode layer 50B, located on the first main surface TS1 and the second main surface TS2 of the laminate 10. In this embodiment, the second Cu plating layer 61B is further positioned to cover the portion of the internal electrode layer 30 that is exposed on the first side surface WS1 and the second side surface WS2 of the laminate 10. At this time, the gap between the second thin film layer 51B and the internal electrode layer 30 exposed on the surface of the laminate 10, and the gaps between the multiple internal electrode layers 30 exposed on the surface of the laminate 10 are formed to be narrow, so the plating layer is deposited in these gap regions as well.

[0093] The second Ni plating layer 62B is positioned to cover the second Cu plating layer 61B. The second Sn plating layer 63B is positioned to cover the second Ni plating layer 62B. In this embodiment, the second plating layer 60B is directly electrically connected to the second internal electrode layer 32.

[0094] By providing a plating layer consisting of a Cu plating layer and a Ni plating layer so as to cover the underlying electrode layer, the underlying electrode layer is prevented from being eroded by the solder when mounting the multilayer ceramic capacitor 1. Furthermore, by providing a Sn plating layer on the surface of the Ni plating layer, the wettability of the solder when mounting the multilayer ceramic capacitor 1 is improved. As a result, the multilayer ceramic capacitor 1 can be easily mounted.

[0095] The thickness of each plating layer is preferably 2 μm or more and 15 μm or less. Specifically, the average thickness of each of the first Cu plating layer 61A, the first Ni plating layer 62A, the first Sn plating layer 63A, the second Cu plating layer 61B, the second Ni plating layer 62B, and the second Sn plating layer 63B is preferably 2 μm or more and 15 μm or less. More specifically, the average thickness of the first Cu plating layer 61A and the second Cu plating layer 61B is more preferably 5 μm or more and 8 μm or less. Furthermore, the average thickness of each of the first Ni plating layer 62A, the first Sn plating layer 63A, the second Ni plating layer 62B, and the second Sn plating layer 63B is more preferably 2 μm or more and 4 μm or less.

[0096] In this embodiment, the lengthwise dimension L, which connects the first end face LS1 and the second end face LS2 of the multilayer ceramic capacitor 1 including the laminate 10 and the external electrode 40, is preferably 0.1 mm or more and 0.8 mm or less. In this embodiment, the lengthwise dimension L, which connects the first side face WS1 and the second side face WS2 of the multilayer ceramic capacitor 1, is preferably 0.2 mm or more and 1.6 mm or less. In this embodiment, the heightwise dimension T, which connects the first main face TS1 and the second main face TS2 of the multilayer ceramic capacitor 1, is preferably 0.05 mm or more and 0.2 mm or less. In this embodiment, the lengthwise dimension L of the multilayer ceramic capacitor 1 is smaller than the widthwise dimension W of the multilayer ceramic capacitor 1.

[0097] As described above, in this embodiment, the multilayer ceramic capacitor 1 has the following dimensional relationship: w > l > t, where l is the length in the longitudinal direction connecting the first end face LS1 and the second end face LS2 of the laminate 10, w is the length in the width direction connecting the first side face WS1 and the second side face WS2, and t is the length in the height direction connecting the first main face TS1 and the second main face TS2. This allows for a wider lead-out portion at the end face of the internal electrode layer 30. Furthermore, the distance between the first external electrode 40A and the second external electrode 40B can be shortened, thereby reducing the ESL of the multilayer ceramic capacitor 1.

[0098] Furthermore, in this embodiment, the multilayer ceramic capacitor 1 has dimensions L4 in the longitudinal direction L of the fourth surface 40A4 and L5 in the longitudinal direction L of the fifth surface 40A5 of the first external electrode 40A, which are larger than dimensions L2 in the longitudinal direction L of the second surface 40A2 and L3 in the longitudinal direction L of the third surface 40A3, and the dimensions L9 in the longitudinal direction L of the ninth surface 40B4 and L10 in the longitudinal direction L of the tenth surface 40B5 of the second external electrode 40B, which are larger than dimensions L7 in the longitudinal direction L of the seventh surface 40B2 and L8 in the longitudinal direction L of the eighth surface 40B3. As a result, when soldering the first external electrode 40A and the second external electrode 40B to the land to mount the multilayer ceramic capacitor 1 onto the substrate, it becomes possible to sufficiently wet the solder even on the fourth and fifth surfaces 40A4 and 40A5 of the first external electrode 40A, and the ninth and tenth surfaces 40B5 of the second external electrode 40B, where the amount of solder wetting tends to be low. Therefore, it is possible to suppress changes in the amount of solder on each of these fourth and fifth surfaces 40A4 and 40A5, and the ninth and tenth surfaces 40B5 of the second external electrode 40B, and to suppress differences in tensile stress caused by the solder. Therefore, deterioration of the self-alignment effect is suppressed, and stable mounting is possible. As a result, it is possible to suppress the multilayer ceramic capacitor 1 from tilting or rotating and leading to short-circuit failures. The self-alignment effect refers to the phenomenon during soldering where, due to surface tension acting on the molten solder, a force that reduces its surface area is generated, causing the electronic component to be mounted, supported by the molten solder, to move and thus be positioned. This self-alignment effect prevents misalignment during mounting.

[0099] As described above, it is preferable that the lengthwise dimension L4 of the fourth surface portion 40A4 and the lengthwise dimension L5 of the fifth surface portion 40A5 of the first external electrode 40A are 110% to 245% of the lengthwise dimension L2 of the second surface portion 40A2 and the lengthwise dimension L3 of the third surface portion 40A3. Furthermore, it is preferable that the lengthwise dimension L9 of the ninth surface portion 40B4 and the lengthwise dimension L10 of the tenth surface portion 40B5 of the second external electrode 40B are 110% to 245% of the lengthwise dimension L7 of the seventh surface portion 40B2 and the lengthwise dimension L8 of the eighth surface portion 40B3. If the above ratio falls below 110%, it becomes difficult to suppress changes in the amount of solder in the fourth face portion 40A4 and the fifth face portion 40A5, as well as in the ninth face portion 40B4 and the tenth face portion 40B5 of the second external electrode 40B. This makes it difficult to suppress differences in tensile stress caused by the solder, and the multilayer ceramic capacitor 1 may rotate when mounted. On the other hand, if the above ratio falls above 245%, depending on the amount of solder, the first external electrode 40A and the second external electrode 40B may conduct electricity, causing a short circuit. Therefore, it is preferable that the above ratio is between 110% and 245%.

[0100] The following describes modified examples of the layer configuration of the external electrode 40 of the multilayer ceramic capacitor 1 of this embodiment. In the following description, components identical to those in the above embodiment will be denoted by the same reference numerals, and detailed descriptions will be omitted. Figures 11A and 11B are cross-sectional views showing modified examples of the layer configuration of the external electrode 40 of the multilayer ceramic capacitor 1 of this embodiment, and correspond to Figures 10A and 10B.

[0101] In this modified example, the configuration of the external electrode 40 differs from that of the above embodiment.

[0102] The first external electrode 40A has a first base electrode layer 50A and a first plating layer 60A. In this modified example, the first base electrode layer 50A is composed of a first baked layer 52A. In this modified example, the first plating layer 60A has a first Ni plating layer 62A and a first Sn plating layer 63A.

[0103] The second external electrode 40B has a second base electrode layer 50B and a second plating layer 60B. In this modified example, the second base electrode layer 50B is composed of a second baking layer 52B. In this modified example, the second plating layer 60B has a second Ni plating layer 62B and a second Sn plating layer 63B.

[0104] In this modified example, the first base electrode layer 50A, similar to the first external electrode 40A described above, has a first surface portion located on the first end face LS1, a second surface portion located on a part of the first main surface TS1, a third surface portion located on a part of the second main surface TS2, a fourth surface portion located on a part of the first side surface WS1, and a fifth surface portion located on a part of the second side surface WS2. In this modified example, the first base electrode layer 50A is connected to the first internal electrode layer 31.

[0105] The first Ni plating layer 62A is positioned to cover the first underlay electrode layer 50A. The first Sn plating layer 63A is positioned to cover the first Ni plating layer 62A.

[0106] In this modified example, the second base electrode layer 50B, similar to the second external electrode 40B described above, has, for example, a sixth surface located on the second end face LS2, a seventh surface located on a part of the first main surface TS1, an eighth surface located on a part of the second main surface TS2, a ninth surface located on a part of the first side surface WS1, and a tenth surface located on a part of the second side surface WS2. In this modified example, the second base electrode layer 50B is connected to the second internal electrode layer 32.

[0107] The second Ni plating layer 62B is positioned to cover the second under electrode layer 50B. The second Sn plating layer 63B is positioned to cover the second Ni plating layer 62B.

[0108] The first baked layer 52A constituting the first base electrode layer 50A and the second baked layer 52B constituting the second base electrode layer 50B may, for example, be formed by applying a conductive paste containing glass and metal to the laminate and baking it. When the laminated chip before firing and the conductive paste applied to the laminated chip are fired simultaneously, it is preferable to form the baked layer by baking a ceramic material added instead of the glass component. In this case, it is particularly preferable to use the same type of ceramic material as the dielectric layer 20 as the added ceramic material.

[0109] When the base electrode layer is formed of a baked layer, it is preferable that the first plating layer 60A and the second plating layer 60B have a two-layer structure in which a Sn plating layer is formed on top of a Ni plating layer. In this case, the Ni plating layer prevents the base electrode layer from being corroded by the solder when mounting the multilayer ceramic capacitor 1. The Sn plating layer also improves the wettability of the solder when mounting the multilayer ceramic capacitor 1. This facilitates the mounting of the multilayer ceramic capacitor 1.

[0110] Furthermore, the first plating layer 60A and the second plating layer 60B are not limited to a two-layer structure, but may be formed as a three-layer structure including Cu plating, as in the above embodiment, or may have other layer configurations.

[0111] The thickness of each plating layer is preferably 2 μm or more and 15 μm or less. That is, the average thickness of each of the first Ni plating layer 62A, the first Sn plating layer 63A, the second Ni plating layer 62B, and the second Sn plating layer 63B is preferably 2 μm or more and 15 μm or less. More specifically, the average thickness of each of the first Ni plating layer 62A, the first Sn plating layer 63A, the second Ni plating layer 62B, and the second Sn plating layer 63B is more preferably 2 μm or more and 4 μm or less.

[0112] Next, the manufacturing method of the multilayer ceramic capacitor 1 of this embodiment will be described.

[0113] A dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30 are prepared. The dielectric sheet and the conductive paste for the internal electrode contain a binder and a solvent. The binder and solvent may be known. A paste made of a conductive material is, for example, a metal powder to which an organic binder and an organic solvent are added.

[0114] A conductive paste for the internal electrode layer 30 is printed onto the dielectric sheet using a printing plate designed to form the shape of the internal electrode layer 30 in this embodiment, for example, by screen printing or gravure printing. This prepares a dielectric sheet with the pattern of the first internal electrode layer 31 formed on it, and a dielectric sheet with the pattern of the second internal electrode layer 32 formed on it.

[0115] A predetermined number of dielectric sheets without printed internal electrode layer patterns are stacked to form the first main surface outer layer 12 on the first main surface TS1 side. On top of this, dielectric sheets with printed first internal electrode layer 31 patterns and dielectric sheets with printed second internal electrode layer 32 patterns are stacked alternately in sequence to form the inner layer 11. On top of this inner layer 11, a predetermined number of dielectric sheets without printed internal electrode layer patterns are stacked to form the second main surface outer layer 13 on the second main surface TS2 side. This completes the production of the laminated sheet.

[0116] Laminated sheets are pressed in the lamination direction by means of hydrostatic pressing or other methods to produce laminated blocks.

[0117] The laminated block is cut to a predetermined size, thereby producing laminated chips. At this time, the corners and edges of the laminated chips may be rounded by barrel polishing or other methods.

[0118] The laminated chips are fired to produce the laminated body 10. The firing temperature depends on the materials of the dielectric layer 20 and the internal electrode layer 30, but is preferably between 900°C and 1400°C.

[0119] In this embodiment, the base electrode layer is formed by a thin film layer. When the base electrode layer is formed by a thin film layer, the thin film layer is formed in the area of ​​the laminate 10 where the external electrode is to be formed by masking or the like. The thin film layer is formed by a thin film formation method such as sputtering or vapor deposition. In this embodiment, the sputtered electrode as a thin film layer is formed by sputtering.

[0120] Figures 12 to 14 show intermediate states in the manufacturing process of the multilayer ceramic capacitor of this embodiment, after the thin film layers have been placed on the laminate 10 but before the plating layer has been placed. Figure 12 shows the state in which the first thin film layer 51A and the second thin film layer 51B have been placed on the laminate 10, and corresponds to the LT cross section of Figure 6. Figure 13 shows the state in which the first thin film layer 51A has been placed on the laminate 10, and corresponds to the WT cross section of Figure 7. Figure 14 shows the state in which the first thin film layer 51A and the second thin film layer 51B have been placed on the laminate 10, and corresponds to Figure 9, showing the surface of the first side surface WS1 of the laminate 10.

[0121] The first thin film layer 51A formed by the sputtering electrode is located on a portion of the first end face LS1 side of the first main surface TS1 and on a portion of the first end face LS1 side of the second main surface TS2. The second thin film layer 51B formed by the sputtering electrode is located on a portion of the second end face LS2 side of the first main surface TS1 and on a portion of the second end face LS2 side of the second main surface TS2.

[0122] In this embodiment, the thin film layer formed by the sputtering electrode is arranged to slightly wrap around a portion of the first main surface TS1 and a portion of the second main surface TS2, and continuously from the portions of the first main surface TS1 and the second main surface TS2, to a portion of the first side surface WS1 and a portion of the second side surface WS2. This makes it possible to control the distance between the thin film layer arranged on a portion of the first side surface WS1 and a portion of the second side surface WS2 and the internal electrode film exposed on the first side surface WS1 and the second side surface WS2. Therefore, it is possible to deposit a plating layer on the surface of the laminate 10 between the thin film layer arranged on a portion of the first side surface WS1 and a portion of the second side surface WS2 and the internal electrode layer exposed on the first side surface WS1 and the second side surface WS2.

[0123] Subsequently, a plating layer is formed on the surface of the underlying electrode layer and the laminate, which consist of a thin film layer. In this embodiment, three plating layers are formed: a Cu plating layer, a Ni plating layer, and a Sn plating layer.

[0124] The plating layer is formed by electroplating. Barrel plating is preferred as the plating method.

[0125] Here, when forming a thin film layer so that it wraps around to a portion of the first side surface WS1 and a portion of the second side surface WS2, the distance between the thin film layer and the internal electrode layer exposed on the first side surface WS1 and the second side surface WS2 of the laminate 10 can be controlled. Therefore, it becomes easy to deposit a plating layer even on the surface of the laminate 10 between the thin film layer positioned on a portion of the first side surface WS1 and a portion of the second side surface WS2 and the internal electrode layer exposed on the first side surface WS1 and the second side surface WS2.

[0126] Furthermore, the plating layer is positioned to cover the exposed portions of the internal electrode layers on the first side surface WS1 and the second side surface WS2 of the laminate 10. At this time, the gaps between the thin film layer and the internal electrode layers exposed on the surface of the laminate 10, as well as the gaps between the multiple internal electrode layers exposed on the surface of the laminate 10, are formed to be narrow, so the plating layer is deposited in these gap regions as well.

[0127] When the base electrode layer is formed by baking, a conductive paste that will become the first base electrode layer is applied to the first surface portion located on the first end surface LS1 of the laminate 10, the second surface portion located in part on the first main surface TS1, the third surface portion located in part on the second main surface TS2, the fourth surface portion located in part on the first side surface WS1, and the fifth surface portion located in part on the second side surface WS2. Furthermore, a conductive paste that will become the second base electrode layer is applied to the sixth surface portion located on the second end surface LS2 of the laminate 10, the seventh surface portion located in part on the first main surface TS1, the eighth surface portion located in part on the second main surface TS2, the ninth surface portion located in part on the first side surface WS1, and the tenth surface portion located in part on the second side surface WS2.

[0128] Furthermore, when firing the laminated chip before firing and the conductive paste applied to the laminated chip simultaneously, it is preferable to form the baked layer by baking a ceramic material added instead of the glass component. In this case, it is particularly preferable to use the same type of ceramic material as the dielectric layer 20 as the added ceramic material. In this case, the conductive paste is applied to the laminated chip before firing, and the laminated chip and the conductive paste applied to the laminated chip are fired simultaneously to form a laminated body 10 with a baked layer.

[0129] Subsequently, a plating layer is formed on the surface of the base electrode layer and the laminate 10, which consist of a baked layer. When the base electrode layer is formed of a baked layer, two plating layers are formed, for example, a Ni plating layer and a Sn plating layer. The plating layer is formed by an electrolytic plating method. Barrel plating is preferred as the plating method.

[0130] Through this manufacturing process, a multilayer ceramic capacitor 1 is produced.

[0131] Note that the configuration of the external electrode 40 is not limited to the configuration described above. The following describes a modified arrangement of the external electrode 40 of the multilayer ceramic capacitor 1 of this embodiment. In the following description, the same reference numerals are used for components identical to those in the above embodiment, and detailed explanations are omitted. Figure 15 is a cross-sectional view showing a modified arrangement of the external electrode 40 of the multilayer ceramic capacitor 1 of this embodiment, and corresponds to Figure 1.

[0132] In this modified example, the placement of the external electrodes 40 differs from that of the above embodiment. In this modified example, the first external electrode 40A and the second external electrode 40B are placed on only one of either the first main surface TS1 or the second main surface TS2.

[0133] For example, the first external electrode 40A in this modified example has a first surface portion 40A1 located on the first end face LS1, a third surface portion 40A3 located on a part of the second main surface TS2, a fourth surface portion 40A4 located on a part of the first side surface WS1, and a fifth surface portion 40A5 located on a part of the second side surface WS2. In other words, the first external electrode 40A in this modified example is not formed on the first main surface TS1.

[0134] For example, the second external electrode 40B of this modified example has a sixth face portion 40B1 located on the second end face LS2, an eighth face portion 40B3 located on a part of the second main surface TS2, a ninth face portion 40B4 located on a part of the first side surface WS1, and a tenth face portion 40B5 located on a part of the second side surface WS2. In other words, the second external electrode 40B of this modified example is not formed on the first main surface TS1.

[0135] This configuration also suppresses the deterioration of the self-alignment effect and enables stable mounting. Furthermore, by not placing the first external electrode 40A and the second external electrode 40B on either the first main surface TS1 or the second main surface TS2, the height dimension T of the multilayer ceramic capacitor 1 can be reduced, further reducing the height of the multilayer ceramic capacitor 1. In addition, by not placing the first external electrode 40A and the second external electrode 40B on either the first main surface TS1 or the second main surface TS2, the height dimension of the laminate 10 can be secured by the thickness of the external electrodes 40. Therefore, it becomes possible to increase the volume of the effective layer portion of the laminate 10, thereby increasing the capacitance of the multilayer ceramic capacitor 1.

[0136] The multilayer ceramic capacitor 1 of this embodiment provides the following effects.

[0137] (1) The multilayer ceramic capacitor 1 of this embodiment has a plurality of stacked dielectric layers 20 and a plurality of internal electrode layers 30 stacked on the dielectric layers 20, and a laminate 10 having a first main surface TS1 and a second main surface TS2 facing each other in the height direction, a first end surface LS1 and a second end surface LS2 facing each other in the length direction perpendicular to the height direction, and a first side surface WS1 and a second side surface WS2 facing each other in the width direction perpendicular to the height direction and the length direction, and a first surface portion 40A1 located on the first end surface LS1, and A first external electrode 40A having at least one of a second surface portion 40A2 located on a part of the first main surface TS1 and a third surface portion 40A3 located on a part of the second main surface TS2, a fourth surface portion 40A4 located on a part of the first side surface WS1, and a fifth surface portion 40A5 located on a part of the second side surface WS2, and a sixth surface portion 40B1 located on the second end surface LS2, and a seventh surface portion 40B2 located on a part of the first main surface TS1 and an eighth surface portion 40B3 located on a part of the second main surface TS2 A multilayer ceramic capacitor 1 having at least one of the two, and a second external electrode 40B having a ninth surface portion 40B4 located on a part of the first side surface WS1 and a tenth surface portion 40B5 located on a part of the second side surface WS2, wherein when l is the length in the longitudinal direction connecting the first end face LS1 and the second end face LS2 of the laminate 10, w is the length in the width direction connecting the first side surface WS1 and the second side surface WS2, and t is the length in the height direction connecting the first main surface TS1 and the second main surface TS2, w > l > In terms of dimensional relationship t, the lengthwise dimension L4 of the fourth face portion 40A4 and the lengthwise dimension L5 of the fifth face portion 40A5 of the first external electrode 40A are larger than the lengthwise dimension L2 of the second face portion 40A2 and the lengthwise dimension L3 of the third face portion 40A3, and the lengthwise dimension L9 of the ninth face portion 40B4 and the lengthwise dimension L10 of the tenth face portion 40B5 of the second external electrode 40B are larger than the lengthwise dimension L7 of the seventh face portion 40B2 and the lengthwise dimension L8 of the eighth face portion 40B3. This allows for a wider lead-out portion at the end face of the internal electrode layer 30. Furthermore, the distance between the first external electrode 40A and the second external electrode 40B can be shortened, thereby reducing the ESL of the multilayer ceramic capacitor 1.

[0138] Furthermore, when soldering the first external electrode 40A and the second external electrode 40B to mount the multilayer ceramic capacitor 1 onto a substrate, it becomes possible to sufficiently wet the solder even in the fourth and fifth surfaces 40A4 and 40A5 of the first external electrode 40A, and the ninth and tenth surfaces 40B4 of the second external electrode 40B, where the amount of solder wetting tends to be low. As a result, it is possible to suppress changes in the amount of solder in each of these fourth and fifth surfaces 40A4 and 40A5, and the ninth and tenth surfaces 40B5 of the second external electrode 40B, and to suppress differences in tensile stress caused by the solder. Therefore, it is possible to provide an LW reverse type multilayer ceramic capacitor that suppresses deterioration of the self-alignment effect and enables stable mounting.

[0139] (2) In the multilayer ceramic capacitor 1 of this embodiment, the lengthwise dimension L4 of the fourth face portion 40A4 and the lengthwise dimension L5 of the fifth face portion 40A5 of the first external electrode 40A are 110% to 245% of the lengthwise dimension L2 of the second face portion 40A2 and the lengthwise dimension L3 of the third face portion 40A3, and the lengthwise dimension L9 of the ninth face portion 40B4 and the lengthwise dimension L10 of the tenth face portion 40B5 of the second external electrode 40B are 110% to 245% of the lengthwise dimension L7 of the seventh face portion 40B2 and the lengthwise dimension L8 of the eighth face portion 40B3. This makes the above-mentioned effects more pronounced.

[0140] (3) In the multilayer ceramic capacitor 1 of this embodiment, the internal electrode layer 30 has a first internal electrode layer 31 and a second internal electrode layer 32. The first internal electrode layer 31 has a first opposing electrode portion 31A located inside the laminate 10 and a first lead portion 31B connected to the first opposing electrode portion 31A and exposed on a first end face LS1, a part of the first side surface WS1, and a part of the second side surface WS2. The second internal electrode layer 32 has a second opposing electrode portion 32A located inside the laminate 10 and a second lead portion 32B connected to the second opposing electrode portion 32A and exposed on a second end face LS2, a part of the first side surface WS1, and a part of the second side surface WS2. As a result, the distance between the second lead portion 31B of the first internal electrode layer 31 and the second lead portion 32B of the second external electrode 40B can be shortened, thereby shortening the path through which the current flows. Thus, the ESL can be reduced.

[0141] (4) In the multilayer ceramic capacitor 1 of this embodiment, the first external electrode 40A has a first base electrode layer 50A and a first plating layer 60A disposed on the first base electrode layer 50A, and the second external electrode 40B has a second base electrode layer 50B and a second plating layer 60B disposed on the second base electrode layer 50B, and the first base electrode layer 50A and the second base electrode layer 50B are sputtered electrodes. This makes it possible to form the external electrodes with a thin thickness, and the structure makes it easier to secure the thickness of the laminate 10, so that capacitance and the strength of the laminate 10 can be secured.

[0142] (5) In the multilayer ceramic capacitor 1 of this embodiment, the length t in the height direction T connecting the first main surface TS1 and the second main surface TS2 of the laminate 10 is 150 μm or less. The effects of this embodiment can be appropriately obtained in such a low-profile multilayer ceramic capacitor.

[0143] (6) In the multilayer ceramic capacitor 1 of this embodiment, the length t in the height direction T connecting the first main surface TS1 and the second main surface TS2 of the laminate 10 is 100 μm or less. The effects of this embodiment can be appropriately obtained in such a low-profile multilayer ceramic capacitor.

[0144] (7) In the multilayer ceramic capacitor 1 of this embodiment, the length t in the height direction T connecting the first main surface TS1 and the second main surface TS2 of the laminate 10 is 50 μm or less. The effects of this embodiment can be appropriately obtained in such a low-profile multilayer ceramic capacitor.

[0145] <Example of experiment> As a sample for the experiment, a multilayer ceramic capacitor was fabricated and its mountability was evaluated.

[0146] First, as a sample for Example 1, a multilayer ceramic capacitor 1 with the following specifications, as shown in Figures 1 to 10B, was manufactured according to the manufacturing method described above. Also, as a sample for Comparative Example 1, a multilayer ceramic capacitor 101 was manufactured, as shown in Figure 16A, in which the longitudinal dimensions of the side surfaces of the external electrodes 140 (first external electrode 140A, second external electrode 140B) were the same size as the longitudinal dimensions of the main surface. Furthermore, as a sample for Comparative Example 2, a multilayer ceramic capacitor 201 was manufactured, as shown in Figure 17A, in which the longitudinal dimensions of the side surfaces of the external electrodes 240 (first external electrode 240A, second external electrode 240B) were the same size as the longitudinal dimensions of the main surface, and a recess R was provided that extended from the edge of the external electrodes toward the end face of the laminate 10.

[0147] Figure 16A is an external perspective view of the multilayer ceramic capacitor 101 of Comparative Example 1, and corresponds to Figure 1. Figure 16B shows the first internal electrode layer 131 of the multilayer ceramic capacitor 101 of Comparative Example 1, and corresponds to Figure 8A. Figure 16C shows the second internal electrode layer 132 of the multilayer ceramic capacitor 101 of Comparative Example 1, and corresponds to Figure 8B. Figure 17A is an external perspective view of the multilayer ceramic capacitor 201 of Comparative Example 2, and corresponds to Figure 1. Figure 17B shows the first internal electrode layer 231 of the multilayer ceramic capacitor 201 of Comparative Example 2, and corresponds to Figure 8A. Figure 17C shows the second internal electrode layer 232 of the multilayer ceramic capacitor 201 of Comparative Example 2, and corresponds to Figure 8B. Note that the external electrodes are omitted in Figures 16B, 16C, 17B, and 17C.

[0148] (Configuration of Example 1) • Dimensions of the multilayer ceramic capacitor: L × W × T = 0.520 mm × 1.000 mm × 0.100 mm • Dielectric layer ceramic material: BaTiO3 • Capacity: 0.47μF • Rated voltage: 4V • Material of the internal electrode layer: Ni • Pattern of the internal electrode layer: The pattern shown in Figures 8A and 8B. • Structure of the external electrode: Underlay electrode layer: Thin film layer (sputtered electrode) Substrate electrode layer material: Two-layer structure consisting of a NiCr layer and a NiCu layer. Thickness of the underlying electrode layer: Main surface thickness 0.2 μm (thickness of the underlying electrode layer placed on the first main surface TS1 and the second main surface TS2, respectively) Plating layer: Three-layer structure consisting of Cu plating, Ni plating, and Sn plating. Cu plating thickness: 5.5 μm Ni plating thickness: 2.5 μm Sn plating thickness: 3.2 μm The lengthwise dimension of each side surface (fourth and fifth surfaces) of the first external electrode is 180% of the lengthwise dimension of each main surface (second and third surfaces) of the first external electrode. The lengthwise dimension of each side surface (the 9th and 10th surfaces) of the second external electrode is 180% of the lengthwise dimension of each main surface (the 7th and 8th surfaces) of the second external electrode.

[0149] (Composition of Comparative Example 1) • Dimensions of the multilayer ceramic capacitor: L × W × T = 0.520 mm × 1.000 mm × 0.100 mm • Dielectric layer ceramic material: BaTiO3 • Capacity: 0.47μF • Rated voltage: 4V • Material of the internal electrode layer: Ni • Pattern of the internal electrode layer: The pattern shown in Figures 16B and 16C. • Structure of the external electrode: Base electrode layer: A baked layer formed by applying and baking a conductive paste. Material of the base electrode layer: Ni Thickness of the base electrode layer: End face thickness 10 μm, side face thickness 5 μm, main face thickness 5 μm (thickness of the base electrode layer placed on the first main face TS1 and the second main face TS2, respectively) Plating layer: Three-layer structure consisting of Cu plating, Ni plating, and Sn plating. Cu plating thickness: 5.5 μm Ni plating thickness: 2.5 μm Sn plating thickness: 3.2 μm

[0150] (Configuration of Comparative Example 2) • Dimensions of the multilayer ceramic capacitor: L × W × T = 0.520 mm × 1.000 mm × 0.100 mm • Dielectric layer ceramic material: BaTiO3 • Capacity: 0.47μF • Rated voltage: 4V • Material of the internal electrode layer: Ni • Pattern of the internal electrode layer: The pattern shown in Figures 17B and 17C. • Structure of the external electrode: Underlay electrode layer: Thin film layer (sputtered electrode) Substrate electrode layer material: Two layers: NiCr layer and NiCu layer Thickness of the underlying electrode layer: Main surface thickness 0.2 μm (thickness of the underlying electrode layer placed on the first main surface TS1 and the second main surface TS2, respectively) Plating layer: Three-layer structure consisting of Cu plating, Ni plating, and Sn plating. Cu plating thickness: 5.5 μm Ni plating thickness: 2.5 μm Sn plating thickness: 3.2 μm

[0151] Next, we evaluated the implementability using the fabricated samples.

[0152] (Evaluation of implementability 1) The implementability was evaluated using the sample from Example 1 and the samples from Comparative Examples 1 and 2. Each evaluation was performed using 100 samples. Table 1 shows the results of the implementability evaluation.

[0153] [Table 1]

[0154] In Comparative Example 1, eight samples exhibited rotational failure. It is presumed that the increased amount of solder used in the evaluation resulted in a difference in how the solder wetted the first and second external electrodes, leading to the rotational failure.

[0155] In Comparative Example 2, 15 samples exhibited rotational failure. Of these, two were mounted with a large amount of rotation, and one external electrode straddled lands with different polarities, resulting in a short-circuit failure. In the samples of Comparative Example 2, variations in the formation position and thickness of the base electrode layer and the plating layer placed on top of it caused variations in the area and shape of the external electrodes covering the edges of the first and second side surfaces of the laminate. This likely led to variations in how the solder wetted the external electrodes on the first and second side surfaces, potentially resulting in significant differences in the amount of solder wetting. As a result, it is presumed that differences in the tensile stress applied to the multilayer ceramic capacitor caused rotational failure.

[0156] The evaluation method used in this experimental example is described below.

[0157] (Method for evaluating implementability) Figures 18A to 18D illustrate the method for evaluating mountability. First, solder (solder composition Sn-3.0Ag-0.5Cu) is printed onto two lands 310A and 310B located on the glass epoxy substrate 300 shown in Figure 18A. The amount of solder used at this time was 1.5 times the amount used in a normal test to create more severe conditions than those in a normal test. Specifically, a thickness of 150 μm of solder was printed onto each land. As shown in Figure 18A, the width of the land was 1.0 mm, the length of the land was 0.3 mm, and the distance between the two lands was 0.2 mm.

[0158] Next, the multilayer ceramic capacitor is placed on a soldered land. At this time, as shown in Figure 18B, a reference line is taken perpendicular to the width direction of the land at the center of the land's width, and the multilayer ceramic capacitor is placed so that the center of the multilayer ceramic capacitor's width W is located 0.1 mm offset from the reference line in the width direction of the land. At this time, the angle θ between the land and the multilayer ceramic capacitor shown in Figure 18C, that is, the acute angle θ between one of the opposing inner sides of the two lands and the first end face LS1 side or the second end face LS2 side of the external electrode of the multilayer ceramic capacitor, is placed so that it is within 5°.

[0159] Subsequently, the external electrodes of the multilayer ceramic capacitor are soldered to the pads by reflow soldering, and the multilayer ceramic capacitor is mounted on the substrate. After mounting, the mounting state of the multilayer ceramic capacitor is observed, and those where the angle θ between the pad and the multilayer ceramic capacitor is tilted by 5° or more are considered to have a rotation defect. Furthermore, as shown in Figure 18D, if the multilayer ceramic capacitor rotates significantly and is mounted so that the first or second external electrode straddles two pads, it is considered to have a short-circuit defect.

[0160] (Evaluation of implementability 2) In the multilayer ceramic capacitor of Example 1 with the above specifications, 100 additional samples of Examples 2 to 5 were fabricated, each with varying ratios A and B, and their mountability was evaluated in the same manner as above. Table 2 shows the ratios A and B for Examples 1 to 6, along with the evaluation results for mountability.

[0161] "Ratio A": The ratio of the lengthwise dimensions of each side surface (fourth and fifth surfaces) of the first external electrode to the lengthwise dimensions of each surface (second and third surfaces) on the main surface side of the first external electrode. "Ratio B": The ratio of the lengthwise dimensions of each side surface (9th and 10th surface) of the second external electrode to the lengthwise dimensions of each surface (7th and 8th surface) on the main surface side of the second external electrode.

[0162] [Table 2]

[0163] In Example 2, where ratios A and B were 105%, one sample exhibited rotation. This is presumed to be because the difference in tensile stress caused by the solder was not easily suppressed, resulting in rotation. On the other hand, in Example 6, where ratios A and B were 250%, the distance between the surface of the first external electrode on the side and the surface of the second external electrode became shorter, causing solder to adhere to both and conduct electricity, resulting in a short circuit. Therefore, it is preferable that ratios A and B be between 110% and 245%.

[0164] In calculating the above ratios A and B, the dimensions in the length direction L of the second and third surfaces 40A2 and 40A3 of the first external electrode 40A, which are the main surface surfaces, and the seventh and eighth surfaces 40B2 and 40B3 of the second external electrode 40B, as well as the dimensions in the length direction L of the fourth and fifth surfaces 40A4 and 40A5 of the first external electrode 40A, which are the side surfaces, and the ninth and tenth surfaces 40B4 and 40B5 of the second external electrode 40B, are measured by the following method.

[0165] (Measurement method for the surface on the main surface side) The dimensions L in the longitudinal direction of the second surface 40A2 and the seventh surface 40B2 are measured by a microscope at a position halfway across the width W when observed from the first main surface TS1 of the laminate 10. Similarly, the dimensions L in the longitudinal direction of the third surface 40A3 and the eighth surface 40B3 are measured by a microscope at a position halfway across the width W when observed from the second main surface TS2 of the laminate 10.

[0166] (Method for measuring the side surface) The lengthwise dimension L of the fourth face 40A4 and the ninth face 40B4 is measured by a microscope at a position halfway through the height T when observed from the first side surface WS1 of the laminate 10. Similarly, the lengthwise dimension L of the fifth face 40A5 and the tenth face 40B5 is measured by a microscope at a position halfway through the height T when observed from the second side surface WS2 of the laminate 10.

[0167] The present invention is not limited to the configuration of the above embodiments, and can be modified and applied as appropriate without altering the essence of the invention. Furthermore, a combination of two or more of the desirable configurations described in the above embodiments also constitutes the present invention.

[0168] (1) A laminate comprising a plurality of dielectric layers and a plurality of internal electrode layers stacked alternately in the height direction, having a first main surface and a second main surface opposite to each other in the height direction, a first end surface and a second end surface opposite to each other in the length direction perpendicular to the height direction, and a first side surface and a second side surface opposite to each other in the width direction perpendicular to the height direction and the length direction, A first external electrode having a first surface portion located on the first end face, at least one of a second surface portion located on a part of the first main surface and a third surface portion located on a part of the second main surface, a fourth surface portion located on a part of the first side surface, and a fifth surface portion located on a part of the second side surface, A multilayer ceramic capacitor having a second external electrode having a sixth face portion located on the second end face, at least one of a seventh face portion located on a part of the first main face and an eighth face portion located on a part of the second main face, a ninth face portion located on a part of the first side surface, and a tenth face portion located on a part of the second side surface, When the length in the longitudinal direction connecting the first end face and the second end face of the laminate is l, the length in the width direction connecting the first side surface and the second side surface is w, and the length in the height direction connecting the first main surface and the second main surface is t, the dimensional relationship is w > l > t. The longitudinal dimensions of the fourth and fifth surfaces of the first external electrode are larger than the longitudinal dimensions of the second and third surfaces. A multilayer ceramic capacitor in which the longitudinal dimensions of the 9th and 10th faces of the second external electrode are larger than the longitudinal dimensions of the 7th and 8th faces.

[0169] (2) The dimensions in the longitudinal direction of the fourth and fifth surfaces of the first external electrode are 110% or more and 245% or less of the dimensions in the longitudinal direction of the second and third surfaces. The multilayer ceramic capacitor according to (1), wherein the longitudinal dimensions of the ninth and tenth faces of the second external electrode are 110% or more and 245% or less of the longitudinal dimensions of the seventh and eighth faces.

[0170] (3) The internal electrode layer comprises a first internal electrode layer and a second internal electrode layer. The first internal electrode layer has a first opposing electrode portion located inside the laminate, and a first lead portion connected to the first opposing electrode portion and exposed on the first end face, a part of the first side surface, and a part of the second side surface. The multilayer ceramic capacitor according to (1) or (2), wherein the second internal electrode layer has a second counter electrode portion located inside the laminate and a second lead portion connected to the second counter electrode portion and exposed on the second end face, a part of the first side surface, and a part of the second side surface.

[0171] (4) The first external electrode comprises a first base electrode layer and a first plating layer disposed on the first base electrode layer. The second external electrode comprises a second base electrode layer and a second plating layer disposed on the second base electrode layer. The multilayer ceramic capacitor according to any one of (1) to (3), wherein the first base electrode layer and the second base electrode layer are sputtered electrodes.

[0172] (5) The multilayer ceramic capacitor according to any one of (1) to (4), wherein the length in the height direction connecting the first main surface and the second main surface of the laminate is 150 μm or less.

[0173] (6) The multilayer ceramic capacitor according to any one of (1) to (4), wherein the length in the height direction connecting the first main surface and the second main surface of the laminate is 100 μm or less.

[0174] (7) The multilayer ceramic capacitor according to any one of (1) to (4), wherein the length in the height direction connecting the first main surface and the second main surface of the laminate is 50 μm or less. [Explanation of symbols]

[0175] 1. Multilayer ceramic capacitor 10 Laminate 11 Inner layer 12. First main surface side outer layer 13. Second main surface side outer layer 20 Dielectric layer 30 Internal electrode layer 31 First internal electrode layer 31A First counter electrode section 31B First drawer section 31C Second drawer section 31D Third drawer section 32 Second internal electrode layer 32A Second counter electrode section 32B Fourth drawer section 32C Fifth drawer section 32D Sixth drawer 40 External electrode 40A First external electrode 40A1 First side 40A2 2nd side 40A3 Third side 40A4 4th side 40A5 5th side 40B Second external electrode 40B1 6th side 40B2 7th side 40B3 8th side 40B4 9th side 40B5 10th side 50A First base electrode layer 50B Second Underlay Electrode Layer 51A First thin film layer 51B Second thin film layer 60A First plating layer 60B Second plating layer L (Length direction) W (width direction) T Stacking direction LS1 First end face LS2 Second end face WS1 First Aspect WS2 Second Aspect TS1 First main surface TS2 Second main surface l Length in the longitudinal direction w (width) t is the length in the height direction.

Claims

1. A laminate comprising a plurality of dielectric layers and a plurality of internal electrode layers stacked alternately in the height direction, having a first main surface and a second main surface opposite to each other in the height direction, a first end surface and a second end surface opposite to each other in the length direction perpendicular to the height direction, and a first side surface and a second side surface opposite to each other in the width direction perpendicular to the height direction and the length direction, A first external electrode having a first surface portion located on the first end face, at least one of a second surface portion located on a part of the first main surface and a third surface portion located on a part of the second main surface, a fourth surface portion located on a part of the first side surface, and a fifth surface portion located on a part of the second side surface, A multilayer ceramic capacitor having a second external electrode having a sixth face portion located on the second end face, at least one of a seventh face portion located on a part of the first main surface and an eighth face portion located on a part of the second main surface, a ninth face portion located on a part of the first side surface, and a tenth face portion located on a part of the second side surface, When the length in the longitudinal direction connecting the first end face and the second end face of the laminate is l, the length in the width direction connecting the first side surface and the second side surface is w, and the length in the height direction connecting the first main surface and the second main surface is t, the dimensional relationship is w > l > t. The longitudinal dimensions of the fourth and fifth surfaces of the first external electrode are larger than the longitudinal dimensions of the second and third surfaces. The longitudinal dimensions of the ninth and tenth surfaces of the second external electrode are larger than the longitudinal dimensions of the seventh and eighth surfaces. The fourth, fifth, ninth, and tenth surfaces have a plating layer. The internal electrode layer is exposed on the first side surface and the second side surface, The internal electrode layer exposed on the first side surface is directly connected to the plating layers on the fourth and fifth surfaces. A multilayer ceramic capacitor in which the internal electrode layer exposed on the second side surface is directly connected to the plating layers on the ninth and tenth surfaces.

2. The longitudinal dimensions of the fourth and fifth surfaces of the first external electrode are 110% to 245% of the longitudinal dimensions of the second and third surfaces. The multilayer ceramic capacitor according to claim 1, wherein the longitudinal dimensions of the ninth and tenth faces of the second external electrode are 110% or more and 245% or less of the longitudinal dimensions of the seventh and eighth faces.

3. The internal electrode layer comprises a first internal electrode layer and a second internal electrode layer. The first internal electrode layer has a first opposing electrode portion located inside the laminate, and a first lead portion connected to the first opposing electrode portion and exposed on the first end face, a part of the first side surface, and a part of the second side surface. The multilayer ceramic capacitor according to claim 1, wherein the second internal electrode layer has a second counter electrode portion located inside the laminate and a second lead portion connected to the second counter electrode portion and exposed on the second end face, a part of the first side surface, and a part of the second side surface.

4. The first external electrode comprises a first base electrode layer and a first plating layer disposed on the first base electrode layer. The second external electrode comprises a second base electrode layer and a second plating layer disposed on the second base electrode layer. The multilayer ceramic capacitor according to any one of claims 1 to 3, wherein the first base electrode layer and the second base electrode layer are sputtered electrodes.

5. The multilayer ceramic capacitor according to any one of claims 1 to 3, wherein the length in the height direction connecting the first main surface and the second main surface of the laminate is 150 μm or less.

6. The multilayer ceramic capacitor according to claim 5, wherein the length in the height direction connecting the first main surface and the second main surface of the laminate is 100 μm or less.

7. The multilayer ceramic capacitor according to claim 6, wherein the length in the height direction connecting the first main surface and the second main surface of the laminate is 50 μm or less.

8. The multilayer ceramic capacitor according to any one of claims 1 to 3, wherein the leading edges of the fourth, fifth, ninth, and tenth surfaces in the longitudinal direction are parallel to the height direction.

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