Video signal processing device

Abstract

PURPOSE: To provide a video signal processing device that, while suppressing an increase in circuit scale, detects freezing of a video.CONSTITUTION: The video signal processing device comprises: a selection output unit that, upon receiving a video signal, sequentially selects and outputs a series of image data pieces for first to k-th divided image regions; a CRC computation circuit that executes CRC computation on the series of pixel data pieces outputted from the selection output unit; a computation result allocation unit that generates first to k-th inspection values corresponding to the first to k-th divided image regions, on the basis of the result of CRC computation; a sticking determination unit that determines whether there is a frame-to-frame change in the video of the first to k-th divided image regions, on the basis of the first to k-th inspection values corresponding to one frame and first to k-th inspection values corresponding to the other frames; and a video freeze detection unit that checks whether or not there continues a no-change state in the video over a prescribed number of frame periods, and thereby detects whether or not freezing of the video occurs.SELECTED DRAWING: Figure 2

Description

Technical Field

[0004] , , , , ,

[0006] , , , ,

[0005] , , , ,

[0001] The present invention relates to a video signal processing apparatus for detecting sticking of a video signal.

Background Art

[0002] In recent years, in a vehicle display system or the like that displays video captured by an in-vehicle camera on a display, a video signal processing apparatus having a function of detecting sticking of a video signal, so-called freezing, has been proposed (for example, Patent Document 1).

[0003] In the above video signal processing apparatus, video data of the current frame captured by the camera is compared with video data of one frame before, and when both match, it is determined that the video has frozen. At that time, since the amount of video data is generally large, the video data for one frame is divided into a plurality of data pieces, and the corresponding data pieces are compared with each other to determine the presence or absence of freezing.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In a freeze detection circuit as in the above prior art, CRC calculation is performed for each of the divided data pieces, and the presence or absence of freezing is determined by comparing the calculation result for the current frame with the calculation result for one frame before. For this reason, it is necessary to provide a corresponding number of CRC calculation circuits for the number of divided data pieces, and there is a problem that the circuit scale becomes large. [[ID=四十一]]

[0006] This invention has been made in view of the above-mentioned problems, and aims to provide a video signal processing device that can detect video freezing while suppressing an increase in circuit size. [Means for solving the problem]

[0007] The semiconductor device according to the present invention receives a video signal that spans multiple frames and includes a sequence of multiple pixel data fragments, and sequentially selects and outputs a sequence of image data fragments of the first to k (k is an integer of 2 or more) divided image regions that are at the same position across the multiple frames, and applies CRC (Cyclic Redundancy) to the sequence of pixel data fragments output from the selection output unit. The system is characterized by including: a CRC calculation circuit that performs a Check) calculation; a calculation result distribution unit that generates first to k inspection values ​​corresponding to the first to k divided image regions based on the calculation results of the CRC calculation circuit; a fixation determination unit that determines whether or not there is a change between frames in the video of the first to k divided image regions based on the first to k inspection values ​​corresponding to one frame of the video signal and the first to k inspection values ​​corresponding to other frames, and generates first to k fixation determination signals representing the respective determination results; and a video freeze detection unit that detects whether or not a freeze has occurred in the video based on the video signal by determining whether or not a state in which there is no change in the video continues for a predetermined number of frame periods based on the first to k fixation determination signals. [Effects of the Invention]

[0008] According to the video signal processing device of the present invention, it is possible to detect video freezing while suppressing an increase in circuit size. [Brief explanation of the drawing]

[0009] [Figure 1] This block diagram shows a schematic configuration of a driver assistance system including a video signal processing device according to the present invention. [Figure 2] This is a block diagram showing the internal configuration of the video freeze detection circuit in Example 1. [Figure 3]This figure shows the timing for performing CRC calculation and holding the calculation result for each of the video data fragments corresponding to multiple areas. [Figure 4] This block diagram shows the internal configuration of the video freeze detection circuit in the comparative example. [Figure 5] This is a block diagram showing the internal configuration of the video freeze detection circuit in Example 2. [Modes for carrying out the invention]

[0010] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following descriptions and accompanying drawings of each embodiment, substantially identical or equivalent parts are denoted by the same reference numerals. [Examples]

[0011] Figure 1 is a block diagram illustrating the schematic configuration of a driver assistance system 10 including a video signal processing device according to the present invention. The driver assistance system 10 includes a camera 100, a video signal processing device 200, a driving assistance device 300, and a display unit 400.

[0012] Camera 100 is installed on the vehicle and captures the scenery in front of, behind, and on both sides of the vehicle. It generates a video signal that includes a sequence of pixel data fragments corresponding to each pixel and supplies this as a captured video signal VD to the video signal processing device 200.

[0013] Each pixel data fragment in the captured video signal VD consists of 24 bits of data, where, for example, the brightness levels of red, green, and blue are each represented by 8 bits. Therefore, if the number of pixels in one frame of the captured video signal VD is n (where n is an integer greater than or equal to 2), the captured video signal VD containing n pixel data fragments, each consisting of 24 bits of data, is supplied to the video signal processing device 200 for each frame.

[0014] The video signal processing device 200 includes a video freeze detection circuit 21 and a video adjustment circuit 22. The video freeze detection circuit 21 detects whether the video captured by the camera 100 is in a state where it has not changed, a so-called frozen state, based on the captured video signal VD, and supplies a freeze detection signal FS indicating the detection result to the video adjustment circuit 22. In other words, the video freeze detection circuit 21 supplies a freeze detection signal FS to the video adjustment circuit 22 indicating "frozen" if the captured video is in a frozen state, and "not frozen" if it is not in a frozen state.

[0015] When the video adjustment circuit 22 receives a freeze detection signal FS indicating "no freeze," it adjusts the color tone, brightness, contrast, etc., of the captured video signal VD and supplies the resulting signal to the driving support device 300 as the captured video signal VCD. On the other hand, when the video adjustment circuit 22 receives a freeze detection signal FS indicating "freeze present," it supplies a video signal indicating this to the driving support device 300 as the captured video signal VCD. For example, the video adjustment circuit 22 supplies the driving support device 300 with a captured video signal VCD that indicates the captured video is frozen, either in text or with a single color (e.g., blue) across the entire screen.

[0016] The driving support device 300 performs various driving support controls based on the captured video signal VCD, such as distance control to maintain a constant distance from the vehicle in front, lane departure prevention control to encourage driving along the driving lane, proximity notification control to alert the driver of the approaching vehicle, and collision avoidance control. In this case, the driving support device 300 supplies video representing various warning or instruction messages associated with the driving support control to the display unit 400 as a driving support image signal. Alternatively, the driving support device 300 may supply a video signal in which the above-mentioned warning or instruction messages are superimposed on the video based on the captured video signal VCD, or the captured video signal VCD itself, to the display unit 400 as a monitor video signal.

[0017] Furthermore, the driving support device 300 has a navigation function for guiding the way to its own current position and the destination, and supplies a map image signal representing a map image of the surroundings including the own current position to the display unit 400.

[0018] In addition to the main display that displays a video based on the above-described map image signal and driving support image signal, the display unit 400 includes, for example, a light-emitting indicator mounted on the door mirror or a rear monitor display serving as an interior mirror. For example, when the camera 100 captures a view behind the vehicle, the rear monitor display displays a video based on the captured video signal VCD. Incidentally, when the video freeze detection circuit 21 detects that the captured video by the camera 100 is in a frozen state, the main display and the rear monitor display display a video indicating that fact in characters or a single color over the entire screen.

[0019] Next, the detailed configuration of the video freeze detection circuit 21 will be described.

[0020] FIG. 2 is a block diagram showing an example of the internal configuration of the video freeze detection circuit 21. The video freeze detection circuit 21 includes an area determination control unit 11, a selection unit 12, a CRC calculation circuit 13, a CRC calculation result distribution unit 14, a calculation result holding unit 15, a sticking determination unit 16, continuous count determination units 17A to 17D, and a four-area determination unit 18.

[0021] The area determination control unit 11 is a block that performs control for the selection unit 12 to select a video signal (that is, a series of pixel data pieces) to be the target of CRC calculation from the captured video signal VD. In the present embodiment, four areas out of the image area for one frame are set in advance in a register (not shown) provided in the area determination control unit 11 as target areas for video freeze detection, that is, target areas for CRC calculation. The four areas are divided image areas located at the same position in one screen over a plurality of frames.

[0022] Figure 3 shows an example of four image regions that are the target areas for detecting video freezes (hereinafter referred to as the freeze detection target regions). Here, it shows the case where the first area A1, second area A2, third area A3, and fourth area A4 of the image FM for one frame are set as the freeze detection target regions, respectively. Thus, the freeze detection target regions do not necessarily have to be contiguous regions, and they may be regions of different sizes.

[0023] The area to be determined to be stuck is set based, for example, on the vertical position and width and the horizontal position and width. In this embodiment, since the video signal processing device 200 is mounted on the driver assistance system 10, an image area containing information useful for driver assistance, such as the display position of instruments and warning lights, is set as the area to be determined to be stuck.

[0024] The area determination control unit 11 sequentially determines whether each sequence of pixel data fragments included in the captured video signal VD corresponds to a fixation determination area, and controls the selection operation by the selection unit 12 based on the determination result.

[0025] Referring again to Figure 2, the selection unit 12 selects a sequence of pixel data pieces to be subjected to CRC calculation for each pixel data piece, line by line, in accordance with the determination and control of the area to be fixed by the area determination control unit 11, and supplies it to the CRC calculation circuit 13. For example, in the example shown in Figure 3, the sequence of pixel data pieces in the first line, from row p to row q, that is, the region corresponding to the first line of the second area A2, is selected as the sequence of pixel data pieces to be subjected to CRC calculation. Similarly, in the second line, the regions from row n to row m and from row p to row q, that is, the regions corresponding to the first area A1 and the second area A2, are selected as the sequence of pixel data pieces to be subjected to CRC calculation.

[0026] In other words, the area determination control unit 11 and the selection unit 12 constitute a selection output unit that sequentially selects and outputs a sequence of image data fragments of four divided image regions that are in the same position across the multiple frames, respectively, from the captured video signal VD.

[0027] The CRC calculation circuit 13 performs a CRC (Cyclic Redundancy Check) calculation on the sequence of pixel data fragments, line by line, supplied from the selection unit 12. Specifically, the CRC calculation circuit 13 calculates the remainder when the bit sequence corresponding to the sequence of pixel data fragments is divided by a predetermined generating polynomial. The CRC calculation circuit 13 then supplies the calculated remainder as the calculated value Cr to the CRC calculation result distribution unit 14.

[0028] The CRC calculation result distribution unit 14 distributes the calculated value Cr, which is the calculation result of the CRC calculation circuit 13, to calculated values ​​Cr1 to Cr4, which correspond to four fixation determination target areas. For example, calculated value Cr1 corresponds to the first area A1, calculated value Cr2 to the second area A2, calculated value Cr3 to the third area A3, and calculated value Cr4 to the fourth area A4.

[0029] The calculation result holding unit 15 holds the calculated values ​​Cr1 to Cr4 output from the CRC calculation result distribution unit 14 for a period of one frame, and then outputs them. The calculation result holding unit 15 consists of a first calculation result holding unit 15A, a second calculation result holding unit 15B, a third calculation result holding unit 15C, and a fourth calculation result holding unit 15D.

[0030] The first calculation result holding unit 15A holds the calculated value Cr1 output from the CRC calculation result distribution unit 14 and outputs a delayed calculated value Cd1 with a delay of the duration of one frame. The second calculation result holding unit 15B holds the calculated value Cr2 output from the CRC calculation result distribution unit 14 and outputs a delayed calculated value Cd2 with a delay of the duration of one frame. The third calculation result holding unit 15C holds the calculated value Cr3 output from the CRC calculation result distribution unit 14 and outputs a delayed calculated value Cd3 with a delay of the duration of one frame. The fourth calculation result holding unit 15D holds the calculated value Cr4 output from the CRC calculation result distribution unit 14 and outputs a delayed calculated value Cd4 with a delay of the duration of one frame.

[0031] The fixation determination unit 16 determines whether or not image fixation has occurred between frames based on the calculated values ​​Cr1 to Cr4 output from the CRC calculation result distribution unit 14 and the delay calculated values ​​Cd1 to Cd4 output from the calculation result holding unit 15. The fixation determination unit 16 consists of a first fixation determination unit 16A, a second fixation determination unit 16B, a third fixation determination unit 16C, and a fourth fixation determination unit 16D.

[0032] The first fixation determination unit 16A determines whether the calculated value Cr1 and the delayed calculated value Cd1 are the same, and supplies a fixation determination signal C1 indicating "no change" if they are the same, and "change present" if they are different to each other, to the continuous count determination unit 17A. Similarly, the second fixation determination unit 16B determines whether the calculated value Cr2 and the delayed calculated value Cd2 are the same, and supplies a fixation determination signal C2 indicating the determination result to the continuous count determination unit 17B. The third fixation determination unit 16C determines whether the calculated value Cr3 and the delayed calculated value Cd3 are the same, and supplies a fixation determination signal C3 indicating the determination result to the continuous count determination unit 17C. The fourth fixation determination unit 16D determines whether the calculated value Cr4 and the delayed calculated value Cd4 are the same, and supplies a fixation determination signal C4 indicating the determination result to the continuous count determination unit 17D.

[0033] The consecutive count determination unit 17A receives the fixation determination signal C1 and determines whether the "no change" determination result is continuous for a period of M frames or more (where M is an integer greater than or equal to 1), and outputs a determination result J1 indicating that determination result. Similarly, the consecutive count determination units 17B to 17D receive the fixation determination signals C2 to C4 and determine whether the "no change" determination result is continuous for a period of M frames or more, and output determination results J2 to J4 respectively indicating that determination result.

[0034] The 4-area determination unit 18 determines whether or not the video freeze has occurred based on the determination results J1 to J4 supplied from the consecutive count determination units 17A to 17D, and outputs a freeze detection signal FS indicating the determination result. For example, the areas to be detected as stuck (i.e., the first area A1 to the fourth area A4) are assigned a priority order in advance, and the 4-area determination unit 18 determines whether or not the video freeze has occurred by weighting the determination results J1 to J4 according to that priority order. The 4-area determination unit 18 may also determine whether or not the video freeze has occurred using only any of the determination results J1 to J4.

[0035] As described above, in the video freeze detection circuit 21 of this embodiment, the selection unit 12 supplies a sequence of pixel data fragments, one line at a time, corresponding to the area to be determined as fixed to the CRC calculation circuit 13. As a result, the CRC calculation is performed sequentially by time division.

[0036] Figure 4 is a block diagram showing the configuration of a comparative example video freeze detection circuit 21A, which differs from the video freeze detection circuit 21 of this embodiment in that a CRC calculation circuit is provided for each of the four areas to be determined to be stuck.

[0037] In the comparative example video freeze detection circuit 21A, the video signal splitting unit 22 splits the captured video signal VD frame by frame to generate split video signals SP1, SP2, SP3, and SP4. The split video signals SP1, SP2, SP3, and SP4 are video signals corresponding to four fixation target regions.

[0038] Furthermore, in the comparative example video freeze detection circuit 21A, a first CRC calculation circuit 13A, a second CRC calculation circuit 13B, a third CRC calculation circuit 13C, and a fourth CRC calculation circuit 13D are provided, corresponding to each of the divided video signals SP1 to SP4. The first CRC calculation circuits 13A to the fourth CRC calculation circuits 13D each perform CRC calculations independently and output the judgment results.

[0039] In contrast, in the video freeze detection circuit 21 of this embodiment, as described above, the CRC calculation circuit 13 receives a sequence of pixel data fragments from the selection unit 12 and is configured to sequentially perform CRC calculations in a time-division manner. Therefore, only one CRC calculation circuit is needed, and there is no need to provide multiple CRC calculation circuits as in the comparative example.

[0040] Therefore, the video freeze detection circuit 21 of this embodiment makes it possible to detect video freezes while keeping the circuit size down. [Examples]

[0041] Next, Embodiment 2 of the present invention will be described. The video signal processing device of Embodiment 2 differs from the video signal processing device of Embodiment 1 in the configuration of the video freeze detection circuit.

[0042] Figure 5 is a block diagram showing the configuration of the video freeze detection circuit 21B of Embodiment 2. The video freeze detection circuit 21B includes a time division processing unit 26 for determining fixation and a time division processing unit 27 for determining the number of consecutive occurrences.

[0043] The time-division fixing determination processing unit 26 is a processing unit that performs time-division fixing determination processing for each divided image region. Specifically, the time-division fixing determination processing unit 26 sequentially performs time-division fixing determination for the first target region for fixing determination (first area A1) based on a comparison of the calculated value Cr1 and the delayed calculated value Cd1, fixing determination for the second target region for fixing determination (second area A2) based on a comparison of the calculated value Cr2 and the delayed calculated value Cd2, fixing determination for the third target region for fixing determination (third area A3) based on a comparison of the calculated value Cr3 and the delayed calculated value Cd3, and fixing determination for the fourth target region for fixing determination (fourth area A4) based on a comparison of the calculated value Cr4 and the delayed calculated value Cd4. The time-division fixing determination processing unit 26 has, for example, an internal counter (not shown), and performs time-division processing based on the count value of the internal counter.

[0044] The time-division processing unit 27 for determining consecutive counts is a processing unit that performs time-division processing for determining consecutive counts for each divided image region. Specifically, the time-division processing unit 27 receives a fixation determination signal C1 indicating the result of the fixation determination for the first fixation determination target region (first area A1), a fixation determination signal C2 indicating the result of the fixation determination for the second fixation determination region (second area A2), a fixation determination signal C3 indicating the result of the fixation determination for the third fixation determination region (third area A3), and a fixation determination signal C4 indicating the result of the fixation determination for the fourth fixation determination region (fourth area A4). Based on these, it determines whether the "no change" determination result continues for a period of M frames or more (where M is an integer of 1 or more), and outputs determination results J1 to J4 indicating the determination result for each divided image region. The time-division processing unit 27 has, for example, an internal counter (not shown), and performs time-division processing based on the count value of the internal counter.

[0045] In this embodiment, the video freeze detection circuit 21B is provided with one time-division processing unit 26 for fixation determination and one time-division processing unit 27 for consecutive count determination, each of which performs processing in a time-division manner. Therefore, compared to the video freeze detection circuit 21 of Embodiment 1, which has four fixation determination units and four consecutive count determination units corresponding to each of the four fixation determination target areas, the circuit size can be further reduced.

[0046] In other words, the video signal processing device equipped with the video freeze detection circuit 21B of this embodiment makes it possible to detect video freezes while further suppressing the increase in circuit size.

[0047] It should be noted that the present invention is not limited to those shown in the above embodiments. For example, in the above embodiments, the case in which fixation determination is performed on four fixation determination target regions was described as an example. However, the number of segmented image regions subject to fixation determination is not limited to this, and it is sufficient to perform fixation determination on k (k is an integer of 2 or more) fixation determination target regions.

[0048] Furthermore, in the above embodiment, the 4-area determination unit 18 received the determination results J1 to J4 for the first to fourth fixation determination areas, and by weighting and selecting from these results, it was explained as an example of determining whether or not the video is frozen. However, the area determination unit 18 may be configured to select from the determination results at an earlier stage, rather than receiving all of the determination results J1 to J4. For example, if only the fixation determination results for the first area A1 and the second area A2 of the first to fourth areas A4 are needed, the fixation determination by the fixation determination unit 16 and the continuity determination by the continuity determination units 17A to 17D may be performed using only the calculation results corresponding to the first area A1 and the second area A2.

[0049] Furthermore, in the above-described embodiment 2, the case in which the fixation determination time-division processing unit 26 and the consecutive count determination time-division processing unit 27 each perform processing in time division was described as an example. However, at least one of these may be configured to perform processing in time division, while the other performs processing separately as in embodiment 1.

[0050] Furthermore, the above embodiment described an example in which the video freeze detection result is used in a driver assistance system that assists in driving a vehicle. However, the video signal processing device of the present invention is not limited to being installed in a driver assistance system, but can be applied to any system that needs to detect video freezes. [Explanation of symbols]

[0051] 10. Driver assistance systems 21. Video freeze detection circuit 100 Cameras 200 Video signal processing equipment 300 Driving support system 400 Display 11 Area determination control unit 12 Selection Section 13. CRC calculation circuit 14 CRC calculation result distribution section 15 Operation result holding section 15A 1st calculation result holding section 15B 2nd calculation result holding section 15C Third calculation result holding section 15D 4th calculation result holding section 16 Adhesion determination section 16A 1st sticking judgment part 16B 2nd sticking judgment part 16C 3rd adhesion judgment part 16D 4th sticking judgment part 17A~17D Consecutive Count Determination Unit 18 4-area determination unit 22 Video adjustment circuit 26. Split processing unit during fixation determination 27. Time-divided processing unit for determining consecutive counts

Claims

1. A selection output unit receives a video signal that spans multiple frames and includes a sequence of multiple pixel data fragments, and sequentially selects and outputs a sequence of image data fragments of the first to k (where k is an integer of 2 or more) divided image regions that are at the same position across the multiple frames, A CRC (Cyclic Redundancy Check) calculation circuit performs a CRC calculation on the sequence of pixel data fragments output from the selection output unit, A calculation result distribution unit generates first to k inspection values ​​corresponding to the first to k divided image regions, respectively, based on the calculation results of the CRC calculation circuit, A fixation determination unit determines whether there is a change between frames in the video of the first to k divided image regions based on the first to k inspection values ​​corresponding to one frame of the video signal and the first to k inspection values ​​corresponding to other frames, and generates first to k fixation determination signals representing the respective determination results. A video freeze detection unit detects whether or not a freeze has occurred in the video based on the video signal by determining whether or not the video remains unchanged for a predetermined number of frame periods based on the first to k-th fixation determination signals, Includes, The video freeze detection unit includes first to k consecutive count determination units, each of which performs a consecutive count determination process to determine whether or not the state of no change in the video continues for a predetermined number of frame periods for each of the first to k divided image regions. A video signal processing device characterized by detecting whether or not a freeze has occurred in the video based on the video signal, based on the processing result of the consecutive count determination process for at least one of the first to k divided image regions.

2. The image signal processing apparatus according to claim 1, characterized in that the fixation determination unit includes first to k fixation determination circuits that determine whether or not there is a change between frames in the image of the first to k divided image regions, respectively.

3. The video signal processing device according to claim 1, characterized in that the adhesion determination unit sequentially determines, in a time-division manner, whether or not there is a change in the video between frames for each of the first to k divided video regions, based on the first to k inspection values.

4. The video signal processing apparatus according to any one of 1 to 3, characterized in that the video freeze detection unit sequentially determines, in a time-division manner, whether or not the state in which there is no change in the video continues for a predetermined number of frame periods for each of the first to k divided image regions.

5. The aforementioned video signal is composed of multiple lines, each consisting of a sequence of pixel data fragments, for each frame. The video signal processing apparatus according to any one of claims 1 to 4, characterized in that the selection output unit sequentially selects and outputs a series of image data pieces of the first to k divided image regions for each series of pixel data pieces corresponding to one line of the video signal.

Images