Data storage device and method for bit error rate (BER) balancing based on dynamic detection time

Abstract

This invention provides a data storage device and method for balancing the bit error rate (BER) based on dynamic detection time. [Solution] The data storage device 100 comprises a memory 104 having multilevel memory cells and one or more processors 138, one or more processors individually or in combination determining a detection time for reading one of a plurality of pages based on the number of read thresholds involved in reading one of the plurality of pages, and reading one of the plurality of pages using the determined detection time.

Description

[Technical Field]

[0001] The memory of a data storage device may contain memory cells that store two or more bits of data per cell. For example, a quad-level cell (QLC) can store four bits of data. The four bits of data in a QLC cell belong to four pages (lower page, middle page, upper page, and top page), and data can be stored in various logical pages using mapping. For example, using a 4-4-3-4 mapping, data is written to a QLC cell such that the lower, middle, and top pages can be read by sensing the cell voltage in four steps, while the upper page can be read by sensing the cell voltage in three steps. This mapping distributes the number of transitions between adjacent states almost equally across the logical pages. This mapping can be used to balance the bit error rate (BER) between pages. [Brief explanation of the drawing]

[0002] [Figure 1A] This is a block diagram of a data storage device according to one embodiment. [Figure 1B] This is a block diagram illustrating a memory module in one embodiment. [Figure 1C] This is a block diagram illustrating one embodiment of a hierarchical storage system. [Figure 2A] This is a block diagram illustrating the components of a controller for a data storage device illustrated in Figure 1A, according to one embodiment. [Figure 2B] This is a block diagram illustrating the components of a data storage device illustrated in Figure 1A, according to one embodiment. [Figure 3] This is a block diagram of a host and data storage device in one embodiment. [Figure 4] This is a diagram of the 4-3-4-4 bit error rate (BER) balance mapping of the embodiment. [Figure 5] This is a diagram of the non-balanced mapping of 1-2-4-8 in one embodiment. [Figure 6] This is a graph of BER versus stabilization time for the embodiment. [Figure 7] This is a flowchart of the method for an embodiment of BER equilibration based on dynamic detection time. [Modes for carrying out the invention]

[0003] The following embodiments generally relate to data storage devices and methods for bit error rate (BER) balancing based on dynamic detection time. In one embodiment, a data storage device is provided comprising a memory having a multilevel memory cell and one or more processors. The one or more processors are configured, individually or in combination, to determine a detection time for reading one of a plurality of pages based on a number of read thresholds involved in reading one of the plurality of pages, and to read one of the plurality of pages using the determined detection time.

[0004] Another embodiment provides a method to be performed in a data storage device having a multilevel memory cell. This method includes storing multiple pages of data in memory using a mapping that results in an unbalanced bit error rate (BER) among multiple pages, and mitigating the unbalanced BER among the multiple pages by dynamically adjusting the voltage stabilization period of the read voltage depending on which of the multiple pages is being read.

[0005] In yet another embodiment, a data storage device is provided comprising a memory having a multilevel memory cell configured to store multiple pages of data, and means for reading one of the multiple pages using a voltage stabilization time associated with one of the multiple pages, each of the multiple pages being associated with a different voltage stabilization time based on the bit error rate vulnerability of that page.

[0006] Other embodiments are also possible, and each embodiment can be used individually or in combination. Accordingly, various embodiments are described herein with reference to the accompanying drawings.

[0007] Embodiment

[0008] The following embodiments relate to data storage devices (DSDs). As used herein, “data storage device” refers to a non-volatile device that stores data. Examples of DSDs include, but are not limited to, hard disk drives (HDDs), solid state drives (SSDs), tape drives, and hybrid drives. Illustrative details of DSDs are provided below.

[0009] Examples of data storage devices suitable for use in implementing aspects of these embodiments are shown in Figures 1A and 1C. Note that these are merely examples, and other implementations may be used. Figure 1A is a block diagram illustrating a data storage device 100 according to one embodiment. Referring to Figure 1A, the data storage device 100 in this example includes a controller 102 coupled to a non-volatile memory which may consist of one or more non-volatile memory dies 104. As used herein, the term die refers to a collection of non-volatile memory cells and associated circuits for managing the physical operation of those non-volatile memory cells, formed on a single semiconductor substrate. The controller 102 interfaces with a host system and transmits command sequences for read, program, and erase operations to the non-volatile memory dies 104. Also as used herein, the phrases “communicating with” or “coupled with” may mean directly communicating / coupled, or indirectly communicating / coupled through one or more components, which may or may not be illustrated or described herein. The communication / coupled may be wired or wireless.

[0010] The controller 102 (which may be a non-volatile memory controller (e.g., a flash, resistive random-access memory (ReRAM), phase-change memory (PCM), or magnetoresistive random-access memory (MRAM) controller)) may include, individually or in combination, one or more components configured to perform certain functions, including but not limited to those described herein and illustrated in the flowcharts. For example, as shown in Figure 2A, the controller 102 may include one or more processors 138 configured individually or in combination to perform functions, including but not limited to those described herein and illustrated in the flowcharts, by executing computer-readable program code stored in one or more non-temporary memories 139 (e.g., random access memory (RAM) 116 or read-only memory (ROM) 118) inside and / or outside the controller 102. As another example, one or more components may include, but are not limited to, circuitry such as logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers.

[0011] In one exemplary embodiment, the non-volatile memory controller 102 is a device that manages data stored in non-volatile memory by any suitable operating system and communicates with a host, such as a computer or electronic device. In addition to the specific functions described herein, the non-volatile memory controller 102 may have a variety of other functions. For example, the non-volatile memory controller may format the non-volatile memory to ensure that the memory functions properly, map out faulty non-volatile memory cells, and allocate spare cells to replace future failed cells. Some portions of the spare cells may be used to operate the non-volatile memory controller and hold firmware (and / or other metadata used for housekeeping and tracking) to implement other features. While operating, the host can communicate with the non-volatile memory controller when it needs to read data from or write data to the non-volatile memory. If the host provides a logical address from which data is read / written, the non-volatile memory controller can translate the logical address received from the host into a physical address in the non-volatile memory. Non-volatile memory controllers can also perform a variety of memory management functions, including, but are not limited to, wear leveling (distributing writes to avoid wearing out certain blocks of memory that would otherwise be repeatedly written to) and garbage collection (moving only valid pages of data to new blocks after a block is full, so that full blocks can be erased and reused).

[0012] The non-volatile memory die 104 may include any suitable non-volatile storage medium, including resistive random-access memory (ReRAM), magnetoresistive random-access memory (MRAM), phase-change memory (PCM), NAND flash memory cells, and / or NOR flash memory cells. The memory cells may take the form of solid-state (e.g., flash) memory cells and may be once programmable, multiple times programmable, or many times programmable. The memory cells may also be single-level cells (SLC), multiple-level cells (MLC) (e.g., dual-level cells, triple-level cells (TLC), quad-level cells (QLC), etc.), or other memory cell level technologies currently known or to be developed may be used. Furthermore, the memory cells may be manufactured in two-dimensional or three-dimensional form.

[0013] The interface between the controller 102 and the non-volatile memory die 104 may be any preferred flash interface, such as toggle mode 200, 400, or 800. In one embodiment, the data storage device 100 may be a card-based system such as a Secure Digital (SD) or Micro Secure Digital (microSD) card. In another embodiment, the data storage device 100 may be part of an embedded data storage device.

[0014] In the example illustrated in Figure 1A, the data storage device 100 (sometimes referred to herein as a storage module) includes a single channel between the controller 102 and the non-volatile memory die 104; however, the subject matter described herein is not limited to having a single memory channel. For example, in some architectures (such as those shown in Figures 1B and 1C), depending on the capabilities of the controller, two, four, eight or more memory channels may exist between the controller and the memory device. In any of the embodiments described herein, even if a single channel is shown in the drawings, two or more channels may exist between the controller and the memory die.

[0015] Figure 1B illustrates a storage module 200 including a plurality of non-volatile data storage devices 100. Thus, the storage module 200 may include a host and a storage controller 202 that interfaces with a data storage device 204 containing the plurality of data storage devices 100. The interface between the storage controller 202 and the data storage devices 100 may be a bus interface such as a serial advanced technology attachment (SATA), peripheral component interconnect express (PCIe) interface, double-data-rate (DDR) interface, or serial attached small-scale compute interface (SAS / SCSI). In one embodiment, the storage module 200 may be a solid-state drive (SSD) or a non-volatile dual in-line memory module (NVDIMM), as found in server PCs or portable computing devices such as laptop computers and tablet computers.

[0016] FIG. 1C is a block diagram illustrating a hierarchical memory system. The hierarchical memory system 250 includes a plurality of memory controllers 202, each of which controls a respective data storage device 204. A host system 252 can access the memory within the memory system 250 via a bus interface. In one embodiment, the bus interface can be a Non-Volatile Memory Express (NVMe) or Fibre Channel over Ethernet (FCoE) interface. In one embodiment, the system illustrated in FIG. 1C can be a rack-mountable mass storage system accessible by a plurality of host computers, such as would be found in a data center or other location where large amounts of storage are required.

[0017] Referring again to FIG. 2A, the controller 102 in this example also includes a front-end module 108 that interface-connects with a host, a back-end module 110 that interface-connects with one or more non-volatile memory dies 104, and various other components or modules such as, but not limited to, a buffer manager / bus controller module that manages buffers in the RAM 116 and controls internal bus arbitration of the controller 102. The modules can include one or more processors or components, as discussed above. The ROM 118 can store system boot code. In FIG. 2A, it is illustrated as being disposed separately from the controller 102, but in other embodiments, one or both of the RAM 116 and the ROM 118 can be disposed within the controller 102. In still other embodiments, portions of the RAM 116 and the ROM 118 can be disposed both within and outside the controller 102.

[0018] The front-end module 108 includes a host interface 120 and a physical layer interface (PHY) 122 that provide an electrical interface with the host or a next-level storage controller. The choice of host interface 120 may depend on the type of memory being used. Examples of host interface 120 include, but are not limited to, SATA, SATA Express, serially attached small computer system interface (SAS), Fibre Channel, universal serial bus (USB), PCIe, and NVMe. The host interface 120 typically facilitates the transfer of data, control signals, and timing signals.

[0019] The backend module 110 includes an error correction code (ECC) engine 124 that encodes data bytes received from the host and decodes and error-corrects data bytes read from the non-volatile memory. A command sequencer 126 generates command sequences such as program and erase command sequences that are sent to the non-volatile memory die 104. A RAID (Redundant Array of Independent Drives) module 128 manages the generation of RAID parity and the recovery of failed data. RAID parity can be used as an additional level of integrity protection for the data written to the memory device 104. In some cases, the RAID module 128 can be part of the ECC engine 124. A memory interface 130 provides command sequences to the non-volatile memory die 104 and receives status information from the non-volatile memory die 104. In one embodiment, the memory interface 130 can be a double data rate (DDR) interface such as a toggle mode 200, 400, or 800 interface. The controller 102 in this example also includes a media management layer 137 and a flash control layer 132 that controls the overall operation of the backend module 110.

[0020] The data storage device 100 also includes other discrete components 140 such as an external electrical interface, external RAM, resistors, capacitors, or other components that can interface with the controller 102. In an alternative embodiment, one or more of the physical layer interface 122, RAID module 128, media management layer 138, and buffer management / bus controller are optional components that are not required for the controller 102.

[0021] Figure 2B is a block diagram illustrating the components of the non-volatile memory die 104 in more detail. The non-volatile memory die 104 includes peripheral circuits 141 and a non-volatile memory array 142. The non-volatile memory array 142 includes non-volatile memory cells used to store data. The non-volatile memory cells may be any suitable non-volatile memory cells, including two-dimensional and / or three-dimensional ReRAM, MRAM, PCM, NAND flash memory cells and / or NOR flash memory cells. The non-volatile memory die 104 further includes a data cache 156 and address decoders 148, 150 for caching data. In this example, the peripheral circuits 141 include a state machine 152 that provides status information to the controller 102. The peripheral circuits 141 may also comprise one or more components configured to perform certain functions, individually or in combination, including but not limited to the functions described herein and illustrated in the flowcharts. For example, as shown in Figure 2B, the memory die 104 may comprise one or more processors 168 configured individually or in combination to execute computer-readable program code stored in one or more non-temporary memories 169, stored in a memory array 142, or stored outside the memory die 104. As another example, one or more components may include, but are not limited to, circuitry such as logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers.

[0022] In addition to, or instead of, one or more processors 138 (or more generally, components) in the controller 102 and one or more processors 168 (or more generally, components) in the memory die 104, the data storage device 100 may comprise another set of one or more processors (or more generally, components). Generally, one or more processors (or more generally, components) in the data storage device 100, wherever they are located and how many there are, may be configured individually or in combination to perform a variety of functions, including, but not limited to, those described herein and illustrated in the flowcharts. For example, one or more processors (or components) may be located in the controller 102, in the memory device 104, and / or elsewhere in the data storage device 100. Also, different functions may be performed using different processors (or components), or combinations of processors (or components). Furthermore, means for performing functions may be implemented using a controller comprising one or more components (e.g., the processors or other components described above).

[0023] Returning to Figure 2A, the flash control layer 132 (which will be referred to herein as the flash translation layer (FTL)) handles flash errors and interfaces with the host. In particular, the FTL, which may be an algorithm within the firmware, is responsible for the internal memory management and translates writes from the host into writes to memory 104. The FTL may be necessary because memory 104 may have limited durability, can only be written to in page multiples, and / or cannot be written to unless erased as a block. The FTL understands these potential limitations of memory 104, which may not be visible to the host. Therefore, the FTL attempts to translate writes from the host into writes to memory 104.

[0024] The FTL may include a logical-to-physical address (L2P) map (sometimes referred to herein as a table or data structure) and allocated cache memory. In this way, the FTL translates logical block addresses ("logical block addresses, LBAs") from the host to physical addresses in memory 104. The FTL may include, but is not limited to, power-off recovery (so that the data structure of the FTL can be recovered in the event of a sudden power loss) and wear leveling (so that wear is uniform across memory blocks to prevent excessive wear on certain blocks which would lead to a greater likelihood of failure).

[0025] Referring again to the drawings, Figure 3 is a block diagram of a host 300 and a data storage device 100 according to one embodiment. The host 300 can take any preferred form, including but not limited to a computer, mobile phone, tablet, wearable device, digital video recorder, surveillance system, etc. The host 300 in this embodiment (here, a computing device) comprises one or more processors 330 and one or more memories 340. In one embodiment, computer-readable program code stored in one or more memories 340 configures one or more processors 330 to perform operations described herein as being executed by the host 300. Thus, actions performed by the host 300 may be referred to herein as being performed by an application (computer-readable program code) running on the host 300. For example, the host 300 may be configured to send data (e.g., initially stored in the host's memory 340) to the data storage device 100 for storage in the host's memory 104.

[0026] In one embodiment, the memory 104 of the data storage device 100 may include a matrix of memory cells. Each of these cells may be a single-level cell (SLC) capable of storing one bit per cell, or, depending on the storage technology, a multi-level cell (MLC) capable of storing two or more bits per cell. When an MLC memory stores three or four bits per cell, the memory may be referred to as a triple-level cell (TLC) memory or a quad-level cell (QLC) memory, respectively. The following examples describe QLC memory, but it should be understood that any suitable memory technology currently available or to be developed in the future can be used. For example, technologies with other numbers of bits per cell (e.g., TLC) can be used.

[0027] There are multiple ways to store and retrieve data from QLC cells, which can be organized into pages and blocks. In this example, write and read operations are performed at the page level, with one page being 16KB. Four bits within a QLC cell belong to four pages: a low page, a middle page, a high page, and a top page. With four 16KB pages, each page can hold 4,096 data samples, and each sample (e.g., a single element of a 32-bit vector) is 32 bits (i.e., each sample is stored in 32 cells, and each bit is stored in a separate cell). When a write operation is performed in a QLC cell, all four pages may be available. The content of four bits in a QLC cell can be represented as voltage values ​​at the charge gate of the QLC cell. For example, a QLC partition can contain 16 voltage levels arranged in the four logical pages shown as low, middle, high, and top pages. This voltage representation of bit values ​​can be configured so that each individual bit of the stored number can be detected in the minimum number of steps of a voltage sensing operation.

[0028] Logical bit mapping (encoding schemes) can be used to store data on various logical pages of a multibit memory cell. For example, bit error rate (BER) balanced mapping can be used to equalize both the reliability of logical pages (i.e., the vulnerability of different logical pages to erroneous bit flips) and the read latency from different logical pages. For example, the 4-4-3-4 encoding mechanism is a standard bit mapping for QLC cells (used, for example, in BiCS5 memory arrays). In the 4-4-3-4 encoding mechanism, data is written to the QLC cell such that the lower, middle, and top pages can be read by sensing the cell voltage in four steps, while the upper page can be read by sensing the cell voltage in three steps. This standard mapping may also be a gray mapping where the bits representing adjacent states differ by only one bit from each other. This gray mapping characteristic also improves memory reliability.

[0029] Figure 4 shows a 4-3-4-4 bit error rate (BER) balanced mapping of an embodiment. As shown in Figure 4, in a standard Gray code BER balanced mapping, the number of transitions between adjacent states is divided almost equally among logical pages. This mapping has advantages in terms of both reliability and latency. However, this "balanced" mapping is not actually balanced in that the middle page has 3 transitions and the other pages have 4 transitions. Since the vulnerability of data to errors is set according to the "weakest link" (i.e., according to the cell of the logical page with the highest BER), the inventors recognized the need to mitigate the inherent BER differences between logical pages in the "balanced" mapping. Note that while a 4-3-4-4 mapping is used in this example, other fairly balanced mappings can be used.

[0030] In non-balanced mappings, the importance of mitigating the different BERs inherently associated with different logical pages becomes even greater. Figure 5 shows an example of a non-balanced mapping (here, a 1-2-4-8 mapping). As shown in Figure 5, in this mapping, lower pages have only one transition between adjacent states, middle pages have two transitions, upper pages have four transitions, and top pages have eight transitions. This 1-2-4-8 mapping involves one sense operation for lower pages, two sense operations for middle pages, four sense operations for upper pages, and eight sense operations for top pages. Such mappings can result in non-uniform characteristics of logical pages. Because logical pages may have more transitions between 0 and 1, they may be more vulnerable to larger bit errors (due to the increased number of associated sense operations required to read their data), as well as having larger read latencies.

[0031] While balanced mapping offers advantages in terms of reliability, unbalanced mapping can provide the advantages of significantly reduced latency and power consumption, which may be desirable in some applications. For example, unbalanced mapping can be used to enable high-speed read operations (using gears with different data resolutions), as described in U.S. Patent Application No. 19 / 035262, filed January 23, 2025, entitled "Data Storage Device and Method for Non-Balanced Mapping for Variable Read Resolution" (Agent Reference No. 10519 / 4281 (WDA-8003-US)), which is incorporated herein by reference. Another example is the use of unbalanced mapping to support page-by-page programming, thereby reducing the need to buffer large amounts of data.

[0032] Logical pages with unbalanced BERs can impair the overall memory tolerance to BERs. This is because data is typically distributed across logical pages (i.e., equally divided among lower, middle, upper, and top pages), and the ability to reliably retrieve data is determined by the BER of the worst page. The BER level of data not only limits tolerance to uncorrectable error correction code (UECC) events but also affects how often fast decoding (sometimes called "FP mode") is applied, which translates to increased decoding latency and increased power consumption.

[0033] Several measures can be used to handle logical pages with unbalanced intrinsic BERs. For example, one option is to use different parity assignments for each logical page. Assigning more redundant parity bits may allow the use of code with higher BER tolerance. Such areas of more parity can be assigned to logical pages with higher intrinsic BERs. For example, referring to the 4-3-4-4 mapping in Figure 4, more parity can be assigned to lower, upper, and top pages than to middle pages. However, the inherent drawback of this approach is the complexity (and system overhead and inefficiency) of processing different codes at once.

[0034] Another option is to arrange the verification levels of different states unevenly. In this way, the voltage states of logical pages that are more vulnerable to BER can be placed further apart from each other to reduce the amount of state overlap. However, this approach can require very careful fine-tuning and may negatively affect the BER of other pages. Furthermore, such gradual BER balancing tends to become unstable due to memory voltage drift over time (as well as an increase in program erase counts and / or a decrease in data retention).

[0035] Another option is to simply leave the unbalanced BER as is and design the ECC solution according to the worst BER. However, this requires higher ECC overprovisioning and can increase memory costs. Also, this approach may be acceptable for fairly balanced gray mappings (such as 4-3-4-4 mappings), but can be very inefficient for unbalanced gray mappings (such as 1-2-4-8 mappings).

[0036] The following embodiments may be used to provide alternative solutions for handling and mitigating unbalanced BER equalization, addressing this challenge from a different perspective. More specifically, in one embodiment, BER equalization is based on applying different read detection timings to different logical pages.

[0037] As background, data read operations from NAND memory are performed by applying a voltage (Vcg) to the cell. The main part of the read operation is the voltage stabilization period, which is derived from the physical phenomenon of resistive-capacitive (RC) delay. After the Vcg applied to the cell stabilizes, there is another (short) time (sensing integration period) during which the sense amplifier integrates the current flowing through the memory cell as an indicator of the cell voltage level. The measured BER decreases along with the time elapsed during the voltage stabilization period until its value stabilizes, as shown in the graph in Figure 6.

[0038] In one embodiment, the controller 102 of the data storage device 100 is configured to set the length of the voltage stabilization period according to the inherent BER vulnerability of different logical pages. That is, the timing used to detect a particular page may be a function of the number of read thresholds involved in reading the page. Pages with a higher number of read thresholds can use more relaxed timing for detection (to provide a longer voltage stabilization time), which can lead to a minimization of their BER. Pages with a lower number of read thresholds can use more aggressive timing (to provide a shorter voltage stabilization time), which can lead to a reduction in page read latency and an increase in their BER. Overall, the use of this embodiment can result in equalization of the BER across pages while further minimizing the read latency of pages with a lower number of read thresholds. This provides the data storage device with the benefit of supporting data retrieval at multiple read resolutions, as referenced above. For example, frequently accessed low-resolution data (e.g., low-resolution weights of a large language model (LLM), or low-resolution images) can be stored in pages with a small number of read thresholds, thus benefiting from lower read latency. Typically, more rarely accessed high-resolution data (e.g., high-resolution weights of an LLM, or high-resolution versions of images) can be stored in pages with a large number of read thresholds, thus potentially requiring higher read latency (though this may be acceptable due to infrequent access).

[0039] For example, the 1-2-4-8 non-balanced mapping shown in Figure 5 involves the inherent phenomenon of uneven BERs across different logical pages, with lower pages having the lowest BER, intermediate pages having a higher BER, upper pages having an even higher BER, and the top page having the highest BER. To equalize the BERs across different logical pages, the controller 102 in this embodiment, in conjunction with other known methods of BER equalization (such as validation level optimization or different parity assignments per page), may perform the following: Top >T Upper >T Middle >T Lower Thus, different durations T of the voltage stabilization period can be used for different pages, where T represents the page detection time. T can be controlled by detecting the voltage stabilization period.

[0040] In one embodiment, T Top / T Middle / T Upper / T Lower The relationship can be set in a predetermined manner according to a typical relationship between the BER and stabilization period of different pages (for example, as shown in the graph in Figure 6). These relationships between the detection timings of logical pages can be pre-tuned to change with the lifetime of the data storage device 100, or as a function of other operating parameters that affect the device BER. For example, different timings can be set depending on the program-erase count (PEC), read / write temperature, time pool (TMPL), etc. In another embodiment, the stabilization period can be adaptively adjusted via feedback from the controller 102 according to the observed BER (or syndrome weight) of different logical pages.

[0041] Referring again to the drawings, Figure 7 is a flowchart 700 of an embodiment of a method for adaptive setting of stabilization periods to equalize BER unbalanced mappings. This method starts from a default voltage stabilization period (710). For example, in the case of a 1-2-4-8 mapping, TTop >T Upper >T Middle >T Lower where T indicates the page detection time. In this example, during the ongoing operation of the data storage device 100, the controller 102 of the data storage device 100 determines (730) that Mod(PEC / 100) is zero. When Mod(PEC / 100) is zero, the controller 102 updates the stabilization period (740). The update of the stabilization period can be performed in a fixed manner (i.e., pre-set) according to several parameter values, such as program erase count or time pool value (e.g., exceptional X-Temp value, etc.), although it is not limited.

[0042] When Mod(PEC / 100) is not zero, the controller 102 determines (750) whether there is an instruction from the data storage device 100 indicating that the stabilization period needs to be adjusted. This necessity can be initiated, for example, by observing the exceptional BER, syndrome weight, and / or decoding duration for different logical pages. When there is an instruction from the data storage device 100, the controller 102 updates the stabilization period as discussed above (740). When there is no instruction from the data storage device 100, the controller 102 continues the ongoing operation of the data storage device 100 (720).

[0043] There are several advantages associated with these embodiments. For example, these embodiments can be used to help equalize the BER of different logical pages without requiring the use of complex solutions such as different ECC redundancy for logical pages. This can be particularly beneficial when supporting multiple data retrieval solutions, as referenced above. Also, balancing the BER using these embodiments can improve performance and reduce costs. Furthermore, it should be noted that the embodiments described herein can be used alone or in combination with other BER equalization measures (such as the measures described above, but not limited to these). Combining BER equalization measures can provide advantages (for example, when there is a need to address this problem in import situations and complex situations).

[0044] Finally, as mentioned above, any suitable type of memory can be used. Semiconductor memory devices include volatile memory devices such as dynamic random access memory ("DRAM") or static random access memory ("SRAM") devices, non-volatile memory devices such as resistive random access memory ("ReRAM"), electrically erasable programmable read-only memory ("EEPROM"), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory ("FRAM"), and magnetoresistive random access memory ("MRAM"), as well as other semiconductor elements capable of storing information. Each type of memory device may have a different configuration. For example, flash memory devices may be configured in a NAND or NOR configuration.

[0045] Memory devices can be formed from passive and / or active elements in any combination. As a non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include resistivity switching memory elements such as antifuses and phase-change materials, and optionally steering elements such as diodes. Furthermore, as a non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements with charge storage regions such as floating gates, conductive nanoparticles, or charge-storage dielectric materials.

[0046] Multiple memory elements may be configured to be connected in series or so that each element is individually accessible. As a non-limiting example, a flash memory device with a NAND configuration (NAND memory) typically includes memory elements connected in series. A NAND memory array may be configured such that the array consists of multiple strings of memory, each string consisting of multiple memory elements that share a single bit line and are accessed as a group. Alternatively, memory elements may be configured so that each element is individually accessible, for example, in a NOR memory array. NAND and NOR memory configurations are examples, and memory elements may be configured in other ways.

[0047] Semiconductor memory elements placed within and / or on the substrate may be arranged in two or three dimensions, such as in a two-dimensional memory structure or a three-dimensional memory structure.

[0048] In a two-dimensional memory structure, semiconductor memory elements are arranged within a single plane or at a single memory device level. Typically, in a two-dimensional memory structure, the memory elements are arranged in a plane (e.g., the xz plane) that extends substantially parallel to the main surface of the substrate supporting the memory elements. The substrate may be a wafer on which layers of memory elements are formed or within it, or it may be a carrier substrate to which memory elements are attached after they have been formed. In non-limiting embodiments, the substrate may include a semiconductor such as silicon.

[0049] Memory elements may be arranged in an ordered array, such as multiple rows and / or columns, at the level of a single memory device. However, memory elements may be arranged in an irregular or non-orthogonal configuration. Each memory element may have two or more electrodes or contact lines, such as bit lines and word lines.

[0050] A three-dimensional memory array is arranged such that memory elements occupy multiple planes or multiple memory device levels, thereby forming a three-dimensional structure (i.e., in the x, y, and z directions, where the y direction is substantially perpendicular to the main surface of the substrate, and the x and z directions are substantially parallel to the main surface of the substrate).

[0051] As a non-limiting embodiment, a three-dimensional memory structure may be arranged vertically as a stack of multiple two-dimensional memory devices. As another non-limiting example, a three-dimensional memory array may be arranged as multiple vertical columns (e.g., columns substantially perpendicular to the main plane of the substrate, i.e., extending in the y-direction) each having multiple memory elements within each column. The columns may be arranged in a two-dimensional configuration, e.g., in the xz plane, resulting in a three-dimensional arrangement of memory elements having elements on multiple vertically stacked memory planes. Other configurations of three-dimensional memory elements can also constitute a three-dimensional memory array.

[0052] As a non-restrictive example, in a three-dimensional NAND memory array, memory elements may be joined together to form a NAND string within a single horizontal (e.g., xz) memory device level. Alternatively, memory elements may be joined together to form a vertical NAND string that spans multiple horizontal memory device levels. Other three-dimensional configurations can be envisioned where some NAND strings contain memory elements within a single memory level, and others contain memory elements that span multiple memory levels. Three-dimensional memory arrays can also be designed in NOR and ReRAM configurations.

[0053] Typically, in a monolithic three-dimensional memory array, one or more memory device levels are formed on a single substrate. If necessary, a monolithic three-dimensional memory array may also have one or more memory layers within a single substrate, at least partially. In non-limiting embodiments, the substrate may include a semiconductor such as silicon. In a monolithic three-dimensional array, the layers constituting each memory device level of the array are typically formed on layers of memory device levels beneath the array. However, adjacent memory device level layers in a monolithic three-dimensional memory array may be shared, or there may be intervening layers between the memory device levels.

[0054] In this case as well, two-dimensional arrays can be formed separately and then packaged together to form a non-monolithic memory device having multiple memory layers. For example, a non-monolithic stacked memory can be constructed by forming memory levels on separate substrates and then stacking the memory levels on top of each other. The substrates may be thinned or removed from the memory device levels before stacking, but since the memory device levels are initially formed on separate substrates, the resulting memory array is not a monolithic three-dimensional memory array. Furthermore, multiple two-dimensional or three-dimensional memory arrays (monolithic or non-monolithic) can be formed on separate chips and then packaged together to form a stacked chip memory device.

[0055] Related circuitry is typically required for the operation of memory elements and for communication with them. As a non-limiting example, a memory device may have circuitry used to control and drive memory elements to achieve functions such as programming and reading. This related circuitry may be on the same substrate as the memory elements and / or on a separate substrate. For example, a controller for memory read / write operations may be located on a separate controller chip and / or on the same substrate as the memory elements.

[0056] Those skilled in the art will recognize that the present invention is not limited to the two-dimensional and three-dimensional structures described herein, but encompasses all relevant memory structures within the spirit and scope of the invention as described herein and as understood by those skilled in the art.

[0057] The above detailed description is intended to be understood not as a definition of the present invention, but as an illustrative example of selected forms that the invention may take. Only the following claims, including all equivalents, are intended to define the scope of the claimed invention. Finally, it should be noted that any aspect of the embodiments described herein may be used individually or in combination with others.

Claims

1. A memory having a multilevel memory cell configured to store multiple pages of data, Individually or in combination, The detection time for reading one of the multiple pages is determined based on the number of read thresholds involved in reading one of the multiple pages. A data storage device comprising one or more processors configured to read one of the plurality of pages using the determined detection time.

2. The data storage device according to claim 1, wherein each of the plurality of pages is associated with a different detection time, and using different detection times to read different pages among the plurality of pages reduces the unbalanced bit error rate among the plurality of pages.

3. The data storage device according to claim 2, wherein the aforementioned unbalanced bit error rate is caused by a 4-4-3-4 mapping.

4. The data storage device according to claim 2, wherein the aforementioned unbalanced bit error rate is caused by 1-2-4-8 mapping.

5. The data storage device according to claim 1, wherein the multilevel memory cell comprises a quad-level cell (QLC) configured to store the top page, upper page, middle page, and lower page of data, and the detection time for the top page, upper page, middle page, and lower page increases progressively.

6. The data storage device according to claim 1, wherein the detection time for the plurality of pages is predetermined.

7. The data storage device according to claim 1, wherein the detection time for the plurality of pages is dynamically adjusted.

8. The detection time for the plurality of pages is dynamically adjusted based on the program erase count, read / write temperature, and / or timepool parameters, according to claim 7, the data storage device.

9. The data storage device according to claim 1, wherein one or more processors are further configured to support data retrieval at multiple read resolutions, individually or in combination.

10. The data storage device according to claim 1, wherein the memory comprises a three-dimensional memory.

11. In a data storage device equipped with multilevel memory cells, Storing multiple pages of data in the memory using a mapping that results in an unbalanced bit error rate (BER) among the multiple pages, A method comprising reducing the unbalanced BER among the plurality of pages by dynamically adjusting the voltage stabilization period of the read voltage depending on which of the plurality of pages is being read.

12. The method according to claim 11, wherein the voltage stabilization period is dynamically adjusted based on the program erase count, read / write temperature, and / or timepool parameters.

13. The method according to claim 11, wherein the voltage stabilization period is dynamically adjusted based on the observed bit error rate and / or observed syndrome weight.

14. The method according to claim 11, wherein the mapping includes a 4-4-3-4 mapping.

15. The method according to claim 11, wherein the mapping includes a 1-2-4-8 mapping.

16. The method according to claim 11, further comprising performing an action to further alleviate the unbalanced BER between the plurality of pages.

17. The method according to claim 16, wherein the operation includes using a different parity assignment for each of the plurality of pages.

18. The method according to claim 16, wherein the operation includes using a different verification level for each of the plurality of pages.

19. The method according to claim 16, wherein the operation includes using an error correction code designed for the worst BER in the plurality of pages.

20. A memory having a multilevel memory cell configured to store multiple pages of data, A data storage device comprising means for reading one of a plurality of pages using a voltage stabilization time associated with one of the plurality of pages, wherein each of the plurality of pages is associated with a different voltage stabilization time based on the bit error rate vulnerability of that page.

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