Semiconductor memory

Abstract

To suppress an increase in circuit area.SOLUTION: A semiconductor storage device (1) includes a memory cell array (3) in which a plurality of memory cells (MC) is connected to a bit line pair (BLT). Upon data reading of the memory cell (MC), a replica bit line signal is outputted to a replica bit line (TRKBL) in response to a replica word line signal, and a sense amplifier signal (SAE) changes in response to the replica bit line signal whereby a sense amplifier circuit (21) is driven. Moreover, upon data writing onto the memory cell (MC), a low potential side of the bit line pair targeted for writing is set at a negative potential by a negative potential boost signal (BOOSTX) outputted from a negative potential generation circuit (25).SELECTED DRAWING: Figure 1B

Description

Technical Field

[0001] This disclosure relates to a semiconductor memory device.

Background Art

[0002] With the increase in the speed of semiconductor memory devices, it has become difficult to generate various operation signals required for their operations at appropriate timings.

[0003] Patent Document 1 discloses a semiconductor memory device that uses a replica circuit to generate a start signal for a sense amplifier circuit in a semiconductor memory device. The replica circuit includes replica memory cells having a structure similar to the memory cells included in the memory array.

[0004] Patent Document 2 shows that negative bit line technology is used as a write assist technique in a semiconductor memory device. In this device, a dummy bit line is connected as a load to a circuit that generates a timing signal for pulling down the bit line to a negative potential.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0006] However, a circuit for generating a start signal for a conventional sense amplifier circuit is used only when reading data from a memory cell and is not used when writing data to the memory cell (see, for example, Patent Document 1). Therefore, a separate circuit for data writing is required.

[0007] Furthermore, conventional write assist technology is used only when writing data to a memory cell and not when reading data from the memory cell (see, for example, Patent Document 2). Therefore, a separate circuit is required for data reading.

[0008] In other words, with conventional technology, if you try to handle both data reading and data writing to a memory cell, you need to install separate circuits for each, which leads to the problem of increased circuit area.

[0009] This disclosure is made to solve the above-mentioned problems and aims to eliminate the area overhead caused by having separate circuits for data reading and writing. [Means for solving the problem]

[0010] In one aspect of the present disclosure, the semiconductor memory device includes a memory cell array comprising a plurality of memory cells, each of which is connected to a corresponding bit line pair; a replica bit line circuit comprising a plurality of replica memory cells, the plurality of replica memory cells outputting a replica bit line signal to a common replica bit line in response to a replica word line signal; a sense amplifier circuit that amplifies the signal of the bit line pair in response to a sense amplifier activation signal generated based on the replica bit line signal; and a function to lower the potential of one bit line of the bit line pair connected to the memory cell to be written to, and to negatively charge the bit line on the lower potential side in response to a negative potential boost signal. The system comprises a writing circuit that sets the potential to a certain level, and a circuit that generates the negative potential boost signal, the negative potential boost signal generation circuit which includes the replica bit line in the signal generation path of the negative potential boost signal, wherein when data is read from the memory cell, the replica bit line signal is output to the replica bit line in accordance with the replica word line signal, and the sense amplifier circuit is driven by the sense amplifier activation signal changing in accordance with the replica bit line signal, and when data is written to the memory cell, the negative potential boost signal output from the negative potential boost signal generation circuit sets the low potential side of the bit line pair to be written to a negative potential.

[0011] According to this embodiment, the sense amplifier activation signal generated based on the replica bit line signal can be used to supply the sense amplifier circuit with the optimal activation timing. Furthermore, since the replica bit line connected to the replica memory cell is connected to the signal generation path of the negative potential boost signal, the signal can be output from the negative potential boost signal generation circuit at the optimal activation timing without the need to provide a new dummy bit line. In other words, since control signals corresponding to data reading and writing are generated using a single replica circuit, the area overhead that would be incurred by providing separate circuits for data reading and writing can be eliminated. [Effects of the Invention]

[0012] According to this disclosure, in a semiconductor memory device, a single replica circuit is used to generate control signals corresponding to data reading and writing, thereby eliminating the area overhead that would otherwise be incurred by providing separate circuits for data reading and writing. [Brief explanation of the drawing]

[0013] [Figure 1A] Functional block diagram illustrating a part of the configuration of a semiconductor memory device (first embodiment) [Figure 1B] This figure shows an example of the circuit configuration of an amplifier circuit constituting a semiconductor memory device (first embodiment). [Figure 2] Figure 1A shows an example of a memory cell circuit configuration. [Figure 3] Figure 1A shows an example of the circuit configuration of a replica cell. [Figure 4A] Diagram illustrating the generation path of the sense amplifier activation signal. [Figure 4B] Diagram illustrating the generation path of a negative potential boost signal. [Figure 5] Timing chart showing an example of operation of a semiconductor memory device (first embodiment) [Figure 6] Figure 1B equivalent to a semiconductor memory device (modification example 1 of the first embodiment) [Figure 7] Figure 1A equivalent to a semiconductor memory device (modified example 2 of the first embodiment) [Figure 8] Figure 1B equivalent to a semiconductor memory device (modified example 2 of the first embodiment) [Figure 9] Figure 1B equivalent to the semiconductor memory device (second embodiment) [Figure 10] Timing chart showing an example of operation of a semiconductor memory device (second embodiment) [Modes for carrying out the invention]

[0014] Hereinafter, embodiments will be described with reference to the drawings. In the following description, the same reference numerals may be used to describe a signal line and the signal passing through the signal line.

[0015] <First Embodiment> The semiconductor memory device 1 includes a memory cell array 3, a replica bit line circuit 4, and an amplifier circuit 2.

[0016] FIG. 1 (FIGS. 1A and 1B) shows a configuration example of the semiconductor memory device 1 according to the first embodiment. The semiconductor memory device 1 includes the configuration 1a in FIG. 1A and the configuration 1b in FIG. 1B. FIG. 1A shows a configuration example of the memory array 3, the replica bit line circuit 4, and their peripheral circuits as the configuration 1a. FIG. 1B shows a configuration example of the amplifier circuit 2 and its peripheral circuits as the configuration 1b.

[0017] -Memory Cell Array- As shown in FIG. 1A, the memory cell array 3 includes a plurality of memory cells MC arranged in an array of m rows (m is a natural number) × n columns (n is a natural number).

[0018] The memory cell array 3 includes a plurality (m in FIG. 1A) of word lines WL arranged corresponding to the rows of the memory cells MC, and a plurality (n in FIG. 1A) of bit line pairs BLT arranged corresponding to the columns of the memory cells MC. The bit line pair BLT is composed of paired bit lines BL and BLX. The word line WL extends in the first direction (hereinafter referred to as the "row direction"). The bit lines BL and BLX extend in a second direction (hereinafter referred to as the "column direction") intersecting the first direction. Each memory cell MC is connected to the word line WL of the corresponding row and the bit line pair BLT (bit lines BL and BLX) of the corresponding column according to the arrangement position.

[0019] The word line WL is connected to the row decoder 8. The row decoder 8 activates the word line WL of the row including the memory cell MC to be operated according to the row address specified by the CPU (not shown).

[0020] <000The bit line pair BLT is connected to amplifier circuit 2, which will be described later.

[0021] Figure 2 is a circuit diagram showing the internal configuration of the memory cell MC in Figure 1A. In Figure 2, the memory cell MC comprises N-type transistors NA1 and NA2, P-type transistors PL1 and PL2, and N-type transistors ND1 and ND2.

[0022] N-type transistor NA1 has its gate connected to the word line WL and its source connected to the bit line BL. N-type transistor NA2 has its gate connected to the word line WL and its source connected to the bit line BLX. P-type transistor PL1 has the power supply voltage VDD as its source and its drain connected to the drain of N-type transistor NA1. N-type transistor ND1 has its gate connected to the gate of P-type transistor PL1, its drain connected to the drain of P-type transistor PL1, and its source connected to ground potential VSS. P-type transistor PL2 has its gate connected to the drain of N-type transistor NA1, its source connected to the power supply voltage VDD, and its drain connected to the drain of N-type transistor NA2. N-type transistor ND2 has its gate connected to the gate of P-type transistor PL2, its drain connected to the drain of P-type transistor PL2, and its source connected to ground potential VSS. The connection node between the gate of P-type transistor PL1 and the gate of N-type transistor ND1 is connected to the drain of N-type transistor NA2.

[0023] Here, a first inverter is formed by a P-type transistor PL1 and an N-type transistor ND1. A second inverter is formed by a P-type transistor PL2 and an N-type transistor ND2. A latch circuit is formed by connecting the input terminal of the first inverter to the output terminal of the second inverter, and connecting the output terminal of the first inverter to the input terminal of the second inverter.

[0024] -Replica Bit Wire Circuit- Returning to Figure 1A, the replica bit line circuit 4 comprises multiple replica memory cells RMCs arranged in a column direction. In the example in Figure 1A, the replica bit line circuit 4 comprises m replica memory cells RMCs.

[0025] Figure 3 is a circuit diagram showing the internal configuration of the replica memory cell RMC shown in Figure 1A. In Figure 3, the transistors constituting the replica memory cell RMC are the same size as the transistors constituting the memory cell MC shown in Figure 2.

[0026] In the replica memory cell (RMC), the power supply voltage VDD is supplied to the gates of the P-type transistor PL1 and the N-type transistor ND1 in the aforementioned latch circuit.

[0027] Furthermore, replica memory cells (RMCs) differ from memory cells (MCs) in that the gate of the N-type transistor NA1 is connected to the replica word line TRKWL. The replica word line TRKWL of some replica memory cells (RMCs) is connected to the row decoder 8, while the replica word line TRKWL of the remaining replica memory cells (RMCs) is connected to ground potential VSS. By changing the number of replica memory cells (RMCs) connected to this row decoder 8, the delay amount, which will be described later, can be adjusted. In the following explanation, replica memory cells (RMCs) whose replica word line TRKWL is connected to the row decoder 8 may be referred to as first replica memory cells (RMCs), and replica memory cells (RMCs) whose replica word line TRKWL is connected to ground potential VSS may be referred to as second replica memory cells (RMCs) to distinguish them. The input signal received from the replica word line TRKWL of the first replica memory cell (RMC) is generated based on the precharge signal PCG and the read enable signal RE.

[0028] During data retrieval, the replica word line TRKWL of the first replica memory cell RMC becomes "H level" (hereinafter simply referred to as 'H'), causing the replica bit line TRKBL to become "L level" (hereinafter simply referred to as 'L'). As a result, the replica bit line signal TRKBL is output from the first replica memory cell RMC. Based on this replica bit line signal TRKBL, the sense amplifier activation signal SAE, which will be described later, is then generated.

[0029] Furthermore, during data writing, the replica word line TRKWL becomes 'L', and the first replica memory cell RMC does not operate. As a result, the first and second replica memory cells RMC act only as load capacitance for the replica bit line TRKBL. The detailed timing will be explained later.

[0030] -Amplifier Circuit- As shown in Figure 1B, in this example, one amplifier circuit 2 is provided for every two columns. Specifically, the column connected to bit line pair BLT[0] (hereinafter referred to as the "first column") and the column connected to bit line pair BLT[1] (hereinafter referred to as the "second column") are connected to amplifier circuit 2.

[0031] The amplifier circuit 2 comprises a sense amplifier circuit 21, a writing circuit, a negative potential boost signal generation circuit, and a negative potential generation circuit 25.

[0032] (Sense amplifier circuit) The sense amplifier circuit 21 amplifies the signal from the bit line pair BLT in response to the sense amplifier activation signal SAE and outputs it to the read data line pair RDT. The read data line pair RDT consists of a pair of read data lines RD and RDX.

[0033] More specifically, in this example, a column selector 23 is provided between the first and second columns and the sense amplifier circuit 21. The column selector 23 selects one of the first or second columns based on the column selection signal RCA(RCA0X,RCA1X). The column selection signal RCA is generated in the column control circuit 22 based on the column selection signal COLX[1:0].

[0034] The sense amplifier circuit 21 receives the signal from the bit line pair BLT of the selected column, amplifies the signal, and outputs it to the read data line pair RDT.

[0035] In Figure 4A, the generation path of the sense amplifier activation signal SAE is shown by a thick solid line in a circuit configuration common to Figure 1B. The sense amplifier activation signal SAE is generated using a predetermined combinational circuit based on the replica bit line signal TRKBL output from the first replica memory cell RMC. In other words, the replica bit line signal TRKBL output from the first replica memory cell RMC is supplied to the above combinational circuit via the replica bit line TRKBL.

[0036] (Programming circuit) The writing circuit includes a write amplifier that has the function of raising the potential of one bit line of the bit line pair BLT to be written and lowering the potential of the other bit line. Furthermore, the write amplifier has the function of lowering the bit line on the lower potential side of the bit line pair BLT (the "other bit line" mentioned above) to a negative potential in response to a negative potential boost signal BOOSTX. The writing circuit also includes a write driver 26 driven by the write signal WRITE. The write signal WRITE is generated based on the write enable signal WE and the precharge signal PCG. In addition, a precharge circuit 24 that operates based on the precharge signal PCG is provided in each column.

[0037] (Negative potential boost signal generation circuit) The negative potential boost signal generation circuit is a circuit that generates the negative potential boost signal BOOSTX described above and supplies it to the light amplifier. The signal generation path for the negative potential boost signal BOOSTX includes the replica bit line TRKBL.

[0038] In the negative potential generation circuit 25, the signal generation path for the negative potential boost signal BOOSTX forms a circuit equivalent to the data writing path. Here, "equivalent circuit" refers to a circuit configured such that the delay amount in the signal generation path is as similar as possible.

[0039] After forming an equivalent circuit as described above, we add configurations that increase the delay amount of some circuits and make changes to various design parameters. As a result, the negative potential drive of the low-potential bit lines by the negative potential boost signal BOOSTX will only occur after the low-potential bit lines BL / BLX are reliably driven to the ground potential VSS.

[0040] A specific example is explained below. In Figure 4B, the signal generation path for the negative potential boost signal BOOSTX is shown by a thick solid line, in a circuit configuration common to Figure 1B. In other words, in this example, the circuits located in the signal generation path for the negative potential boost signal BOOSTX constitute the negative potential boost signal generation circuit.

[0041] In the example shown in Figure 4B, the signal generation path for the negative potential boost signal BOOSTX includes, in addition to the replica bit line TRKBL, a first replica circuit 51, a second replica circuit 52, and a third replica circuit 53.

[0042] The first replica circuit 51 is a replica circuit of the light driver 26. Specifically, it is a replica circuit using transistors of the same size and polarity as the light driver 26, and the circuit is configured so that the input-output delay is as close as possible to that of the light driver 26.

[0043] The second replica circuit 52 is a replica circuit of the combinational circuit within frame 28 in Figure 4B. The second replica circuit 52 is configured so that the input-output delay is as similar as possible to that of the combinational circuit within frame 28.

[0044] The third replica circuit 53 is a replica circuit of the combinational circuit within frame 29 in Figure 4B. The third replica circuit 53 is configured so that the input-output delay is as close as possible to that of the combinational circuit within frame 29.

[0045] In this way, by providing the first to third replica circuits 51 to 53 in the signal generation path of the negative potential boost signal BOOSTX, it is possible to generate a delay equivalent to that of the light amplifier circuit.

[0046] In the signal generation path of the negative potential boost signal BOOSTX configured as described above, for example, the driving force of transistor TN0 in the third replica circuit 53 corresponding to transistor TN2 in frame 29 is made smaller than that of transistor TN2. Similarly, the driving force of transistor TN1 in the third replica circuit 53 corresponding to transistor TN3 in frame 29 is made smaller than that of transistor TN3. The method for reducing the driving capability of transistors TN0 and TN1 at this time is not particularly limited, but for example, it may be done by reducing the gate width, increasing the gate length, and / or increasing the threshold voltage.

[0047] -Semiconductor memory device operation- Next, referring to Figure 5, the data read operation and data write operation to the memory cell MC in the semiconductor memory device 1 will be explained.

[0048] (Data reading operation) First, let's explain the data read operation of the memory cell MC. In this example, we will explain the case where the first column is selected when the column selection signal COLX[0]='L' is set, and the bit line BL[0]='L' is read.

[0049] First, the light enable signal WE goes 'L' before the precharge signal PCG rises. The light enable signal WE remains in the same state during the period when the precharge signal PCG is 'H'.

[0050] After the 'L' state of the write enable signal WE is confirmed, the precharge signal PCG and the signal PCGSA, which is an expanded pulse width version of the precharge signal PCG, rise to 'H'. Signal PCGSA is a signal that goes 'H' only during data readout operations.

[0051] When the precharge signal PCG rises, the word line signal WL and the replica word line signal TRKWL corresponding to the memory cell MC to be read rise to 'H'. Also, almost simultaneously with the rise of the precharge signal PCG, the column selection signal COLX[0] and the signal READX fall to 'L'. The signal READX is a signal that changes based on the write enable signal WE and the precharge signal PCG.

[0052] When the word line signal WL and the replica word line signal TRKWL rise to 'H', the bit line signal BL[0] and the replica bit line signal TRKBL begin to fall to 'L'.

[0053] Here, the replica bit line signal TRKBL is adjusted so that when the bit line signal BL[0] drops to the level required for sense amplifier operation, it drops to the threshold of the NOR gate (e.g., 1 / 2VDD). The NOR gate is a circuit that receives the replica bit line signal TRKBL as input.

[0054] The sense amplifier activation signal SAE changes based on the output of this NOR circuit. Specifically, when the bit line signal BL[0] drops to the level required for sense amplifier operation, the sense amplifier activation signal SAE rises to 'H'. This activates the sense amplifier, reading 'L' as the read data signal RD[0] and 'H' as the read data signal RDX[0].

[0055] Then, after the sense amplifier activation signal SAE becomes 'H', the precharge signal PCG, word line signal WL, and replica word line signal TRKWL become 'L', and the column selection signal COLX[0] and signal READX become 'H'. Subsequently, the bit line signal BL[0] is precharged to 'H'.

[0056] Once the readout output is confirmed, the PCGSA signal becomes 'L', the sense amplifier activation signal SAE also becomes 'L', and the readout operation ends.

[0057] As described above, by using the replica memory cell RMC for the read operation, the optimal startup timing can be supplied to the sense amplifier circuit 21.

[0058] (Data writing operation) Next, we will explain the data writing operation to the memory cell MC. In this example, we will explain the case where the first column is selected by setting the column selection signal COLX[0]='L', and the write data signal WDX[0]='H' is written to the bit line BL[0]. In other words, the bit line BL[0]='L' is written.

[0059] First, the light enable signal WE goes 'H' before the precharge signal PCG rises. As mentioned above, the light enable signal WE remains in the same state for the duration that the precharge signal PCG is 'H'.

[0060] After the 'H' state of the write enable signal WE is confirmed, the precharge signal PCG rises to 'H'. During data writing, the signal PCGSA remains 'L' and does not change.

[0061] The write data signal WDX[0] goes high before the word line signal WL and the write signal WRITE rise. Since the write data signal WDX[0] is the inverse of the write data signal WD[0], the write data signal WD[0] goes low. This state is maintained while the word line signal WL and the write signal WRITE are in the high state.

[0062] When the precharge signal PCG rises, the word line signal WL and the write signal WRITE rise to 'H'. Also, almost simultaneously with the rise of the precharge signal PCG, the column selection signal COLEX[0] falls to 'L'.

[0063] At this time, the write enable signal WE='H', so the inverse signal RE of the write enable signal WE is 'L'. Consequently, the replica word line signal TRKWL remains 'L', and unlike during data reading, the replica memory cell RMC does not operate.

[0064] When the word line signal WL rises to 'H', the bit line signal BL[0] begins to fall to 'L'. Additionally, the replica bit line signal TRKBL, which is located in the signal generation path of the negative potential boost signal BOOSTX, also begins to fall.

[0065] During the falling edge of the replica bit line signal TRKBL, the replica bit line TRKBL and the replica memory cell RMC act as loads for the replica bit line signal TRKBL.

[0066] Here, the negative potential boost signal BOOSTX is adjusted to become 'L' when the bit line signal BL[0] drops to ground potential VSS. As a result, the signal WGND becomes negative, causing the bit line signal BL[0] to also become negative, and the desired data is written to the memory cell MC to be written.

[0067] When the write operation is complete, the precharge signal PCG, word line signal WL, and write signal WRITE become 'L', and the column selection signal COLEX[0] becomes 'H'. Then, when the precharge signal PCG becomes 'L', the bit line signal BL[0] is precharged to 'H'.

[0068] As described above, for the write operation, in generating the timing signal using negative bit line technology, the replica bit line TRKBL connected to the replica memory cell RMC is connected, so the optimal startup timing can be supplied to the negative potential generation circuit 25 without providing a new dummy bit line.

[0069] As described above, this embodiment makes it possible to realize a circuit that generates various operating signals for the semiconductor memory device 1 at appropriate timings without area overhead. More specifically, a single replica circuit is used to generate control signals corresponding to data reading and writing. This makes it possible to generate control signals at the optimal startup timing and eliminates the area overhead that would otherwise be incurred by providing separate circuits for data reading and writing.

[0070] -Experimental Variation 1- Here, we will describe a modified example 1 of the semiconductor memory device according to the first embodiment.

[0071] Figure 6 is a diagram corresponding to Figure 1B for this modified example 1. The configuration of Figure 1A can be the same as that of the first embodiment described above.

[0072] Figure 6 differs from Figure 1B in that a delay buffer 56 is provided at the location that is both the replica bit line TRKBL and the signal generation path for the negative potential boost signal BOOSTX.

[0073] By providing the delay buffer 56 in this way, in addition to adjusting the delay amount in transistors TN0 and TN1 as described above, or alternatively, adjusting the delay in the signal generation path of the negative potential boost signal BOOSTX, thereby optimizing the timing of the negative potential boost signal BOOSTX.

[0074] -Variation 2- Here, we will describe a modified example 2 of the semiconductor memory device 1 according to the first embodiment.

[0075] Figure 7 is the equivalent of Figure 1A for this modified example 2. Also, Figure 8 is the equivalent of Figure 1B for this modified example 2.

[0076] This modified version 2 differs from the configuration in Figure 1A in that the replica bit line TRKBL is branched into two. In this modified version, as shown in Figure 7, the replica bit line TRKBL comprises a first replica bit line TRKBL1 and a second replica bit line TRKBL2.

[0077] The first replica bit line TRKBL1 corresponds to the replica bit line TRKBL in Figure 1A, extends parallel to the bit line pair BLT, and is connected to each of the multiple replica memory cells RMC.

[0078] The second replica bit line TRKBL2 branches off at the connection point between the first replica bit line TRKBL1 and the replica memory cell RMC, which is the furthest from the amplifier circuit 2. After branching, the second replica bit line TRKBL2 folds back at a point further from the amplifier circuit 2 than the furthest replica memory cell RMC, and extends parallel to the first replica bit line TRKBL1.

[0079] The first replica bit line TRKBL1 is used to supply the replica bit line signal TRKBL for generating the sense amplifier activation signal SAE. In other words, the first replica bit line TRKBL1 is connected to the circuit for generating the sense amplifier activation signal SAE.

[0080] Furthermore, the first replica bit line TRKBL1 is connected to the output node of transistor TN0 of the third replica circuit 53, which constitutes the negative potential boost signal generation circuit. The circuit after transistor TN0 (a "NOR circuit" in this example) is connected via the first replica bit line TRKBL1 and the second replica bit line TRKBL2. As a result, a larger resistor and capacitance than those shown in Figure 1A are connected between transistor TN0 and the subsequent circuit, which increases the delay amount. Consequently, it becomes easier to optimize the timing of the negative potential boost signal BOOSTX.

[0081] The branching point of the replica bit line TRKBL is not limited to the connection point (position in Figure 7) between the replica memory cell RMC, which is the furthest from the amplifier circuit 2, and the first replica bit line TRKBL1. For example, the second replica bit line TRKBL2 may be branched from the first replica bit line TRKBL1 at an intermediate position in the column direction (vertical direction in the diagram) of the multiple replica memory cells RMC. The second replica bit line TRKBL2 may then be extended parallel to the first replica bit line TRKBL1.

[0082] In this way, by changing the branching position of the second replica bit line TRKBL2, the resistance value of the generation path for the negative potential boost signal BOOSTX can be changed. In other words, the delay amount of the negative potential boost signal BOOSTX can be adjusted.

[0083] Furthermore, when viewed as a generation path for the sense amplifier activation signal SAE, the resistance remains the same compared to the first embodiment, but the capacitance doubles. In this regard, for example, if you want to output the sense amplifier activation signal SAE at the same timing as in the first embodiment, you can increase the number of replica memory cells RMC connected in parallel to the first replica bit line TRKBL1 (for example, by doubling them).

[0084] <Second Embodiment> Here, we will describe the semiconductor memory device 1 according to the second embodiment.

[0085] Figure 9 is a diagram corresponding to Figure 1B for the second embodiment. The configuration in Figure 1A can be the same as that of the first embodiment described above. Here, we will mainly explain the differences from the first embodiment.

[0086] In this embodiment, the column selection function is omitted from the first embodiment. In the example in Figure 9, compared to Figure 1B, the column selection signal COLEX[1:0] is absent, and the corresponding circuit (e.g., column selector 23 and column control circuit 22) is also omitted. As a result, in the generation path of the negative potential boost signal BOOSTX, the circuit related to the above-mentioned column selection function (e.g., second replica circuit 52) ​​is omitted.

[0087] The rest of the configuration and operation are generally the same as in the first embodiment, and a detailed explanation is omitted here. Figure 10 shows a timing chart illustrating an example of operation of the semiconductor memory device 1 according to this embodiment, and is a diagram corresponding to Figure 5 of the first embodiment. As shown in Figure 10, compared to Figure 5, the column selection signal COLX[0] and the signal READX are absent, but the rest of the operation is generally the same as in Figure 5.

[0088] Based on the above, the same effects as those of the first embodiment described above can be obtained in this embodiment as well.

[0089] -Experimental Variation 1- In the second embodiment described above, as in the case of Figure 6, a delay buffer 56 may be provided at a position that is the replica bit line TRKBL and is also the signal generation path for the negative potential boost signal BOOSTX.

[0090] By providing the delay buffer 56 in this way, in addition to adjusting the delay amount in transistors TN0 and TN1, or alternatively, adjusting the delay in the signal generation path of the negative potential boost signal BOOSTX, the timing of the negative potential boost signal BOOSTX can be optimized.

[0091] -Variation 2- In the second embodiment described above, the replica bit line TRKBL may be branched into a first replica bit line TRKBL1 and a second replica bit line TRKBL2, similar to the modification 2 of the first embodiment.

[0092] In this way, by branching the replica bit line TRKBL, a larger resistor and capacitance than those shown in Figure 9 are connected between transistor TN0 and the subsequent circuit, thereby increasing the delay amount. As a result, it becomes easier to optimize the timing of the negative potential boost signal BOOSTX.

[0093] In this modified example 2, as in the case of modified example 2 of the first embodiment, the branching position of the second replica bit line TRKBL2 may be changed. By doing so, the delay amount of the negative potential boost signal BOOSTX can be adjusted. [Industrial applicability]

[0094] According to this disclosure, it is possible to realize a circuit that generates various operating signals for semiconductor memory devices at the appropriate timing without area overhead, making it extremely useful. [Explanation of Symbols]

[0095] 1. Semiconductor memory 3 Memory cell array 21 Sense Amplifier Circuit 25. Negative Potential Boost Signal Generation Circuit 51. First replica circuit (replica circuit) 56 Delay buffer MC memory cell BLT Bit Line Pair TRKBL Replica Bit Wire SAE Sense Amplifier Activation Signal BOOSTX Negative Potential Boost Signal

Claims

1. A semiconductor memory device, A memory cell array comprising multiple memory cells, wherein each of the multiple memory cells is connected to a corresponding bit line pair, A replica bit line circuit includes multiple replica memory cells, wherein the multiple replica memory cells output a replica bit line signal to a common replica bit line in response to a replica word line signal, A sense amplifier circuit that amplifies the signal of the bit line pair in accordance with a sense amplifier activation signal generated based on the replica bit line signal, A writing circuit that has the function of lowering the potential of one bit line of a pair of bit lines connected to the memory cell to be written to, and that lowers the potential of the bit line on the lower potential side in response to a negative potential boost signal, A circuit for generating the negative potential boost signal, comprising a negative potential boost signal generation circuit including the replica bit line and a buffer circuit connected to the replica bit line in the signal generation path of the negative potential boost signal, When reading data from the memory cell, the replica bit line signal is output to the replica bit line in accordance with the replica word line signal, and the sense amplifier circuit is driven by a change in the sense amplifier activation signal in accordance with the replica bit line signal. When writing data to the memory cell, the negative potential boost signal output from the negative potential boost signal generation circuit is used to make the lower potential side of the bit line pair to be written a negative potential. A semiconductor memory device characterized by the following features.

2. In the semiconductor memory device according to claim 1, The replica bit line includes a first replica bit line extending parallel to the bit line pair and connected to the plurality of replica memory cells, and a second replica bit line branching off from the first replica bit line and extending parallel to the first replica bit line. The replica bit line signal is supplied to the sense amplifier circuit via the first replica bit line. The signal generation path for the negative potential boost signal includes the first replica bit line and the second replica bit line. A semiconductor memory device characterized by the following features.

3. In the semiconductor memory device according to claim 2, The second replica bit line is branched at the connection point between the first replica bit line and the replica memory cell furthest from the negative potential boost signal generation circuit, and is folded back at a position further away than the replica memory cell at the furthest end. A semiconductor memory device characterized by the following features.

4. In the semiconductor memory device according to claim 1, The memory cell array is composed of multiple columns, each of which is a unit formed by multiple memory cells connected to a common bit line pair. The system includes a column selector that selects a column from among the aforementioned multiple columns to be used for reading data or writing data. A semiconductor memory device characterized by the following features.

5. In the semiconductor memory device according to claim 1, The aforementioned buffer circuit is A replica circuit of a write driver connected to the replica bit line and outputting a control signal when data is written to the memory cell, Includes a delay buffer connected to the replica bit line, which inputs the control signal and outputs a delayed signal of the control signal, A semiconductor memory device characterized by the following features.

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