Semiconductor equipment

Abstract

Provided is a semiconductor device that is capable of multipoint measurement. According to the present invention, a semiconductor device has a first layer and a second layer that is on the first layer. The first layer has a first multiplexer, a second multiplexer, m analog switches that are electrically connected to the first multiplexer (m being an integer that is at least 1), and n analog switches that are electrically connected to the second multiplexer (n being an integer that is at least 1), and the second layer has m×n transistors. Each of the m analog switches is electrically connected to n transistors, and each of the n analog switches is electrically connected to m transistors.

Description

[Technical Field]

[0001] One aspect of the present invention relates to a method for producing metal oxides. Alternatively, one aspect of the present invention relates to transistors, semiconductor devices, and electronic devices. Alternatively, one aspect of the present invention relates to a method for manufacturing semiconductor devices. Alternatively, one aspect of the present invention relates to semiconductor wafers and modules.

[0002] In this specification, the term "semiconductor device" refers to any device that can function by utilizing semiconductor properties. Semiconductor elements such as transistors, as well as semiconductor circuits, computing devices, and memory devices, are all forms of semiconductor devices. Display devices (such as liquid crystal displays and light-emitting displays), projection devices, lighting devices, electro-optical devices, energy storage devices, memory devices, semiconductor circuits, imaging devices, and electronic devices may also be considered to have semiconductor devices.

[0003] Furthermore, one aspect of the present invention is not limited to the above-mentioned technical field. One aspect of the invention disclosed herein relates to a product, a method, or a method of manufacture. Another aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. [Background technology]

[0004] In recent years, the development of semiconductor devices has progressed, with LSIs, CPUs, and memory being the main components used in semiconductor devices. A CPU is an assembly of semiconductor elements that have semiconductor integrated circuits (at least transistors and memory) formed on chips by processing semiconductor wafers, and electrodes that serve as connection terminals are formed on them.

[0005] Semiconductor circuits (IC chips) such as LSIs, CPUs, and memory are mounted on circuit boards, such as printed circuit boards, and used as components in various electronic devices.

[0006] Furthermore, the technology of constructing transistors using semiconductor thin films formed on substrates with insulating surfaces is attracting attention. These transistors are widely applied in electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors are attracting attention as other materials.

[0007] Furthermore, transistors using oxide semiconductors are known to have extremely low leakage current in the non-conductive state. For example, Patent Document 1 discloses a low-power CPU that utilizes the low leakage current characteristic of transistors using oxide semiconductors. Also, for example, Patent Document 2 discloses a memory device that can retain its contents for a long period of time by utilizing the low leakage current characteristic of transistors using oxide semiconductors.

[0008] Furthermore, in recent years, with the miniaturization and weight reduction of electronic devices, there has been an increasing demand for even higher density integrated circuits. There is also a need to improve the productivity of semiconductor devices, including integrated circuits. [Prior art documents] [Patent Documents]

[0009] [Patent Document 1] Japanese Patent Publication No. 2012-257187 [Patent Document 2] Japanese Patent Publication No. 2011-151383 [Overview of the project] [Problems that the invention aims to solve]

[0010] One aspect of the present invention aims to provide a semiconductor device capable of multi-point measurement. Alternatively, one aspect of the present invention aims to provide a semiconductor device with less variation in the electrical characteristics of transistors. Alternatively, one aspect of the present invention aims to provide a semiconductor device with good reliability. Alternatively, one aspect of the present invention aims to provide a semiconductor device having good electrical characteristics. Alternatively, one aspect of the present invention aims to provide a semiconductor device with a large on-current. Alternatively, one aspect of the present invention aims to provide a semiconductor device that can be miniaturized or highly integrated. Alternatively, one aspect of the present invention aims to provide a semiconductor device with low power consumption.

[0011] Furthermore, the description of these problems does not preclude the existence of other problems. Moreover, one aspect of the present invention does not need to solve all of these problems. Other problems will naturally become apparent from the description in the specification, drawings, and claims, and it is possible to extract other problems from the description in the specification, drawings, and claims. [Means for solving the problem]

[0012] One aspect of the present invention is a semiconductor device having a first layer, a second layer on the first layer, a first wiring, a second wiring, and a third wiring. The first layer has a first multiplexer, a second multiplexer, and first to fourth analog switches, and the second layer has first to fourth transistors. Each of the first to fourth transistors has a source, a drain, and a first gate. The first wiring is electrically connected to one of the sources and drains of each of the first to fourth transistors. The first terminals of the first analog switch and the second analog switch are electrically connected to the first multiplexer, and the second terminals of the first analog switch and the second analog switch are electrically connected to the second wiring. The third terminal of the first analog switch is electrically connected to the source and drain of the first and second transistors, respectively, and the third terminal of the second analog switch is electrically connected to the source and drain of the third and fourth transistors, respectively. The first terminals of the third and fourth analog switches are electrically connected to the second multiplexer, and the second terminals of the third and fourth analog switches are electrically connected to the third wiring. The third terminal of the third analog switch is electrically connected to the first gate of the first and third transistors, respectively, and the third terminal of the fourth analog switch is electrically connected to the first gate of the second and fourth transistors, respectively.

[0013] Preferably, the semiconductor device further has a fourth wiring, each of the first to fourth transistors further has a second gate, and the fourth wiring is electrically connected to the second gate of each of the first to fourth transistors.

[0014] Furthermore, in the above-mentioned semiconductor device, it is preferable that each of the first to fourth transistors has a metal oxide in the channel formation region.

[0015] Furthermore, in the above semiconductor device, it is preferable that the metal oxide comprises indium, gallium, and zinc.

[0016] In the above-described semiconductor device, it is preferable that each of the first to fourth analog switches is composed of a CMOS circuit.

[0017] Furthermore, in the above-mentioned semiconductor device, it is preferable that the transistors in the CMOS circuit have silicon in the channel formation region.

[0018] Another aspect of the present invention is a semiconductor device having a first layer, a second layer on the first layer, a first wiring, a second wiring, and a third wiring. The first layer has a first multiplexer, a second multiplexer, and first to third analog switches, and the second layer has a first transistor and a third transistor. Each of the first and third transistors has a source, a drain, and a first gate. The first wiring is electrically connected to one of the sources and drains of the first and third transistors, respectively. The first terminals of the first and second analog switches are electrically connected to the first multiplexer, and the second terminals of the first and second analog switches are electrically connected to the second wiring. The third terminal of the first analog switch is electrically connected to the source and the other drain of the first transistor, and the third terminal of the second analog switch is electrically connected to the source and the other drain of the third transistor. The first terminal of the third analog switch is electrically connected to the second multiplexer, the second terminal of the third analog switch is electrically connected to the third wiring, and the third terminal of the third analog switch is electrically connected to the first gate of the first transistor and the first gate of the third transistor.

[0019] Preferably, the semiconductor device further has a fourth wiring, each of the first transistor and the third transistor further has a second gate, and the fourth wiring is electrically connected to the second gate of each of the first transistor and the third transistor.

[0020] Furthermore, in the semiconductor device described above, it is preferable that each of the first transistor and the third transistor has a metal oxide in the channel formation region.

[0021] Furthermore, in the above semiconductor device, it is preferable that the metal oxide comprises indium, gallium, and zinc.

[0022] In the semiconductor device described above, it is preferable that each of the first to third analog switches is composed of a CMOS circuit.

[0023] Furthermore, in the above-mentioned semiconductor device, it is preferable that the transistors in the CMOS circuit have silicon in the channel formation region.

[0024] Another aspect of the present invention is a semiconductor device having a first layer, a second layer on the first layer, a first wiring, a second wiring, and a third wiring. The first layer has a first multiplexer, a second multiplexer, a first analog switch, a third analog switch, and a fourth analog switch, and the second layer has a first transistor and a second transistor. Each of the first and second transistors has a source, a drain, and a first gate. The first wiring is electrically connected to one of the sources and drains of the first and second transistors, respectively. The first terminal of the first analog switch is electrically connected to the first multiplexer, the second terminal of the first analog switch is electrically connected to the second wiring, and the third terminal of the first analog switch is electrically connected to the other of the sources and drains of the first and second transistors, respectively. The first terminals of the third analog switch and the fourth analog switch are electrically connected to the second multiplexer, and the second terminals of the third analog switch and the fourth analog switch are electrically connected to the third wiring. The third terminal of the third analog switch is electrically connected to the first gate of the first transistor, and the third terminal of the fourth analog switch is electrically connected to the first gate of the second transistor.

[0025] Preferably, the semiconductor device further has a fourth wiring, each of the first transistor and the second transistor further has a second gate, and the fourth wiring is electrically connected to the second gate of each of the first transistor and the second transistor.

[0026] Furthermore, in the semiconductor device described above, it is preferable that each of the first transistor and the second transistor has a metal oxide in the channel formation region.

[0027] Furthermore, in the above semiconductor device, it is preferable that the metal oxide comprises indium, gallium, and zinc.

[0028] In the semiconductor device described above, it is preferable that the first analog switch, the third analog switch, and the fourth analog switch are each composed of a CMOS circuit.

[0029] Furthermore, in the above-mentioned semiconductor device, it is preferable that the transistors in the CMOS circuit have silicon in the channel formation region. [Effects of the Invention]

[0030] According to one aspect of the present invention, a semiconductor device capable of multi-point measurement can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with less variation in the electrical characteristics of transistors can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with good reliability can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device having good electrical characteristics can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with a large on-current can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with low power consumption can be provided.

[0031] Furthermore, the description of these effects does not preclude the existence of other effects. Moreover, one embodiment of the present invention does not need to possess all of these effects. Other effects will naturally become apparent from the description in the specification, drawings, and claims, and it is possible to extract other effects from the description in the specification, drawings, and claims. [Brief explanation of the drawing]

[0032] Figure 1A is a top view of a semiconductor device according to one embodiment of the present invention. Figures 1B to 1D are cross-sectional views of a semiconductor device according to one embodiment of the present invention. Figures 2A and 2B are cross-sectional views of a semiconductor device according to one embodiment of the present invention. Figure 3A is a top view of a semiconductor device according to one embodiment of the present invention. Figures 3B to 3D are cross-sectional views of a semiconductor device according to one embodiment of the present invention. Figure 4A is a top view of a semiconductor device according to one embodiment of the present invention. Figures 4B to 4D are cross-sectional views of a semiconductor device according to one embodiment of the present invention. Figure 5A is a top view of a semiconductor device according to one embodiment of the present invention. Figures 5B to 5D are cross-sectional views of a semiconductor device according to one embodiment of the present invention. Figure 6A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 6B to 6D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figure 7A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 7B to 7D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figure 8A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 8B to 8D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figure 9A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 9B to 9D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figure 10A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 10B to 10D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figure 11A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 11B to 11D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figure 12A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 12B to 12D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figure 13A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 13B to 13D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figure 14A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 14B to 14D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figure 15A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 15B to 15D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figure 16A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 16B to 16D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figure 17A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 17B to 17D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figure 18 is a top view illustrating a microwave processing apparatus according to one aspect of the present invention. Figure 19 is a cross-sectional view illustrating a microwave processing apparatus according to one aspect of the present invention. Figure 20 is a cross-sectional view illustrating a microwave apparatus according to one aspect of the present invention. Figure 21 is a cross-sectional view illustrating a microwave processing apparatus according to one aspect of the present invention. Figure 22A is a plan view of a semiconductor device according to one embodiment of the present invention. Figures 22B and 22C are cross-sectional views of a semiconductor device according to one embodiment of the present invention. Figure 23 is a diagram showing the circuit diagram of a semiconductor device. Figure 24A is a perspective view of a semiconductor device. Figure 24B is a perspective view illustrating the configuration of the semiconductor device. Figures 25A and 25B are top views illustrating the layout of a group of transistors in a semiconductor device according to one embodiment of the present invention. Figures 26A and 26B are top views illustrating the layout of a group of transistors in a semiconductor device according to one embodiment of the present invention. Figures 27A and 27B are top views illustrating the layout of a group of transistors in a semiconductor device according to one embodiment of the present invention. Figures 28A and 28B are top views illustrating the layout of a group of transistors in a semiconductor device according to one embodiment of the present invention. Figure 29 is a cross-sectional view showing the configuration of a storage device according to one aspect of the present invention. Figure 30 is a cross-sectional view showing the configuration of a storage device according to one aspect of the present invention. Figure 31 is a cross-sectional view of a semiconductor device according to one aspect of the present invention. Figures 32A and 32B are cross-sectional views of a semiconductor device according to one embodiment of the present invention. Figure 33 is a cross-sectional view of a semiconductor device according to one aspect of the present invention. Figure 34A is a block diagram showing an example of the configuration of a storage device according to one aspect of the present invention. Figure 34B is a perspective view showing an example of the configuration of a storage device according to one aspect of the present invention. Figures 35A to 35H are circuit diagrams showing an example of the configuration of a storage device according to one aspect of the present invention. Figures 36A and 36B are schematic diagrams of a semiconductor device according to one aspect of the present invention. Figure 37 is a diagram illustrating an example of a CPU configuration. Figures 38A and 38B illustrate an example of a CPU configuration. Figure 39 shows an example of a CPU configuration. Figures 40A and 40B illustrate an example of an electronic component. Figures 41A to 41E are schematic diagrams of a storage device according to one aspect of the present invention. Figures 42A to 42H show an electronic device according to one aspect of the present invention. Figure 43 illustrates the correlation between heat treatment temperature and the sheet resistance of the oxide. Figures 44A and 44B show the Id-Vg characteristics of the prototype transistor. Figures 45A1, 45B1, 45C1, and 45D1 illustrate capacitance. Figures 45A2, 45B2, 45C2, and 45D2 show the gate voltage-capacitance characteristics of the prototype transistor. Figure 46 shows the temperature-off-current characteristics of the prototype transistor under the measurement environment. Figure 47 is a cross-sectional TEM image of a semiconductor device. Figure 48 is a diagram illustrating the arrangement of the TEGs. Figures 49A to 49F illustrate the threshold voltage variation of transistors. Figures 50A to 50F illustrate the threshold voltage variation of transistors. Figures 51A to 51F illustrate the variation in the field-effect mobility of transistors. Figures 52A to 52F illustrate the variation in the field-effect mobility of transistors. Figures 53A and 53B illustrate the arrangement method of transistors. Figures 54A and 54B show the Id-Vg characteristics of a transistor. Figures 55A to 55C illustrate the threshold voltage variation of transistors. Figure 56A is a top view of the semiconductor device according to this embodiment. Figures 56B to 56D are cross-sectional views of the semiconductor device according to this embodiment. Figure 57 shows the stress time dependence of ΔVsh in the +GBT stress test according to this embodiment. Figure 58 illustrates the time dependence of Vth in the OS transistor after X-ray irradiation. Figure 59 illustrates the time dependence of the S value of the OS transistor after X-ray irradiation. Figure 60A illustrates the X-ray dose dependence of Vth for an OS transistor. Figure 60B illustrates the X-ray dose dependence of S value for an OS transistor. Figures 60C and 60D show the calculation results. Figures 61A to 61C illustrate the transistor structure used in the calculations. Figure 62 is an optical microscope image of the prototype chip. Figure 63 is the circuit diagram of the prototype OS flip-flop. Figures 64A and 64B show the dependence of the threshold voltage of the OS transistor on the total X-ray dose. Figure 65 shows the dependence of the threshold voltage of the OS transistor on the total X-ray dose. Figures 66A and 66B show the dependence of the threshold voltage of the OS transistor on the total X-ray dose. Figure 67 shows the dependence of the threshold voltage of the OS transistor on the total X-ray dose. Figure 68 is a flowchart showing the X-ray irradiation test method. Figures 69A and 69B show the Id-Vg characteristics of an OS transistor. Figures 70A and 70B show the difference in threshold voltages of OS transistors. Figures 71A and 71B show the fluctuations in the threshold voltage of the OS transistor. Figures 72A and 72B show the variation in the threshold voltage of the OS transistor. Figures 73A and 73B show the variation in the threshold voltage of the OS transistor. Figure 74 illustrates the evaluation environment for X-ray irradiation tests. Figures 75A and 75B show the variation in the threshold voltage of the OS transistor. Figure 76A shows the variation in the threshold voltage of the OS transistor. Figure 76B shows the variation in SS of the OS transistor. Figure 76C shows the variation in the field-effect mobility of the OS transistor. Figures 77A and 77B show the Id-Vg characteristics of the prototype transistor. [Modes for carrying out the invention]

[0033] The embodiments will be described below with reference to the drawings. However, it will be readily apparent to those skilled in the art that the embodiments can be implemented in many different ways, and their form and details can be modified in various ways without departing from the spirit and scope. Therefore, the present invention is not to be construed as being limited to the following embodiments.

[0034] Furthermore, in drawings, size, layer thickness, or area may be exaggerated for clarity. Therefore, they are not necessarily limited to that scale. Also, the drawings are schematic representations of ideal examples and are not limited to the shapes or values ​​shown in the drawings. For example, in actual manufacturing processes, layers, resist masks, etc., may be unintentionally reduced due to processes such as etching, but this may not be reflected in the drawings for ease of understanding. In addition, in drawings, the same reference numerals may be used in common across different drawings for the same part or parts with similar functions, and repeated explanations may be omitted. Also, when referring to similar functions, the hatch pattern may be the same, and no specific reference numeral may be assigned.

[0035] Furthermore, in particular, in top views (also called "plan views"), perspective views, etc., descriptions of some components may be omitted to facilitate understanding of the invention. In addition, descriptions of some hidden lines may be omitted.

[0036] Furthermore, the ordinal numbers used in this specification, such as "first," "second," etc., are for convenience only and do not indicate the order of processes or stacking. Therefore, for example, "first" can be replaced with "second" or "third," etc., as appropriate in the explanation. Also, the ordinal numbers described in this specification may not be the same as the ordinal numbers used to specify an aspect of the present invention.

[0037] Furthermore, in this specification, terms indicating placement, such as "above" and "below," are used for convenience to explain the positional relationships between components with reference to the drawings. The positional relationships between components change as appropriate depending on the direction in which each component is depicted. Therefore, the terms used are not limited to those described in the specification and can be appropriately rephrased depending on the situation.

[0038] For example, if it is explicitly stated in this specification that X and Y are connected, then the disclosure in this specification includes cases where X and Y are electrically connected, where X and Y are functionally connected, and where X and Y are directly connected. Therefore, it is not limited to predetermined connection relationships, such as those shown in the figures or text, but also includes connection relationships other than those shown in the figures or text. Here, X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0039] Furthermore, in this specification, a transistor is defined as an element having at least three terminals, including a gate, a drain, and a source. It also has a region where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode) (hereinafter also referred to as the channel-forming region), and current can flow between the source and the drain through the channel-forming region. In this specification, the channel-forming region refers to the region through which current primarily flows.

[0040] Furthermore, the functions of the source or drain may be reversed when transistors of different polarities are used, or when the direction of current changes during circuit operation. For this reason, the terms source and drain may be used interchangeably in this specification.

[0041] The channel length refers to the distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in the region where the semiconductor (or the part of the semiconductor through which current flows when the transistor is ON) and the gate electrode overlap, or in the channel formation region, as seen in a top view of a transistor. It should be noted that the channel length is not necessarily the same in all regions of a single transistor. That is, the channel length of a single transistor may not be a single fixed value. Therefore, in this specification, the channel length is defined as any one value, maximum value, minimum value, or average value in the channel formation region.

[0042] Channel width refers to the length of the channel formation region perpendicular to the channel length direction, for example, in a top view of a transistor, where the semiconductor (or the part of the semiconductor through which current flows when the transistor is ON) and the gate electrode overlap, or within the channel formation region. Note that the channel width is not necessarily the same across all regions in a single transistor. That is, the channel width of a single transistor may not be a single fixed value. Therefore, in this specification, the channel width is defined as any one value, maximum value, minimum value, or average value within the channel formation region.

[0043] In this specification, depending on the transistor structure, the channel width in the region where the channel is actually formed (hereinafter also referred to as the "effective channel width") may differ from the channel width shown in the top view of the transistor (hereinafter also referred to as the "apparent channel width"). For example, when the gate electrode covers the side surface of the semiconductor, the effective channel width may become larger than the apparent channel width, and this effect may not be negligible. For example, in a miniature transistor where the gate electrode covers the side surface of the semiconductor, the proportion of the channel formation region formed on the side surface of the semiconductor may be large. In that case, the effective channel width will be larger than the apparent channel width.

[0044] In such cases, it can be difficult to estimate the effective channel width through actual measurements. For example, estimating the effective channel width from design values ​​requires the assumption that the semiconductor shape is known. Therefore, if the semiconductor shape is not precisely known, it is difficult to accurately measure the effective channel width.

[0045] In this specification, when simply referred to as "channel width," it may refer to the apparent channel width. Alternatively, when simply referred to as "channel width," it may refer to the effective channel width. Note that channel length, channel width, effective channel width, apparent channel width, etc., can be determined by analyzing cross-sectional TEM images, etc.

[0046] Impurities in semiconductors refer to elements other than the main components that make up the semiconductor. For example, elements with a concentration of less than 0.1 atomic percent can be considered impurities. The presence of impurities can cause, for example, an increase in the defect level density of the semiconductor or a decrease in crystallinity. In the case of oxide semiconductors, impurities that alter the properties of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of oxide semiconductors, such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Water can also function as an impurity. Furthermore, for example, the inclusion of impurities can cause oxygen vacancies (V) in oxide semiconductors. O (Also known as an oxygen vacancy) may form.

[0047] In this specification, silicon oxide nitride refers to a material whose composition contains more oxygen than nitrogen. Similarly, silicon oxide nitride refers to a material whose composition contains more nitrogen than oxygen. Similarly, aluminum oxide nitride refers to a material whose composition contains more oxygen than nitrogen. Similarly, aluminum oxide nitride refers to a material whose composition contains more nitrogen than oxygen. Similarly, hafnium oxide nitride refers to a material whose composition contains more oxygen than nitrogen. Similarly, hafnium oxide nitride refers to a material whose composition contains more nitrogen than oxygen.

[0048] Furthermore, in this specification, the term "insulator" may be replaced with "insulating film" or "insulating layer." Similarly, the term "conductor" may be replaced with "conductive film" or "conductive layer." Finally, the term "semiconductor" may be replaced with "semiconductor film" or "semiconductor layer."

[0049] Furthermore, in this specification, "parallel" means a state in which two lines are positioned at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case of -5 degrees or more and 5 degrees or less is also included. Also, "approximately parallel" means a state in which two lines are positioned at an angle of -30 degrees or more and 30 degrees or less. Also, "perpendicular" means a state in which two lines are positioned at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included. Also, "approximately perpendicular" means a state in which two lines are positioned at an angle of 60 degrees or more and 120 degrees or less.

[0050] In this specification, "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also called oxide semiconductors or simply OS), etc. For example, when a metal oxide is used in the semiconductor layer of a transistor, that metal oxide may be referred to as an oxide semiconductor. In other words, when an OS transistor is described, it can be rephrased as a transistor having a metal oxide or oxide semiconductor.

[0051] Furthermore, in this specification, normally off means that when no potential is applied to the gate, or when the gate is given a ground potential, the drain current flowing through the transistor per 1 μm of channel width is 1 × 10⁻¹⁶ at room temperature. -20 A or less, 1 × 10 at 85℃ -18 A or less, or 1 × 10 at 125°C -16 This means being less than or equal to A.

[0052] Furthermore, in this specification, "voltage" and "potential" may be used interchangeably as appropriate. "Voltage" is the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be replaced with "potential." Note that the ground potential does not necessarily mean 0V. Also, potential is relative, and as the reference potential changes, the potential applied to the wiring, the potential applied to the circuit, and the potential output from the circuit also change.

[0053] In this specification, when the same symbol is used for multiple elements, and especially when it is necessary to distinguish them, an identifying symbol such as "_1", "[n]", or "[m,n]" may be added to the symbol.

[0054] (Embodiment 1) In this embodiment, an example of a semiconductor device having a transistor 200 according to one aspect of the present invention, and a method for manufacturing the same, will be described using Figures 1A to 22C.

[0055] <Example of semiconductor device configuration> The configuration of a semiconductor device having transistor 200 will be explained using Figure 1. Figures 1A to 1D are top views and cross-sectional views of the semiconductor device having transistor 200. Figure 1A is a top view of the semiconductor device. Figures 1B to 1D are cross-sectional views of the semiconductor device. Here, Figure 1B is a cross-sectional view of the area indicated by the dashed line A1-A2 in Figure 1A, and is also a cross-sectional view of transistor 200 in the channel length direction. Figure 1C is a cross-sectional view of the area indicated by the dashed line A3-A4 in Figure 1A, and is also a cross-sectional view of transistor 200 in the channel width direction. Figure 1D is a cross-sectional view of the area indicated by the dashed line A5-A6 in Figure 1A. Note that some elements have been omitted from the top view of Figure 1A for clarity.

[0056] A semiconductor device according to one aspect of the present invention includes an insulator 212 on a substrate (not shown), an insulator 214 on the insulator 212, a transistor 200 on the insulator 214, an insulator 280 on the transistor 200, an insulator 282 on the insulator 280, an insulator 283 on the insulator 282, an insulator 274 on the insulator 283, and an insulator 285 on the insulator 283 and the insulator 274. The insulators 212, 214, 216, 280, 282, 283, 285, and 274 function as interlayer films. It also has a conductor 240 (conductors 240a and 240b) that is electrically connected to the transistor 200 and functions as a plug. An insulator 241 (insulators 241a and 241b) is provided in contact with the side surface of the conductor 240 that functions as a plug. Furthermore, conductors 246 (conductors 246a and 246b) are provided on the insulator 285 and on the conductor 240, electrically connected to the conductor 240 and functioning as wiring. In addition, the insulator 283 is in contact with a portion of the upper surface of the insulator 214, the side surface of the insulator 216, the side surface of the insulator 222, the side surface of the insulator 275, the side surface of the insulator 280, and the side surface and upper surface of the insulator 282.

[0057] Insulator 241a is provided in contact with the inner wall of the opening of insulators 280, 282, 283, and 285, and conductor 240a is provided in contact with the side surface of insulator 241a. Insulator 241b is provided in contact with the inner wall of the opening of insulators 280, 282, 283, and 285, and conductor 240b is provided in contact with the side surface of insulator 241b. Note that insulator 241 has a structure in which a first insulator is provided in contact with the inner wall of the opening, and a second insulator is provided further inside. Similarly, conductor 240 has a structure in which a first conductor is provided in contact with the side surface of insulator 241, and a second conductor is provided further inside. Here, the height of the upper surface of conductor 240 and the height of the upper surface of insulator 285 in the region overlapping with conductor 246 can be made to be approximately the same.

[0058] While transistor 200 shows a configuration in which a first insulator and a second insulator of insulator 241 are stacked, the present invention is not limited thereto. For example, the insulator 241 may be provided as a single layer or as a stacked structure of three or more layers. Similarly, while transistor 200 shows a configuration in which a first conductor and a second conductor of conductor 240 are stacked, the present invention is not limited thereto. For example, the conductor 240 may be provided as a single layer or as a stacked structure of three or more layers. When a structure has a stacked structure, ordinal numbers may be assigned to distinguish them according to the order of formation.

[0059] [Transistor 200] As shown in Figures 1A to 1D, the transistor 200 comprises an insulator 216 on an insulator 214, a conductor 205 (conductors 205a and 205b) arranged to be embedded in the insulator 216, an insulator 222 on the insulator 216 and on the conductor 205, an insulator 224 on the insulator 222, an oxide 230a on the insulator 224, an oxide 230b on the oxide 230a, a conductor 242a on the oxide 230b, an insulator 271a on the conductor 242a, and an oxide 230b The device comprises a conductor 242b, an insulator 271b on the conductor 242b, an insulator 252 on the oxide 230b, an insulator 250 on the insulator 252, an insulator 254 on the insulator 250, a conductor 260 (conductors 260a and 260b) located on the insulator 254 and overlapping with a portion of the oxide 230b, and an insulator 275 arranged on the insulators 222, 224, oxide 230a, oxide 230b, conductor 242a, conductor 242b, insulator 271a, and insulator 275. Here, as shown in Figures 1B and 1C, insulator 252 is in contact with the top surface of insulator 222, the side surface of insulator 224, the side surface of oxide 230a, the side surface and top surface of oxide 230b, the side surface of conductor 242, the side surface of insulator 271, the side surface of insulator 275, the side surface of insulator 280, and the bottom surface of insulator 250. The top surface of conductor 260 is positioned so as to be roughly the same height as the top of insulator 254, the top of insulator 250, the top of insulator 252, and the top surface of insulator 280. Insulator 282 is in contact with at least a portion of the top surfaces of conductor 260, insulator 252, insulator 250, insulator 254, and insulator 280.

[0060] In the following, oxides 230a and 230b may be collectively referred to as oxide 230. Similarly, conductors 242a and 242b may be collectively referred to as conductor 242. Furthermore, insulators 271a and 271b may be collectively referred to as insulator 271.

[0061] Insulators 280 and 275 are provided with openings that reach oxide 230b. Insulators 252, 250, 254, and 260 are arranged within these openings. In addition, in the channel length direction of transistor 200, conductors 260, 252, 250, and 254 are provided between insulators 271a and conductor 242a, and between insulators 271b and conductor 242b. Insulator 254 has a region in contact with the side surface of conductor 260 and a region in contact with the bottom surface of conductor 260.

[0062] Preferably, the oxide 230 has an oxide 230a disposed on the insulator 224 and an oxide 230b disposed on top of the oxide 230a. By having oxide 230a below oxide 230b, the diffusion of impurities from structures formed below oxide 230a to oxide 230b can be suppressed.

[0063] In the transistor 200, the oxide 230 is shown as having a stacked structure of two layers, oxide 230a and oxide 230b, but the present invention is not limited to this. For example, a single layer of oxide 230b or a stacked structure of three or more layers may be provided, or oxide 230a and oxide 230b may each have a stacked structure.

[0064] Conductor 260 functions as the first gate (also called the top gate) electrode, and conductor 205 functions as the second gate (also called the back gate) electrode. Insulators 252, 250, and 254 function as the first gate insulators, and insulators 222 and 224 function as the second gate insulators. Note that gate insulators are sometimes called gate insulating layers or gate insulating films. Conductor 242a functions as either the source electrode or the drain electrode, and conductor 242b functions as either the source electrode or the drain electrode. At least a portion of the region of oxide 230 that overlaps with conductor 260 functions as a channel-forming region.

[0065] Here, an enlarged view of the vicinity of the channel formation region in FIG. 1B is shown in FIG. 2A. By supplying oxygen to the oxide 230b, a channel formation region is formed in the region between the conductor 242a and the conductor 242b. Thus, as shown in FIG. 2A, the oxide 230b has a region 230bc that functions as the channel formation region of the transistor 200, and regions 230ba and 230bb that are provided so as to sandwich the region 230bc and function as a source region or a drain region. At least a part of the region 230bc overlaps with the conductor 260. In other words, the region 230bc is provided in the region between the conductor 242a and the conductor 242b. The region 230ba is provided to overlap with the conductor 242a, and the region 230bb is provided to overlap with the conductor 242b.

[0066] The region 230bc that functions as the channel formation region is a high-resistance region with a low carrier concentration because it has less oxygen deficiency or a lower impurity concentration than the regions 230ba and 230bb. Therefore, the region 230bc can be said to be of the i-type (intrinsic) or substantially i-type.

[0067] Also, the regions 230ba and 230bb that function as the source region or the drain region are regions with an increased carrier concentration and a reduced resistance due to a large amount of oxygen deficiency or a high impurity concentration such as hydrogen, nitrogen, and metal elements. That is, the regions 230ba and 230bb are n-type regions with a high carrier concentration and a low resistance compared to the region 230bc.

[0068] Here, the carrier concentration of the region 230bc that functions as the channel formation region is preferably 18 cm -3 or less, more preferably 17 cm -3 less, still more preferably 16 cm -3 less, still more preferably 13 cm -3 less, still more preferably 12 cm -3It is even more preferable that it be less than . There are no particular limitations on the lower limit of the carrier concentration in the region 230bc that functions as a channel-forming region, but for example, 1 × 10 -9 cm -3 It can be done this way.

[0069] Furthermore, a region may be formed between region 230bc and region 230ba or region 230bb, where the carrier concentration is equal to or lower than that of regions 230ba and 230bb, and equal to or higher than that of region 230bc. In other words, this region functions as a junction region between region 230bc and region 230ba or region 230bb. The hydrogen concentration in this junction region may be equal to or lower than that of regions 230ba and 230bb, and equal to or higher than that of region 230bc. Also, the oxygen deficiency in this junction region may be equal to or less than that of regions 230ba and 230bb, and equal to or greater than that of region 230bc.

[0070] Although Figure 2A shows an example in which regions 230ba, 230bb, and 230bc are formed in oxide 230b, the present invention is not limited to this. For example, each of the above regions may be formed not only in oxide 230b but also in oxide 230a.

[0071] Furthermore, in oxide 230, it can be difficult to clearly detect the boundaries between each region. The concentrations of metal elements, as well as impurity elements such as hydrogen and nitrogen, detected within each region may not be limited to stepwise changes between regions, but may also change continuously within each region. In other words, the closer a region is to the channel-forming region, the lower the concentrations of metal elements, as well as impurity elements such as hydrogen and nitrogen should be.

[0072] In transistor 200, it is preferable to use a metal oxide (hereinafter also referred to as an oxide semiconductor) that functions as a semiconductor for the oxide 230 (oxide 230a and oxide 230b) which includes the channel formation region.

[0073] Furthermore, the band gap of the metal oxide that functions as a semiconductor is preferably 2 eV or more, and more preferably 2.5 eV or more. By using a metal oxide with a large band gap, the off-current of the transistor can be reduced.

[0074] As oxide 230, for example, a metal oxide such as In-M-Zn oxide having indium, element M, and zinc (element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium) may be used. Alternatively, In-Ga oxide, In-Zn oxide, or indium oxide may be used as oxide 230.

[0075] The oxide 230 preferably has a laminated structure of multiple oxide layers with different chemical compositions. For example, in the metal oxide used for oxide 230a, it is preferable that the atomic ratio of element M to the main metal element is greater than the atomic ratio of element M to the main metal element in the metal oxide used for oxide 230b. Furthermore, in the metal oxide used for oxide 230a, it is preferable that the atomic ratio of element M to In is greater than the atomic ratio of element M to In in the metal oxide used for oxide 230b. This configuration suppresses the diffusion of impurities and oxygen from structures formed below oxide 230a to oxide 230b.

[0076] Furthermore, it is preferable that the atomic ratio of In to element M in the metal oxide used for oxide 230b is greater than the atomic ratio of In to element M in the metal oxide used for oxide 230a. With this configuration, transistor 200 can obtain a large on-current and high frequency characteristics.

[0077] Furthermore, because oxides 230a and 230b share a common element other than oxygen as their main component, the defect level density at the interface between oxides 230a and 230b can be reduced. Because the defect level density at the interface between oxides 230a and 230b can be reduced, the influence of interfacial scattering on carrier conduction is small, resulting in a high on-current.

[0078] Specifically, for oxide 230a, a metal oxide with a composition of In:M:Zn = 1:3:4 [atomic ratio] or close to it, or In:M:Zn = 1:1:0.5 [atomic ratio] or close to it may be used. For oxide 230b, a metal oxide with a composition of In:M:Zn = 1:1:1 [atomic ratio] or close to it, In:M:Zn = 1:1:2 [atomic ratio] or close to it, or In:M:Zn = 4:2:3 [atomic ratio] or close to it may be used. Note that "close to it" includes a range of ±30% of the desired atomic ratio. Furthermore, it is preferable to use gallium as element M. Also, when a single layer of oxide 230b is provided as oxide 230, a metal oxide that can be used for oxide 230a may be applied as oxide 230b.

[0079] Furthermore, when depositing metal oxide films by sputtering, the above atomic ratio is not limited to the atomic ratio of the deposited metal oxide film, but may also be the atomic ratio of the sputtering target used for depositing the metal oxide film.

[0080] It is preferable that oxide 230b is crystalline. In particular, it is preferable to use CAAC-OS (c-axis aligned crystalline oxide semiconductor) as oxide 230b.

[0081] CAAC-OS has a highly crystalline, dense structure, and is free from impurities and defects (e.g., oxygen deficiencies (V)). O It is a metal oxide with few impurities (such as ). In particular, by heat-treating the metal oxide after its formation at a temperature that does not cause polycrystallization of the metal oxide (for example, between 400°C and 600°C), the CAAC-OS can be made to have a more crystalline and dense structure. By increasing the density of the CAAC-OS in this way, the diffusion of impurities or oxygen in the CAAC-OS can be further reduced.

[0082] Furthermore, because it is difficult to identify clear grain boundaries in CAAC-OS, a decrease in electron mobility due to grain boundary issues is less likely to occur. Therefore, metal oxides containing CAAC-OS have stable physical properties. Consequently, metal oxides containing CAAC-OS are highly heat-resistant and reliable.

[0083] Furthermore, by using a crystalline oxide such as CAAC-OS as oxide 230b, the extraction of oxygen from oxide 230b by the source electrode or drain electrode can be suppressed. As a result, even when heat treatment is performed, the extraction of oxygen from oxide 230b is reduced, making transistor 200 stable against high temperatures (so-called thermal budget) in the manufacturing process.

[0084] In transistors using oxide semiconductors, the electrical properties tend to fluctuate and reliability may be poor if impurities and oxygen vacancies are present in the region where the channel is formed in the oxide semiconductor. Furthermore, hydrogen near the oxygen vacancy can fill the oxygen vacancy, creating a defect (hereinafter referred to as V). OOxygen vacancies (sometimes called H) can form and generate electron carriers. Therefore, if the region where channels are formed in an oxide semiconductor contains oxygen vacancies, the transistor is likely to exhibit normally-on characteristics (a characteristic in which channels exist and current flows through the transistor even without applying voltage to the gate electrode). Consequently, in the region where channels are formed in an oxide semiconductor, impurities, oxygen vacancies, and V are likely to be present. O It is preferable that H is reduced as much as possible. In other words, it is preferable that the region in the oxide semiconductor where the channel is formed has a reduced carrier concentration and is type i (intrinsed) or substantially type i.

[0085] In contrast, by placing an insulator containing oxygen that is released by heating (hereinafter sometimes referred to as excess oxygen) near the oxide semiconductor and performing heat treatment, oxygen is supplied from the insulator to the oxide semiconductor, eliminating oxygen deficiencies and V O H can be reduced. However, if an excessive amount of oxygen is supplied to the source or drain region, it may cause a decrease in the on-current of transistor 200 or a decrease in the field-effect mobility. Furthermore, variations in the amount of oxygen supplied to the source or drain region within the substrate surface will result in variations in the characteristics of the semiconductor device containing the transistor.

[0086] Therefore, in an oxide semiconductor, the region 230bc, which functions as a channel-forming region, preferably has a reduced carrier concentration and is i-type or substantially i-type, while the regions 230ba and 230bb, which function as a source region or drain region, preferably have a high carrier concentration and are n-type. In other words, oxygen vacancies and V in region 230bc of the oxide semiconductor O It is preferable to reduce H so that an excessive amount of oxygen is not supplied to regions 230ba and 230bb.

[0087] Therefore, in this embodiment, with the conductor 242a and conductor 242b placed on the oxide 230b, microwave treatment is performed in an oxygen-containing atmosphere to eliminate oxygen deficiencies in region 230bc, and V OThe aim is to reduce H. Here, microwave processing refers to processing using a device that has a power supply that generates high-density plasma using microwaves, for example.

[0088] By performing microwave treatment in an oxygen-containing atmosphere, oxygen gas can be plasmaized using microwaves or high-frequency waves such as RF (Radio Frequency), and this oxygen plasma can be applied. At this time, microwaves or high-frequency waves such as RF can also be irradiated into region 230bc. Due to the action of plasma, microwaves, etc., the V of region 230bc O H is oxygen-deficient (V O The oxygen deficiency can be separated into hydrogen (H) and oxygen, the hydrogen can be removed from region 230bc, and the oxygen deficiency can be repaired with oxygen. Therefore, the hydrogen concentration in region 230bc, the oxygen deficiency, and V O This can reduce H and lower the carrier concentration.

[0089] Furthermore, when performing microwave processing in an oxygen-containing atmosphere, the effects of microwaves, high frequencies such as RF, and oxygen plasma are shielded by conductors 242a and 242b and do not reach regions 230ba and 230bb. In addition, the effect of oxygen plasma can be reduced by insulators 271 and 280, which are provided covering oxide 230b and conductor 242. As a result, during microwave processing, V O This reduces H and prevents excessive oxygen supply, thus preventing a decrease in carrier concentration.

[0090] Furthermore, it is preferable to perform microwave treatment in an oxygen-containing atmosphere after the deposition of the insulating film that will become the insulator 252, or after the deposition of the insulating film that will become the insulator 250. By performing microwave treatment in an oxygen-containing atmosphere via the insulator 252 or insulator 250 in this way, oxygen can be efficiently injected into region 230bc. In addition, by arranging the insulator 252 in contact with the side surface of the conductor 242 and the surface of region 230bc, the injection of more oxygen than necessary into region 230bc can be suppressed, thereby suppressing oxidation of the side surface of the conductor 242. Furthermore, oxidation of the side surface of the conductor 242 can be suppressed when the insulating film that will become the insulator 250 is deposited.

[0091] Furthermore, the oxygen injected into region 230bc can take various forms, including oxygen atoms, oxygen molecules, and oxygen radicals (also called O radicals, which are atoms or molecules with unpaired electrons, or ions). Note that the oxygen injected into region 230bc may be one or more of the above forms, and oxygen radicals are particularly preferred. Additionally, the film quality of insulators 252 and 250 can be improved, thereby increasing the reliability of transistor 200.

[0092] In this way, oxygen vacancies and V are selectively generated in the oxide semiconductor region 230bc. O By removing H, region 230bc can be made i-type or substantially i-type. Furthermore, it is possible to suppress the supply of excess oxygen to regions 230ba and 230bb, which function as source or drain regions, and maintain the state of the n-type region before microwave processing. This suppresses variations in the electrical properties of transistor 200 and prevents variations in the electrical properties of transistor 200 within the substrate plane.

[0093] By adopting the above configuration, it is possible to provide a semiconductor device with minimal variation in transistor characteristics, high reliability, and excellent electrical characteristics.

[0094] Furthermore, as shown in Figure 1C, in a cross-sectional view of the transistor 200 in the channel width direction, there may be a curved surface between the side surface and the top surface of the oxide 230b. In other words, the ends of the side surface and the ends of the top surface may be curved (hereinafter also referred to as rounded).

[0095] The radius of curvature of the curved surface is preferably greater than 0 nm and less than the film thickness of the oxide 230b in the region overlapping with the conductor 242, or less than half the length of the region without the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and 20 nm or less, preferably 1 nm to 15 nm, and more preferably 2 nm to 10 nm. By adopting such a shape, the coverage of the oxide 230b by the insulator 252, insulator 250, insulator 254, and conductor 260 can be improved.

[0096] Furthermore, as shown in Figure 1C and other figures, by providing an insulator 252 made of aluminum oxide or the like in contact with the top and side surfaces of the oxide 230, the indium contained in the oxide 230 may be unevenly distributed at and near the interface between the oxide 230 and the insulator 252. As a result, the atomic ratio near the surface of the oxide 230 becomes similar to that of indium oxide, or similar to that of In-Zn oxide. By increasing the atomic ratio of indium near the surface of the oxide 230, particularly oxide 230b, the field-effect mobility of the transistor 200 can be improved.

[0097] By configuring oxides 230a and 230b as described above, the defect level density at the interface between oxide 230a and oxide 230b can be reduced. As a result, the influence of interface scattering on carrier conduction is reduced, and transistor 200 can obtain a large on-current and high frequency characteristics.

[0098] It is preferable that at least one of insulators 212, 214, 271, 275, 282, 283, and 285 functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from the substrate side or from above the transistor 200 into the transistor 200. Therefore, it is preferable that at least one of insulators 212, 214, 271, 275, 282, 283, and 285 is an insulating material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms (i.e., the above impurities do not easily permeate it). Alternatively, it is preferable to use an insulating material that has the function of suppressing the diffusion of oxygen (e.g., at least one such as oxygen atoms or oxygen molecules) (i.e., the above oxygen does not easily permeate it).

[0099] In this specification, a barrier insulating film refers to an insulating film that has barrier properties. In this specification, barrier properties refer to the function of suppressing the diffusion of the corresponding substance (also called low permeability), or the function of capturing and fixing the corresponding substance (also called gettering).

[0100] For insulators 212, 214, 271, 275, 282, 283, and 285, it is preferable to use insulators that have the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide can be used. For example, for insulators 212, 275, and 283, it is preferable to use silicon nitride, which has higher hydrogen barrier properties. Also, for example, for insulators 214, 271, 282, and 285, it is preferable to use aluminum oxide or magnesium oxide, which have high hydrogen capture and hydrogen fixation functions. This makes it possible to suppress the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200 side via insulators 212 and 214. Alternatively, it is possible to suppress the diffusion of impurities such as water and hydrogen from the interlayer insulating film located outside the insulator 285 towards the transistor 200. Alternatively, it is possible to suppress the diffusion of oxygen contained in the insulator 224, etc., towards the substrate side via the insulators 212 and 214. Alternatively, it is possible to suppress the diffusion of oxygen contained in the insulator 280, etc., upward from the transistor 200 via the insulator 282, etc. Thus, it is preferable to have a structure in which the transistor 200 is surrounded by insulators 212, 214, 271, 275, 282, 283, and 285, which have the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen.

[0101] Here, it is preferable to use oxides having an amorphous structure as insulators 212, 214, 271, 275, 282, 283, and 285. For example, AlO x (x is any number greater than 0), or MgO yIt is preferable to use a metal oxide such as (y is any number greater than 0). In such amorphous metal oxides, oxygen atoms have dangling bonds, and these dangling bonds may have the property of capturing or fixing hydrogen. By using such an amorphous metal oxide as a component of the transistor 200, or by providing it around the transistor 200, hydrogen contained in the transistor 200, or hydrogen present around the transistor 200, can be captured or fixed. It is particularly preferable to capture or fix hydrogen contained in the channel formation region of the transistor 200. By using an amorphous metal oxide as a component of the transistor 200, or by providing it around the transistor 200, a transistor 200 and semiconductor device with good characteristics and high reliability can be manufactured.

[0102] Furthermore, while insulators 212, 214, 271, 275, 282, 283, and 285 are preferably amorphous, they may also have regions of polycrystalline structure. In addition, insulators 212, 214, 271, 275, 282, 283, and 285 may have a multilayer structure in which an amorphous layer and a polycrystalline layer are stacked. For example, a stacked structure in which a polycrystalline layer is formed on top of an amorphous layer is also possible.

[0103] The insulators 212, 214, 271, 275, 282, 283, and 285 may be deposited using, for example, a sputtering method. Since the sputtering method does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration of insulators 212, 214, 271, 275, 282, 283, and 285 can be reduced. The deposition method is not limited to sputtering, and chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), atomic layer deposition (ALD), etc., may be used as appropriate.

[0104] Furthermore, it may be preferable to lower the resistivity of insulators 212, 275, and 283. For example, the resistivity of insulators 212, 275, and 283 may be approximately 1 × 10⁻⁶. 13 By setting the resistivity to Ωcm, insulators 212, 275, and 283 may be able to mitigate the charge-up of conductors 205, 242, 260, or 246 in processes using plasma or the like during semiconductor device manufacturing. The resistivity of insulators 212, 275, and 283 is preferably 1 × 10⁻⁶. 10 Ωcm or more, 1 × 10 15 The density should be less than or equal to Ωcm.

[0105] Furthermore, it is preferable that insulators 216, 274, 280, and 285 have a lower dielectric constant than insulator 214. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance between wirings can be reduced. For example, silicon oxide, silicon oxynitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, and silicon oxide with vacancies may be used as insulators 216, 274, 280, and 285 as appropriate.

[0106] The conductor 205 is arranged to overlap with the oxide 230 and the conductor 260. Here, it is preferable that the conductor 205 is embedded in an opening formed in the insulator 216. In some cases, a portion of the conductor 205 may be embedded in the insulator 214.

[0107] The conductor 205 comprises a conductor 205a and a conductor 205b. The conductor 205a is provided in contact with the bottom surface and side wall of the opening. The conductor 205b is provided so as to be embedded in a recess formed in the conductor 205a. Here, the height of the upper surface of the conductor 205b is approximately equal to the height of the upper surface of the conductor 205a and the height of the upper surface of the insulator 216.

[0108] Here, it is preferable to use a conductive material for the conductor 205a that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one such as oxygen atoms or oxygen molecules).

[0109] By using a conductive material that has the function of reducing hydrogen diffusion for the conductor 205a, it is possible to prevent impurities such as hydrogen contained in the conductor 205b from diffusing into the oxide 230 via the insulator 224, etc. Furthermore, by using a conductive material that has the function of suppressing oxygen diffusion for the conductor 205a, it is possible to suppress the oxidation of the conductor 205b and the decrease in conductivity. As a conductive material that has the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. Therefore, the conductive material can be used as a single layer or in a laminate for the conductor 205a. For example, titanium nitride can be used for the conductor 205a.

[0110] Furthermore, it is preferable to use a conductive material whose main component is tungsten, copper, or aluminum for the conductor 205b. For example, tungsten may be used for the conductor 205b.

[0111] Conductor 205 may function as a second gate electrode. In this case, the threshold voltage (Vth) of transistor 200 can be controlled by changing the potential applied to conductor 205 independently of the potential applied to conductor 260, rather than in conjunction with it. In particular, by applying a negative potential to conductor 205, it is possible to increase the Vth of transistor 200 and reduce the off-current. Therefore, applying a negative potential to conductor 205 reduces the drain current when the potential applied to conductor 260 is 0V compared to not applying a negative potential.

[0112] Furthermore, the electrical resistivity of the conductor 205 is designed considering the potential applied to the conductor 205, and the film thickness of the conductor 205 is set to match this electrical resistivity. The film thickness of the insulator 216 is approximately the same as that of the conductor 205. Here, it is preferable to make the film thicknesses of the conductor 205 and the insulator 216 as thin as possible within the limits permitted by the design of the conductor 205. By making the film thickness of the insulator 216 thin, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, thereby reducing the diffusion of these impurities into the oxide 230.

[0113] Furthermore, as shown in Figure 1A, the conductor 205 should be larger than the size of the region that does not overlap with the conductors 242a and 242b of the oxide 230. In particular, as shown in Figure 1C, it is preferable that the conductor 205 extends to the region outside the edges of the oxide 230a and oxide 230b in the channel width direction. That is, it is preferable that the conductor 205 and the conductor 260 are superimposed on the outside of the side surface of the oxide 230 in the channel width direction, with an insulator in between. With this configuration, the channel formation region of the oxide 230 can be electrically surrounded by the electric field of the conductor 260 which functions as the first gate electrode and the electric field of the conductor 205 which functions as the second gate electrode. In this specification, a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the first gate and the second gate is called a surrounded channel (S-channel) structure.

[0114] In this specification, an S-channel transistor refers to a transistor structure in which the channel formation region is electrically surrounded by the electric fields of one and the other of a pair of gate electrodes. Furthermore, the S-channel structure disclosed in this specification is different from the Fin-type structure and the Planar-type structure. By adopting an S-channel structure, it is possible to create a transistor that has improved resistance to short-channel effects, or in other words, a transistor in which short-channel effects are less likely to occur.

[0115] By setting transistor 200 to normally off and adopting the above-described S-channel structure, the channel formation region can be electrically surrounded. Therefore, transistor 200 can also be considered as having a GAA (Gate All Around) structure or an LGAA (Lateral Gate All Around) structure. By making transistor 200 an S-channel structure, GAA structure, or LGAA structure, the channel formation region formed at or near the interface between oxide 230 and the gate insulator can be made to encompass the entire bulk of oxide 230. Consequently, it becomes possible to improve the current density flowing through the transistor, which can be expected to improve the on-current of the transistor or increase the field-effect mobility of the transistor.

[0116] Furthermore, as shown in Figure 1C, the conductor 205 extends and functions as wiring. However, the configuration is not limited to this, and a conductor that functions as wiring may be provided beneath the conductor 205. Also, it is not necessary to provide one conductor 205 for each transistor. For example, the conductor 205 may be shared by multiple transistors.

[0117] In the transistor 200, the conductor 205 is shown as a stacked structure of conductors 205a and 205b, but the present invention is not limited to this. For example, the conductor 205 may be provided as a single layer or as a stacked structure of three or more layers.

[0118] Insulators 222 and 224 function as gate insulators.

[0119] Preferably, the insulator 222 has the function of suppressing the diffusion of hydrogen (for example, at least one such as a hydrogen atom or a hydrogen molecule). Furthermore, preferably, the insulator 222 has the function of suppressing the diffusion of oxygen (for example, at least one such as an oxygen atom or an oxygen molecule). For example, it is preferable that the insulator 222 has the function of suppressing the diffusion of one or both hydrogen and oxygen more effectively than the insulator 224.

[0120] The insulator 222 may be an insulator containing an oxide of one or both of the insulating materials aluminum and hafnium. Preferably, the insulator is an oxide containing aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). Alternatively, an oxide containing hafnium and zirconium, such as hafnium-zirconium oxide, is preferred. When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses the release of oxygen from the oxide 230 to the substrate side and the diffusion of impurities such as hydrogen from the periphery of the transistor 200 to the oxide 230. Therefore, by providing the insulator 222, the diffusion of impurities such as hydrogen into the inside of the transistor 200 can be suppressed, and the generation of oxygen vacancies in the oxide 230 can be suppressed. In addition, the reaction of the conductor 205 with the oxygen contained in the insulator 224 and the oxide 230 can be suppressed.

[0121] Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the above-mentioned insulator. Alternatively, these insulators may be subjected to nitriding treatment. Furthermore, insulator 222 may be used by laminating silicon oxide, silicon oxide nitride, or silicon nitride onto these insulators.

[0122] Furthermore, the insulator 222 may be a single-layer or multi-layer insulator containing so-called high-k materials, such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, or hafnium-zirconium oxide. As transistors become smaller and more integrated, thinning of the gate insulator can lead to problems such as leakage current. By using a high-k material as the insulator that functions as the gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. In addition, materials with high dielectric constants, such as lead zirconate titanate (PZT), strontium titanate (SrTiO3), and (Ba,Sr)TiO3 (BST), may also be used as the insulator 222.

[0123] The insulator 224 in contact with the oxide 230 can be, for example, silicon oxide, silicon oxide nitride, or the like, as appropriate.

[0124] Furthermore, during the manufacturing process of the transistor 200, it is preferable to perform a heat treatment with the surface of the oxide 230 exposed. This heat treatment may be performed, for example, at a temperature of 100°C to 600°C, more preferably 350°C to 550°C. The heat treatment should be performed in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, it is preferable to perform the heat treatment in an oxygen atmosphere. This allows oxygen to be supplied to the oxide 230, thereby reducing oxygen deficiency. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas, and then in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the desorbed oxygen. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, and then continuously in an atmosphere of nitrogen gas or an inert gas.

[0125] Furthermore, by performing an oxygenation treatment on oxide 230, oxygen deficiencies in oxide 230 can be repaired by the supplied oxygen. In addition, the supplied oxygen reacts with the hydrogen remaining in oxide 230, removing the hydrogen as H2O (dehydration). As a result, the hydrogen remaining in oxide 230 recombines with the oxygen deficiencies and V O This can suppress the formation of H.

[0126] Furthermore, the insulators 222 and 224 may have a laminated structure of two or more layers. In this case, the laminated structure is not limited to being made of the same material, but may be made of different materials. Also, the insulator 224 may be formed in an island-like manner by being superimposed with the oxide 230a. In this case, the insulator 275 will be in contact with the side surface of the insulator 224 and the upper surface of the insulator 222. In this specification, "island-like" refers to a state in which two or more layers formed in the same process and using the same material are physically separated.

[0127] Conductors 242a and 242b are provided in contact with the upper surface of oxide 230b. Conductors 242a and 242b function as the source electrode or drain electrode of transistor 200, respectively.

[0128] As the conductor 242 (conductor 242a and conductor 242b), it is preferable to use, for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. In one embodiment of the present invention, a nitride containing tantalum is particularly preferred. Alternatively, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen.

[0129] Furthermore, hydrogen contained in oxide 230b, etc., may diffuse into conductor 242a or conductor 242b. In particular, by using tantalum-containing nitrides for conductor 242a and conductor 242b, hydrogen contained in oxide 230b, etc., is more likely to diffuse into conductor 242a or conductor 242b, and the diffused hydrogen may combine with nitrogen present in conductor 242a or conductor 242b. In other words, hydrogen contained in oxide 230b, etc., may be absorbed by conductor 242a or conductor 242b.

[0130] Furthermore, it is preferable that no curved surface is formed between the side surface of the conductor 242 and the top surface of the conductor 242. By using a conductor 242 without such a curved surface, the cross-sectional area of ​​the conductor 242 in the channel width direction can be increased, as shown in Figure 1D. This increases the conductivity of the conductor 242 and increases the on-current of the transistor 200.

[0131] Furthermore, when heat treatment is performed with the conductor 242a (conductor 242b) and the oxide 230b in contact, the sheet resistance of the oxide 230b in the region overlapping with the conductor 242a (conductor 242b) may decrease. Also, the carrier concentration may increase. Therefore, the oxide 230b in the region overlapping with the conductor 242a (conductor 242b) can be made to have a self-aligned low resistance.

[0132] The insulator 271a is provided in contact with the upper surface of the conductor 242a, and the insulator 271b is provided in contact with the upper surface of the conductor 242b. It is preferable that the insulator 271 functions as at least a barrier insulating film against oxygen. Therefore, it is preferable that the insulator 271 has a function to suppress the diffusion of oxygen. For example, it is preferable that the insulator 271 has a function to suppress the diffusion of oxygen more than the insulator 280. As the insulator 271, for example, an insulator such as aluminum oxide or magnesium oxide may be used.

[0133] The insulator 275 is provided so as to cover the insulator 224, oxide 230a, oxide 230b, conductor 242, and insulator 271. Preferably, the insulator 275 has the function of capturing and fixing hydrogen. In that case, it is preferable that the insulator 275 includes silicon nitride or an insulator such as an amorphous metal oxide, for example, aluminum oxide or magnesium oxide. Alternatively, for example, a laminated film of aluminum oxide and silicon nitride on the aluminum oxide may be used as the insulator 275.

[0134] By providing the insulators 271 and 275 described above, the conductor 242 can be surrounded by an insulator that has barrier properties against oxygen. In other words, the oxygen contained in the insulators 224 and 280 can be prevented from diffusing into the conductor 242. This prevents the conductor 242 from being directly oxidized by the oxygen contained in the insulators 224 and 280, which would increase its resistivity and reduce the on-current.

[0135] The insulator 252 functions as part of the gate insulator. Preferably, the insulator 252 is a barrier insulating film against oxygen. The insulator 252 can be any insulator that can be used for the insulator 282 described above. The insulator 252 may be an insulator containing an oxide of either or both aluminum and hafnium. Examples of such insulators include aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and an oxide containing hafnium and silicon (hafnium silicate). In this embodiment, aluminum oxide is used as the insulator 252. In this case, the insulator 252 is an insulator containing at least oxygen and aluminum.

[0136] As shown in Figure 1C, the insulator 252 is provided in contact with the top and side surfaces of oxide 230b, the side surface of oxide 230a, the side surface of insulator 224, and the top surface of insulator 222. In other words, the regions of oxide 230a, oxide 230b, and insulator 224 that overlap with the conductor 260 are covered by the insulator 252 in the cross-section in the channel width direction. This allows the insulator 252, which has an oxygen barrier property, to block the desorption of oxygen from oxide 230a and oxide 230b during heat treatment, etc. Thus, the formation of oxygen vacancies in oxide 230a and oxide 230b can be reduced. As a result, oxygen vacancies and V formed in region 230bc can be reduced. O H can be reduced. Therefore, the electrical characteristics of transistor 200 can be improved, and its reliability can be enhanced.

[0137] Conversely, even if an excess amount of oxygen is present in the insulator 280 and insulator 250, it is possible to suppress the excessive supply of such oxygen to oxides 230a and 230b. Therefore, it is possible to suppress the excessive oxidation of regions 230ba and 230bb via region 230bc, which would otherwise cause a decrease in the on-current of transistor 200 or a decrease in field-effect mobility.

[0138] Furthermore, as shown in Figure 1B, the insulator 252 is provided in contact with the sides of the conductor 242, insulator 271, insulator 275, and insulator 280. Therefore, oxidation of the side surface of the conductor 242 and the formation of an oxide film on that side surface can be reduced. This suppresses a decrease in the on-current of the transistor 200 or a decrease in the field-effect mobility.

[0139] Furthermore, the insulator 252, along with the insulator 254, the insulator 250, and the conductor 260, must be provided in an opening formed in the insulator 280 or the like. In order to miniaturize the transistor 200, it is preferable that the film thickness of the insulator 252 be thin. The film thickness of the insulator 252 is 0.1 nm or more and 5.0 nm or less, preferably 0.5 nm or more and 3.0 nm or less, and more preferably 1.0 nm or more and 3.0 nm or less. In this case, it is sufficient that the insulator 252 has a region with the above-mentioned film thickness in at least a part of it. Also, it is preferable that the film thickness of the insulator 252 is thinner than the film thickness of the insulator 250. In this case, it is sufficient that the insulator 252 has a region with a film thickness thinner than the insulator 250 in at least a part of it.

[0140] To deposit the insulator 252 with a thin film thickness as described above, it is preferable to use the ALD method. ALD methods include thermal ALD, which uses only thermal energy for the reaction between the precursor and reactant, and plasma-enhanced ALD (PEALD), which uses plasma-excited reactants. The PEALD method is preferable in some cases because the use of plasma allows for film deposition at lower temperatures.

[0141] The ALD method utilizes the self-regulating properties of atoms to deposit atoms layer by layer, resulting in several advantages: ultra-thin film deposition is possible, deposition on structures with high aspect ratios is possible, film deposition with fewer defects such as pinholes is possible, film deposition with excellent coverage is possible, and film deposition is possible at low temperatures. Therefore, the insulator 252 can be deposited with good coverage on the sides of openings formed in the insulator 280, etc., with the thin film thickness described above.

[0142] Note that precursors used in the ALD method may contain carbon and other impurities. Therefore, films formed by the ALD method may contain more carbon and other impurities compared to films formed by other film deposition methods. The quantity of impurities can be quantified using secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), or Auger electron spectroscopy (AES).

[0143] Furthermore, by appropriately adjusting the film deposition conditions for the insulating film that will become the insulator 250, the microwave treatment conditions in an oxygen-containing atmosphere, and the amount of oxygen added to the insulator 280 by the deposition of the insulator 282, the oxygen vacancies and V formed in region 230bc can be controlled. O In some cases, it is possible to reduce H and suppress excessive oxidation of regions 230ba and 230bb. In such cases, by omitting the insulator 252, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.

[0144] The insulator 250 functions as part of the gate insulator. It is preferable that the insulator 250 is placed in contact with the upper surface of the insulator 252. The insulator 250 can be silicon oxide, silicon oxynitride, silicon nitride, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, or porous silicon oxide. Silicon oxide and silicon oxynitride are particularly preferred because they are stable with respect to heat. In this case, the insulator 250 will be an insulator having at least oxygen and silicon.

[0145] Similar to the insulator 224, it is preferable that the insulator 250 has a reduced concentration of impurities such as water and hydrogen. The film thickness of the insulator 250 is preferably 1 nm to 20 nm, and more preferably 0.5 nm to 15.0 nm. In this case, it is sufficient that the insulator 250 has a region with the above-mentioned film thickness in at least a portion of it.

[0146] Figures 1A to 1D show a configuration in which the insulator 250 is a single layer, but the present invention is not limited to this, and a laminated structure of two or more layers is also possible. For example, as shown in Figure 2B, the insulator 250 may be a laminated structure of two layers: an insulator 250a and an insulator 250b on top of the insulator 250a.

[0147] As shown in Figure 2B, when the insulator 250 has a two-layer laminated structure, it is preferable that the lower insulator 250a is formed using an insulator that is easily permeable to oxygen, and the upper insulator 250b is formed using an insulator that has the function of suppressing the diffusion of oxygen. With this configuration, the diffusion of oxygen contained in the insulator 250a to the conductor 260 can be suppressed. In other words, the reduction in the amount of oxygen supplied to the oxide 230 can be suppressed. In addition, oxidation of the conductor 260 by the oxygen contained in the insulator 250a can be suppressed. For example, the insulator 250a may be made using a material that can be used for the insulator 250 described above, and the insulator 250b may be an insulator containing an oxide of either aluminum or hafnium or both. As such an insulator, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and silicon (hafnium silicate), etc. can be used. In this embodiment, hafnium oxide is used as the insulator 250b. In this case, the insulator 250b is an insulator having at least oxygen and hafnium. The film thickness of the insulator 250b is 0.5 nm or more and 5.0 nm or less, preferably 1.0 nm or more and 5.0 nm or less, and more preferably 1.0 nm or more and 3.0 nm or less. In this case, it is sufficient that the insulator 250b has at least a portion of the above-mentioned film thickness region.

[0148] Furthermore, when silicon oxide or silicon oxynitride is used for insulator 250a, an insulating material with a high dielectric constant, such as a high-k material, may be used for insulator 250b. By making the gate insulator a laminated structure of insulator 250a and insulator 250b, a laminated structure that is stable against heat and has a high dielectric constant can be made. Therefore, it becomes possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulator. In addition, it becomes possible to thin the equivalent oxide film thickness (EOT) of the insulator that functions as a gate insulator. Thus, the dielectric breakdown voltage of insulator 250 can be increased.

[0149] The insulator 254 functions as part of the gate insulator. Preferably, a barrier insulating film against hydrogen is used as the insulator 254. This prevents impurities such as hydrogen contained in the conductor 260 from diffusing into the insulator 250 and oxide 230b. The insulator 254 can be any insulator that can be used for the insulator 283 described above. For example, silicon nitride deposited by the PEALD method can be used as the insulator 254. In this case, the insulator 254 will be an insulator containing at least nitrogen and silicon.

[0150] Furthermore, the insulator 254 may also have barrier properties against oxygen. This can suppress the diffusion of oxygen contained in the insulator 250 into the conductor 260.

[0151] Furthermore, the insulator 254, along with the insulator 252, the insulator 250, and the conductor 260, must be provided in an opening formed in the insulator 280 or the like. In order to miniaturize the transistor 200, it is preferable that the film thickness of the insulator 254 be thin. The film thickness of the insulator 254 is 0.1 nm or more and 5.0 nm or less, preferably 0.5 nm or more and 3.0 nm or less, and more preferably 1.0 nm or more and 3.0 nm or less. In this case, it is sufficient that the insulator 254 has a region with the above-mentioned film thickness in at least a part of it. Also, it is preferable that the film thickness of the insulator 254 is thinner than the film thickness of the insulator 250. In this case, it is sufficient that the insulator 254 has a region with a thinner film thickness than the insulator 250 in at least a part of it.

[0152] Furthermore, as shown in Figure 2B, when the insulator 250 has a two-layer laminated structure, by using an insulator 250b that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, such as hafnium oxide, the insulator 250b can also perform the function of the insulator 254. In such a case, by omitting the insulator 254, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.

[0153] The conductor 260 functions as the first gate electrode of the transistor 200. Preferably, the conductor 260 has a conductor 260a and a conductor 260b disposed on top of the conductor 260a. For example, it is preferable that the conductor 260a is arranged to enclose the bottom and sides of the conductor 260b. Also, as shown in Figures 1B and 1C, the top surface of the conductor 260 is roughly the same as the top surface of the insulator 250. In Figures 1B and 1C, the conductor 260 is shown as a two-layer structure of conductor 260a and conductor 260b, but it may also be a single-layer structure or a stacked structure of three or more layers.

[0154] It is preferable to use a conductive material for the conductor 260a that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one such as oxygen atoms or oxygen molecules).

[0155] Furthermore, because the conductor 260a has the function of suppressing oxygen diffusion, it is possible to suppress the oxidation of the conductor 260b by the oxygen contained in the insulator 250, which would otherwise reduce its conductivity. As a conductive material that has the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc.

[0156] Furthermore, since the conductor 260 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, the conductor 260b can be a conductive material mainly composed of tungsten, copper, or aluminum. The conductor 260b may also be in a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material.

[0157] Furthermore, in transistor 200, the conductor 260 is formed self-aligningly to fill the openings formed in the insulator 280 and the like. By forming the conductor 260 in this way, the conductor 260 can be reliably positioned in the region between the conductors 242a and 242b without the need for alignment.

[0158] Furthermore, as shown in Figure 1C, in the channel width direction of the transistor 200, with reference to the bottom surface of the insulator 222, the height of the bottom surface of the conductor 260 in the region where the conductor 260 and the oxide 230b do not overlap is preferably lower than the height of the bottom surface of the oxide 230b. By configuring the conductor 260, which functions as a gate electrode, to cover the side and top surfaces of the channel formation region of the oxide 230b via the insulator 250 or the like, it becomes easier to apply the electric field of the conductor 260 to the entire channel formation region of the oxide 230b. Therefore, the on-current of the transistor 200 can be increased and the frequency characteristics can be improved. With reference to the bottom surface of the insulator 222, the difference between the height of the bottom surface of the conductor 260 in the region where the oxide 230a and oxide 230b and the conductor 260 do not overlap and the height of the bottom surface of the oxide 230b is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, and more preferably 5 nm or more and 20 nm or less.

[0159] The insulator 280 is provided on the insulator 275, and openings are formed in the regions where the insulators 252, 250, 254, and conductor 260 are provided. The upper surface of the insulator 280 may also be flattened.

[0160] The insulator 280, which functions as an interlayer film, preferably has a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance occurring between wiring can be reduced. The insulator 280 is preferably made of the same material as the insulator 216, for example. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Alternatively, materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are particularly preferred because they can easily form regions containing oxygen that is desorbed by heating.

[0161] It is preferable that the concentration of impurities such as water and hydrogen in the insulator 280 is reduced. For example, the insulator 280 may be an oxide containing silicon, such as silicon oxide or silicon oxynitride.

[0162] The insulator 282 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen into the insulator 280 from above, and preferably has the function of capturing impurities such as hydrogen. Furthermore, the insulator 282 preferably functions as a barrier insulating film that suppresses the permeation of oxygen. As the insulator 282, an amorphous metal oxide, such as aluminum oxide, may be used. In this case, the insulator 282 will be an insulator having at least oxygen and aluminum. By providing an insulator 282 that is in contact with the insulator 280 in the region sandwiched between the insulator 212 and the insulator 283 and has the function of capturing impurities such as hydrogen, impurities such as hydrogen contained in the insulator 280 can be captured, and the amount of hydrogen in that region can be kept constant. In particular, using aluminum oxide with an amorphous structure as the insulator 282 is preferable because it may be possible to capture or fix hydrogen more effectively. This makes it possible to manufacture a transistor 200 and a semiconductor device that have good characteristics and are highly reliable.

[0163] The insulator 283 functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen into the insulator 280 from above. The insulator 283 is placed on top of the insulator 282. Preferably, the insulator 283 is a silicon-containing nitride such as silicon nitride or silicon nitride oxide. For example, silicon nitride deposited by sputtering may be used as the insulator 283. By depositing the insulator 283 by sputtering, a high-density silicon nitride film can be formed. Alternatively, as the insulator 283, silicon nitride deposited by PEALD or CVD may be further laminated on top of the silicon nitride deposited by sputtering.

[0164] It is preferable that the conductors 240a and 240b are made of conductive materials mainly composed of tungsten, copper, or aluminum. Furthermore, the conductors 240a and 240b may be arranged in a laminated structure.

[0165] Furthermore, when the conductor 240 has a laminated structure, it is preferable to use a conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen for the first conductor arranged in the vicinity of the insulators 285, 283, 282, 280, 275, and 271. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, etc. The conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or a laminate. In addition, it is possible to suppress the mixing of impurities such as water and hydrogen contained in the layer above insulator 283 into the oxide 230 through conductors 240a and 240b.

[0166] As insulators 241a and 241b, barrier insulating films that can be used for insulator 275 and the like may be used. For example, silicon nitride, aluminum oxide, silicon oxide nitride, and other insulators may be used as insulators 241a and 241b. Since insulators 241a and 241b are provided in contact with insulators 283, 282, and 271, impurities such as water and hydrogen contained in insulator 280 and the like can be prevented from mixing into the oxide 230 through conductors 240a and 240b. Silicon nitride is particularly suitable because of its high blocking properties for hydrogen. In addition, it is possible to prevent oxygen contained in insulator 280 from being absorbed by conductors 240a and 240b.

[0167] When the insulators 241a and 241b are arranged in a laminated structure as shown in Figure 1B, it is preferable that the first insulator in contact with the inner wall of the opening, such as the insulator 280, and the second insulator inside it, use a combination of an oxygen barrier insulating film and a hydrogen barrier insulating film.

[0168] For example, aluminum oxide deposited by the ALD method can be used as the first insulator, and silicon nitride deposited by the PEALD method can be used as the second insulator. This configuration suppresses oxidation of the conductor 240 and further reduces the incorporation of hydrogen into the conductor 240.

[0169] Furthermore, conductors 246 (conductors 246a and 246b) that function as wiring may be placed in contact with the upper surfaces of conductor 240a and conductor 240b. It is preferable that the conductors 246 be made of a conductive material mainly composed of tungsten, copper, or aluminum. The conductors may also be in a laminated structure, for example, a laminate of titanium or titanium nitride with the conductive material. The conductors may also be formed to be embedded in an opening provided in the insulator.

[0170] <Component materials for semiconductor devices> The following describes the constituent materials that can be used in semiconductor devices.

[0171] <<Substrate>> As the substrate for forming transistor 200, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate may be used. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon and germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Furthermore, there are semiconductor substrates having insulating regions within the aforementioned semiconductor substrates, such as SOI (Silicon On Insulator) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, there are substrates having metal nitrides or metal oxides. Furthermore, there are substrates on which a conductor or semiconductor is provided on an insulating substrate, substrates on which a conductor or insulator is provided on a semiconductor substrate, and substrates on which a semiconductor or insulator is provided on a conductive substrate. Alternatively, substrates with elements mounted on them may be used. Examples of elements mounted on the substrate include capacitive elements, resistive elements, switch elements, light-emitting elements, and memory elements.

[0172] <<Insulator>> Insulators include insulating oxides, nitrides, oxidized nitrides, nitride oxides, metal oxides, metal oxidized nitrides, and metal nitride oxides.

[0173] For example, as transistors become smaller and more integrated, thinning of the gate insulator can lead to problems such as leakage current. By using a high-k material for the insulator that functions as the gate insulator, it is possible to lower the voltage during transistor operation while maintaining the physical film thickness. On the other hand, by using a material with a low dielectric constant for the insulator that functions as the interlayer film, parasitic capacitance between wiring can be reduced. Therefore, it is best to select the material according to the function of the insulator.

[0174] Furthermore, examples of insulators with high dielectric constants include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxidized nitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxidized nitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0175] Insulators with low dielectric constants include silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide with vacancies, or resins.

[0176] Furthermore, the electrical properties of transistors using metal oxides can be stabilized by surrounding them with an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen. As an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used in a single layer or in a multilayer structure. Specifically, as an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon oxide nitride, and silicon nitride can be used.

[0177] Furthermore, the insulator that functions as a gate insulator is preferably an insulator that has a region containing oxygen that is desorbed by heating. For example, by having a silicon oxide or silicon oxynitride having a region containing oxygen that is desorbed by heating in contact with the oxide 230, the oxygen deficiency of the oxide 230 can be compensated for.

[0178] <<Conductive material>> As the conductor, it is preferable to use a metallic element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above metallic elements, or an alloy combining the above metallic elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. Alternatively, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements like phosphorus, or silicides such as nickel silicide may be used.

[0179] Furthermore, multiple conductive layers formed from the above materials may be used in a laminated structure. For example, a laminated structure may be formed by combining the aforementioned metal element material with an oxygen-containing conductive material. Alternatively, a laminated structure may be formed by combining the aforementioned metal element material with a nitrogen-containing conductive material. Alternatively, a laminated structure may be formed by combining the aforementioned metal element material with an oxygen-containing conductive material and a nitrogen-containing conductive material.

[0180] Furthermore, when using an oxide in the channel formation region of a transistor, it is preferable to use a laminated structure for the conductor functioning as the gate electrode, which combines a material containing the aforementioned metal element with a conductive material containing oxygen. In this case, it is preferable to place the conductive material containing oxygen on the channel formation region side. By placing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is more easily supplied to the channel formation region.

[0181] In particular, it is preferable to use a conductive material containing metal elements and oxygen contained in the metal oxide in which the channel is formed as the conductor that functions as the gate electrode. Alternatively, conductive materials containing the aforementioned metal elements and nitrogen may be used. For example, conductive materials containing nitrogen such as titanium nitride and tantalum nitride may be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon-doped indium tin oxide may be used. In addition, indium gallium zinc oxide containing nitrogen may be used. By using such materials, it may be possible to capture hydrogen contained in the metal oxide in which the channel is formed. Alternatively, it may be possible to capture hydrogen that is mixed in from an external insulator or the like.

[0182] <<Metal Oxides>> It is preferable to use a metal oxide (oxide semiconductor) that functions as a semiconductor as oxide 230. Below, metal oxides applicable to oxide 230 according to the present invention will be described.

[0183] The metal oxide preferably contains at least indium or zinc. In particular, it is preferable that it contains indium and zinc. In addition, it is preferable that it contains aluminum, gallium, yttrium, tin, etc. It may also contain one or more selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc.

[0184] Here, we consider the case where the metal oxide is an In-M-Zn oxide containing indium, element M, and zinc. Element M is aluminum, gallium, yttrium, or tin. Other elements that can be used for element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt. However, it is also possible to use a combination of multiple of the aforementioned elements for element M. In particular, it is preferable that element M is one or more elements selected from gallium, aluminum, yttrium, and tin.

[0185] In particular, it is preferable to use an oxide containing indium (In), gallium (Ga), and zinc (Zn) (also written as IGZO) as the semiconductor layer of the transistor. Alternatively, an oxide containing indium (In), aluminum (Al), and zinc (Zn) (also written as IAZO) may be used as the semiconductor layer of the transistor. Alternatively, an oxide containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn) (IAGZO) may be used as the semiconductor layer of the transistor.

[0186] In this specification, metal oxides containing nitrogen may also be collectively referred to as metal oxides. Furthermore, metal oxides containing nitrogen may also be called metal oxynitrides.

[0187] In the following sections, we will describe oxides containing indium (In), gallium (Ga), and zinc (Zn) as examples of metal oxides. Note that oxides containing indium (In), gallium (Ga), and zinc (Zn) are sometimes called In-Ga-Zn oxides.

[0188] <Classification of crystal structures> Examples of crystalline structures for oxide semiconductors include amorphous (including completely amorphous), CAAC (c-axis-aligned crystalline), nc (nanocrystalline), CAC (cloud-aligned composite), single crystal, and polycrystal.

[0189] The crystal structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. For example, it can be evaluated using the XRD spectrum obtained from a GIXD (Grazing-Incidence XRD) measurement. The GIXD method is also known as the thin-film method or the Seemann-Bohlin method. In the following text, the XRD spectrum obtained from a GIXD measurement may simply be referred to as the XRD spectrum.

[0190] For example, in a quartz glass substrate, the peak shape of the XRD spectrum is nearly symmetrical. On the other hand, in an In-Ga-Zn oxide film with a crystalline structure, the peak shape of the XRD spectrum is asymmetrical. The asymmetrical shape of the XRD spectrum peaks clearly indicates the presence of crystals in the film or substrate. In other words, if the peak shape of the XRD spectrum is not symmetrical, the film or substrate cannot be said to be in an amorphous state.

[0191] Furthermore, the crystalline structure of a film or substrate can be evaluated by the diffraction pattern (also called the nano-beam electron diffraction pattern) observed using nano-beam electron diffraction (NBED). For example, a halo is observed in the diffraction pattern of a quartz glass substrate, confirming that the quartz glass is in an amorphous state. On the other hand, a spot-like pattern is observed in the diffraction pattern of an In-Ga-Zn oxide film deposited at room temperature, rather than a halo. Therefore, it is presumed that an In-Ga-Zn oxide film deposited at room temperature is in an intermediate state, neither single-crystal nor polycrystalline, nor amorphous, and cannot be concluded to be in an amorphous state.

[0192] <<Oxide semiconductor structure>> It should be noted that oxide semiconductors may be classified differently from those described above when considering their structure. For example, oxide semiconductors can be divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the aforementioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors also include polycrystalline oxide semiconductors, pseudo-amorphous oxide semiconductors (a-like OS), and amorphous oxide semiconductors.

[0193] Here, we will explain the details of the CAAC-OS, nc-OS, and a-like OS mentioned above.

[0194] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, the c-axis of which is oriented in a specific direction. This specific direction is the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. If we consider the atomic arrangement as a lattice arrangement, then a crystalline region is also a region with a aligned lattice arrangement. Furthermore, CAAC-OS has regions where multiple crystalline regions are connected in the ab-plane direction, and these regions may exhibit distortion. Distortion refers to a point in the connected region where the orientation of the lattice arrangement changes between a region with a aligned lattice arrangement and another region with a aligned lattice arrangement. In short, CAAC-OS is an oxide semiconductor that is c-axis oriented and does not exhibit clear orientation in the ab-plane direction.

[0195] Each of the above-mentioned crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of that crystalline region will be less than 10 nm. When a crystalline region is composed of many minute crystals, the maximum diameter of that crystalline region may be around several tens of nm.

[0196] Furthermore, in In-Ga-Zn oxides, CAAC-OS tends to have a layered crystalline structure (also called a layered structure) consisting of layers containing indium (In) and oxygen (hereinafter referred to as the In layer) and layers containing gallium (Ga), zinc (Zn), and oxygen (hereinafter referred to as the (Ga,Zn) layer). Note that indium and gallium are mutually substitutable. Therefore, the (Ga,Zn) layer may contain indium. Also, the In layer may contain gallium. Also, the In layer may contain zinc. This layered structure can be observed, for example, as a lattice image in high-resolution TEM (Transmission Electron Microscope) images.

[0197] When structural analysis of a CAAC-OS film is performed using an XRD instrument, for example, out-of-plane XRD measurements using θ / 2θ scanning show a peak indicating c-axis orientation at 2θ = 31° or nearby. Note that the position of the c-axis orientation peak (value of 2θ) may vary depending on the type and composition of the metal elements constituting the CAAC-OS.

[0198] Furthermore, for example, multiple bright spots are observed in the electron diffraction pattern of a CAAC-OS film. These spots are observed at point-symmetric positions with respect to the incident electron beam spot (also called the direct spot) that passed through the sample.

[0199] When the crystal region is observed from the specific direction described above, the lattice arrangement within that crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. Furthermore, the strain may have lattice arrangements such as pentagons or heptagons. Moreover, in CAAC-OS, clear grain boundaries cannot be observed even near the strain. In other words, it can be seen that the formation of grain boundaries is suppressed by the strain in the lattice arrangement. This is thought to be because CAAC-OS can tolerate strain due to the fact that the arrangement of oxygen atoms is not dense in the ab-plane direction, and the bond distance between atoms changes due to the substitution of metal atoms.

[0200] Furthermore, a crystal structure in which clear grain boundaries can be observed is called a polycrystalline material. Grain boundaries act as recombination centers, trapping carriers and potentially causing a decrease in transistor on-current and field-effect mobility. Therefore, CAAC-OS, in which clear grain boundaries cannot be observed, is one of the crystalline oxides with a suitable crystal structure for the semiconductor layer of a transistor. In addition, a structure containing Zn is preferred for the composition of CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are preferred because they can suppress the generation of grain boundaries more effectively than In oxide.

[0201] CAAC-OS is an oxide semiconductor with high crystallinity and no clearly defined grain boundaries. Therefore, CAAC-OS is less susceptible to the decrease in electron mobility caused by grain boundaries. Furthermore, since the crystallinity of oxide semiconductors can decrease due to the inclusion of impurities and the generation of defects, CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Consequently, oxide semiconductors containing CAAC-OS have stable physical properties. Therefore, oxide semiconductors containing CAAC-OS are heat-resistant and highly reliable. In addition, CAAC-OS is stable even at high temperatures (so-called thermal budget) during the manufacturing process. Therefore, using CAAC-OS in transistors with metal oxide in the channel formation region (sometimes called OS transistors) allows for greater flexibility in the manufacturing process.

[0202] [nc-OS] nc-OS exhibits periodicity in atomic arrangement in minute regions (e.g., regions between 1 nm and 10 nm, particularly between 1 nm and 3 nm). In other words, nc-OS contains minute crystals. These minute crystals are also called nanocrystals because their size is, for example, between 1 nm and 10 nm, particularly between 1 nm and 3 nm. Furthermore, nc-OS shows no regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Consequently, depending on the analytical method, nc-OS may be indistinguishable from a-like OS or amorphous oxide semiconductors. For example, when structural analysis of an nc-OS film is performed using an XRD instrument, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Also, when electron diffraction (also called limited-field electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter larger than that of the nanocrystals (e.g., 50 nm or larger), a diffraction pattern resembling a halo pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystal (for example, 1 nm to 30 nm), an electron diffraction pattern may be obtained in which multiple spots are observed within a ring-shaped region centered on the direct spot.

[0203] [a-like OS] a-like OS is an oxide semiconductor having a structure between nc-OS and amorphous oxide semiconductors. a-like OS has porous or low-density regions. That is, a-like OS has lower crystallinity compared to nc-OS and CAAC-OS. Also, a-like OS has a higher hydrogen concentration in the film compared to nc-OS and CAAC-OS.

[0204] <<Oxide Semiconductor Composition>> Next, we will explain the details of CAC-OS mentioned above. Note that CAC-OS refers to the material composition.

[0205] [CAC-OS] CAC-OS is a material composition in which, for example, the elements constituting the metal oxide are unevenly distributed in sizes of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or close to that size. In the following, a state in which one or more metal elements are unevenly distributed in a metal oxide, and the regions containing these metal elements are mixed in sizes of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or close to that size, is also referred to as a mosaic or patchy state.

[0206] Furthermore, CAC-OS is a composite metal oxide having a mosaic-like structure formed by the separation of the material into a first region and a second region, with the first region distributed within the film (hereinafter also referred to as a cloud-like structure). In other words, CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.

[0207] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS of In-Ga-Zn oxide, the first region is the region where [In] is greater than the [In] in the composition of the CAC-OS film. The second region is the region where [Ga] is greater than the [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is the region where [In] is greater than the [In] in the second region, and [Ga] is smaller than the [Ga] in the second region. The second region is the region where [Ga] is greater than the [Ga] in the first region, and [In] is smaller than the [In] in the first region.

[0208] Specifically, the first region described above is a region whose main components are indium oxide, indium zinc oxide, etc. The second region described above is a region whose main components are gallium oxide, gallium zinc oxide, etc. In other words, the first region can be rephrased as a region whose main component is In. Similarly, the second region can be rephrased as a region whose main component is Ga.

[0209] Furthermore, a clear boundary may not be observed between the first region and the second region described above.

[0210] Furthermore, CAC-OS in In-Ga-Zn oxide refers to a material composition containing In, Ga, Zn, and O, in which regions with Ga as the main component and regions with In as the main component are arranged in a mosaic-like fashion, with these regions existing randomly. Therefore, it is presumed that CAC-OS has a structure in which the metallic elements are unevenly distributed.

[0211] CAC-OS can be formed, for example, by sputtering under conditions where the substrate is not heated. When forming CAC-OS by sputtering, one or more gases selected from inert gases (typically argon), oxygen gas, and nitrogen gas may be used as the deposition gas. Furthermore, a lower ratio of the oxygen gas flow rate to the total deposition gas flow rate during deposition is preferable. For example, the ratio of the oxygen gas flow rate to the total deposition gas flow rate during deposition should be 0% or more and less than 30%, preferably 0% or more and 10% or less.

[0212] Furthermore, for example, in the case of CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) confirms that it has a structure in which regions mainly composed of In (first region) and regions mainly composed of Ga (second region) are unevenly distributed and mixed.

[0213] Here, the first region is a region with higher conductivity compared to the second region. In other words, the conductivity of the metal oxide is exhibited when carriers flow through the first region. Therefore, a high field-effect mobility (μ) can be achieved when the first region is distributed in a cloud-like manner within the metal oxide.

[0214] On the other hand, the second region is a region with higher insulating properties compared to the first region. In other words, the distribution of the second region within the metal oxide can suppress leakage current.

[0215] Therefore, when CAC-OS is used in a transistor, the conductivity due to the first region and the insulation due to the second region work complementaryly to give CAC-OS a switching function (on / off function). In other words, CAC-OS has conductive function in part of the material, insulating function in part of the material, and semiconductor function as a whole. By separating the conductive function and the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I on This enables high field-effect mobility (μ) and good switching operation.

[0216] Furthermore, transistors using CAC-OS offer high reliability. Therefore, CAC-OS is ideal for various semiconductor devices, including display devices.

[0217] Oxide semiconductors can take on diverse structures, each possessing different properties. One embodiment of the present invention may include two or more of the following: amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, CAC-OS, nc-OS, and CAAC-OS.

[0218] <Transistors containing oxide semiconductors> Next, we will explain the case where the above oxide semiconductor is used in a transistor.

[0219] By using the above-mentioned oxide semiconductor in transistors, transistors with high field-effect mobility can be realized. Furthermore, highly reliable transistors can be achieved.

[0220] It is preferable to use an oxide semiconductor with a low carrier concentration for the transistor. For example, the carrier concentration of an oxide semiconductor is 1 × 10⁻⁶. 17 cm -3 The following is preferably 1 × 10 15 cm -3 More preferably 1 × 10 13 cm -3 More preferably 1 × 10 11 cm -3 More preferably 1 × 10 10 cm -3 It is less than 1 × 10 -9 cm -3 This concludes the explanation. Furthermore, when lowering the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film should be lowered to reduce the defect level density. In this specification, a low impurity concentration and low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic. Note that oxide semiconductors with low carrier concentrations are sometimes referred to as high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors.

[0221] Furthermore, oxide semiconductor films that are highly pure or substantially highly pure have a low defect level density, which may result in a low trap level density.

[0222] Furthermore, charges trapped in the trap levels of oxide semiconductors can take a long time to disappear, sometimes behaving like fixed charges. Therefore, transistors in which channel formation regions are formed in oxide semiconductors with a high trap level density may exhibit unstable electrical properties.

[0223] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Further, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, etc. Note that the impurities in the oxide semiconductor refer to, for example, components other than the main components constituting the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic% can be said to be an impurity.

[0224] <Impurity> Here, the effects of various impurities in the oxide semiconductor will be described.

[0225] In the oxide semiconductor, when silicon or carbon, which is one of the Group 14 elements, is contained, defect levels are formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the oxide semiconductor (the concentration obtained by secondary ion mass spectrometry (SIMS)) is set to 2×10 18 atoms / cm 3 or less, preferably 2×10 17 atoms / cm 3 or less.

[0226] [[ID=२२]]Further, when an alkali metal or an alkaline earth metal is contained in the oxide semiconductor, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have normally-on characteristics. For this reason, the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is set to 1×10 18 atoms / cm 3 or less, preferably 2×10 16 atoms / cm 3 or less.

[0227] Furthermore, in oxide semiconductors, the presence of nitrogen generates electrons, which act as carriers, increasing the carrier concentration and making it easier for the semiconductor to become n-type. As a result, transistors using oxide semiconductors containing nitrogen tend to exhibit normally-on characteristics. Alternatively, the presence of nitrogen in oxide semiconductors can lead to the formation of trap levels. As a result, the electrical properties of the transistor may become unstable. For this reason, the nitrogen concentration in oxide semiconductors obtained by SIMS should be set to 5 × 10⁻⁶. 19 atoms / cm 3 Less than 5 × 10 18 atoms / cm 3 More preferably 1 × 10 18 atoms / cm 3 More preferably 5 × 10 17 atoms / cm 3 Do the following:

[0228] Furthermore, hydrogen contained in oxide semiconductors can react with oxygen bonded to metal atoms to form water, potentially creating oxygen vacancies. Hydrogen can then fill these vacancies, generating electrons as carriers. Additionally, some of the hydrogen can combine with oxygen bonded to metal atoms to generate electrons. Therefore, transistors using oxide semiconductors containing hydrogen tend to exhibit normally-on characteristics. For this reason, it is preferable to reduce the hydrogen content in oxide semiconductors as much as possible. Specifically, the hydrogen concentration in the oxide semiconductor obtained by SIMS should be 1 × 10⁻⁶. 20 atoms / cm 3 Less than 1 × 10 19 atoms / cm 3 Less than 5x10 18 atoms / cm 3 Less than 1 × 10 18 atoms / cm 3 Make it less than.

[0229] By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of a transistor, stable electrical characteristics can be imparted.

[0230] <<Other Semiconductor Materials>> The semiconductor material that can be used for oxide 230 is not limited to the metal oxides described above. A semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may be used as oxide 230. For example, it is preferable to use semiconductors of elemental elements such as silicon, compound semiconductors such as gallium arsenide, or layered materials that function as semiconductors (also called atomic layer materials, two-dimensional materials, etc.) as semiconductor materials. In particular, it is preferable to use layered materials that function as semiconductors as semiconductor materials.

[0231] In this specification, the term "layered material" refers to a group of materials having a layered crystalline structure. A layered crystalline structure is a structure in which layers formed by covalent or ionic bonds are stacked via weaker bonds than covalent or ionic bonds, such as van der Waals forces. Layered materials have high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0232] Layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogens. Chalcogens are a general term for elements belonging to Group 16, and include oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.

[0233] As oxide 230, it is preferable to use, for example, a transition metal chalcogenide that functions as a semiconductor. Specific examples of transition metal chalcogenides applicable as oxide 230 include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum tellurium (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten tellurium (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2).

[0234] <Method for fabricating semiconductor devices> Next, a method for manufacturing a semiconductor device, which is one embodiment of the present invention as shown in Figures 1A to 1D, will be explained using Figures 6A to 17D.

[0235] In each figure, A shows a top view. In each figure, B is a cross-sectional view corresponding to the area indicated by the dashed line A1-A2 in A, and is also a cross-sectional view of transistor 200 in the channel length direction. In each figure, C is a cross-sectional view corresponding to the area indicated by the dashed line A3-A4 in A, and is also a cross-sectional view of transistor 200 in the channel width direction. In each figure, D is a cross-sectional view of the area indicated by the dashed line A5-A6 in A. Note that in the top view A of each figure, some elements have been omitted for clarity.

[0236] In the following, insulating materials for forming insulators, conductive materials for forming conductors, or semiconductor materials for forming semiconductors can be deposited using methods such as sputtering, CVD, MBE, PLD, and ALD as appropriate.

[0237] Sputtering methods include RF sputtering, which uses a high-frequency power supply; DC sputtering, which uses a direct current power supply; and pulsed DC sputtering, which changes the voltage applied to the electrodes in pulses. RF sputtering is mainly used for depositing insulating films, while DC sputtering is mainly used for depositing conductive metal films. Pulsed DC sputtering is mainly used when depositing compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0238] Furthermore, CVD methods can be classified into plasma CVD (PECVD), which utilizes plasma; thermal CVD (TCVD), which utilizes heat; and photo CVD (Photo CVD), which utilizes light. They can also be further divided into metal CVD (MCVD) and metal-organic CVD (MOCVD) depending on the source gas used.

[0239] Plasma CVD allows for the production of high-quality films at relatively low temperatures. Thermal CVD, on the other hand, does not use plasma, thus minimizing plasma damage to the workpiece. For example, wiring, electrodes, and elements (transistors, capacitive elements, etc.) contained in semiconductor devices can be charged up by receiving charge from the plasma. In this case, the accumulated charge can destroy the wiring, electrodes, and elements contained in the semiconductor device. In contrast, thermal CVD, which does not use plasma, does not cause such plasma damage, thus increasing the yield of semiconductor devices. Furthermore, because thermal CVD does not cause plasma damage during film formation, films with fewer defects can be obtained.

[0240] Furthermore, ALD methods such as thermal ALD, which carries out the reaction of the precursor and reactant using only thermal energy, and PEALD, which uses plasma-excited reactants, can be used.

[0241] CVD and ALD methods differ from sputtering, where particles emitted from a target or other source are deposited. Therefore, they are less affected by the shape of the workpiece and provide good step-level coating. In particular, the ALD method is suitable for coating the surface of openings with high aspect ratios due to its excellent step-level coating and uniform thickness. However, because the ALD method has a relatively slow deposition rate, it is sometimes preferable to use it in combination with other deposition methods that have a faster deposition rate, such as the CVD method.

[0242] Furthermore, the CVD method allows for the deposition of films with any desired composition by changing the flow rate ratio of the raw material gases. For example, in the CVD method, films with continuously changing compositions can be deposited by changing the flow rate ratio of the raw material gases while the film is being deposited. When depositing films while changing the flow rate ratio of the raw material gases, the time required for film deposition can be shortened compared to depositing films using multiple deposition chambers, because time spent on transport or pressure adjustment is eliminated. Therefore, it may be possible to increase the productivity of semiconductor devices.

[0243] Furthermore, the ALD method allows for the deposition of films with any desired composition by simultaneously introducing multiple different types of precursors. Alternatively, when introducing multiple different types of precursors, films with any desired composition can be deposited by controlling the number of cycles for each precursor.

[0244] First, a substrate (not shown) is prepared, and an insulator 212 is deposited on the substrate (see Figures 6A to 6D). The deposition of the insulator 212 is preferably carried out using a sputtering method. By using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulator 212 can be reduced. However, the deposition of the insulator 212 is not limited to the sputtering method; CVD, MBE, PLD, ALD, etc., may be used as appropriate.

[0245] In this embodiment, as the insulator 212, silicon nitride is formed by pulsed DC sputtering using a silicon target in an atmosphere containing nitrogen gas. By using the pulsed DC sputtering method, generation of particles due to arcing on the target surface can be suppressed, so that the film thickness distribution can be made more uniform. Also, by using a pulsed voltage, the rise and fall of discharge can be made steeper than in the case of a high-frequency voltage. As a result, power can be supplied to the electrodes more efficiently, improving the sputtering rate and film quality.

[0246] By using an insulator such as silicon nitride through which impurities such as water and hydrogen hardly permeate, diffusion of impurities such as water and hydrogen contained in the layer below the insulator 212 can be suppressed. Also, by using an insulator such as silicon nitride through which copper hardly permeates as the insulator 212, even if a conductor in the layer below the insulator 212 (not shown) uses a metal such as copper that easily diffuses, diffusion of the metal upward through the insulator 212 can be suppressed.

[0247] Next, an insulator 214 is formed on the insulator 212 (see FIGS. 6A to 6D). The formation of the insulator 214 is preferably performed using a sputtering method. By using a sputtering method that does not require a molecule containing hydrogen in the film-forming gas, the hydrogen concentration in the insulator 214 can be reduced. However, the formation of the insulator 214 is not limited to the sputtering method, and a CVD method, MBE method, PLD method, ALD method, etc. may be appropriately used.

[0248] In this embodiment, as the insulator 214, aluminum oxide is formed by pulsed DC sputtering using an aluminum target in an atmosphere containing oxygen gas. By using the pulsed DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved. Here, RF power may be applied to the substrate. The amount of oxygen injected into the layer below the insulator 214 can be controlled by the magnitude of the RF power applied to the substrate. The RF power is 0 W / cm 2 to 1.86 W / cm 2The following applies: In other words, the amount of oxygen injected can be varied to suit the characteristics of the transistor by changing the RF power used during the formation of the insulator 214. Therefore, an amount of oxygen suitable for improving the reliability of the transistor can be injected. Furthermore, the RF frequency is preferably 10 MHz or higher. Typically, it is 13.56 MHz. The higher the RF frequency, the less damage can be inflicted on the substrate.

[0249] It is preferable to use an amorphous metal oxide, such as aluminum oxide, as the insulator 214, which has a high ability to capture and fix hydrogen. This allows for the capture or fixation of hydrogen contained in the insulator 216, etc., preventing the hydrogen from diffusing into the oxide 230. In particular, it is preferable to use amorphous aluminum oxide, or aluminum oxide with an amorphous structure, as the insulator 214, as this may allow for more effective capture or fixation of hydrogen. This makes it possible to manufacture a transistor 200 and semiconductor device with good properties and high reliability.

[0250] Next, an insulator 216 is deposited on the insulator 214. The deposition of the insulator 216 is preferably carried out using a sputtering method. By using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulator 216 can be reduced. However, the deposition of the insulator 216 is not limited to the sputtering method; CVD, MBE, PLD, ALD, etc., may be used as appropriate.

[0251] In this embodiment, silicon oxide is deposited as the insulator 216 using a silicon target in an atmosphere containing oxygen gas by pulsed DC sputtering. By using pulsed DC sputtering, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved.

[0252] It is preferable to deposit insulators 212, 214, and 216 continuously without exposure to the atmosphere. For example, a multi-chamber type deposition apparatus can be used. This allows for the deposition of insulators 212, 214, and 216 with reduced hydrogen content in the films, and further reduces the incorporation of hydrogen into the films between each deposition process.

[0253] Next, an opening is formed in the insulator 216 that reaches the insulator 214. The opening includes, for example, grooves and slits. In some cases, the term "opening" refers to the region in which the opening is formed. The opening may be formed using wet etching, but dry etching is preferable for microfabrication. Furthermore, it is preferable to select an insulator 214 that functions as an etching stopper film when etching the insulator 216 to form grooves. For example, if silicon oxide or silicon oxynitride is used for the insulator 216 in which grooves are formed, silicon nitride, aluminum oxide, or hafnium oxide may be used for the insulator 214.

[0254] As a dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high-frequency voltage to one electrode of the parallel plate electrodes. Alternatively, it may be configured to apply multiple different high-frequency voltages to one electrode of the parallel plate electrodes. Alternatively, it may be configured to apply a high-frequency voltage of the same frequency to each of the parallel plate electrodes. Alternatively, it may be configured to apply high-frequency voltages of different frequencies to each of the parallel plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. A dry etching apparatus having a high-density plasma source may be, for example, an inductively coupled plasma (ICP) etching apparatus.

[0255] After the opening is formed, a conductive film that will become the conductor 205a is deposited. It is desirable that the conductive film contains a conductor that has the function of suppressing oxygen permeation. For example, tantalum nitride, tungsten nitride, titanium nitride, etc. can be used. Alternatively, a laminated film can be formed of a conductor that has the function of suppressing oxygen permeation and a tantalum, tungsten, titanium, molybdenum, aluminum, copper, or molybdenum-tungsten alloy. The conductive film can be deposited using sputtering, CVD, MBE, PLD, ALD, etc.

[0256] In this embodiment, titanium nitride is deposited as a conductive film that forms the conductor 205a. By using such a metal nitride as a layer beneath the conductor 205b, oxidation of the conductor 205b by the insulator 216 and the like can be suppressed. Furthermore, even if a highly diffusive metal such as copper is used as the conductor 205b, it is possible to prevent the metal from diffusing out of the conductor 205a.

[0257] Next, a conductive film to form the conductor 205b is deposited. This conductive film can be made of materials such as tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy. The conductive film can be deposited using methods such as plating, sputtering, CVD, MBE, PLD, or ALD. In this embodiment, tungsten is used as the conductive film.

[0258] Next, a CMP (Chemical Mechanical Polishing) treatment is performed to remove a portion of the conductive film that will become conductor 205a and the conductive film that will become conductor 205b, exposing the insulator 216 (see Figures 6A to 6D). As a result, conductor 205a and conductor 205b remain only in the openings. Note that a portion of the insulator 216 may be removed during this CMP treatment.

[0259] Next, an insulator 222 is deposited on the insulator 216 and the conductor 205 (see Figures 7A to 7D). It is preferable to deposit an insulator 222 containing an oxide of either or both aluminum and hafnium. Preferably, the insulator containing an oxide of either or both aluminum and hafnium is an aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). Alternatively, hafnium zirconium oxide is preferred. An insulator containing an oxide of either or both aluminum and hafnium has barrier properties against oxygen, hydrogen, and water. Because the insulator 222 has barrier properties against hydrogen and water, the diffusion of hydrogen and water contained in the structure surrounding the transistor 200 into the transistor 200 through the insulator 222 is suppressed, thereby suppressing the generation of oxygen vacancies in the oxide 230.

[0260] The insulator 222 can be deposited using sputtering, CVD, MBE, PLD, ALD, or the like. In this embodiment, hafnium oxide is deposited as the insulator 222 using the ALD method. In particular, it is preferable to use a method for forming hafnium oxide with reduced hydrogen concentration, which is one aspect of the present invention.

[0261] Next, it is preferable to perform a heat treatment. The heat treatment should be performed at a temperature of 250°C to 650°C, preferably 300°C to 500°C, and more preferably 320°C to 450°C. The heat treatment should be performed in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when performing the heat treatment in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas should be about 20%. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas, and then further in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the desorbed oxygen.

[0262] Furthermore, it is preferable that the gas used in the above heat treatment is highly purified. For example, the amount of water contained in the gas used in the above heat treatment should be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent as much as possible from moisture or other substances being incorporated into the insulator 222 and the like.

[0263] In this embodiment, as a heat treatment, after the insulator 222 is formed, the insulator is treated at a temperature of 400°C for 1 hour with a flow rate ratio of nitrogen gas to oxygen gas of 4:1. This heat treatment can remove impurities such as water and hydrogen contained in the insulator 222. Furthermore, when an oxide containing hafnium is used as the insulator 222, a portion of the insulator 222 may crystallize as a result of this heat treatment. The heat treatment can also be performed at a later time, such as after the formation of the insulator 224.

[0264] Next, an insulating film 224A is deposited on the insulator 222 (see Figures 7A to 7D). The insulating film 224A can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. In this embodiment, silicon oxide is deposited as the insulating film 224A using the sputtering method. By using the sputtering method, which does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulating film 224A can be reduced. Since the insulating film 224A will come into contact with the oxide 230a in a later step, it is preferable that the hydrogen concentration is reduced in this way.

[0265] Next, oxide films 230A and 230B are sequentially deposited on the insulating film 224A (see Figures 7A to 7D). It is preferable to deposit oxide films 230A and 230B continuously without exposing them to the atmosphere. By depositing the films without exposure to the atmosphere, it is possible to prevent impurities or moisture from the atmosphere from adhering to oxide films 230A and 230B, and to keep the vicinity of the interface between oxide films 230A and 230B clean.

[0266] The oxide films 230A and 230B can be deposited using sputtering, CVD, MBE, PLD, ALD, and the like. The ALD method is preferred for depositing oxide films 230A and 230B because it allows for the formation of films with uniform thickness even in grooves or openings with large aspect ratios. The PEALD method is also preferred because it allows for the formation of oxide films 230A and 230B at lower temperatures compared to the thermal ALD method. In this embodiment, the oxide films 230A and 230B are deposited using sputtering.

[0267] For example, when depositing oxide films 230A and 230B by sputtering, oxygen or a mixture of oxygen and a noble gas is used as the sputtering gas. By increasing the proportion of oxygen in the sputtering gas, the excess oxygen in the deposited oxide film can be increased. Furthermore, when depositing the above oxide films by sputtering, the above-mentioned In-M-Zn oxide target can be used.

[0268] In particular, during the formation of the oxide film 230A, some of the oxygen contained in the sputtering gas may be supplied to the insulating film 224A. Therefore, the proportion of oxygen contained in the sputtering gas should be 70% or more, preferably 80% or more, and more preferably 100%.

[0269] Furthermore, when the oxide film 230B is formed by sputtering, if the proportion of oxygen in the sputtering gas is set to be more than 30% but 100% or less, preferably 70% or more but 100%, an oxygen-rich oxide semiconductor is formed. Transistors using an oxygen-rich oxide semiconductor in the channel formation region can achieve relatively high reliability. However, the present invention is not limited to this. When the oxide film 230B is formed by sputtering, if the proportion of oxygen in the sputtering gas is set to be 1% or more but 30% or less, preferably 5% or more but 20%, an oxygen-deficient oxide semiconductor is formed. Transistors using an oxygen-deficient oxide semiconductor in the channel formation region can achieve relatively high field-effect mobility. In addition, the crystallinity of the oxide film can be improved by performing film formation while heating the substrate.

[0270] In this embodiment, oxide film 230A is formed by sputtering using an oxide target with an In:Ga:Zn ratio of 1:3:4. Oxide film 230B is formed by sputtering using an oxide target with an In:Ga:Zn ratio of 4:2:4.1, an In:Ga:Zn ratio of 1:1:1, or an In:Ga:Zn ratio of 1:1:2. Each oxide film can be formed according to the desired properties of oxide 230a and oxide 230b by appropriately selecting the deposition conditions and atomic ratios.

[0271] Furthermore, it is preferable to deposit the insulating film 224A, oxide film 230A, and oxide film 230B by sputtering without exposure to the atmosphere. For example, a multi-chamber type deposition apparatus can be used. This reduces the incorporation of hydrogen into the films between each deposition process for the insulating film 224A, oxide film 230A, and oxide film 230B.

[0272] Next, it is preferable to perform a heat treatment. The heat treatment should be performed within a temperature range in which the oxide films 230A and 230B do not undergo polycrystallization, and should be performed between 250°C and 650°C, preferably between 400°C and 600°C. The heat treatment should be performed in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when performing the heat treatment in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas should be about 20%. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas, and then in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the desorbed oxygen.

[0273] Furthermore, it is preferable that the gas used in the above heat treatment is highly purified. For example, the amount of water contained in the gas used in the above heat treatment should be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent as much as possible from the incorporation of water and other substances into the oxide film 230A and oxide film 230B.

[0274] In this embodiment, the heat treatment involves a nitrogen gas to oxygen gas flow rate ratio of 4:1 and a treatment at a temperature of 400°C for 1 hour. This heat treatment including oxygen gas can reduce impurities such as carbon, water, and hydrogen in oxide films 230A and 230B. By reducing impurities in the films in this way, the crystallinity of oxide film 230B can be improved, resulting in a denser, more compact structure. This increases the crystalline region in oxide films 230A and 230B, and reduces in-plane variation of the crystalline region in oxide films 230A and 230B. Therefore, in-plane variation in the electrical characteristics of transistor 200 can be reduced.

[0275] Furthermore, by performing the heat treatment, hydrogen in the insulator 216, insulating film 224A, oxide film 230A, and oxide film 230B moves to the insulator 222 and is absorbed into the insulator 222. In other words, hydrogen in the insulator 216, insulating film 224A, oxide film 230A, and oxide film 230B diffuses into the insulator 222. Consequently, the hydrogen concentration in the insulator 222 increases, while the hydrogen concentrations in the insulator 216, insulating film 224A, oxide film 230A, and oxide film 230B decrease.

[0276] In particular, the insulating film 224A functions as a gate insulator for the transistor 200, and the oxide films 230A and 230B function as channel formation regions for the transistor 200. Therefore, a transistor 200 having insulating films 224A, oxide films 230A and 230B with reduced hydrogen concentrations is preferred because it has good reliability.

[0277] Next, a conductive film 242A is deposited on the oxide film 230B (see Figures 7A to 7D). The conductive film 242A can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. For example, tantalum nitride can be deposited as the conductive film 242A using sputtering. Before depositing the conductive film 242A, a heat treatment may be performed. This heat treatment may be performed under reduced pressure, and the conductive film 242A may be deposited continuously without exposure to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide film 230B can be removed, and the moisture and hydrogen concentrations in the oxide film 230A and the oxide film 230B can be further reduced. The heat treatment temperature is preferably between 100°C and 400°C. In this embodiment, the heat treatment temperature is set to 200°C.

[0278] Next, an insulating film 271A is deposited on the conductive film 242A (see Figures 7A to 7D). The insulating film 271A can be deposited using sputtering, CVD, MBE, PLD, or ALD. It is preferable to use an insulating film 271A that has the function of suppressing oxygen permeation. For example, aluminum oxide or silicon nitride can be deposited as the insulating film 271A by sputtering.

[0279] Furthermore, it is preferable to deposit the conductive film 242A and the insulating film 271A by sputtering without exposure to the atmosphere. For example, a multi-chamber deposition apparatus can be used. This reduces the amount of hydrogen in the films when depositing the conductive film 242A and the insulating film 271A, and also reduces the amount of hydrogen introduced into the films between each deposition process. In addition, if a hard mask is to be provided on the insulating film 271A, the hard mask film can also be deposited continuously without exposure to the atmosphere.

[0280] Next, the insulating film 224A, oxide film 230A, oxide film 230B, conductive film 242A, and insulating film 271A are processed into island-like structures using lithography to form the insulator 224, oxide 230a, oxide 230b, conductive layer 242B, and insulating layer 271B (see Figures 8A to 8D). Here, the insulator 224, oxide 230a, oxide 230b, conductive layer 242B, and insulating layer 271B are formed so that at least a portion of them overlaps with the conductor 205. The above processing can be performed using either dry etching or wet etching. Dry etching is suitable for microfabrication. Furthermore, the processing of the insulating film 224A, oxide film 230A, oxide film 230B, conductive film 242A, and insulating film 271A may be carried out under different conditions.

[0281] In lithography, the resist is first exposed through a mask. Next, the exposed area is removed or left intact using a developer to form a resist mask. Then, the conductor, semiconductor, or insulator can be processed into a desired shape by etching through the resist mask. For example, the resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, or EUV (Extreme Ultraviolet) light. Alternatively, immersion technology can be used, where a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. In addition, an electron beam or ion beam may be used instead of the aforementioned light. When using an electron beam or ion beam, a mask is not required. The resist mask can be removed by dry etching such as ashing, wet etching, dry etching followed by wet etching, or wet etching followed by dry etching.

[0282] Furthermore, a hard mask made of an insulator or conductor may be used beneath the resist mask. When using a hard mask, an insulating film or conductive film that serves as the hard mask material is formed on the conductive film 242A, a resist mask is formed on top of it, and a hard mask of the desired shape can be formed by etching the hard mask material. Etching of the conductive film 242A, etc., may be performed after removing the resist mask, or it may be performed while the resist mask remains. In the latter case, the resist mask may disappear during etching. The hard mask may also be removed by etching after etching of the conductive film 242A, etc. On the other hand, if the hard mask material does not affect subsequent processes or can be used in subsequent processes, it is not always necessary to remove the hard mask. In this embodiment, an insulating layer 271B is used as the hard mask.

[0283] Here, since the insulating layer 271B functions as a mask for the conductive layer 242B, the conductive layer 242B does not have a curved surface between its side and top surfaces, as shown in Figures 8B to 8D. As a result, the conductors 242a and 242b shown in Figures 1B and 1D have angular ends where their side and top surfaces intersect. Because the ends where the side and top surfaces of the conductor 242 intersect are angular, the cross-sectional area of ​​the conductor 242 is larger compared to when the ends have a curved surface. As a result, the resistance of the conductor 242 is reduced, and the on-current of the transistor 200 can be increased.

[0284] Furthermore, as shown in Figures 8B to 8D, the sides of the insulator 224, oxide 230a, oxide 230b, conductive layer 242B, and insulating layer 271B may be tapered. In this specification, a tapered shape refers to a shape in which at least a part of the side surface of the structure is inclined with respect to the substrate surface. For example, it is preferable that the angle between the inclined side surface and the substrate surface (hereinafter sometimes referred to as the taper angle) is less than 90°. For example, the insulator 224, oxide 230a, oxide 230b, conductive layer 242B, and insulating layer 271B may have a taper angle of 60° or more and less than 90°. By making the sides tapered in this way, the coverage of the insulator 275 and other materials can be improved in subsequent processes, and defects such as porosity can be reduced.

[0285] However, the above is not limited to the above, and the sides of the insulator 224, oxide 230a, oxide 230b, conductive layer 242B, and insulating layer 271B may be configured to be approximately perpendicular to the upper surface of the insulator 222. Such a configuration makes it possible to reduce the area and increase the density when providing multiple transistors 200.

[0286] Furthermore, by-products generated during the etching process may form in layers on the sides of the insulator 224, oxide 230a, oxide 230b, conductive layer 242B, and insulating layer 271B. In this case, the layered by-products will be formed between the insulator 224, oxide 230a, oxide 230b, conductive layer 242B, and insulating layer 271B and the insulator 275. Therefore, it is preferable to remove the layered by-products formed in contact with the upper surface of the insulator 222.

[0287] Next, an insulator 275 is formed by covering the insulator 224, oxide 230a, oxide 230b, conductive layer 242B, and insulating layer 271B (see Figures 9A to 9D). Here, it is preferable that the insulator 275 is in close contact with the upper surface of the insulator 222 and the side surface of the insulator 224. The insulator 275 can be formed using sputtering, CVD, MBE, PLD, ALD, etc. It is preferable that the insulator 275 is an insulating film that has the function of suppressing oxygen permeation. For example, as the insulator 275, aluminum oxide can be formed using the sputtering method, and silicon nitride can be formed on top of it using the PEALD method. By making the insulator 275 such a layered structure, the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen may be improved.

[0288] In this way, oxide 230a, oxide 230b, and conductive layer 242B can be covered with insulator 275 and insulating layer 271B, which have the function of suppressing oxygen diffusion. This reduces the direct diffusion of oxygen from insulator 280, etc., to insulator 224, oxide 230a, oxide 230b, and conductive layer 242B in subsequent processes.

[0289] Next, an insulating film, which will become an insulating film 280, is deposited on the insulator 275. The insulating film can be deposited using sputtering, CVD, MBE, PLD, ALD, or the like. For example, a silicon oxide film can be deposited as the insulating film using sputtering. By depositing the insulating film using sputtering in an oxygen-containing atmosphere, an insulating film 280 containing excess oxygen can be formed. Furthermore, by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulating film 280 can be reduced. Note that a heat treatment may be performed before depositing the insulating film. The heat treatment may be performed under reduced pressure, and the insulating film may be deposited continuously without exposure to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the insulating film 275 can be removed, and the moisture and hydrogen concentrations in the oxide 230a, oxide 230b, and insulating film 224 can be further reduced. The heat treatment conditions described above can be used for this heat treatment.

[0290] Next, the insulating film that will become the insulator 280 is subjected to CMP treatment to form an insulator 280 with a flat top surface (see Figures 9A to 9D). Alternatively, silicon nitride may be deposited on the insulator 280 by, for example, a sputtering method, and the silicon nitride may be subjected to CMP treatment until it reaches the insulator 280.

[0291] Next, a portion of the insulator 280, a portion of the insulator 275, a portion of the insulating layer 271B, and a portion of the conductive layer 242B are processed to form an opening that reaches the oxide 230b. Preferably, the opening is formed so as to overlap with the conductor 205. The formation of the opening creates the insulator 271a, the insulator 271b, the conductor 242a, and the conductor 242b (see Figures 10A to 10D).

[0292] Here, as shown in Figures 10B and 10C, the sides of the insulators 280, 275, 271, and conductor 242 may be tapered. Also, the taper angle of the insulator 280 may be larger than the taper angle of the conductor 242. In addition, although not shown in Figures 10A to 10C, the upper part of the oxide 230b may be removed when forming the above-mentioned opening.

[0293] Furthermore, the processing of a portion of the insulator 280, a portion of the insulator 275, a portion of the insulating layer 271B, and a portion of the conductive layer 242B can be carried out using either a dry etching method or a wet etching method. Dry etching is suitable for microfabrication. Moreover, these processing methods may be carried out under different conditions. For example, a portion of the insulator 280 may be processed by dry etching, a portion of the insulator 275 and a portion of the insulating layer 271B may be processed by wet etching, and a portion of the conductive layer 242B may be processed by dry etching.

[0294] Here, impurities may adhere to the sides of oxide 230a, the top and sides of oxide 230b, the sides of conductor 242, the sides of insulator 280, etc., or diffuse into these surfaces. A step to remove such impurities may be performed. In addition, a damaged area may be formed on the surface of oxide 230b during the dry etching process. Such a damaged area may be removed. Examples of such impurities include those resulting from components contained in insulator 280, insulator 275, a part of insulating layer 271B, and conductive layer 242B, components contained in materials used in the apparatus used to form the opening, and components contained in the gas or liquid used for etching. Examples of such impurities include hafnium, aluminum, silicon, tantalum, fluorine, and chlorine.

[0295] In particular, impurities such as aluminum and silicon may reduce the crystallinity of oxide 230b. Therefore, it is preferable to remove impurities such as aluminum and silicon from the surface of oxide 230b and its vicinity. Furthermore, it is preferable to reduce the concentration of such impurities. For example, the concentration of aluminum atoms on the surface of oxide 230b and its vicinity should be 5.0 atomic% or less, preferably 2.0 atomic% or less, more preferably 1.5 atomic% or less, even more preferably 1.0 atomic% or less, and even more preferably less than 0.3 atomic%.

[0296] Furthermore, due to impurities such as aluminum and silicon, the crystallinity of oxide 230b is low in certain regions, and therefore, V O A large amount of H is formed, making it easier for the transistor to become normally-on. Therefore, it is preferable that regions with low crystallinity of oxide 230b are reduced or removed.

[0297] In contrast, it is preferable that the oxide 230b has a layered CAAC structure. In particular, it is preferable that the CAAC structure extends to the lower end of the drain of the oxide 230b. Here, in the transistor 200, the conductor 242a or conductor 242b, and its vicinity, function as a drain. That is, it is preferable that the oxide 230b near the lower end of the conductor 242a (conductor 242b) has a CAAC structure. In this way, even at the drain end, which significantly affects the drain breakdown voltage, the region of low crystallinity of the oxide 230b is removed and a CAAC structure is present, which further suppresses fluctuations in the electrical characteristics of the transistor 200. Furthermore, the reliability of the transistor 200 can be improved.

[0298] In order to remove impurities and other contaminants adhering to the oxide 230b surface during the etching process described above, a cleaning treatment is performed. Cleaning methods include wet cleaning using a cleaning solution (which can also be called wet etching), plasma treatment using plasma, and heat treatment. These cleaning methods may be combined as appropriate. Note that this cleaning treatment may deepen the grooves.

[0299] Wet cleaning may be performed using aqueous solutions of ammonia water, oxalic acid, phosphoric acid, hydrofluoric acid, etc., diluted with carbonated water or distilled water, distilled water, carbonated water, etc. Alternatively, ultrasonic cleaning may be performed using these aqueous solutions, distilled water, or carbonated water. Alternatively, these cleaning methods may be combined as appropriate.

[0300] In this specification, an aqueous solution obtained by diluting hydrofluoric acid with pure water is sometimes referred to as diluted hydrofluoric acid, and an aqueous solution obtained by diluting ammonia water with pure water is sometimes referred to as diluted ammonia water. The concentration and temperature of the aqueous solution may be adjusted as appropriate depending on the impurities to be removed and the configuration of the semiconductor device to be cleaned. The ammonia concentration of the diluted ammonia water should be 0.01% to 5%, preferably 0.1% to 0.5%. The hydrogen fluoride concentration of the diluted hydrofluoric acid should be 0.01 ppm to 100 ppm, preferably 0.1 ppm to 10 ppm.

[0301] For ultrasonic cleaning, a frequency of 200 kHz or higher is preferable, and a frequency of 900 kHz or higher is even more preferable. Using this frequency can reduce damage to oxides such as 230b.

[0302] Furthermore, the above cleaning process may be performed multiple times, and the cleaning solution may be changed each time. For example, the first cleaning process may be performed using diluted hydrofluoric acid or diluted ammonia water, and the second cleaning process may be performed using pure water or carbonated water.

[0303] In this embodiment, the cleaning process described above involves wet cleaning using diluted ammonia water. This cleaning process removes impurities that have adhered to the surface or diffused into the interior, such as oxide 230a and oxide 230b. Furthermore, it can improve the crystallinity of oxide 230b.

[0304] Heat treatment may be performed after the etching or cleaning described above. The heat treatment should be performed at a temperature of 100°C to 450°C, preferably 350°C to 400°C. The heat treatment should be performed in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, it is preferable to perform the heat treatment in an oxygen atmosphere. This allows oxygen to be supplied to oxides 230a and 230b, thereby reducing oxygen deficiency. Furthermore, such heat treatment can improve the crystallinity of oxide 230b. The heat treatment may also be performed under reduced pressure. Alternatively, after heat treatment in an oxygen atmosphere, continuous heat treatment in a nitrogen atmosphere may be performed without exposure to the atmosphere.

[0305] Next, the insulating film 252A is deposited (see Figures 11A to 11D). The insulating film 252A can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. It is preferable to deposit the insulating film 252A using the ALD method. As mentioned above, it is preferable to deposit the insulating film 252A with a thin film thickness, and it is necessary to minimize variations in film thickness. In contrast, the ALD method is a film deposition method that alternately introduces a precursor and a reactant (e.g., an oxidizing agent), and the film thickness can be adjusted by the number of times this cycle is repeated, thus enabling precise film thickness adjustment. Also, as shown in Figures 11B and 11C, the insulating film 252A needs to be deposited with good coverage on the bottom and side surfaces of openings formed in the insulator 280, etc. In particular, it is preferable to deposit it with good coverage on the top and side surfaces of the oxide 230 and the side surfaces of the conductor 242. Since atomic layers can be deposited one by one on the bottom and side surfaces of the opening, the insulating film 252A can be formed on the opening with good coverage.

[0306] Furthermore, when the insulating film 252A is deposited by the ALD method, ozone (O3), oxygen (O2), water (H2O), etc., can be used as oxidizing agents. By using hydrogen-free oxidizing agents such as ozone (O3) and oxygen (O2), the amount of hydrogen diffusing into the oxide 230b can be reduced.

[0307] In this embodiment, aluminum oxide is deposited as the insulating film 252A by thermal ALD method.

[0308] Next, it is preferable to perform microwave processing in an oxygen-containing atmosphere (see Figures 11A to 11D). Here, microwave processing refers to processing using a device that has a power supply that generates high-density plasma using microwaves, for example. In this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less.

[0309] As shown in Figures 11B to 11D, the dotted lines represent microwaves, high frequencies such as RF, oxygen plasma, or oxygen radicals. For microwave processing, it is preferable to use a microwave processing apparatus that has a power supply for generating high-density plasma using microwaves. Here, the frequency of the microwave processing apparatus should be 300 MHz or more and 300 GHz or less, preferably 2.4 GHz or more and 2.5 GHz or less, for example, 2.45 GHz. By using high-density plasma, high-density oxygen radicals can be generated. The power of the power supply for applying microwaves to the microwave processing apparatus should be 1000 W or more and 10000 W or less, preferably 2000 W or more and 5000 W or less. The microwave processing apparatus may also have a power supply for applying RF to the substrate side. Furthermore, by applying RF to the substrate side, oxygen ions generated by the high-density plasma can be efficiently guided into the oxide 230b.

[0310] Furthermore, the above microwave treatment is preferably performed under reduced pressure, with a pressure of 10 Pa to 1000 Pa, preferably 300 Pa to 700 Pa. The treatment temperature should be 750°C or lower, preferably 500°C or lower, for example, around 400°C. Alternatively, after oxygen plasma treatment, heat treatment may be performed continuously without exposure to the outside air. For example, heat treatment may be performed at 100°C to 750°C, preferably 300°C to 500°C.

[0311] Furthermore, for example, the above microwave treatment may be carried out using oxygen gas and argon gas. Here, the oxygen flow rate ratio (O2 / (O2+Ar)) should be greater than 0% and 100% or less. Preferably, the oxygen flow rate ratio (O2 / (O2+Ar)) should be greater than 0% and 50% or less. More preferably, the oxygen flow rate ratio (O2 / (O2+Ar)) should be 10% or more and 40% or less. Even more preferably, the oxygen flow rate ratio (O2 / (O2+Ar)) should be 10% or more and 30% or less. In this way, by performing microwave treatment in an oxygen-containing atmosphere, the carrier concentration in region 230bc can be reduced. In addition, by preventing an excessive amount of oxygen from being introduced into the chamber during microwave treatment, it is possible to prevent an excessive decrease in carrier concentration in regions 230ba and 230bb.

[0312] As shown in Figures 11B to 11D, by performing microwave treatment in an oxygen-containing atmosphere, the oxygen gas can be plasma-generated using microwaves or high-frequency waves such as RF, and this oxygen plasma can be applied to the region between the conductors 242a and 242b of the oxide 230b. At this time, microwaves or high-frequency waves such as RF can also be irradiated onto region 230bc. In other words, microwaves or high-frequency waves such as RF, oxygen plasma, etc., can be applied to region 230bc shown in Figure 2A. Due to the action of plasma, microwaves, etc., the V of region 230bc O By cleaving H, hydrogen can be removed from region 230bc. In other words, V contained in region 230bc O H can be reduced. Therefore, oxygen deficiency and V in region 230bc are reduced. O By reducing H, the carrier concentration can be lowered. Furthermore, by supplying oxygen radicals generated in the oxygen plasma or oxygen contained in the insulator 250 to the oxygen vacancy formed in region 230bc, the oxygen vacancy in region 230bc can be further reduced, and the carrier concentration can be lowered.

[0313] Meanwhile, conductors 242a and 242b are provided on regions 230ba and 230bb shown in Figure 2A. Here, it is preferable that the conductor 242 functions as a shielding film against the effects of microwaves, high frequencies such as RF, and oxygen plasma when microwave processing is performed in an oxygen-containing atmosphere. For this reason, it is preferable that the conductor 242 has the function of shielding electromagnetic waves between 300 MHz and 300 GHz, for example, between 2.4 GHz and 2.5 GHz.

[0314] As shown in Figures 11B to 11D, conductors 242a and 242b shield against microwaves, high-frequency waves such as RF, and oxygen plasma, so these effects do not extend to regions 230ba and 230bb. As a result, microwave processing does not affect regions 230ba and 230bb. O This reduces H and prevents excessive oxygen supply, thus preventing a decrease in carrier concentration.

[0315] Furthermore, an insulator 252 having barrier properties against oxygen is provided in contact with the sides of the conductors 242a and 242b. This suppresses the formation of oxide films on the sides of the conductors 242a and 242b due to microwave processing.

[0316] Furthermore, since the film quality of the insulator 252 can be improved, the reliability of the transistor 200 is enhanced.

[0317] As described above, oxygen vacancies and V can be selectively generated in the oxide semiconductor region 230bc. O By removing H, region 230bc can be made i-type or substantially i-type. Furthermore, it is possible to suppress the supply of excess oxygen to regions 230ba and 230bb, which function as source or drain regions, and maintain the state of the n-type region before microwave processing. This suppresses variations in the electrical properties of transistor 200 and prevents variations in the electrical properties of transistor 200 within the substrate plane.

[0318] In microwave processing, electromagnetic interaction between microwaves and molecules in oxide 230b can directly transfer thermal energy to oxide 230b. This thermal energy can cause oxide 230b to heat up. This type of heat treatment is sometimes called microwave annealing. Performing microwave processing in an oxygen-containing atmosphere can sometimes achieve effects equivalent to oxygen annealing. Furthermore, if oxide 230b contains hydrogen, this thermal energy may be transferred to the hydrogen in oxide 230b, causing activated hydrogen to be released from oxide 230b.

[0319] Next, an insulating film 250A is deposited (see Figures 12A to 12D). A heat treatment may be performed before depositing the insulating film 250A, and this heat treatment may be carried out under reduced pressure, allowing for continuous deposition of the insulating film 250A without exposure to the atmosphere. Furthermore, it is preferable to carry out this heat treatment in an atmosphere containing oxygen. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the insulating film 252A can be removed, and the moisture and hydrogen concentrations in oxides 230a and 230b can be further reduced. The temperature of the heat treatment is preferably between 100°C and 400°C.

[0320] The insulating film 250A can be deposited using methods such as sputtering, CVD, PECVD, MBE, PLD, and ALD. Furthermore, it is preferable to deposit the insulating film 250A using a deposition method that utilizes a gas with reduced or removed hydrogen atoms. This reduces the hydrogen concentration of the insulating film 250A. Since the insulating film 250A will later become an insulator 250 facing the oxide 230b via a thin insulating film 252, it is preferable that the hydrogen concentration is reduced in this manner.

[0321] In this embodiment, silicon oxidnitride is used as the insulating film 250A and deposited by the PECVD method.

[0322] Furthermore, when the insulator 250 is made into a two-layer laminated structure as shown in Figure 2B, the insulating film that will become the insulator 250b should be deposited after the insulating film 250A has been deposited. The insulating film that will become the insulator 250b can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. It is preferable that the insulating film that will become the insulator 250b be formed using an insulator that has the function of suppressing the diffusion of oxygen. With such a configuration, the diffusion of oxygen contained in the insulator 250a to the conductor 260 can be suppressed. In other words, the decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. In addition, oxidation of the conductor 260 by oxygen contained in the insulator 250a can be suppressed. The insulating film that will become the insulator 250b can be made using the same material as the insulator 222. For example, hafnium oxide can be deposited as the insulating film that will become the insulator 250b by thermal ALD.

[0323] Microwave treatment may be performed after the deposition of the insulating film 250A (see Figures 12A to 12D). The microwave treatment may use the same microwave treatment conditions as those used after the deposition of the insulating film 252A. Alternatively, the microwave treatment may be performed after the deposition of the insulating film 250A without performing the microwave treatment after the deposition of the insulating film 252A. Furthermore, if an insulating film that will become an insulator 250b is provided as described above, microwave treatment may be performed after the deposition of the insulating film that will become the insulator 250b. The microwave treatment may use the same microwave treatment conditions as those used after the deposition of the insulating film 252A. Alternatively, the microwave treatment may be performed after the deposition of the insulating film that will become the insulator 250b without performing the microwave treatment after the deposition of either the insulating film 252A or the insulating film 250A.

[0324] Furthermore, after the deposition of insulating film 252A and insulating film 250A, and after the deposition of the insulating film that will become insulator 250b, a heat treatment may be performed while maintaining a reduced pressure state. By performing such a treatment, hydrogen can be efficiently removed from insulating film 252A, insulating film 250A, insulating film that will become insulator 250b, oxide 230b, and oxide 230a. In addition, some of the hydrogen may be gettered into the conductor 242 (conductor 242a and conductor 242b). Alternatively, the step of performing a heat treatment while maintaining a reduced pressure state after microwave treatment may be repeated multiple times. By repeating the heat treatment, hydrogen can be removed even more efficiently from insulating film 252A, insulating film 250A, insulating film that will become insulator 250b, oxide 230b, and oxide 230a. The heat treatment temperature is preferably 300°C to 500°C. Furthermore, the above-mentioned microwave treatment, i.e., microwave annealing, may also serve as the heat treatment. If the oxide 230b, etc., is sufficiently heated by microwave annealing, the heat treatment may not be necessary.

[0325] Furthermore, by performing microwave treatment to modify the film quality of the insulating film 252A, insulating film 250A, and insulating film 250b, the diffusion of hydrogen, water, impurities, etc. can be suppressed. Therefore, in subsequent processes such as deposition of a conductive film that becomes the conductor 260, or post-treatment such as heat treatment, the diffusion of hydrogen, water, impurities, etc., to oxides 230b, oxides 230a, etc., via the insulating film 252 can be suppressed.

[0326] Next, the insulating film 254A is deposited (see Figures 13A to 13D). The insulating film 254A can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. It is preferable to deposit the insulating film 254A using the ALD method, similar to the insulating film 252A. By depositing the film using the ALD method, the insulating film 254A can be deposited with a thin film thickness and good coverage. In this embodiment, silicon nitride is deposited as the insulating film 254A using the PEALD method.

[0327] Next, a conductive film to become conductor 260a and a conductive film to become conductor 260b are deposited in sequence. The conductive films to become conductor 260a and conductor 260b can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. In this embodiment, titanium nitride is deposited as the conductive film to become conductor 260a using the ALD method, and tungsten is deposited as the conductive film to become conductor 260b using the CVD method.

[0328] Next, by CMP treatment, insulating films 252A, 250A, 254A, the conductive film that will become conductor 260a, and the conductive film that will become conductor 260b are polished until the insulator 280 is exposed, thereby forming insulators 252, 250, 254, and conductor 260 (conductors 260a and 260b) (see Figures 14A to 14D). As a result, insulator 252 is positioned to cover the opening that reaches oxide 230b. Conductor 260 is positioned to fill the opening via insulators 252, 250, and 254.

[0329] Next, a heat treatment may be performed under the same conditions as the heat treatment described above. In this embodiment, the treatment is performed at a temperature of 400°C for 1 hour in a nitrogen atmosphere. This heat treatment can reduce the moisture concentration and hydrogen concentration in the insulator 250 and insulator 280. After the heat treatment, the insulator 282 may be deposited continuously without exposure to the atmosphere.

[0330] Next, insulators 282 are formed on insulators 252, 250, 254, 260, and 280 (see Figures 14A to 14D). The insulator 282 can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. It is preferable to deposit the insulator 282 using sputtering. By using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulator 282 can be reduced.

[0331] In this embodiment, aluminum oxide is deposited as the insulator 282 using a pulsed DC sputtering method with an aluminum target in an atmosphere containing oxygen gas. By using the pulsed DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved.

[0332] Furthermore, by using the sputtering method to deposit the insulator 282 in an oxygen-containing atmosphere, oxygen can be added to the insulator 280 during film formation. This allows the insulator 280 to contain excess oxygen. In this case, it is preferable to deposit the insulator 282 while heating the substrate.

[0333] Next, an etching mask is formed on the insulator 282 by lithography, and a portion of the insulator 282, a portion of the insulator 280, a portion of the insulator 275, a portion of the insulator 222, and a portion of the insulator 216 are processed until the upper surface of the insulator 214 is exposed (see Figures 15A to 15D). This processing may be done using wet etching, but dry etching is preferable for fine processing.

[0334] Next, a heat treatment may be performed. The heat treatment should be performed at a temperature of 250°C to 650°C, preferably 350°C to 600°C. Furthermore, it is preferable that this heat treatment temperature is lower than the heat treatment temperature performed after the formation of the oxide film 230B. The heat treatment should be performed in an atmosphere of nitrogen gas or an inert gas. By performing this heat treatment, some of the oxygen added to the insulator 280 diffuses into the oxide 230 via the insulator 250, etc.

[0335] Furthermore, by performing this heat treatment, oxygen contained in insulator 280 and hydrogen combined with that oxygen can be released to the outside from the side surface of insulator 280, which was formed by processing insulators 282, 280, 275, 222, and 216. The hydrogen combined with oxygen is released as water. Therefore, the amount of unwanted oxygen and hydrogen contained in insulator 280 can be reduced.

[0336] Furthermore, an insulator 252 is provided in contact with the upper and side surfaces of the oxide 230 in the region where the oxide 230 overlaps with the conductor 260. Since the insulator 252 has an oxygen barrier property, it can reduce the diffusion of excess oxygen into the oxide 230. This allows oxygen to be supplied in such a way that excess oxygen is not supplied to region 230bc and its vicinity. This suppresses oxidation of the side surfaces of the conductor 242 by excess oxygen, while preventing oxygen deficiencies and V2 formation in region 230bc. O H can be reduced. Therefore, the electrical characteristics of transistor 200 can be improved, and its reliability can be enhanced.

[0337] On the other hand, when transistors 200 are densely integrated, the volume of insulator 280 per transistor 200 may become excessively small. In this case, the amount of oxygen diffused into the oxide 230 during the heat treatment described above becomes significantly smaller. When the oxide 230 is heated while in contact with an oxide insulator that does not contain sufficient oxygen (for example, insulator 250), there is a risk that the oxygen constituting the oxide 230 will be desorbed. However, in the transistor 200 shown in this embodiment, an insulator 252 is provided in contact with the upper and side surfaces of the oxide 230 in the region that overlaps with the conductor 260 of the oxide 230. Since the insulator 252 has barrier properties against oxygen, the desorption of oxygen from the oxide 230 can be reduced even during the heat treatment described above. As a result, oxygen deficiencies and V are formed in region 230bc. O H can be reduced. Therefore, the electrical characteristics of transistor 200 can be improved, and its reliability can be enhanced.

[0338] As described above, in the semiconductor device according to this embodiment, a transistor with good electrical characteristics and good reliability can be formed whether the amount of oxygen supplied from the insulator 280 is high or low. Therefore, a semiconductor device is provided that suppresses variations in the electrical characteristics of the transistor 200 within the substrate surface.

[0339] Next, an insulator 283 is formed on the insulator 282 (see Figures 16A to 16D). The insulator 283 can be deposited using sputtering, CVD, MBE, PLD, or ALD. It is preferable to deposit the insulator 283 using sputtering. By using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulator 283 can be reduced. The insulator 283 may also be multilayered. For example, silicon nitride may be deposited using sputtering, and then silicon nitride may be deposited on the silicon nitride using the ALD method. By encasing the transistor 200 with the highly barrier insulators 283 and 214, moisture and hydrogen can be prevented from entering from the outside.

[0340] Next, an insulator 274 is formed on the insulator 283. The insulator 274 can be deposited using sputtering, CVD, MBE, PLD, or ALD. In this embodiment, silicon oxide is deposited as the insulator 274 by the CVD method.

[0341] Next, the upper surface of the insulator 274 is flattened by polishing it using CMP (see Figures 16A to 16D) until the insulator 283 is exposed. This CMP process may remove a portion of the upper surface of the insulator 283.

[0342] Next, an insulator 285 is formed on the insulator 274 and the insulator 283 (see Figures 17A to 17D). The insulator 285 can be deposited using sputtering, CVD, MBE, PLD, or ALD. It is preferable to deposit the insulator 285 using sputtering. By using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulator 285 can be reduced.

[0343] In this embodiment, silicon oxide is deposited as the insulator 285 by sputtering.

[0344] Next, openings reaching the conductor 242 are formed in insulators 271, 275, 280, 282, 283, and 285 (see Figures 17A and 17B). These openings can be formed using lithography. In Figure 17A, the shape of the opening is circular in a top view, but it is not limited to this. For example, the opening may be approximately circular, such as an ellipse, polygonal, such as a quadrilateral, or a polygonal shape with rounded corners in a top view.

[0345] Next, an insulating film to form the insulator 241 is deposited, and the insulating film is anisotropically etched to form the insulator 241 (see Figure 17B). The insulating film can be deposited using sputtering, CVD, MBE, PLD, or ALD. It is preferable to use an insulating film that has the function of suppressing oxygen permeation. For example, it is preferable to deposit aluminum oxide using the ALD method, and then deposit silicon nitride on top of it using the PEALD method. Silicon nitride is preferred because it has high blocking properties for hydrogen.

[0346] Furthermore, for the anisotropic etching of the insulating film that will become the insulator 241, a dry etching method, for example, can be used. By providing the insulator 241 on the side walls of the opening, the permeation of oxygen from the outside can be suppressed, and oxidation of the conductors 240a and 240b that will be formed next can be prevented. In addition, impurities such as water and hydrogen contained in the insulator 280 can be prevented from diffusing into the conductors 240a and 240b.

[0347] Next, conductive films that will become conductor 240a and conductor 240b are formed. It is desirable that the conductive films have a laminated structure that includes a conductor that has the function of suppressing the permeation of impurities such as water and hydrogen. For example, it can be a laminate of tantalum nitride, titanium nitride, etc., and tungsten, molybdenum, copper, etc. The conductive films can be formed using sputtering, CVD, MBE, PLD, or ALD methods.

[0348] Next, by performing a CMP (Chemical Polishing) treatment, a portion of the conductive film that will become conductors 240a and 240b is removed, exposing the upper surface of the insulator 285. As a result, the conductive film remains only in the openings, making it possible to form conductors 240a and 240b with flat upper surfaces (see Figures 17A to 17D). Note that this CMP treatment may remove a portion of the upper surface of the insulator 285.

[0349] Next, a conductive film to form the conductor 246 is deposited. This conductive film can be deposited using methods such as sputtering, CVD, MBE, PLD, or ALD.

[0350] Next, a conductive film to become the conductor 246 is processed by lithography to form a conductor 246a that contacts the upper surface of the conductor 240a, and a conductor 246b that contacts the upper surface of the conductor 240b. At this time, a portion of the insulator 285 in the region where the conductors 246a and 246b do not overlap with the insulator 285 may be removed.

[0351] Based on the above, a semiconductor device having the transistor 200 shown in Figures 1A to 1D can be fabricated. As shown in Figures 6A to 17D, the transistor 200 can be fabricated using the semiconductor device fabrication method shown in this embodiment.

[0352] <Microwave Processing Equipment> The following describes a microwave processing apparatus that can be used in the manufacturing method of the semiconductor device described above.

[0353] First, we will explain the configuration of a manufacturing equipment that minimizes the inclusion of impurities during the manufacturing of semiconductor devices and other equipment, using Figures 18 to 21.

[0354] Figure 18 schematically shows a top view of a single-wafer multi-chamber manufacturing apparatus 2700. The manufacturing apparatus 2700 includes an atmospheric substrate supply chamber 2701 equipped with a cassette port 2761 for housing substrates and an alignment port 2762 for aligning substrates; an atmospheric substrate transport chamber 2702 for transporting substrates from the atmospheric substrate supply chamber 2701; a load lock chamber 2703a for loading substrates and switching the pressure inside the chamber from atmospheric pressure to reduced pressure or from reduced pressure to atmospheric pressure; an unload lock chamber 2703b for unloading substrates and switching the pressure inside the chamber from reduced pressure to atmospheric pressure or from atmospheric pressure to reduced pressure; a transport chamber 2704 for transporting substrates in a vacuum; and chambers 2706a, 2706b, 2706c, and 2706d.

[0355] Furthermore, the atmospheric substrate transport chamber 2702 is connected to the load lock chamber 2703a and the unload lock chamber 2703b, the load lock chamber 2703a and the unload lock chamber 2703b are connected to the transport chamber 2704, and the transport chamber 2704 is connected to chambers 2706a, 2706b, 2706c, and 2706d.

[0356] Furthermore, gate valves GV are provided at the connection points of each chamber, and each chamber can be independently maintained in a vacuum state, except for the atmospheric substrate supply chamber 2701 and the atmospheric substrate transport chamber 2702. In addition, a transport robot 2763a is provided in the atmospheric substrate transport chamber 2702, and a transport robot 2763b is provided in the transport chamber 2704. Transport robots 2763a and 2763b can transport substrates within the manufacturing apparatus 2700.

[0357] The back pressure (total pressure) in the transport chamber 2704 and each chamber is, for example, 1 × 10⁻⁶ -4 Pa or less, preferably 3 × 10 -5 Pa or less, more preferably 1 × 10⁻⁶ -5 The pressure shall be less than or equal to Pa. Furthermore, the partial pressure of gas molecules (atoms) with a mass-to-charge ratio (m / z) of 18 in the transport chamber 2704 and each chamber shall be, for example, 3 × 10⁻⁶. -5Below Pa, preferably 1×10 -5 Below Pa, more preferably 3×10 -6 Below Pa. Also, the partial pressure of gas molecules (atoms) with m / z = 28 in the transfer chamber 2704 and each chamber is, for example, 3×10 -5 Below Pa, preferably 1×10 -5 Below Pa, more preferably 3×10 -6 Below Pa. Also, the partial pressure of gas molecules (atoms) with m / z = 44 in the transfer chamber 2704 and each chamber is, for example, 3×10 -5 Below Pa, preferably 1×10 -5 Below Pa, more preferably 3×10 -6 Below Pa.

[0358] Note that the total pressure and partial pressure in the transfer chamber 2704 and each chamber can be measured using an ionization vacuum gauge, a mass spectrometer, etc.

[0359] Also, the transfer chamber 2704 and each chamber are preferably configured to have little external leakage or internal leakage. For example, the leak rate of the transfer chamber 2704 is 1×10 0 Below Pa / min, preferably 5×10 -1 Below Pa / min. Also, the leak rate of each chamber is 1×10 -1 Below Pa / min, preferably 5×10 -2 Below Pa / min.

[0360] Note that the leak rate can be derived from the total pressure and partial pressure measured using an ionization vacuum gauge, a mass spectrometer, etc. For example, it may be derived from the total pressure 10 minutes after starting evacuation with a vacuum pump such as a turbomolecular pump and the total pressure 10 minutes after closing the valve. Note that the total pressure 10 minutes after starting the above evacuation is preferably the average value when the total pressure is measured multiple times. <00,01315> The leak rate depends on both external and internal leaks. External leaks occur when gas enters from outside the vacuum system due to tiny holes, faulty seals, etc. Internal leaks are caused by leaks from valves or other partitions within the vacuum system, or by the release of gas from internal components. To keep the leak rate below the aforementioned values, countermeasures must be taken from both external and internal leaks.

[0362] For example, the opening and closing parts of the conveying chamber 2704 and each chamber may be sealed with metal gaskets. Preferably, the metal gaskets are made of metal coated with iron fluoride, aluminum oxide, or chromium oxide. Metal gaskets offer better adhesion than O-rings, reducing external leakage. Furthermore, using a passivated metal coated with iron fluoride, aluminum oxide, or chromium oxide suppresses the release of impurity-containing gases from the metal gasket, thereby reducing internal leakage.

[0363] Furthermore, aluminum, chromium, titanium, zirconium, nickel, or vanadium, which emit less impurity-containing gas, are used as components of the manufacturing apparatus 2700. Alternatively, the aforementioned metals that emit less impurity-containing gas may be used as a coating on an alloy containing iron, chromium, and nickel. Alloys containing iron, chromium, and nickel are rigid, heat-resistant, and suitable for processing. Here, reducing the surface area by reducing surface irregularities of the components through polishing or other means can reduce the emission of gas.

[0364] Alternatively, the components of the aforementioned manufacturing apparatus 2700 may be coated with iron fluoride, aluminum oxide, chromium oxide, or the like.

[0365] The components of the manufacturing apparatus 2700 are preferably made of metal as much as possible. For example, when installing viewing windows made of quartz or the like, it is advisable to thinly coat the surface with iron fluoride, aluminum oxide, chromium oxide, etc., to suppress the release of gases.

[0366] The adsorbed substances present in the transport chamber 2704 and each chamber do not affect the pressure in the transport chamber 2704 and each chamber because they are adsorbed onto the inner walls, but they cause gas release when the transport chamber 2704 and each chamber are evacuated. Therefore, although there is no correlation between the leak rate and the exhaust rate, it is important to use a pump with high exhaust capacity to desorb as much of the adsorbed substances present in the transport chamber 2704 and each chamber as possible and evacuate them in advance. In addition, the transport chamber 2704 and each chamber may be baked to promote the desorption of adsorbed substances. Baking can increase the desorption rate of adsorbed substances by about 10 times. Baking should be performed at a temperature between 100°C and 450°C. At this time, if the adsorbed substances are removed while introducing an inert gas into the transport chamber 2704 and each chamber, the desorption rate of water and other substances that are difficult to desorb by exhaust alone can be further increased. In addition, the desorption rate of adsorbed substances can be further increased by heating the introduced inert gas to approximately the same temperature as the baking temperature. It is preferable to use a noble gas as the inert gas here.

[0367] Alternatively, it is preferable to increase the pressure in the transport chamber 2704 and each chamber by introducing an inert gas such as a heated noble gas or oxygen, and then exhaust the transport chamber 2704 and each chamber again after a certain period of time. By introducing a heated gas, adsorbed substances can be removed from the transport chamber 2704 and each chamber, thereby reducing the amount of impurities present in the transport chamber 2704 and each chamber. This process is most effective when repeated 2 to 30 times, preferably 5 to 15 times. Specifically, the pressure in the transport chamber 2704 and each chamber can be increased to 0.1 Pa to 10 kPa, preferably 1 Pa to 1 kPa, and more preferably 5 Pa to 100 Pa by introducing an inert gas or oxygen with a temperature of 40°C to 400°C, preferably 50°C to 200°C, and the pressure can be maintained for 1 minute to 300 minutes, preferably 5 minutes to 120 minutes. Subsequently, the transport chamber 2704 and each chamber are evacuated for a period of 5 minutes to 300 minutes, preferably 10 minutes to 120 minutes.

[0368] Next, chambers 2706b and 2706c will be described using the schematic cross-sectional diagrams shown in Figure 19.

[0369] Chambers 2706b and 2706c are chambers capable of performing microwave processing on an object to be processed. The only difference between chambers 2706b and 2706c is the atmosphere used during microwave processing. Other configurations are common to both chambers, and will therefore be described together below.

[0370] Chambers 2706b and 2706c each have a slot antenna plate 2808, a dielectric plate 2809, a substrate holder 2812, and an exhaust port 2819. Outside of chambers 2706b and 2706c, a gas supply source 2801, a valve 2802, a high-frequency generator 2803, a waveguide 2804, a mode converter 2805, a gas pipe 2806, a waveguide 2807, a matching box 2815, a high-frequency power supply 2816, a vacuum pump 2817, and a valve 2818.

[0371] The high-frequency generator 2803 is connected to the mode converter 2805 via a waveguide 2804. The mode converter 2805 is connected to the slot antenna plate 2808 via a waveguide 2807. The slot antenna plate 2808 is positioned in contact with the dielectric plate 2809. The gas supply source 2801 is connected to the mode converter 2805 via a valve 2802. Gas is then supplied to chambers 2706b and 2706c through a gas pipe 2806 that passes through the mode converter 2805, waveguide 2807, and dielectric plate 2809. The vacuum pump 2817 has the function of exhausting gas and other substances from chambers 2706b and 2706c via a valve 2818 and an exhaust port 2819. The high-frequency power supply 2816 is connected to the substrate holder 2812 via a matching box 2815.

[0372] The substrate holder 2812 has the function of holding the substrate 2811. For example, it has the function of electrostatically or mechanically chucking the substrate 2811. It also functions as an electrode to which power is supplied from the high-frequency power supply 2816. It also has an internal heating mechanism 2813 and has the function of heating the substrate 2811.

[0373] As the vacuum pump 2817, for example, a dry pump, mechanical booster pump, ion pump, titanium sublimation pump, cryopump, or turbomolecular pump can be used. In addition to the vacuum pump 2817, a cryotrap may also be used. Using a cryopump and cryotrap is particularly preferable because it allows for efficient water removal.

[0374] Furthermore, the heating mechanism 2813 may be, for example, a heating mechanism that uses a resistance heating element. Alternatively, it may be a heating mechanism that heats by heat conduction or thermal radiation from a heated medium such as a gas. For example, RTA (Rapid Thermal Annealing) such as GRTA (Gas Rapid Thermal Annealing) or LRTA (Lamp Rapid Thermal Annealing) can be used. GRTA performs heat treatment using a high-temperature gas. An inert gas is used as the gas.

[0375] Furthermore, the gas supply source 2801 may be connected to the purifier via a mass flow controller. It is preferable to use a gas with a dew point of -80°C or lower, preferably -100°C or lower. For example, oxygen gas, nitrogen gas, and noble gases (such as argon gas) may be used.

[0376] For example, silicon oxide (quartz), aluminum oxide (alumina), or yttrium oxide (yttria) may be used as the dielectric plate 2809. Furthermore, another protective layer may be formed on the surface of the dielectric plate 2809. The protective layer may be made of magnesium oxide, titanium oxide, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silicon oxide, aluminum oxide, or yttrium oxide. Since the dielectric plate 2809 will be exposed to particularly high-density regions of the high-density plasma 2810 described later, providing a protective layer can mitigate damage. As a result, an increase in particles during processing can be suppressed.

[0377] The high-frequency generator 2803 has the function of generating microwaves in frequencies such as 0.3 GHz to 3.0 GHz, 0.7 GHz to 1.1 GHz, or 2.2 GHz to 2.8 GHz. The microwaves generated by the high-frequency generator 2803 are transmitted to the mode converter 2805 via the waveguide 2804. In the mode converter 2805, the microwaves transmitted as TE mode are converted to TEM mode. The microwaves are then transmitted to the slot antenna plate 2808 via the waveguide 2807. The slot antenna plate 2808 is provided with multiple slot holes, and the microwaves pass through these slot holes and the dielectric plate 2809. This generates an electric field below the dielectric plate 2809, thereby generating a high-density plasma 2810. The high-density plasma 2810 contains ions and radicals depending on the type of gas supplied from the gas supply source 2801. For example, oxygen radicals are present.

[0378] At this time, the ions and radicals generated in the high-density plasma 2810 can modify the film on the substrate 2811. It is preferable to apply a bias to the substrate 2811 using the high-frequency power supply 2816. For example, the high-frequency power supply 2816 can be an RF (Radio Frequency) power supply with frequencies such as 13.56 MHz or 27.12 MHz. By applying a bias to the substrate, the ions in the high-density plasma 2810 can efficiently reach deep into the openings of the film on the substrate 2811.

[0379] For example, oxygen radical treatment using high-density plasma 2810 can be performed by introducing oxygen from gas supply source 2801 in chamber 2706b or chamber 2706c.

[0380] Next, chambers 2706a and 2706d will be described using the schematic cross-sectional diagrams shown in Figure 20.

[0381] Chambers 2706a and 2706d are chambers capable of irradiating the workpiece with electromagnetic waves, for example. The only difference between chambers 2706a and 2706d is the type of electromagnetic wave they emit. Since many other components are common to both, they will be described together below.

[0382] Chambers 2706a and 2706d each have one or more lamps 2820, a substrate holder 2825, a gas inlet 2823, and an exhaust port 2830. Outside of chambers 2706a and 2706d, a gas supply source 2821, a valve 2822, a vacuum pump 2828, and a valve 2829 are provided.

[0383] The gas supply source 2821 is connected to the gas inlet 2823 via valve 2822. The vacuum pump 2828 is connected to the exhaust port 2830 via valve 2829. The lamp 2820 is positioned opposite the substrate holder 2825. The substrate holder 2825 has the function of holding the substrate 2824. The substrate holder 2825 also has an internal heating mechanism 2826 that has the function of heating the substrate 2824.

[0384] For lamp 2820, for example, a light source having the function of emitting electromagnetic waves such as visible light or ultraviolet light may be used. For example, a light source having the function of emitting electromagnetic waves with peaks in wavelengths of 10 nm to 2500 nm, 500 nm to 2000 nm, or 40 nm to 340 nm may be used.

[0385] For example, lamp 2820 can be a light source such as a halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, or high-pressure mercury lamp.

[0386] For example, electromagnetic waves emitted from the lamp 2820 can be partially or entirely absorbed by the substrate 2824, thereby modifying the film on the substrate 2824. For example, defects can be created or reduced, or impurities can be removed. Furthermore, if the substrate 2824 is heated during the process, the creation or reduction of defects or the removal of impurities can be performed more efficiently.

[0387] Alternatively, for example, the substrate holder 2825 may be heated by electromagnetic waves emitted from the lamp 2820, thereby heating the substrate 2824. In this case, the substrate holder 2825 does not need to have a heating mechanism 2826 inside.

[0388] For vacuum pump 2828, refer to the description for vacuum pump 2817. For heating mechanism 2826, refer to the description for heating mechanism 2813. For gas supply source 2821, refer to the description for gas supply source 2801.

[0389] The microwave processing apparatus that can be used in this embodiment is not limited to the one described above. The microwave processing apparatus 2900 shown in Figure 21 can be used. The microwave processing apparatus 2900 has a quartz tube 2901, an exhaust port 2819, a gas supply source 2801, a valve 2802, a high-frequency generator 2803, a waveguide 2804, a gas pipe 2806, a vacuum pump 2817, and a valve 2818. The microwave processing apparatus 2900 also has a substrate holder 2902 inside the quartz tube 2901 that holds a plurality of substrates 2811 (2811_1 to 2811_n, where n is an integer of 2 or more). The microwave processing apparatus 2900 may also have a heating means 2903 on the outside of the quartz tube 2901.

[0390] Microwaves generated by the high-frequency generator 2803 are irradiated onto a substrate placed inside the quartz tube 2901 via the waveguide 2804. The vacuum pump 2817 is connected to the exhaust port 2819 via the valve 2818, and can adjust the pressure inside the quartz tube 2901. The gas supply source 2801 is connected to the gas pipe 2806 via the valve 2802, and can introduce a desired gas into the quartz tube 2901. The heating means 2903 can heat the substrate 2811 inside the quartz tube 2901 to a desired temperature. Alternatively, the heating means 2903 may heat the gas supplied from the gas supply source 2801. The microwave processing device 2900 can perform heating and microwave processing on the substrate 2811 simultaneously. Alternatively, the substrate 2811 can be heated first, followed by microwave processing, or the substrate 2811 can be microwaved first, followed by heating.

[0391] Substrates 2811_1 to 2811_n may all be processing substrates forming semiconductor devices or memory devices, or some of the substrates may be dummy substrates. For example, substrates 2811_1 and 2811_n may be dummy substrates, and substrates 2811_2 to 2811_n-1 may be processing substrates. Alternatively, substrates 2811_1, 2811_2, 2811_n-1, and 2811_n may be dummy substrates, and substrates 2811_3 to 2811_n-2 may be processing substrates. Using dummy substrates is preferable because it allows multiple processing substrates to be processed uniformly during microwave processing or heat processing, reducing variations between processing substrates. For example, it is preferable to place dummy substrates on the processing substrates closest to the high-frequency generator 2803 and waveguide 2804, as this suppresses direct exposure of the processing substrates to microwaves.

[0392] By using the above manufacturing equipment, it becomes possible to modify the film while suppressing the inclusion of impurities in the processed material.

[0393] <Modified examples of semiconductor devices> In the following section, an example of a semiconductor device, which is one embodiment of the present invention, will be described using Figures 3A to 5D.

[0394] Each Figure A shows a top view of a semiconductor device. Each Figure B is a cross-sectional view corresponding to the area indicated by the dashed line A1-A2 in Figure A. Each Figure C is a cross-sectional view corresponding to the area indicated by the dashed line A3-A4 in Figure A. Each Figure D is a cross-sectional view corresponding to the area indicated by the dashed line A5-A6 in Figure A. In the top view of Figure A, some elements have been omitted for clarity.

[0395] In the semiconductor devices shown in Figures A to D, structures having the same function as those constituting the semiconductor device shown in <Examples of Semiconductor Device Configurations> are denoted by the same reference numerals. Furthermore, in this section as well, the materials used for the semiconductor device components are those described in detail in <Examples of Semiconductor Device Configurations>.

[0396] <Example 1 of a semiconductor device> The semiconductor devices shown in Figures 3A to 3D are modified versions of the semiconductor devices shown in Figures 1A to 1D. The semiconductor devices shown in Figures 3A to 3D differ from those shown in Figures 1A to 1D in that they do not have an insulator 282. Therefore, in the semiconductor devices shown in Figures 3A to 3D, the insulator 283 is in contact with the upper surface of the conductor 260, the upper surface of the insulator 280, the uppermost part of the insulator 254, the uppermost part of the insulator 250, and the uppermost part of the insulator 252.

[0397] For example, if sufficient oxygen can be supplied to the oxide 230 by microwave processing as shown in Figure 11 or Figure 12, the region 230bc can be substantially made i-type without providing an insulator 282 and adding oxygen to the insulator 280. In such cases, as shown in Figures 3A to 3D, by using a configuration without an insulator 282, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.

[0398] <Modified example of a semiconductor device 2> The semiconductor devices shown in Figures 4A to 4D are modified versions of the semiconductor devices shown in Figures 1A to 1D. The semiconductor devices shown in Figures 4A to 4D differ from those shown in Figures 1A to 1D in that they are provided with oxide 243 (oxide 243a, oxide 243b). Oxide 243a is provided between oxide 230b and conductor 242a, and oxide 243b is provided between oxide 230b and conductor 242b. Here, it is preferable that oxide 243a is in contact with the upper surface of oxide 230b and the lower surface of conductor 242a. It is also preferable that oxide 243b is in contact with the upper surface of oxide 230b and the lower surface of conductor 242b.

[0399] It is preferable that the oxide 243 has the function of suppressing oxygen permeation. Placing the oxide 243, which has the function of suppressing oxygen permeation, between the conductor 242, which functions as a source electrode or drain electrode, and the oxide 230b is preferable because it reduces the electrical resistance between the conductor 242 and the oxide 230b. With such a configuration, it may be possible to improve the electrical characteristics, field effect mobility, and reliability of the transistor 200.

[0400] Furthermore, a metal oxide containing element M may be used as oxide 243. In particular, element M may be aluminum, gallium, yttrium, or tin. It is also preferable that oxide 243 has a higher concentration of element M than oxide 230b. Gallium oxide may also be used as oxide 243. Furthermore, a metal oxide such as In-M-Zn oxide may be used as oxide 243. Specifically, in the metal oxide used for oxide 243, it is preferable that the atomic ratio of element M to In is greater than the atomic ratio of element M to In in the metal oxide used for oxide 230b. The film thickness of oxide 243 is preferably 0.5 nm to 5 nm, more preferably 1 nm to 3 nm, and even more preferably 1 nm to 2 nm. It is also preferable that oxide 243 is crystalline. When oxide 243 is crystalline, the release of oxygen in oxide 230 can be suitably suppressed. For example, if oxide 243 has a hexagonal crystal structure, it may be possible to suppress the release of oxygen from oxide 230.

[0401] <Modified example of semiconductor device 3> The semiconductor devices shown in Figures 5A to 5D are modified versions of the semiconductor devices shown in Figures 1A to 1D. The semiconductor devices shown in Figures 5A to 5D differ from those shown in Figures 1A to 1D in that the insulator 283 is in contact with a part of the upper surface of the insulator 212. Therefore, the transistor 200 is placed within the region sealed by the insulator 283 and the insulator 212. This configuration prevents hydrogen contained outside the sealed region from entering the sealed region. Furthermore, although the transistor 200 shown in Figures 5A to 5D is shown with the insulator 212 and the insulator 283 provided as single layers, the present invention is not limited to this. For example, the insulator 212 and the insulator 283 may each be provided as a stacked structure of two or more layers.

[0402] OS transistors, such as transistor 200, exhibit small fluctuations in electrical properties due to radiation exposure, meaning they have high resistance to radiation, making them suitable for use in environments where radiation may be incident. For example, OS transistors are suitable for use in outer space. Specifically, OS transistors can be used in transistors that constitute semiconductor devices installed in space shuttles, artificial satellites, space probes, etc. Examples of radiation include X-rays and neutrons. Furthermore, outer space generally refers to altitudes of 100 km or higher, but the term "outer space" as used herein may also include the thermosphere, mesosphere, and stratosphere.

[0403] Alternatively, for example, OS transistors can be used in semiconductor devices installed in robots used in nuclear power plants and radioactive waste treatment or disposal facilities. They are particularly suitable for use in semiconductor devices installed in remotely operated robots used for tasks such as dismantling reactor facilities, removing nuclear fuel or fuel debris, and conducting on-site surveys of spaces with high levels of radioactive materials.

[0404] Alternatively, for example, OS transistors can be suitably used as transistors constituting semiconductor devices provided in electronic equipment used in radiotherapy. An example of such electronic equipment is an X-ray detection panel used in radiography.

[0405] <Examples of semiconductor device applications> In the following section, an example of a semiconductor device according to one aspect of the present invention will be described using Figure 22.

[0406] Figure 22A shows a top view of the semiconductor device 500. The x-axis in Figure 22A is taken parallel to the channel length direction of the transistor 200, and the y-axis is taken perpendicular to the x-axis. Figure 22B is a cross-sectional view corresponding to the area indicated by the dashed line A1-A2 in Figure 22A, and is also a cross-sectional view of the transistor 200 in the channel length direction. Figure 22C is a cross-sectional view corresponding to the area indicated by the dashed line A3-A4 in Figure 22A, and is also a cross-sectional view of the aperture region 400 and its vicinity. Note that some elements have been omitted from the top view of Figure 22A for clarity.

[0407] In the semiconductor devices shown in Figures 22A to 22C, structures having the same function as those constituting the semiconductor device shown in <Example of Semiconductor Device Configuration> are denoted by the same reference numerals. Furthermore, in this section as well, the materials used for the semiconductor device components are those described in detail in <Example of Semiconductor Device Configuration>.

[0408] The semiconductor device 500 shown in Figures 22A to 22C is a modified version of the semiconductor device shown in Figures 1A to 1D. The semiconductor device 500 shown in Figures 22A to 22C differs from the semiconductor device shown in Figures 1A to 1D in that an opening region 400 is formed in the insulator 282 and the insulator 280. It also differs from the semiconductor device shown in Figures 1A to 1D in that a sealing portion 265 is formed to surround the plurality of transistors 200.

[0409] The semiconductor device 500 has a plurality of transistors 200 and a plurality of aperture regions 400 arranged in a matrix. A plurality of conductors 260, which function as gate electrodes for the transistors 200, are provided extending in the y-axis direction. The aperture regions 400 are formed in areas that do not overlap with the oxide 230 and the conductors 260. Furthermore, a sealing portion 265 is formed to surround the plurality of transistors 200, the plurality of conductors 260, and the plurality of aperture regions 400. Note that the number, arrangement, and size of the transistors 200, conductors 260, and aperture regions 400 are not limited to the structure shown in Figure 22, but can be appropriately set according to the design of the semiconductor device 500.

[0410] As shown in Figures 22B and 22C, the sealing portion 265 is provided so as to surround the multiple transistors 200, insulators 216, 222, 275, 280, and 282. In other words, insulator 283 is provided so as to cover insulators 216, 222, 275, 280, and 282. Also, in the sealing portion 265, insulator 283 is in contact with the upper surface of insulator 214. Furthermore, on the sealing portion 265, insulator 274 is provided between insulators 283 and 285. The upper surface of insulator 274 is approximately the same height as the uppermost surface of insulator 283. Insulator 274 can be made of the same type of insulator as insulator 280.

[0411] This structure allows multiple transistors 200 to be enclosed by insulators 283, 214, and 212. Preferably, one or more of insulators 283, 214, and 212 function as a barrier insulating film against hydrogen. This prevents hydrogen contained outside the sealing portion 265 from entering the sealing portion 265.

[0412] As shown in Figure 22C, the insulator 282 has an opening in the opening region 400. In addition, the insulator 280 may have a groove that overlaps the opening of the insulator 282 in the opening region 400. The depth of the groove in the insulator 280 should not be too deep, except to expose the upper surface of the insulator 275, for example, it should be about 1 / 4 to 1 / 2 of the maximum film thickness of the insulator 280.

[0413] Furthermore, as shown in Figure 22C, the insulator 283 is in contact with the side surface of the insulator 282, the side surface of the insulator 280, and the upper surface of the insulator 280 inside the opening region 400. In addition, a portion of the insulator 274 may be formed within the opening region 400 to fill in the recess formed in the insulator 283. In this case, the height of the upper surface of the insulator 274 formed within the opening region 400 and the uppermost surface of the insulator 283 may be approximately the same.

[0414] With such an opening region 400 formed and the insulator 280 exposed through the opening in the insulator 282, heat treatment can be performed to supply oxygen to the oxide 230 while diffusing some of the oxygen contained in the insulator 280 outward from the opening region 400. This ensures that sufficient oxygen is supplied from the insulator 280 containing oxygen that is released by heating to the region in the oxide semiconductor that functions as a channel-forming region and its vicinity, while preventing the supply of an excessive amount of oxygen.

[0415] At this time, the hydrogen contained in the insulator 280 can combine with oxygen and be released to the outside through the opening region 400. The hydrogen combined with oxygen is released as water. Therefore, the amount of hydrogen contained in the insulator 280 can be reduced, and the mixing of hydrogen contained in the insulator 280 into the oxide 230 can be reduced.

[0416] Furthermore, although the shape of the aperture region 400 in a top view in Figure 22A is approximately rectangular, the present invention is not limited to this. For example, the shape of the aperture region 400 in a top view may be rectangular, elliptical, circular, rhombus, or a combination thereof. Also, the area and spacing of the aperture region 400 can be appropriately set according to the design of the semiconductor device including the transistors 200. For example, in areas where the density of transistors 200 is low, the area of ​​the aperture region 400 can be increased or the spacing of the aperture region 400 can be decreased. Also, for example, in areas where the density of transistors 200 is high, the area of ​​the aperture region 400 can be decreased or the spacing of the aperture region 400 can be increased.

[0417] According to one aspect of the present invention, a novel transistor can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with less variation in transistor characteristics can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device having good electrical characteristics can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with good reliability can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with high on-current can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with high field-effect mobility can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with good frequency characteristics can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with low power consumption can be provided.

[0418] The configurations and methods described in this embodiment can be implemented by appropriately combining at least a part thereof with other embodiments and other examples described herein.

[0419] (Embodiment 2) In this embodiment, one form of semiconductor device will be described using Figures 23 and 24. The semiconductor device described in this embodiment is an evaluation element (also called a TEG) capable of multi-point measurement.

[0420] Figure 23 is a circuit diagram of the TEG900, an example of a semiconductor device according to one aspect of the present invention.

[0421] The TEG900 has a group of transistors called TRA and a peripheral circuit called PC.

[0422] The transistor group TRA has m × n transistors (transistors Tr[1,1] to transistors Tr[m,n] shown in Figure 23) where m and n are independent integers of 1 or greater.

[0423] The peripheral circuit PC has two multiplexers (multiplexer MUXX and multiplexer MUXY), m analog switches (analog switch ASX[1] to analog switch ASX[m]), and n analog switches (analog switch ASY[1] to analog switch ASY[n]). An analog switch is an electronic component that switches an analog signal on or off in response to an input control signal. Here, the control signal refers to a digital potential (a voltage condition with two or more values), and the analog signal refers to an analog potential (a voltage condition with two or more values). Analog switches are also called transmission gates.

[0424] Furthermore, the TEG900 is electrically connected to wiring WX, WY, DL, TGL, BGL, and SL.

[0425] Wiring WX is electrically connected to the multiplexer MUXX. Wiring WY is electrically connected to the multiplexer MUXY. Wiring BGL is electrically connected to the second gate of each transistor Tr[1,1] through Tr[m,n]. Wiring SL is electrically connected to either the source or the drain of each transistor Tr[1,1] through Tr[m,n].

[0426] Furthermore, if the first gate and the second gate of each of the transistors Tr[1,1] to Tr[m,n] are electrically connected, the TEG900 does not need to have wiring BGL. Also, if the transistors Tr[1,1] to Tr[m,n] are single-gate transistors, that is, transistors without a second gate, the TEG900 does not need to have wiring BGL.

[0427] Wiring WX is supplied with control signals used by the multiplexer MUXX. Wiring WY is supplied with control signals used by the multiplexer MUXY.

[0428] The first terminal of each analog switch ASX[1] through ASX[m] is electrically connected to the multiplexer MUXX. The second terminal of each analog switch ASX[1] through ASX[m] is electrically connected to the wiring DL. The third terminal of analog switch ASX[i] (where i is an integer between 1 and m) is electrically connected to the other end of the source and drain of each transistor Tr[i,1] through Tr[i,n].

[0429] The multiplexer MUXX has the function of controlling the on / off state of each of the analog switches ASX[1] through ASX[m]. Specifically, the multiplexer MUXX has the function of turning on one of the m analog switches ASX or turning off all of the analog switches ASX based on the control signal received from the wiring WX. For example, when the potential of the signal supplied from the multiplexer MUXX is high, the analog switch ASX is turned off, and when the potential of the signal supplied from the multiplexer MUXX is low, the analog switch ASX is turned on. When analog switch ASX[i] is on, wiring DL conducts to the other source and drain of each of the transistors Tr[i,1] through Tr[i,n]. At this time, the potential of wiring DL is supplied to the other source and drain of each of the transistors Tr[i,1] through Tr[i,n].

[0430] The first terminal of each analog switch ASY[1] through ASY[n] is electrically connected to the multiplexer MUXY. The second terminal of each analog switch ASY[1] through ASY[n] is electrically connected to the wiring TGL. The third terminal of analog switch ASY[j] (where j is an integer between 1 and n) is electrically connected to the first gate of each transistor Tr[j,1] through Tr[j,n].

[0431] The multiplexer MUXY has the function of controlling the on / off state of each of the analog switches ASY[1] through ASY[n]. Specifically, the multiplexer MUXY has the function of turning on one of the n analog switches ASY or turning off all of the analog switches ASY based on the control signal received from the wiring WY. For example, when the potential of the signal supplied from the multiplexer MUXY is high, the analog switch ASY is turned on, and when the potential of the signal supplied from the multiplexer MUXY is low, the analog switch ASY is turned off. Alternatively, when the potential of the signal supplied from the multiplexer MUXY is high, the analog switch ASY is turned off, and when the potential of the signal supplied from the multiplexer MUXY is low, the analog switch ASY is turned on. When analog switch ASY[j] is on, the wiring TGL and the first gates of each of the transistors Tr[1,j] through Tr[m,j] are conducted. At this time, the potential of the wiring DL is supplied to the first gate of each of the transistors Tr[1,j] through Tr[n,j].

[0432] As shown in Figure 23, the TEG900 allows for the selection of a target transistor from among m × n transistors and the measurement of its electrical characteristics. In other words, the TEG900 is a TEG capable of multi-point measurement.

[0433] The multiplexer MUXX, the multiplexer MUXY, the analog switch ASX, and the analog switch ASY are preferably each independently composed of a CMOS (Complementary Metal Oxide Semiconductor) circuit or a unipolar circuit, and more preferably the multiplexer MUXX, the multiplexer MUXY, the analog switch ASX, and the analog switch ASY are composed of a CMOS circuit or a unipolar circuit.

[0434] Furthermore, it is preferable to stack the layer containing the peripheral circuit PC and the layer containing the transistor group TRA.

[0435] Figure 24A shows a perspective view of the TEG900. The TEG900 has layers 910 and 920. Figure 24B is a perspective view illustrating the configuration of the TEG900, showing layers 910 and 920 separately.

[0436] Layer 910 has peripheral circuit PC. In other words, layer 910 has multiplexer MUXX, multiplexer MUXY, analog switch ASX, and analog switch ASY. Layer 920 has transistor group TRA.

[0437] Layer 910 may be formed using single-crystal semiconductors, polycrystalline semiconductors, microcrystalline semiconductors, or amorphous semiconductors, either individually or in combination. Examples of semiconductor materials include silicon and germanium. Compound semiconductors such as silicon-germanium, silicon carbide, gallium arsenide, oxide semiconductors, and nitride semiconductors may also be used. Note that transistors with silicon in the channel formation region are sometimes called Si transistors.

[0438] Additionally, gallium arsenide, aluminum gallium arsenide, indium gallium arsenide, gallium nitride, indium phosphide, silicon germanium, and other materials applicable to HEMTs (High Electron Mobility Transistors) may be used.

[0439] Layer 920 can be formed using an oxide semiconductor or a semiconductor material capable of forming a thin film, such as silicon. By using thin-film formation technology, the peripheral circuit PC included in layer 910 and the transistor group TRA included in layer 920 can be arranged three-dimensionally. Therefore, the occupied area of ​​TEG900 can be reduced.

[0440] Alternatively, layer 920 may be formed on another substrate and bonded to layer 910.

[0441] For example, the peripheral circuit PC is constructed using a CMOS circuit, and the transistor group TRA is constructed using the transistor 200 described in Embodiment 1. Specifically, the peripheral circuit PC is composed of Si transistors, and the transistor group TRA is composed of OS transistors. Since the layer containing the Si transistors and the layer containing the OS transistors can be formed monolithically, this configuration allows for shorter wiring between the peripheral circuit and the OS transistors, and enables measurement of the electrical characteristics of multiple OS transistors with a short TAT (Turn Around Time). Furthermore, the pitch width between OS transistors can be narrowed.

[0442] Alternatively, for example, the peripheral circuit PC and the transistor group TRA may be composed of the transistor 200 described in Embodiment 1. Specifically, the peripheral circuit PC and the transistor group TRA are composed of OS transistors. The layer containing the OS transistors is stackable. Therefore, by stacking the layer containing the OS transistors used in the peripheral circuit PC and the layer containing the OS transistors used in the transistor group TRA, the wiring connecting the peripheral circuit and the OS transistors can be shortened, and the electrical characteristics of multiple OS transistors can be measured with a short turnaround time (TAT). In addition, the pitch width between OS transistors can be narrowed.

[0443] Furthermore, the peripheral circuit PC and the transistor group TRA may be formed in three or more layers. For example, some of the transistors included in the peripheral circuit PC may be composed of Si transistors, all the other transistors included in the peripheral circuit PC may be composed of OS transistors, and the transistor group TRA may be composed of OS transistors. In this case, the TEG900 may have a layer containing Si transistors, a first layer on the said layer containing OS transistors, and a second layer on the first layer containing OS transistors. The OS transistors included in the first layer may be used as all the other transistors included in the peripheral circuit PC, and the OS transistors included in the second layer may be used as the transistor group TRA. This configuration can further reduce the occupied area of ​​the TEG900.

[0444] Alternatively, the peripheral circuit PC and the transistor group TRA may be formed on the same layer.

[0445] <Layout of the transistor group TRA> Next, the layout of the transistor group TRA in the TEG900 shown in Figure 23 will be explained using Figures 25A to 28B.

[0446] Figure 25A shows an example of a top view of a part of the transistor group TRA shown in Figure 23. Figure 25A also illustrates the layout of the transistor group TRA shown in Figure 23. Figure 25A shows transistors Tr[i,j], Tr[i,j+1], Tr[i+1,j], and Tr[i+1,j+1] from the transistor group TRA shown in Figure 23. Note that some elements have been omitted from the top view of Figure 25A for clarity.

[0447] The oxide OS is a metal oxide containing a channel-forming region. In Figure 25A, the oxide OS of a transistor is separated from the oxide OS of adjacent transistors in the channel length direction of that transistor. Furthermore, the oxide OS of a transistor is separated from the oxide OS of adjacent transistors in the channel width direction of that transistor.

[0448] Conductive vias function as wiring or plugs. Conductive vias are electrically connected to the source or drain of a transistor and to conductor WIR1 or conductor WIR2. For example, in Figure 25A, a conductive via connected to one of the source and drain of transistor Tr[i,j] is connected to conductor WIR1[i], and a conductive via connected to the other of the source and drain of transistor Tr[i,j] is connected to conductor WIR2[i].

[0449] The conductor TGE functions as the first gate of the transistor. In Figure 25A, the conductor TGE[j] has a region that overlaps with the oxide OS present in transistors Tr[i,j] and Tr[i+1,j], respectively. Similarly, the conductor TGE[j+1] has a region that overlaps with the oxide OS present in transistors Tr[i,j+1] and Tr[i+1,j+1], respectively.

[0450] The conductor BGE functions as the second gate of the transistor. In Figure 25A, the conductor BGE[j] has a region that overlaps with the oxide OS present in transistors Tr[i,j] and Tr[i+1,j], respectively. Similarly, the conductor BGE[j+1] has a region that overlaps with the oxide OS present in transistors Tr[i,j+1] and Tr[i+1,j+1], respectively. Furthermore, the conductor BGE[j] has a region that overlaps with the conductor TGE[j] via the oxide OS present in transistors Tr[i,j] and Tr[i+1,j], respectively. Similarly, the conductor BGE[j+1] has a region that overlaps with the conductor TGE[j+1] via the oxide OS present in transistors Tr[i,j+1] and Tr[i+1,j+1], respectively.

[0451] Conductor WIR1 functions as wiring. In Figure 25A, conductor WIR1[i] is electrically connected to one of the sources and drains of transistors Tr[i,j] and Tr[i,j+1] via conductor VIA. Similarly, conductor WIR1[i+1] is electrically connected to one of the sources and drains of transistors Tr[i+1,j] and Tr[i+1,j+1] via conductor VIA.

[0452] Conductor WIR2 functions as wiring. In Figure 25A, conductor WIR2[i] is electrically connected to the other source and drain of transistors Tr[i,j] and Tr[i,j+1] via conductor VIA. Similarly, conductor WIR2[i+1] is electrically connected to the other source and drain of transistors Tr[i+1,j] and Tr[i+1,j+1] via conductor VIA.

[0453] As the transistor Tr, for example, the transistor 200 described in Embodiment 1 can be used. In this case, oxide OS corresponds to oxide 230 described in Embodiment 1, conductor TGE corresponds to conductor 260 described in Embodiment 1, conductor BGE corresponds to conductor 205 described in Embodiment 1, and conductor VIA corresponds to conductor 240 described in Embodiment 1. Also, for example, conductor WIR1 corresponds to one of conductors 246a and 246b described in Embodiment 1, and conductor WIR2 corresponds to the other of conductors 246a and 246b described in Embodiment 1.

[0454] For example, conductor WIR2[i] corresponds to wiring that is electrically connected to analog switch ASX[i], and conductor WIR1[i] corresponds to wiring SL or wiring that is electrically connected to wiring SL.

[0455] Note that the configuration of the transistor group TRA in the TEG900 is not limited to the above. Another example of the transistor group TRA in the TEG900 will be explained using Figures 25B, 26A, 26B, 27A, 27B, 28A, and 28B. Note that some elements have been omitted in each figure for clarity.

[0456] Figure 25B is another example of a top view of a part of the transistor group TRA of the TEG900. Figure 25B also illustrates the layout of the transistor group TRA shown in Figure 23. Figure 25B shows transistors Tr[i,j] to Tr[i,j+2] and transistors Tr[i+1,j] to Tr[i+1,j+2] from the transistor group TRA shown in Figure 23.

[0457] The transistor group TRA shown in Figure 25B differs from the transistor group TRA shown in Figure 25A in the configuration or shape of the oxide OS.

[0458] As shown in Figure 25B, the oxide OS extends in the direction of the transistor's channel length. Therefore, some or all of the multiple transistors arranged in the direction of the transistor's channel length share a single oxide OS. For example, the channels of each transistor Tr[i,j] through Tr[i,j+2] are formed in one oxide OS. Similarly, the channels of each transistor Tr[i+1,j] through Tr[i+1,j+2] are formed in a different oxide OS than the one mentioned above.

[0459] The source or drain of a transistor is configured to also serve as the source or drain of a transistor adjacent to it in the channel length direction. For example, one of the source and drain of transistor Tr[i,j+1] also serves as one of the source and drain of transistor Tr[i,j]. Similarly, the other of the source and drain of transistor Tr[i,j+1] also serves as the other of the source and drain of transistor Tr[i,j+2].

[0460] A conductive via that is connected to the source or drain of a transistor is also connected to the source or drain of a transistor adjacent to that transistor in the channel length direction. For example, a conductive via that is connected to one of the source and drains of transistor Tr[i,j+1] is connected to one of the source and drains of transistor Tr[i,j] and to conductor WIR1[i]. Similarly, a conductive via that is connected to the other of the source and drains of transistor Tr[i,j+1] is connected to the other of the source and drains of transistor Tr[i,j+2] and to conductor WIR2[i].

[0461] Furthermore, the conductor TGE[j+2] has regions that overlap with the oxide OS present in transistors Tr[i,j+2] and Tr[i+1,j+2], respectively. In addition, the conductor BGE[j+2] has regions that overlap with the oxide OS present in transistors Tr[i,j+2] and Tr[i+1,j+2], respectively.

[0462] By adopting the configuration shown in Figure 25B, the transistor density of the transistor group TRA can be increased. Therefore, high integration of the semiconductor device can be achieved.

[0463] Figure 26A is another example of a top view of a part of the transistor group TRA in the TEG900. Figure 26A also illustrates the layout of the transistor group TRA shown in Figure 23. Figure 26A shows transistors Tr[i,j], Tr[i,j+1], Tr[i+1,j], and Tr[i+1,j+1] from the transistor group TRA shown in Figure 23.

[0464] The transistor group TRA shown in Figure 26A differs from the transistor group TRA shown in Figure 25A in that it has oxide OSDs.

[0465] As shown in Figure 26A, the oxide OSD is positioned between two adjacent oxide OSs in the channel width direction of the transistor. The oxide OSD is not electrically connected to conductors WIR1 and WIR2.

[0466] Both oxide OS and oxide OSD are formed from the same oxide film. Therefore, oxide OS and oxide OSD are constructed using the same material. In other words, the elements that make up oxide OS and the elements that make up oxide OSD are the same.

[0467] The oxide OSD shown in Figure 26A has the same shape as the oxide OS shown in Figure 26A, but is not limited to this. The oxide OSD may be rectangular, elliptical, circular, rhombic, or substantially rectangular, or it may be a shape that extends in the direction of the transistor channel length, like the oxide OS shown in Figure 25B, or it may be a combination of these shapes.

[0468] By placing oxide OSDs, the pattern density of the oxide formed by the processing of the oxide film can be adjusted. By adjusting the pattern density, the loading effect, which changes the etching rate and etching shape, can be suppressed.

[0469] In this specification, pattern density refers to the area ratio of the formed structure in any given region. For example, if an oxide film is deposited over the entire surface of any given region, the pattern density will be 100 percent. On the other hand, if a portion of the oxide film is removed and multiple oxides are formed, the pattern density of the oxides can be determined by dividing the area of ​​the remaining oxides by the area of ​​the given region.

[0470] Furthermore, by providing oxide OSDs, some of the oxygen added to the oxide OS during transistor fabrication is added to the oxide OSDs. In other words, the amount of oxygen added to the oxide OS can be controlled by adjusting the size and number of oxide OSDs. This allows for the control of oxygen vacancies and V in the channel formation region of the oxide OS. OBy reducing H, excessive oxidation of the source and drain can be suppressed. Therefore, the electrical characteristics of the transistor can be improved, and its reliability can be enhanced.

[0471] In Figure 26A, the oxide OSD has regions that overlap with conductor WIR1 and regions that overlap with conductor WIR2. This configuration allows for high integration of the semiconductor device. Note that the oxide OSD does not necessarily have to overlap with conductor WIR1 or conductor WIR2.

[0472] Figure 26B is another example of a top view of a part of the transistor group TRA of the TEG900. Figure 26B also illustrates the layout of the transistor group TRA shown in Figure 23. Figure 26B shows transistors Tr[i,j] to Tr[i,j+2] and transistors Tr[i+1,j] to Tr[i+1,j+2] from the transistor group TRA shown in Figure 23.

[0473] The transistor group TRA shown in Figure 26B differs from the transistor group TRA shown in Figure 25B in that it has an oxide OSD. Furthermore, the configuration or shape of the oxide OS and oxide OSD in the transistor group TRA shown in Figure 26B differs from the transistor group TRA shown in Figure 26A.

[0474] For details regarding the structure or shape of the oxide OS in the transistor group TRA shown in Figure 26B, please refer to the information explained using Figure 25B.

[0475] The oxide OSD shown in Figure 26B has the same shape as the oxide OS shown in Figure 26B, but is not limited to this. The oxide OSD may be rectangular, elliptical, circular, rhombus, or substantially rectangular, or it may be a combination of these shapes.

[0476] The configuration shown in Figure 26B allows for high integration of the semiconductor device. Furthermore, it suppresses the loading effect. Additionally, it improves the electrical characteristics of the transistors and enhances reliability.

[0477] Figure 27A is another example of a top view of a part of the transistor group TRA of the TEG900. Figure 27A also illustrates the layout of the transistor group TRA shown in Figure 23. Figure 27A shows transistors Tr[i,j], Tr[i,j+1], Tr[i+1,j], Tr[i+1,j+1], Tr[i+2,j], and Tr[i+2,j+1] from the transistor group TRA shown in Figure 23.

[0478] The transistor group TRA shown in Figure 27A differs from the transistor group TRA shown in Figure 25A in the configuration or shape of the conductor WIR2.

[0479] As shown in Figure 27A, the conductor WIR2[i] is electrically connected to the other source and drain of transistors Tr[i,j] and Tr[i,j+1], as well as to the other source and drain of transistors Tr[i+1,j] and Tr[i+1,j+1]. In other words, the conductor WIR2[i] also functions as the conductor WIR2[i+1].

[0480] By adopting the configuration shown in Figure 27A, the spacing between adjacent transistors in the channel width direction can be narrowed. Therefore, high integration of semiconductor devices can be achieved.

[0481] Figure 27B is another example of a top view of a part of the transistor group TRA of the TEG900. Figure 27B also illustrates the layout of the transistor group TRA shown in Figure 23. Figure 27B shows transistors Tr[i,j] to Tr[i,j+2], transistors Tr[i+1,j] to Tr[i+1,j+2], and transistors Tr[i+2,j] to Tr[i+2,j+2] from the transistor group TRA shown in Figure 23.

[0482] The transistor group TRA shown in Figure 27B differs from the transistor group TRA shown in Figure 25B in the configuration or shape of the conductor WIR2. Furthermore, the transistor group TRA shown in Figure 27B differs from the transistor group TRA shown in Figure 27A in the configuration or shape of the oxide OS.

[0483] For details regarding the configuration or shape of the conductor WIR2 in the transistor group TRA shown in Figure 27B, refer to the information explained using Figure 27A. Similarly, for details regarding the configuration or shape of the oxide OS in the transistor group TRA shown in Figure 27B, refer to the information explained using Figure 25B.

[0484] Figure 28A is another example of a top view of a part of the transistor group TRA of the TEG900. Figure 28A also illustrates the layout of the transistor group TRA shown in Figure 23. Figure 28A shows transistors Tr[i,j], Tr[i,j+1], Tr[i+1,j], Tr[i+1,j+1], Tr[i+2,j], and Tr[i+2,j+1] from the transistor group TRA shown in Figure 23.

[0485] The transistor group TRA shown in Figure 28A differs from the transistor group TRA shown in Figure 27A in that it has oxide OSDs.

[0486] For details regarding the oxide OSD present in the transistor group TRA shown in Figure 28A, please refer to the information explained using Figure 26A.

[0487] Figure 28B is another example of a top view of a part of the transistor group TRA of the TEG900. Figure 28B also illustrates the layout of the transistor group TRA shown in Figure 23. Figure 28B shows transistors Tr[i,j] to Tr[i,j+2], transistors Tr[i+1,j] to Tr[i+1,j+2], and transistors Tr[i+2,j] to Tr[i+2,j+2] from the transistor group TRA shown in Figure 23.

[0488] The transistor group TRA shown in Figure 28B differs from the transistor group TRA shown in Figure 27B in that it has an oxide OSD. Furthermore, the configuration or shape of the oxide OS and oxide OSD in the transistor group TRA shown in Figure 28B differs from the transistor group TRA shown in Figure 28A.

[0489] For details regarding the configuration or shape of the oxide OS and oxide OSD in the transistor group TRA shown in Figure 28B, please refer to the information explained using Figure 26B.

[0490] The above is a description of the layout of the transistor group TRA in the TEG900, as shown in Figure 23.

[0491] The configurations and methods described in this embodiment can be implemented by appropriately combining at least a part thereof with other embodiments and other examples described herein.

[0492] (Embodiment 3) In this embodiment, one form of a semiconductor device will be described using Figures 29 to 33.

[0493] [Storage device 1] Figure 29 shows an example of a semiconductor device (memory device) according to one aspect of the present invention. In the semiconductor device according to one aspect of the present invention, transistor 200 is provided above transistor 300, and capacitive element 100 is provided above transistor 300 and transistor 200. Note that the transistor 200 can be the same transistor 200 described in the previous embodiment.

[0494] Transistor 200 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. Because transistor 200 has a small off-current, it can be used in a memory device to retain stored data for a long period of time. In other words, because refresh operations are not required, or are performed very infrequently, the power consumption of the memory device can be significantly reduced.

[0495] In the semiconductor device shown in Figure 29, wire 1001 is electrically connected to the source of transistor 300, and wire 1002 is electrically connected to the drain of transistor 300. Wire 1003 is electrically connected to one of the source and drain of transistor 200, wire 1004 is electrically connected to the first gate of transistor 200, and wire 1006 is electrically connected to the second gate of transistor 200. The gate of transistor 300 and the other of the source and drain of transistor 200 are electrically connected to one of the electrodes of capacitive element 100, and wire 1005 is electrically connected to the other electrode of capacitive element 100.

[0496] Furthermore, the memory devices shown in Figure 29 can be arranged in a matrix to form a memory cell array.

[0497] <Transistor 300> The transistor 300 is provided on a substrate 311 and has a conductor 316 that functions as a gate, an insulator 315 that functions as a gate insulator, a semiconductor region 313 that is part of the substrate 311, and low-resistance regions 314a and 314b that function as a source region or drain region. The transistor 300 may be either a p-channel type or an n-channel type.

[0498] In Figure 29, the transistor 300 has a convex shape in the semiconductor region 313 (part of the substrate 311) where the channel is formed. Furthermore, the sides and top surface of the semiconductor region 313 are covered by a conductor 316 via an insulator 315. The conductor 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. It may also have an insulator in contact with the top of the convex portion, functioning as a mask for forming the convex portion. While this example shows the formation of the convex portion by processing a part of the semiconductor substrate, a semiconductor film with a convex shape may also be formed by processing an SOI substrate.

[0499] Note that the transistor 300 shown in Figure 29 is just one example, and its structure is not limited to that; any appropriate transistor can be used depending on the circuit configuration or driving method.

[0500] <Capacitive element 100> The capacitive element 100 is provided above the transistor 200. The capacitive element 100 has a conductor 110 that functions as a first electrode, a conductor 120 that functions as a second electrode, and an insulator 130 that functions as a dielectric. Here, it is preferable to use an insulator 130 that can be used as the insulator 283 shown in the above embodiment.

[0501] Furthermore, for example, the conductor 112 provided on the conductor 240 and the conductor 110 can be formed simultaneously. The conductor 112 functions as a plug or wiring that electrically connects to the capacitive element 100, the transistor 200, or the transistor 300.

[0502] In Figure 29, the conductors 112 and 110 are shown as single-layer structures, but the configuration is not limited to this, and a laminated structure of two or more layers is also possible. For example, a conductor with high adhesion to both the barrier conductor and the highly conductive conductor may be formed between the barrier conductor and the highly conductive conductor.

[0503] Furthermore, the insulator 130 may be made of, for example, silicon oxide, silicon oxide nitride, silicon nitride, silicon oxide, aluminum oxide, aluminum oxide nitride, aluminum nitride, hafnium oxide, hafnium oxide nitride, hafnium oxide nitride, hafnium nitride, etc., and can be provided in a laminated or single layer.

[0504] For example, it is preferable to use a laminated structure of a material with high dielectric strength, such as silicon oxidnitride, and a high dielectric constant (high-k) material for the insulator 130. With this configuration, the capacitive element 100 can secure sufficient capacitance by having a high dielectric constant (high-k) insulator, and the dielectric strength is improved by having an insulator with high dielectric strength, thereby suppressing electrostatic discharge breakdown of the capacitive element 100.

[0505] High-dielectric constant (high-k) materials (materials with a high relative permittivity) include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxidized nitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxidized nitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0506] On the other hand, materials with high dielectric strength (materials with low dielectric constant) include silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, porous silicon oxide, and resins.

[0507] <Wiring layer> A wiring layer containing interlayer films, wiring, and plugs may be provided between each structure. Furthermore, multiple wiring layers may be provided depending on the design. Here, a conductor functioning as a plug or wiring may be grouped together and assigned the same reference numeral. Also, in this specification, the wiring and the plug that electrically connects to the wiring may be an integrated unit. That is, a part of the conductor may function as wiring, and a part of the conductor may function as a plug.

[0508] For example, on the transistor 300, insulators 320, 322, 324, and 326 are sequentially stacked as interlayer films. Insulators 320, 322, 324, and 326 also have embedded conductive elements such as conductors 328 and 330 that are electrically connected to the capacitive element 100 or the transistor 200. Conductors 328 and 330 function as plugs or wiring.

[0509] Furthermore, the insulator functioning as an interlayer film may also function as a planarizing film that covers the uneven shape beneath it. For example, the upper surface of the insulator 322 may be planarized by a planarizing treatment such as chemical mechanical polishing (CMP) to improve its flatness.

[0510] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in Figure 29, insulators 350, 352, and 354 are stacked in order. Conductors 356 are formed on insulators 350, 352, and 354. The conductor 356 functions as a plug or wiring.

[0511] Similarly, insulators 210, 212, 214, and 216 have conductors 218 and conductors (conductors 205) that constitute the transistor 200 embedded in them. Conductors 218 function as plugs or wires that electrically connect to the capacitive element 100 or the transistor 300. Furthermore, insulators 150 are provided on conductors 120 and insulator 130.

[0512] Here, similar to the insulator 241 shown in the above embodiment, an insulator 217 is provided in contact with the side surface of the conductor 218, which functions as a plug. The insulator 217 is provided in contact with the inner wall of the opening formed in the insulators 210, 212, 214, and 216. In other words, the insulator 217 is provided between the conductor 218 and the insulators 210, 212, 214, and 216. Note that since the conductor 205 can be formed in parallel with the conductor 218, the insulator 217 may also be formed in contact with the side surface of the conductor 205.

[0513] As the insulator 217, for example, an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide may be used. Since the insulator 217 is provided in contact with insulators 210, 212, 214, and 222, it can suppress the mixing of impurities such as water or hydrogen from insulators 210 or 216 into the oxide 230 through the conductor 218. Silicon nitride is particularly suitable because of its high blocking properties for hydrogen. In addition, it can prevent oxygen contained in insulators 210 or 216 from being absorbed by the conductor 218.

[0514] The insulator 217 can be formed in the same manner as the insulator 241. For example, silicon nitride can be deposited using the PEALD method, and an opening reaching the conductor 356 can be formed using anisotropic etching.

[0515] Insulators that can be used as interlayer films include insulating oxides, nitrides, oxidized nitrides, nitride oxides, metal oxides, metal oxidized nitrides, and metal nitride oxides.

[0516] For example, by using a material with a low dielectric constant for the insulator that functions as an interlayer film, parasitic capacitance between wiring can be reduced. Therefore, it is best to select the material according to the function of the insulator.

[0517] For example, it is preferable that insulators 150, 210, 352, and 354 have an insulator with a low dielectric constant. For example, it is preferable that the insulator has fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, porous silicon oxide, or a resin. Alternatively, it is preferable that the insulator has a laminated structure of silicon oxide, silicon oxynitride, silicon nitride, silicon oxide, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, or porous silicon oxide, and a resin. Since silicon oxide and silicon oxynitride are thermally stable, combining them with a resin can create a thermally stable laminated structure with a low dielectric constant. Examples of resins include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, or acrylic.

[0518] Furthermore, the electrical characteristics of a transistor using an oxide semiconductor can be stabilized by surrounding it with an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen. Therefore, insulators 214, 212, and 350 should be insulators that have the function of suppressing the permeation of impurities such as hydrogen and oxygen.

[0519] As an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or in a multilayer structure. Specifically, as an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, silicon nitride or silicon nitride, etc., can be used.

[0520] Conductors that can be used for wiring and plugs may include materials containing one or more metallic elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. Alternatively, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements like phosphorus, or silicides such as nickel silicide may be used.

[0521] For example, conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials formed from the above materials can be used as conductors 328, 330, 356, 218, and 112, either in a single layer or in a laminated form. It is preferable to use high-melting-point materials such as tungsten or molybdenum that provide both heat resistance and conductivity, with tungsten being preferable. Alternatively, it is preferable to form them from low-resistance conductive materials such as aluminum or copper. Using low-resistance conductive materials can reduce wiring resistance.

[0522] <Wiring or plugs in layers containing oxide semiconductors> Furthermore, when an oxide semiconductor is used in the transistor 200, an insulator having an excess oxygen region may be provided near the oxide semiconductor. In that case, it is preferable to provide a barrier insulator between the insulator having the excess oxygen region and the conductor provided on the insulator having the excess oxygen region.

[0523] For example, in Figure 29, an insulator 241 may be provided between the insulator 280 having excess oxygen and the conductor 240. By providing the insulator 241 in contact with the insulators 222, 282, and 283, the transistor 200 can be configured to be sealed by a barrier-type insulator.

[0524] In other words, by providing the insulator 241, the absorption of excess oxygen in the insulator 280 into the conductor 240 can be suppressed. Furthermore, the presence of the insulator 241 can suppress the diffusion of hydrogen, an impurity, into the transistor 200 via the conductor 240.

[0525] Furthermore, as the insulator 241, an insulating material having the function of suppressing the diffusion of impurities such as water or hydrogen, and oxygen, is preferable. For example, silicon nitride, silicon oxide nitride, aluminum oxide, or hafnium oxide are preferred. Silicon nitride is particularly preferred because of its high blocking properties for hydrogen. In addition, other materials such as metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide can also be used.

[0526] Furthermore, as shown in the above embodiment, the transistor 200 may be configured to be sealed with insulators 212, 214, 282, and 283. This configuration reduces the amount of hydrogen contained in insulators 274, 150, etc., that mixes into insulator 280, etc.

[0527] Here, the conductor 240 penetrates insulators 283 and 282, and the conductor 218 penetrates insulators 214 and 212. However, as described above, insulator 241 is provided in contact with conductor 240, and insulator 217 is provided in contact with conductor 218. This reduces the amount of hydrogen that enters the inside of insulators 212, 214, 282, and 283 via conductors 240 and 218. In this way, the transistor 200 is sealed with insulators 212, 214, 282, 283, 241, and 217, reducing the amount of impurities such as hydrogen contained in insulator 274, etc., that enter from the outside.

[0528] <Dicing line> The following describes dicing lines (sometimes called scribe lines, division lines, or cutting lines) that are provided when extracting multiple semiconductor devices as chips by dividing a large-area substrate into individual semiconductor elements. One method of division is to first form grooves (dicing lines) in the substrate to divide the semiconductor elements, and then cut along the dicing lines to divide (divide) the substrate into multiple semiconductor devices.

[0529] Here, for example, as shown in Figure 29, it is preferable to design the region where insulator 283 and insulator 214 are in contact to overlap with the dicing line. In other words, openings are provided in insulators 282, 280, 275, 222, and 216 near the region that will become the dicing line provided on the outer edge of the memory cell having multiple transistors 200.

[0530] In other words, in the openings provided in insulators 282, 280, 275, 222, and 216, insulator 214 and insulator 283 are in contact.

[0531] Furthermore, for example, openings may be provided in insulators 282, 280, 275, 222, 216, and 214. With this configuration, insulator 212 and insulator 283 come into contact at the openings provided in insulators 282, 280, 275, 222, 216, and 214. In this case, insulators 212 and 283 may be formed using the same material and method. By forming insulators 212 and 283 using the same material and method, adhesion can be improved. For example, silicon nitride is preferable.

[0532] This structure allows the transistor 200 to be enclosed by insulators 212, 214, 282, and 283. Since at least one of insulators 212, 214, 282, and 283 has the function of suppressing the diffusion of oxygen, hydrogen, and water, even if the substrate is divided into multiple chips for each circuit region on which the semiconductor element shown in this embodiment is formed, it is possible to prevent impurities such as hydrogen or water from entering from the side of the divided substrate and diffusing into the transistor 200.

[0533] Furthermore, this structure prevents excess oxygen from insulators 280 and 224 from diffusing to the outside. Therefore, excess oxygen from insulators 280 and 224 is efficiently supplied to the oxide in which the channel in transistor 200 is formed. This oxygen reduces oxygen vacancies in the oxide in which the channel in transistor 200 is formed. As a result, the oxide in which the channel in transistor 200 is formed can be made into an oxide semiconductor with a low defect level density and stable properties. In other words, fluctuations in the electrical properties of transistor 200 can be suppressed and reliability can be improved.

[0534] In the memory device shown in Figure 29, the capacitive element 100 is of the planar type, but the memory device shown in this embodiment is not limited to this. For example, as shown in Figure 30, the capacitive element 100 may be of the cylindrical type. In the memory device shown in Figure 30, the configuration below the insulator 150 is the same as that of the semiconductor device shown in Figure 29.

[0535] The capacitive element 100 shown in Figure 30 includes an insulator 150 on an insulator 130, an insulator 142 on an insulator 150, a conductor 115 disposed in an opening formed in the insulators 150 and 142, an insulator 145 on the conductor 115 and 142, a conductor 125 on the insulator 145, and an insulator 152 on the conductor 125 and 145. Here, at least a portion of the conductor 115, the insulator 145, and the conductor 125 are disposed in the opening formed in the insulators 150 and 142.

[0536] The conductor 115 functions as the lower electrode of the capacitive element 100, the conductor 125 functions as the upper electrode of the capacitive element 100, and the insulator 145 functions as the dielectric of the capacitive element 100. In the openings of the insulators 150 and 142, the upper electrode and the lower electrode face each other with the dielectric in between, not only on the bottom surface but also on the sides, allowing for a large capacitance per unit area. Therefore, the deeper the opening, the larger the capacitance of the capacitive element 100 can be. By increasing the capacitance per unit area of ​​the capacitive element 100 in this way, miniaturization or high integration of semiconductor devices can be promoted.

[0537] The insulator 152 may be any insulator that can be used for the insulator 280. Furthermore, the insulator 142 preferably functions as an etching stopper when forming the opening in the insulator 150, and may be any insulator that can be used for the insulator 214.

[0538] The shape of the openings formed in the insulators 150 and 142 when viewed from above may be a rectangle, a polygon other than a rectangle, a polygon with curved corners, or a circle including an ellipse. In this case, it is preferable that the area overlapping between the opening and the transistor 200 is large when viewed from above. By adopting such a configuration, the occupied area of ​​the semiconductor device having the capacitive element 100 and the transistor 200 can be reduced.

[0539] The conductor 115 is positioned in contact with the openings formed in the insulators 142 and 150. Preferably, the upper surface of the conductor 115 is approximately the same as the upper surface of the insulator 142. The lower surface of the conductor 115 is in contact with the conductor 110 through the opening in the insulator 130. The conductor 115 is preferably formed using the ALD method or the CVD method, and for example, any conductor that can be used for the conductor 205 may be used.

[0540] The insulator 145 is arranged to cover the conductor 115 and the insulator 142. For example, it is preferable to deposit the insulator 145 using the ALD method or the CVD method. The insulator 145 can be made of, for example, silicon oxide, silicon oxide nitride, silicon nitride, silicon, zirconium oxide, aluminum oxide, aluminum oxide nitride, aluminum oxide nitride, aluminum nitride, hafnium oxide, hafnium oxide nitride, hafnium nitride, hafnium oxide, hafnium nitride, etc., and can be provided in a laminated or single layer. For example, as the insulator 145, an insulating film laminated in the order of zirconium oxide, aluminum oxide, and zirconium oxide can be used.

[0541] Furthermore, it is preferable to use a material with high dielectric strength, such as silicon oxidative nitride, or a high dielectric constant (high-k) material for the insulator 145. Alternatively, a laminated structure of a material with high dielectric strength and a high dielectric constant (high-k) material may be used.

[0542] High-k dielectric materials (materials with a high relative permittivity) include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxidized nitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxidized nitrides containing silicon and hafnium, and nitrides containing silicon and hafnium. By using such high-k materials, the capacitance of the capacitive element 100 can be sufficiently secured even if the insulator 145 is made thicker. By making the insulator 145 thicker, the leakage current generated between the conductor 115 and the conductor 125 can be suppressed.

[0543] On the other hand, materials with high dielectric strength include silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, porous silicon oxide, and resins. For example, silicon nitride (SiN) deposited using the PEALD method. x ), silicon oxide (SiO2) deposited using the PEALD method x ), silicon nitride (SiN) deposited using the PEALD method x An insulating film can be used that is laminated in the order of zirconium oxide, silicon oxide deposited by the ALD method, and zirconium oxide. Alternatively, an insulating film can be used that is laminated in the order of zirconium oxide, silicon oxide deposited by the ALD method, and zirconium oxide. By using such an insulator with high dielectric strength, the dielectric strength is improved and electrostatic discharge breakdown of the capacitive element 100 can be suppressed.

[0544] The conductor 125 is positioned to fill the openings formed in the insulators 142 and 150. The conductor 125 is also electrically connected to the wiring 1005 via the conductors 140 and 153. The conductor 125 is preferably formed using the ALD method or the CVD method, and for example, any conductor that can be used for the conductor 205 may be used.

[0545] Furthermore, the conductor 153 is provided on the insulator 154 and covered by the insulator 156. The conductor 153 may be any conductor that can be used for the conductor 112, and the insulator 156 may be any insulator that can be used for the insulator 152. Here, the conductor 153 is in contact with the upper surface of the conductor 140 and functions as a terminal of the capacitive element 100, the transistor 200, or the transistor 300.

[0546] [Storage device 2] An example of a semiconductor device (memory device) according to one aspect of the present invention is shown in Figure 31.

[0547] <Example of memory device configuration> Figure 31 is a cross-sectional view of a semiconductor device having a memory device 290. The memory device 290 shown in Figure 31 has a capacitive device 292 in addition to the transistors 200 shown in Figures 1A to 1D. Figure 31 corresponds to a cross-sectional view of the transistor 200 in the channel length direction.

[0548] The capacitive device 292 comprises a conductor 242b, an insulator 271b provided on the conductor 242b, an insulator 275 provided in contact with the upper surface of the insulator 271b, the side surface of the insulator 271b, and the side surface of the conductor 242b, and a conductor 294 on the insulator 275. In other words, the capacitive device 292 constitutes a MIM (Metal-Insulator-Metal) capacitor. One of the pair of electrodes of the capacitive device 292, i.e., the conductor 242b, can also serve as the source electrode of the transistor. Furthermore, the dielectric layer of the capacitive device 292 can also serve as the protective layer provided on the transistor, i.e., the insulator 271 and the insulator 275. Therefore, since part of the transistor manufacturing process can be shared in the manufacturing process of the capacitive device 292, a highly productive semiconductor device can be produced. Furthermore, since one of the pair of electrodes of the capacitive device 292, namely the conductor 242b, also serves as the source electrode of the transistor, it is possible to reduce the area required for the placement of the transistor and the capacitive device.

[0549] For example, the conductor 294 can be any material that can be used for the conductor 242.

[0550] <Examples of memory devices> In the following, using Figures 32A, 32B, and 33, an example of a semiconductor device having a transistor 200 and a capacitive device 292 according to one aspect of the present invention, different from that shown in the previous <Example of Memory Device Configuration>, will be described. In the semiconductor device shown in Figures 32A, 32B, and 33, structures having the same function as those constituting the semiconductor device shown in the previous embodiment and <Example of Memory Device Configuration> (see Figure 31) will be denoted by the same reference numerals. In this section, the materials used for the transistor 200 and the capacitive device 292 are those described in detail in the previous embodiment and <Example of Memory Device Configuration>. Also, in Figures 32A, 32B, and 33, the memory device shown in Figure 31 is used as the memory device, but the invention is not limited to this.

[0551] <<Differential Example of Memory Device 1>> In the following, an example of a semiconductor device 600 having transistors 200a, 200b, capacitive device 292a, and capacitive device 292b according to one aspect of the present invention will be described with reference to Figure 32A.

[0552] Figure 32A is a cross-sectional view in the channel length direction of a semiconductor device 600 having transistors 200a, 200b, capacitive devices 292a, and 292b. Here, the capacitive device 292a has a conductor 242a, an insulator 271a on the conductor 242a, an insulator 275 in contact with the upper surface of the insulator 271a, the side surface of the insulator 271a, and the side surface of the conductor 242a, and a conductor 294a on the insulator 275. The capacitive device 292b has a conductor 242b, an insulator 271b on the conductor 242b, an insulator 275 in contact with the upper surface of the insulator 271b, the side surface of the insulator 271b, and the side surface of the conductor 242b, and a conductor 294b on the insulator 275.

[0553] As shown in Figure 32A, the semiconductor device 600 has a symmetrical configuration with respect to the dashed line A3-A4 as the axis of symmetry. One of the source or drain electrodes of transistor 200a and one of the source or drain electrodes of transistor 200b are combined by the conductor 242c. An insulator 271c is provided on the conductor 242c. Furthermore, the conductor 240, which functions as a plug, serves to connect the conductor 246, which functions as wiring, to transistor 200a, and also connect the conductor 246, which functions as wiring, to transistor 200b. In this way, by using the above configuration for the connections between the two transistors, two capacitive devices, wiring, and plug, a semiconductor device that can be miniaturized or highly integrated can be provided.

[0554] The configurations and effects of transistors 200a, 200b, capacitive device 292a, and 292b can be seen in the example semiconductor device configuration shown in Figure 31.

[0555] <<Modified Memory Device 2>> In the above, transistors 200a, 200b, capacitive device 292a, and capacitive device 292b were given as examples of semiconductor device configurations, but the semiconductor device shown in this embodiment is not limited to these. For example, as shown in Figure 32B, a semiconductor device 600 and a semiconductor device having a similar configuration to semiconductor device 600 may be connected via a capacitive section. In this specification, a semiconductor device having transistors 200a, 200b, capacitive device 292a, and capacitive device 292b is referred to as a cell. The configurations of transistors 200a, 200b, capacitive device 292a, and capacitive device 292b can be considered in the above-mentioned descriptions relating to transistors 200a, 200b, capacitive device 292a, and capacitive device 292b.

[0556] Figure 32B is a cross-sectional view showing a semiconductor device 600 having transistors 200a and 200b, a capacitive device 292a, and a capacitive device 292b, and a cell having a similar configuration to the semiconductor device 600, connected via a capacitive section.

[0557] As shown in Figure 32B, the conductor 294b, which functions as one electrode of the capacitive device 292b of semiconductor device 600, also serves as one electrode of the capacitive device of semiconductor device 601, which has a similar configuration to semiconductor device 600. Although not shown, the conductor 294a, which functions as one electrode of the capacitive device 292a of semiconductor device 600, also serves as one electrode of the capacitive device of the semiconductor device adjacent to the left side of semiconductor device 600, i.e., in the A1 direction in Figure 32B. The same configuration applies to the cells on the right side of semiconductor device 601, i.e., in the A2 direction in Figure 32B. In other words, a cell array (also called a memory device layer) can be formed. This cell array configuration allows for smaller spacing between adjacent cells, thereby reducing the projected area of ​​the cell array and enabling high integration. Furthermore, by arranging the cell array configuration shown in Figure 32B in a matrix, a matrix-shaped cell array can be formed.

[0558] As described above, by forming transistors 200a, 200b, capacitive devices 292a, and 292b with the configuration shown in this embodiment, the cell area can be reduced, and the semiconductor device having a cell array can be miniaturized or highly integrated.

[0559] Furthermore, the cell array may be configured not only in a planar manner but also in a stacked configuration. Figure 33 shows a cross-sectional view of a configuration in which n layers of cell array 610 are stacked. As shown in Figure 33, by stacking multiple cell arrays (cell array 610_1 to cell array 610_n), cells can be accumulated and arranged without increasing the occupied area of ​​the cell array. In other words, a 3D cell array can be constructed.

[0560] The configurations and methods described in this embodiment can be implemented by appropriately combining at least a part thereof with other embodiments and other examples described herein.

[0561] (Embodiment 4) In this embodiment, a transistor using an oxide as a semiconductor (hereinafter sometimes referred to as an OS transistor) and a memory device to which a capacitive element is applied (hereinafter sometimes referred to as an OS memory device) according to one aspect of the present invention will be described with reference to Figures 34A, 34B and 35A to 35H. The OS memory device is a memory device having at least a capacitive element and an OS transistor that controls the charging and discharging of the capacitive element. Because the off-current of the OS transistor is extremely small, the OS memory device has excellent retention characteristics and can function as a non-volatile memory.

[0562] <Example of storage device configuration> Figure 34A shows an example of the configuration of an OS memory device. The storage device 1400 has peripheral circuits 1411 and a memory cell array 1470. The peripheral circuits 1411 have row circuits 1420, column circuits 1430, output circuits 1440, and control logic circuits 1460.

[0563] The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, a write circuit, etc. The precharge circuit has the function of precharging the wiring. The sense amplifier has the function of amplifying the data signal read from the memory cell. The above wiring is connected to the memory cells of the memory cell array 1470, and will be described in more detail later. The amplified data signal is output to the outside of the storage device 1400 as the data signal RDATA via the output circuit 1440. The row circuit 1420 includes, for example, a row decoder, a word line driver circuit, etc., and can select the row to access.

[0564] The storage device 1400 is supplied with a low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 from an external source. The storage device 1400 also receives control signals (CE, WE, RES), an address signal ADDR, and a data signal WDATA from an external source. The address signal ADDR is input to the row decoder and column decoder, and the data signal WDATA is input to the write circuit.

[0565] The control logic circuit 1460 processes externally input control signals (CE, WE, RES) to generate control signals for the row decoder and column decoder. Control signal CE is the chip enable signal, control signal WE is the write enable signal, and control signal RES is the read enable signal. The signals processed by the control logic circuit 1460 are not limited to these; other control signals may be input as needed.

[0566] The memory cell array 1470 has multiple memory cells MC arranged in a matrix and multiple wirings. The number of wirings connecting the memory cell array 1470 to the row circuit 1420 is determined by the configuration of the memory cells MC and the number of memory cells MC in each row. Similarly, the number of wirings connecting the memory cell array 1470 to the column circuit 1430 is determined by the configuration of the memory cells MC and the number of memory cells MC in each row.

[0567] Although Figure 34A shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane, this embodiment is not limited to this. For example, as shown in Figure 34B, the memory cell array 1470 may be provided so as to overlap a part of the peripheral circuit 1411. For example, a sense amplifier may be provided so as to overlap the memory cell array 1470.

[0568] Figures 35A to 35H illustrate examples of memory cell configurations applicable to the above-mentioned memory cell MC.

[0569] [DOSRAM] Figures 35A to 35C show examples of the circuit configuration of a DRAM memory cell. In this specification, a DRAM using a 1OS transistor, 1 capacitance element type memory cell is sometimes referred to as DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 1471 shown in Figure 35A has a transistor M1 and a capacitance element CA. The transistor M1 has a gate (sometimes called a top gate) and a back gate.

[0570] The first terminal of transistor M1 is connected to the first terminal of capacitive element CA, the second terminal of transistor M1 is connected to wiring BIL, the gate of transistor M1 is connected to wiring WOL, and the back gate of transistor M1 is connected to wiring BGL. The second terminal of capacitive element CA is connected to wiring LL.

[0571] Wiring BIL functions as a bit line, and wiring WOL functions as a word line. Wiring LL functions as wiring for applying a predetermined potential to the second terminal of the capacitive element CA. During data writing and reading, wiring LL may be at ground potential or low-level potential. Wiring BGL functions as wiring for applying a potential to the back gate of transistor M1. By applying an arbitrary potential to wiring BGL, the threshold voltage of transistor M1 can be increased or decreased.

[0572] Here, the memory cell 1471 shown in Figure 35A corresponds to the memory device shown in Figure 31. In other words, transistor M1 corresponds to transistor 200, and capacitive element CA corresponds to capacit...

Claims

1. It comprises a first layer, a second layer on the first layer, a first wiring, a second wiring, and a third wiring. The first layer comprises a first multiplexer, a second multiplexer, and first to fourth analog switches. The second layer has first to fourth transistors, Each of the first to fourth transistors has a source, a drain, and a first gate. The first wiring is electrically connected to either the source or the drain of each of the first to fourth transistors. The first terminals of the first analog switch and the second analog switch are electrically connected to the first multiplexer. The second terminals of the first analog switch and the second analog switch are electrically connected to the second wiring. The third terminal of the first analog switch is electrically connected to the other end of the source and drain of the first transistor and the second transistor, respectively. The third terminal of the second analog switch is electrically connected to the other source and drain of the third transistor and the fourth transistor, respectively. The first terminals of the third analog switch and the fourth analog switch are electrically connected to the second multiplexer. The second terminals of the third analog switch and the fourth analog switch are electrically connected to the third wiring. The third terminal of the third analog switch is electrically connected to the first gate of the first transistor and the first gate of the third transistor, The third terminal of the fourth analog switch is electrically connected to the first gate of the second transistor and the fourth transistor, respectively. Semiconductor equipment.

2. In claim 1, It further has a fourth wiring, Each of the first to fourth transistors further has a second gate, The fourth wiring is electrically connected to the second gate of each of the first to fourth transistors. Semiconductor equipment.

3. In claim 1 or claim 2, Each of the first to fourth transistors has a metal oxide in the channel formation region. Semiconductor equipment.

4. In claim 3, The aforementioned metal oxide comprises indium, gallium, and zinc. Semiconductor equipment.

5. In claim 1 or claim 2, Each of the first to fourth analog switches is composed of a CMOS circuit. Semiconductor equipment.

6. In claim 5, The transistor in the CMOS circuit has silicon in the channel formation region. Semiconductor equipment.

7. It comprises a first layer, a second layer on the first layer, a first wiring, a second wiring, and a third wiring. The first layer comprises a first multiplexer, a second multiplexer, and first to third analog switches. The second layer has a first transistor and a third transistor, Each of the first transistor and the third transistor has a source, a drain, and a first gate. The first wiring is electrically connected to one of the sources and drains of the first transistor and the third transistor, The first terminals of the first analog switch and the second analog switch are electrically connected to the first multiplexer. The second terminals of the first analog switch and the second analog switch are electrically connected to the second wiring. The third terminal of the first analog switch is electrically connected to the other of the source and drain of the first transistor. The third terminal of the second analog switch is electrically connected to the other of the source and drain of the third transistor. The first terminal of the third analog switch is electrically connected to the second multiplexer. The second terminal of the third analog switch is electrically connected to the third wiring. The third terminal of the third analog switch is electrically connected to the first gate of the first transistor and the first gate of the third transistor, respectively. Semiconductor equipment.

8. In claim 7, It further has a fourth wiring, Each of the first transistor and the third transistor further has a second gate, The fourth wiring is electrically connected to the second gates of the first transistor and the third transistor, respectively. Semiconductor equipment.

9. In claim 7 or claim 8, Each of the first and third transistors has a metal oxide in the channel formation region. Semiconductor equipment.

10. In claim 9, The aforementioned metal oxide comprises indium, gallium, and zinc. Semiconductor equipment.

11. In claim 7 or claim 8, Each of the first to third analog switches is composed of a CMOS circuit. Semiconductor equipment.

12. In claim 11, The transistor in the CMOS circuit has silicon in the channel formation region. Semiconductor equipment.

13. It comprises a first layer, a second layer on the first layer, a first wiring, a second wiring, and a third wiring. The first layer comprises a first multiplexer, a second multiplexer, a first analog switch, a third analog switch, and a fourth analog switch. The aforementioned second layer has a first transistor and a second transistor, Each of the first transistor and the second transistor has a source, a drain, and a first gate. The first wiring is electrically connected to either the source or the drain of the first transistor and the second transistor, The first terminal of the first analog switch is electrically connected to the first multiplexer. The second terminal of the first analog switch is electrically connected to the second wiring. The third terminal of the first analog switch is electrically connected to the other end of the source and drain of the first transistor and the second transistor, respectively. The first terminals of the third analog switch and the fourth analog switch are electrically connected to the second multiplexer. The second terminals of the third analog switch and the fourth analog switch are electrically connected to the third wiring. The third terminal of the third analog switch is electrically connected to the first gate of the first transistor. The third terminal of the fourth analog switch is electrically connected to the first gate of the second transistor. Semiconductor equipment.

14. In claim 13, It further has a fourth wiring, Each of the first transistor and the second transistor further has a second gate, The fourth wiring is electrically connected to the second gate of the first transistor and the second transistor, respectively. Semiconductor equipment.

15. In claim 13 or claim 14, Each of the first transistor and the second transistor has a metal oxide in the channel formation region. Semiconductor equipment.

16. In claim 15, The aforementioned metal oxide comprises indium, gallium, and zinc. Semiconductor equipment.

17. In claim 13 or claim 14, Each of the first analog switch, the third analog switch, and the fourth analog switch is composed of a CMOS circuit. Semiconductor equipment.

18. In claim 17, The transistor in the CMOS circuit has silicon in the channel formation region. Semiconductor equipment.

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