A memory system combining high-density, low-bandwidth memory and low-density, high-bandwidth memory.

Abstract

To provide an electronic system including a DRAM.SOLUTION: A memory system 10 includes at least two types of DRAMs, which differ in at least one characteristic. For example, one DRAM type may be a high density DRAM, while the other DRAM type may have lower density but may also have lower latency and higher bandwidth than a first DRAM type. The DRAM of the first type may be on one or more first integrated circuits, and the DRAM of a second type may be on one or more second integrated circuits. The first and second integrated circuits may be coupled to each other in a stack. The second integrated circuit may include a physical layer circuit to couple to other circuits (for example, an integrated circuit having a memory controller, such as a system on a chip(SOC)), and the physical layer circuit may be shared by the DRAM in the first integrated circuits.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The embodiments described herein relate to an electronic system including a dynamic random access memory (DRAM).

Background Art

[0002] As DRAM continues to evolve, the design of DRAM has become more complex due to different ideal objectives of DRAM, such as high bandwidth, large capacity, and high-density storage with low power consumption (high energy efficiency). Design choices to improve density / capacity tend to reduce (or at least not increase) the bandwidth. Design choices that can increase the bandwidth tend to reduce (or at least not increase) the capacity and energy efficiency.

Summary of the Invention

[0003] In one embodiment, a memory system can include at least two types of DRAM with at least one different characteristic. For example, one type of DRAM can be high-density DRAM, while the other type of DRAM can have a lower density than the one type of DRAM but also have lower latency and higher bandwidth. The first type of DRAM can be in one or more first integrated circuits, and the second type of DRAM can be in one or more second integrated circuits. By providing a memory system with two types of DRAM (e.g., one high-density and one low-latency, high-bandwidth), very energy-efficient operation can be enabled, thereby fabricating a memory system suitable for portable devices and other devices where energy efficiency and performance per unit of energy consumed are important attributes.

[0004] In one embodiment, the first integrated circuit and the second integrated circuit can be connected to each other in a stack. The second integrated circuit may include a physical layer circuit for connecting to other circuits (e.g., an integrated circuit having a memory controller, such as a system-on-a-chip (SOC)), and this physical layer circuit may be shared by the DRAM of the first integrated circuit. In some embodiments, this memory can be used to achieve high energy efficiency, large capacity, and low latency. For further details, please refer to the attached diagrams briefly described below. [Brief explanation of the drawing]

[0005] [Figure 1] This is a block diagram of one embodiment of a system on a chip (SOC) having a memory controller and physical layer circuits for main memory and cache memory. [Figure 2] This is a block diagram of another embodiment of a SOC having a memory controller and physical layer circuit to a cache memory, which includes another physical layer circuit from the cache memory to the main memory. [Figure 3] This is a block diagram of another embodiment having a main memory and another physical layer circuit comprising a memory controller and physical layer circuit to the cache memory, and another physical layer circuit from the cache memory to the main memory. [Figure 4] Block diagram showing a system-on-a-chip (SOC) and memory for one embodiment. [Figure 5] Block diagram showing an SOC including one or more caches for one embodiment, and main memory connected to the SOC / cache. [Figure 6] Block diagram showing an SOC and multiple memories for one embodiment. [Figure 7] Block diagram showing an SOC containing one or more caches and multiple main memory modules for one embodiment. [Figure 8]This is a block diagram of one embodiment of a system having main memory and cache memory in a package-on-package (POP) configuration. [Figure 9] This is a block diagram of another embodiment of a system having main memory and cache memory in a package-on-package (POP) configuration. [Figure 10] This is a block diagram of one embodiment of a system having main memory and cache memory, wherein the main memory is packaged separately. [Figure 11] This is a block diagram of another embodiment of a system having main memory and cache memory, wherein the main memory is packaged separately. [Figure 12] This is a block diagram of one embodiment of a system including a cache and main memory dynamic random access memory (DRAM). [Figure 13] This is a block diagram of another embodiment of this system. [Figure 14] This is a block diagram of yet another embodiment of this system. [Modes for carrying out the invention]

[0006] The embodiments described in this disclosure may be subject to various modifications and alternative forms, the specific embodiments of which are shown in the drawings as examples and described in detail herein. However, it should be understood that the drawings and the detailed description relating to them are not intended to limit the embodiments to any particular form disclosed, but rather to cover all modifications, equivalents, and alternative forms that fall within the spirit and scope of the appended claims. The titles used herein are for structural purposes only and are not intended to limit the scope of the description. When used throughout this application, the words “may” are used in an allowable sense (i.e., meaning there is a possibility of doing so) rather than an obligatory sense (i.e., meaning it must be done). Similarly, the words “include,” “including,” and “includes” mean “including, but not limited to.”

[0007] Within this disclosure, various entities (which may be referred to in various ways, such as “Units,” “Circuits,” or other components) may be described or claimed as “configured” to perform one or more tasks or operations. This explicit phrase, “entity” configured to perform one or more tasks, is used herein to refer to structures (i.e., physical things such as electronic circuits). More specifically, this explicit phrase is used to indicate that the structure is arranged to perform one or more tasks while in operation. A structure may be said to be “configured” to perform some task even when the structure is not currently in operation. “A clock circuit configured to generate an output clock signal” is intended to cover circuits that perform this function while in operation even when the circuit is not currently in use (e.g., no power is connected to the circuit). Thus, entities described or presented as “configured” to perform some task refer to physical things such as devices, circuits, or memory storing program instructions that are executable to implement that task. This phrase is not used herein to refer to intangible things. Generally, circuits that form a structure corresponding to "configured to..." may include hardware circuits. Hardware circuits can include any combination of combinational logic circuits, clocked memory devices such as flops, registers, and latches, finite state machines, memory such as static random access memory or embedded dynamic random access memory, custom-designed circuits, analog circuits, and programmable logic arrays. Similarly, various units / circuits / components may be described as performing a task(s) for the sake of simplicity of explanation. Such descriptions should be interpreted as including the phrase "configured to...".

[0008] The term "configured to" is not intended to mean "configurable to." For example, an unprogrammed FPGA may be "configurable to" perform some particular function, but it would not be considered "configured to" perform that function. After proper programming, the FPGA can be configured to perform that function, in that case.

[0009] Any claims in the appendix relating to a unit / circuit / component or other structure configured to perform one or more tasks are expressly intended not to invoke the interpretation of Section 112(f) of the U.S. Patent Act with respect to the claim element. Therefore, none of the claims filed in this application are intended to be interpreted as having a means-plus-function element. If the applicant wishes to invoke Section 112(f) during the examination process, it would do so by using the construct “means for” [to perform the function].

[0010] In one embodiment, the hardware circuit according to this disclosure may be implemented by coding the circuit description in a hardware description language (HDL), such as Verilog or VHDL. The HDL description may be synthesized against a library of cells designed for a given integrated circuit manufacturing technique, modified for timing, power, and other reasons, resulting in a final design database that can be sent to a foundry to generate a mask and ultimately manufacture an integrated circuit. Some hardware circuits or parts thereof may also be custom designed in a schematic editor and incorporated into the integrated circuit design along with the synthesized circuit. The integrated circuit may include transistors, and may further include other circuit elements (e.g., passive elements such as capacitors, resistors, and inductors), and interconnections between transistors and circuit elements. Some embodiments may implement multiple integrated circuits connected integrally to realize the hardware circuit, and / or, in some embodiments, discrete elements may be used. Alternatively, the HDL design may be integrated into a programmable logic array, such as a field programmable gate array (FPGA), and may be implemented on an FPGA.

[0011] As used herein, the terms “based on” or “dependent on” are used to describe one or more factors that influence a determination. These terms do not exclude the possibility that additional factors may influence the determination; that is, the determination may be based on the specified factors alone, or on the specified factors plus other unspecified factors. Consider the phrase “determine A based on B.” This phrase specifies that B is a factor used to determine A or that influences the determination of A. This phrase does not exclude the possibility that the determination of A may also be based on some other factor, such as C. This phrase is intended to cover embodiments in which A is determined solely on B. As used herein, the phrase “based on” is synonymous with the phrase “based at least in part on.”

[0012] To indicate that this disclosure is not intended to refer to any particular implementation, but rather to refer to a range of embodiments that fall within the spirit of this disclosure, including the appended claims, this specification includes references to various embodiments. Certain features, structures, or characteristics may be combined in any suitable manner consistent with this disclosure.

[0013] Referring now to Figure 1, a block diagram of one embodiment of a system including a memory system 10 and an integrated circuit 12 is shown. In the illustrated embodiment, the integrated circuit 12 is a system-on-a-chip (SOC), and in other embodiments of this disclosure, an SOC is used as an example. However, any integrated circuit can be used in various embodiments. In the embodiment of Figure 1, the memory 10 includes a plurality of main DRAM chips (DRAMs) 16A to 16D and a cache DRAM 18. The main DRAMs 16A to 16D include physical layer circuits (PHYs) 60A, and the cache DRAM 18 includes a PHY 60B. PHY 60A is connected to PHY 60C in the SOC 12, and PHY 60B is connected to PHY 60D in the SOC 12. More specifically, PHY 60C may be connected to a main memory controller (MC) block 28A, and PHY 60D may be connected to a cache controller block (CC) 28B, both of which may be part of the memory controller 28 (Mem) in Figure 1.

[0014] The memory system 10 may include two different types of DRAM, and the memory controller 28 of the SOC 12 can independently control the main DRAMs 16A-16D and the cache DRAM 18. The combination of the main DRAMs 16A-16D and the cache DRAM 18 provides high bandwidth to the memory agent of the SOC 12, and can also provide overall large storage capacity and low power consumption. The storage capacity can be provided by the main DRAMs 16A-16D, which may have memory designed for density and capacity. The high bandwidth can be provided by a wide interface between the cache DRAM 18 and the SOC 12. A wider interface allows for clock control at slower clock speeds, saving power compared to the fast, narrow interface of conventional synchronous DRAMs. In one embodiment, the interfaces between the cache DRAM 18 and the SOC 12, and between the main DRAMs 16A-16D and the SOC 12 may have different widths (for example, the cache DRAM 18 may have an interface more than twice as wide as the main DRAMs 16A-16D, and in some embodiments, it may be 2-4 times wider). Furthermore, the cache DRAM 18 may include a relatively small memory array that has a lower density but can achieve higher bandwidth with less energy. For example, the memory array may have more banks, a smaller page size, lower latency, more channels, etc., compared to conventional DRAMs or DRAMs 16A-16D. In some embodiments, to reduce power consumption, the memory array may include one or more of the following compared to similar characteristics of DRAMs 16A-16D: fewer memory cells per bit line, fewer memory cells per word line, and / or smaller banks. More specifically, in one embodiment, the memory array of the cache DRAM 18 can trade off a lower density than the main DRAMs 16A to 16D in order to reduce energy consumption.Lower density can be achieved in the cache DRAM 18 by one or more of the following (compared to the main DRAMs 16A-16D): fewer memory cells per bit line, fewer memory cells per word line, more banks, and / or smaller banks. In one embodiment, the cache DRAM 18 may have a memory array that is 4 to 16 times lower in density than the memory arrays of the main DRAMs 16A-16D, preferably 6 to 8 times lower in density. The data path design within the banks and the data path design from the banks to the PHY 60B can be optimized. Furthermore, the data path from the cache DRAM 18 to the SOC 12 may be a point-to-point, low-capacitance, low-voltage connection.

[0015] When two types of DRAM form a memory system, in some embodiments, one of them can be optimized for bandwidth and the other for capacity, thereby achieving both the objectives of increased bandwidth and increased capacity. Furthermore, energy efficiency can be managed in the high-bandwidth portion of the memory (which can be smaller in capacity / smaller in size and therefore have a lower density). The portion of the memory optimized for capacity can have the objectives of lower bandwidth and slower (longer) latency, because these objectives can be achieved by the portion optimized for bandwidth. Similarly, the portion of the memory optimized for bandwidth can have the objective of lower area efficiency, but can improve latency and energy efficiency. In some embodiments, overall, a high-bandwidth, low-latency, energy-efficient, and high-capacity memory system can be realized at low cost. In particular, by implementing the high-density portion (main DRAM 16A-16D) and the high-bandwidth, low-latency portion (cache DRAM 18) together on separate chips that form the main memory system 10, it becomes possible to improve the energy efficiency of each memory 16A-16D and 18, thereby providing a high-performance, high-bandwidth, and highly energy-efficient memory solution. Specific optimizations that can be performed on each memory in various embodiments will be described in more detail below with reference to Figures 12-14.

[0016] In one embodiment, the cache DRAM 18 can implement a simplified command set to reduce the number of commands sent to the cache DRAM 18 for each access. For example, the main DRAMs 16A-16D may include an active command, a column address strobe (CAS) command for each read or write access, and optionally a recharge command. On the other hand, the cache DRAM 18 can support read commands for read access and write commands for write access. Internally, a read or write command in the cache DRAM 18 can trigger multiple internal operations, such as activation, one or more CAS reads or writes (each), and pre-charging. Since only a small number of commands are sent through the interface for a given access, the energy consumption for access can be reduced.

[0017] As shown in the figure, the memory controller 28 controls the main DRAMs 16A - 16D and the cache DRAM 18 independently. In particular, in one embodiment, a main memory controller block 28A and a cache controller block 28B are shown. The main memory controller block 28A can control the main DRAMs 16A - 16D, and the cache controller block 28B can control the cache DRAM 18. Caching of data from the main DRAMs 16A - 16D to the cache DRAM 18 is under the control of the memory controller 28 and can be performed by moving data from the main DRAMs 16A - 16D through the SOC 12 to the cache DRAM 18. That is, the caching policy, allocation, and deallocation of cache lines, etc., can be determined by the memory controller 28. By storing frequently accessed data in the high - bandwidth low - power cache DRAM 18, the effective memory bandwidth can be increased above the memory bandwidth of the main DRAMs 16A - 16D, and at the same time, the large capacity of the main DRAMs 16A - 16D can also be enjoyed. In addition to the main memory controller block 28A and the cache controller block 28B, additional circuitry of the memory controller 28 can coordinate the caching policy, data transfer, etc., or the blocks 28A - 28B can interact directly to perform the caching operation.

[0018] Figure 2 is a block diagram of another embodiment of the main DRAMs 16A - 16D and the cache DRAM 18 connected to the SOC 12. In the embodiment of Figure 2, a single PHY 60D can be implemented in the SOC 12, and the SOC 12 is connected to a single PHY 60B of the cache DRAM 18. There may be logic capable of decoding operations directed to the main DRAMs 16A - 16D, and this decoded operation can be transferred to the DRAMs 16A - 16D through the PHYs 60C and 60A as shown in Figure 2.

[0019] FIG. 3 is a block diagram of a third embodiment of main DRAMs 16A to 16D and cache DRAM 18 connected to SOC 12. In the embodiment of FIG. 3, separate PHYs 60D and 60C can be implemented for cache controller block 28B to communicate with cache DRAM 18 (PHY 60B) and for main memory controller block to communicate with main DRAMs 16A to 16B (PHY 60A), respectively. However, cache DRAM 18 can operate as a host to the transport layer to main DRAMs 16A to 16D that communicates with PHYs 60F of main DRAMs 16A to 16D via PHY 60E, as shown in FIG. 3.

[0020] As shown in FIGS. 1 to 3, in some embodiments, the PHY protocol for cache DRAM 18 may be different from the PHY protocol for main DRAMs 16A to 16D, and both protocols can be supported in various configurations. In other embodiments, the same PHY protocol can be used.

[0021] Figures 4 to 7 illustrate the scalability of the memory system 10 for various applications based on different embodiments of packaging the cache DRAM 18 and main DRAMs 16A to 16D with the SOC 12. For example, in Figures 4 and 6, the main DRAMs 16A to 16D and the cache DRAM 18 (i.e., main memory 10) are packaged separately from the SOC 12. For small form factor devices such as mobile phones, a system like that in Figure 4 can be used, having the memory system 10 on one side of the SOC 12. On the other hand, for larger form factor devices such as tablet computers, laptops, or desktop computers, an embodiment like that in Figure 6 can be used, in which the memory system 10 is formed from multiple parts on various sides of the SOC 12 (e.g., parts 10A, 10B, 10C, and 10D in Figure 6). Any number of parts can be used in various embodiments. Figures 5 and 7 show embodiments in which the SOC 12 and the cache DRAM 18 are packaged together and interface with the main DRAMs 16A to 16D. Figure 5 is similar to Figure 4, and for example, for small form factor devices such as mobile phones, it shows the main DRAMs 16A to 16D on one side of the SOC 12 / cache DRAM 18. On the other hand, for larger form factor devices, embodiments such as those in Figure 7 can be used. In Figure 7, multiple instances of the main DRAMs 16A to 16D are shown on various sides of the SOC 12 and cache DRAM 18. The cache DRAM 18 packaged with the SOC 12 is also scalable in different implementation forms as needed. For example, see Figures 8 and 9 below. Any number of instances can be used in various embodiments. As mentioned above, each main DRAM 16A to 16D shown in Figures 4 to 7 may be one DRAM or multiple DRAMs as needed in various embodiments.

[0022] Figure 8 is a block diagram of one embodiment of the system showing a package 50 including a SOC 12 and a cache DRAM 18. Optionally, in some embodiments, multiple instances of the cache DRAM 18 may be included (for example, a second cache DRAM 18 is shown as a dotted line in Figure 8). The package may also include a connection layer 14 with relatively short interconnections to the cache DRAM 18 (see, for example, Figure 12 and description below for further details). One or more main DRAMs 16A-16D can be assembled with the SOC 12 / cache DRAM 18 in a POP configuration using a package-on-package (POP) substrate 52, and can be connected between the main DRAMs 16A-16D and the connection layer 14 (and further to the SOC 12, the connection layer 14 and wiring on the POP substrate 52, which are not shown in Figure 8). Figure 9 is another example of POP packaging using one or more main DRAMs 16A-16D and the SOC 12 / cache DRAM 18. In the embodiment shown in Figure 9, one cache DRAM 18 (or multiple cache DRAMs 18 in some embodiments) is mounted on the SOC 12 using any desired technique. For example, chip-on-wafer (COW) packaging, wafer-on-wafer (WOW) packaging, and chip-on-chip (COC) packaging can be used.

[0023] In other embodiments, the main DRAMs 16A-16D may be packaged separately from the SOC 12 and cache DRAMs 18. For example, Figures 10 and 11 show the SOC 12 / cache DRAMs 18 as shown in Figures 8 and 9, respectively, but the separately packaged main DRAMs 16A-16D are connected to a system board or main board 54. In some implementation configurations, the embodiments in Figures 10 and 11 may be a multi-chip module (MCM), and the board 54 may be an MCM board. In other embodiments, the main board 54 may be various types of circuit boards, such as a printed circuit board (PCB). Although two sets of main DRAMs 16A-16D are shown, each DRAM may consist of one or more DRAMs, and there may be one DRAM / DRAM set or multiple DRAM sets as shown in Figures 6 and 7.

[0024] Figures 12–14 show various exemplary 2.5D (D) and 3D configurations of the SOC 12, cache DRAM 18, and main DRAMs 16A–16D. However, it should be noted that in other embodiments, any packaging solution including various other 2.5D and / or 3D solutions may be used.

[0025] Next, referring to Figure 12, a block diagram of one embodiment of a system including a memory system 10 and a SOC 12 connected through a connection layer 14 is shown. In the embodiment of Figure 1, the memory 10 includes a plurality of main DRAM chips (DRAMs) 16A to 16D and a cache DRAM 18. Each main DRAM 16A to 16B includes one or more memory arrays 20A to 20H, as shown in Figure 1. The cache DRAM 18 includes a memory array 22 and a physical layer interface circuit (PHY circuit 24). The PHY circuit 24 is connected to the connection layer 14 through the pins of the cache DRAM 18, connected to the pins of the SOC 12 through the connection layer 14, and then connected to the corresponding PHY circuit 26 of the SOC 12. The PHY 26 is connected to the memory controller 28 of the SOC 12, which further includes various other circuits 30 (e.g., processors, peripherals, etc.). The other circuits 30 can be connected to the other side of the connection layer 14 through other pins of the SOC 12 and to other components of the system.

[0026] As described above, the memory system 10 may include two different types of DRAM, and the memory controller 28 of the SOC 12 can independently control the main DRAMs 16A-16D and the cache DRAM 18. Although the embodiment in Figure 1 shows one PHY circuit 24 and one PHY circuit 26, it should be noted that in other embodiments, there may be independent PHY circuits 24 and 26 for the cache DRAM 18 and for the main DRAMs 16A-16D, as described above with respect to the PHY circuits 60A-60D (and 60E and 60F in the embodiment of Figure 3).

[0027] As described above, the memory arrays 20A to 20H can be designed in terms of density to provide high storage capacity per unit area for the DRAMs 16A to 16D. Compared to the cache DRAM 18, the DRAMs 16A to 16D can implement, for example, larger page sizes. The DRAMs 16A to 16D can contain fewer banks compared to the cache DRAM 18. To further increase density, some control logic for the DRAMs 16A to 16D, such as test circuits, redundancy control, error correction code (ECC) mechanisms, reference voltage logic, and temperature control reference logic, can be placed on the cache DRAM 18.

[0028] The smaller the page size of the cache DRAM18 (and the larger the number of open pages due to the increasing number of banks in the cache DRAM18), the more frequent small accesses (compared to its page size) may be facilitated by the numerous memory agents in the SOC12. For example, the processor tends to read only one or a few cache lines of data, where the conventional page size of the DRAM may be 2-4 kilobytes. Each time a page is opened, the entire page of data is read from the memory array and can be captured in the sense amplifier and / or registers for access. When that page is closed and a new page is opened, the entire new page of that data is read. On the other hand, reading smaller pages consumes proportionally less power. When many agents are competing for access to memory, page contention and page open / close may become more frequent, and reducing power consumption per page can lead to a reduction in overall power consumption.

[0029] Therefore, if the data can be reused, the memory controller 28 can be configured to write the data read from the main DRAMs 16A to 16D to the cache DRAM 18. Various caching schemes can be used. However, since the cache DRAM 18 has a higher density than the static RAM on the SOC (on-SOC static RAM, SRAM), it can implement a larger cache than is possible with SRAM. Furthermore, DRAM contains fewer transistors per bit of stored data than SRAM (e.g., 1 transistor per bit compared to 6 transistors per bit), and therefore DRAM has less leakage power per bit than SRAM. Moreover, in some embodiments, the cost of the cache DRAM 18 can be offset to some extent by saving silicon die area on the SOC 12 by reducing the on-chip memory cache.

[0030] The main DRAMs 16A-16D may employ through-silicon-via (TSV) interconnects (e.g., TSV32 shown in Figure 12) to reduce interconnect length and capacitance. The TSV32 can be formed, for example, using known TSV manufacturing techniques. The TSV32 can be connected to each other when the DRAMs 16A-16D are stacked between the memories via pins. DRAM 16D (the main DRAM at the bottom of the stack) can be connected to the cache DRAM 18 via pins, and the cache DRAM 18 can route signals to the PHY circuit 24. The PHY circuit 24 may have output terminals to and / or input terminals from the PHY circuit 26, which are physically located along the edge of the cache DRAM 18, and the input / output terminals of the PHY circuit 26 can similarly be physically located along the edge of the SOC 12. In this way, short wiring paths through the connection layer 14 can be used to connect the PHY circuits 24 / 26. PHY circuits 24 and 26 can be designed to communicate with a fixed, small load through the connection layer 14 via relatively short interconnects. Compared to conventional DRAM interfaces with longer interconnects and multiple DRAM loads, a small, low-power driver can be used.

[0031] Furthermore, since the cache DRAM 18 routes TSV interconnects to desired locations at the edges of the cache DRAM 18, the TSVs can be positioned more freely within the main DRAMs 16A-16D. In some embodiments, congestion can be reduced and more interconnections can be provided than is possible in conventional DRAMs.

[0032] While a TSV is used in the illustrated embodiment, other embodiments may use silicon interposer interconnect or fanout technology, such as the integrated fanout (InFO) available from Taiwan Semiconductor Manufacturing Company (TSMC). The pins referred to herein can be any form of inter-chip interconnect. For example, the pins may be "microbumps," solder balls, or other pin-forming materials. While other embodiments explicitly show solder balls, other pin configurations can also be used in those embodiments.

[0033] The connecting layer 14 may be any form of inter-chip interconnection. For example, the connecting layer 14 may be a silicon interposer, a redistribution layer, a ceramic, an organic material, or a printed circuit board-like substrate.

[0034] Figure 13 is a block diagram of another embodiment of the memory system 10 on the SOC 12. In the embodiment of Figure 2, the packages are directly connected rather than connected through the connection layer 14, so the pins connecting the PHY circuit 24 to the PHY circuit 26 do not need to be on one edge. Pins on the bottom surface of the SOC 12 (not shown) can be used to connect the SOC to the rest of the system. As described above, other embodiments may have separate PHY circuits 24 for the cache DRAM 18 and for the main DRAMs 16A-16D.

[0035] Figure 14 is a block diagram of a third embodiment of a memory system in which a cache DRAM 18 is mounted in a stack with the SOC 12, and main DRAMs 16A to 16D are connected to the SOC 12 through a connection layer 14. In this embodiment, the main DRAMs 16A to 16D are stacked on a base die 40, which routes signals from the TSV 32 to the PHY circuit 24, and then routes them to the PHY 26 of the SOC 12 through short interconnects (near the edge).

[0036] The DRAM18 and SOC12 can be connected using various packaging techniques. Either the DRAM18 or SOC12 may be the "top" chip (where "top" is relative to the orientation in Figure 14). Any 3D chip packaging technique can be used. For example, in various embodiments, one or more of the following can be used: TSV connection, COW packaging, WOW packaging, POP packaging, etc.

[0037] If the above disclosure is fully understood, many variations and modifications will become apparent to those skilled in the art. The following "Claims" are intended to be interpreted to encompass all such variations and modifications.

Claims

1. A system comprising a stack of integrated circuit (IC) dies, Some of the IC die stacks are A plurality of first IC dies including a first type of dynamic random access memory (DRAM), wherein some of the plurality of first IC dies are coupled to at least one adjacent first IC die in the stack, The IC die stack includes a second IC die coupled to a base first IC die among the plurality of first IC dies, wherein the second IC die is A second type of DRAM having a second memory array with a lower density than the first memory array in the first type of DRAM, A system comprising: a first physical layer circuit configured to communicate with the stack of the first IC die.

2. Some of the stacks of the first IC die are coupled using through-silicon via (TSV) interconnects. The first IC die of the base is stacked on the second IC die, The system according to claim 1, wherein the TSV interconnect is coupled to the first physical layer circuit in the second IC die via microbumps.

3. The present invention further comprises a third IC die coupled to the second IC die, wherein the third IC die is A second physical layer circuit configured to communicate with the first physical layer circuit, The system according to claim 1, comprising a memory controller configured to control access to the first type of DRAM and the second type of DRAM.

4. The system according to claim 3, wherein the second IC die is stacked on the third IC die and coupled to the third IC die via microbumps.

5. The system according to claim 3, wherein the second IC die is coupled to the third IC die via a silicon interposer.

6. The second IC die includes pins along one edge of the second IC die for coupling the first physical layer circuit to the second physical layer circuit, The system according to claim 5, wherein the third IC die includes pins for coupling the second physical layer circuit to the first physical layer circuit along one edge of the third IC die.

7. The system according to claim 3, wherein the memory controller is configured to cache information read from the first type of DRAM in the stack of the first IC die in the second type of DRAM in the second IC die.

8. The second IC die includes a third physical layer circuit configured to access the second type of DRAM, The system according to claim 3, wherein the third IC die includes a fourth physical layer circuit coupled to the third physical layer circuit.

9. The system according to claim 1, wherein the first physical layer circuit is configured to access the first type of DRAM and the second type of DRAM.

10. Accessing a plurality of first memory arrays of a first type of dynamic random access memory (DRAM), which are contained on a plurality of first integrated circuit (IC) dies arranged in a stack, via a first physical layer circuit and a memory controller circuit, A method comprising accessing a second memory array of a second type of dynamic random access memory (DRAM) via a second physical layer circuit by a memory controller circuit, wherein the second memory array is contained on a second IC die coupled to a base first IC die among a plurality of first IC dies, and the second memory array has a lower density than some of the plurality of first memory arrays, The first physical layer circuit is included on the second IC die, in a method.

11. The method according to claim 10, wherein the second physical layer circuit is included on the second IC die.

12. The method according to claim 11, wherein the second physical layer circuit is the same as the first physical layer circuit.

13. The memory controller circuit is included on the third IC die, The method according to claim 10, further comprising the memory controller circuit communicating with the first physical layer circuit and the second physical layer circuit via a third physical layer circuit included on the third IC die.

14. The method according to claim 13, further comprising communicating with the first physical layer circuit via the second physical layer circuit using the third physical layer circuit.

15. The method according to claim 10, further comprising the memory controller circuit caching information read from the plurality of first memory arrays in the second memory array.

16. The memory controller circuit accesses one of the first plurality of memory arrays in a first time amount, The memory controller circuit accesses the second memory array in a second time period that is shorter than the first time period, The method according to claim 10, further comprising:

17. A plurality of first integrated circuit (IC) dies arranged in a stack, wherein each of the plurality of first IC dies includes a first type of dynamic random access memory (DRAM), and some of the plurality of first IC dies are coupled to at least one adjacent first IC die in the stack. A stacked memory device comprising: a second IC die stacked beneath a base first IC die among the plurality of first IC dies, The aforementioned second IC die is A second type of DRAM having a second memory array with a lower density than the first memory array in the first type of DRAM, A first physical layer circuit configured to communicate with the stack of the first IC die, A stacked memory device comprising a second physical layer circuit coupled to a pin located at the bottom of the second IC die.

18. The aforementioned second IC die is The stacked memory device according to claim 17, further comprising an ECC circuit configured to generate error correction codes (ECC) for the first type of DRAM.

19. The aforementioned second IC die is The stacked memory device according to claim 17, further comprising a reference voltage circuit configured to control one or more reference voltages for the first type of DRAM.

20. The system further comprises a third IC die, the third IC die being: A third physical layer circuit coupled to the second physical layer circuit via the pin located at the bottom of the second IC die, A memory controller circuit configured to access the first type of DRAM, The stacked memory device according to claim 17, comprising a cache controller circuit configured to access the second type of DRAM.

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