Semiconductor equipment
The semiconductor device optimizes energy loss reduction by controlling the on-off states of transistors with specific emitter region lengths and voltage applications, addressing the transient-on period challenges in power transistors.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- MITSUBISHI ELECTRIC CORP
- Filing Date
- 2023-09-26
- Publication Date
- 2026-05-22
AI Technical Summary
Existing semiconductor devices face challenges in reducing energy loss during the transient-on period, particularly in power transistors with switching functions, where there is a trade-off between voltage in the steady-on state and energy loss during the transition to off.
The semiconductor device incorporates a first and second transistor with specific emitter region lengths and control unit configurations, applying a second off voltage lower than the first to the second gate before the first transistor enters a transient off state, turning on the second transistor before the first, and then turning off the second transistor after the first is on, thereby optimizing energy loss reduction.
This configuration reduces energy loss during the transient-on period by minimizing hole discharge and completing switching faster, while also extending the duration of the short-circuit operation mode and enhancing latch-up tolerance.
Smart Images
Figure 0007864102000001 
Figure 0007864102000002 
Figure 0007864102000003
Abstract
Description
Technical Field
[0001] This disclosure relates to a semiconductor device.
Background Art
[0002] In a power transistor having a switching function, it is ideal that the voltage in the steady-on state and the energy loss during the transition to off are as small as possible. Basically, since there is a trade-off relationship between the voltage in the steady-on state and the energy loss during the transition to off, various techniques have been proposed so far to reduce them.
[0003] For example, in Patent Document 1, a technique for reducing the voltage in the steady-on state and the energy loss during the transition to off by controlling the control timing of two gates in a double-gate structure has been proposed.
[0004] Also, a technique for limiting the saturation current for a certain period of time using a double-gate structure so that the element is not destroyed when the element is short-circuited to the power supply has been devised.
Prior Art Documents
Patent Documents
[0005]
Patent Document 1
Summary of the Invention
Problems to be Solved by the Invention
[0006] However, in the prior art, there has been room for improvement in the control of the gate during the transient-on period and the reduction of the energy loss during the transient-on period.
[0007] Therefore, this disclosure has been made in view of the above problems, and an object thereof is to provide a technique capable of reducing the energy loss during the transient-on period. [Means for solving the problem]
[0008] The semiconductor device according to this disclosure comprises a first transistor including a first gate and a first emitter region provided along the first gate, a second transistor adjacent to the first transistor including a second gate and a second emitter region provided along the second gate, and a control unit for controlling the on and off of the first transistor and the second transistor, wherein in a plan view, the length of the portion of the second emitter region facing the second gate is greater than the length of the portion of the first emitter region facing the first gate, and the control unit applies a second off voltage lower than a first off voltage to the second gate before the first transistor enters a transient off state, turns on the second transistor before the first transistor enters a transient on state, and turns off the second transistor by applying the first off voltage to the second gate after the first transistor has been turned on. [Effects of the Invention]
[0009] According to this disclosure, the control unit applies a second off voltage lower than the first off voltage to the second gate before the first transistor enters a transient off state, turns on the second transistor before the first transistor enters a transient on state, and turns off the second transistor by applying the first off voltage to the second gate after the first transistor has turned on. With such a configuration, energy loss during the transient on period can be reduced. [Brief explanation of the drawing]
[0010] [Figure 1] This diagram shows the configuration of a semiconductor device according to Embodiment 1. [Figure 2] This figure shows a partial configuration of the semiconductor module according to Embodiment 1. [Figure 3] This is a plan view showing the configuration of the chip according to Embodiment 1. [Figure 4] This is an enlarged plan view showing the configuration of the semiconductor device according to Embodiment 1. [Figure 5] It is a cross-sectional view showing the configuration of the semiconductor device according to Embodiment 1. [Figure 6] It is an enlarged plan view showing the configuration of the semiconductor device according to Embodiment 1. [Figure 7] It is a cross-sectional view showing the configuration of the semiconductor device according to Embodiment 1. [Figure 8] It is a cross-sectional view showing the configuration of the semiconductor device according to Embodiment 1. [Figure 9] It is a timing chart showing the control of the control unit according to Embodiment 1. [Figure 10] It is a timing chart showing the control of the control unit according to Embodiment 1. [Figure 11] It is an enlarged plan view showing the configuration of the semiconductor device according to Embodiment 2. [Figure 12] It is an enlarged plan view showing the configuration of the semiconductor device according to Embodiment 3. [Figure 13] It is an enlarged plan view showing the configuration of the semiconductor device according to Embodiment 4. [Figure 14] It is a diagram showing the impurity profiles of the first emitter region and the second emitter region according to Embodiment 4. [Figure 15] It is a timing chart showing the control of the control unit according to Embodiment 5. [Figure 16] It is a diagram showing the relationship between Δt1 / tm and the energy loss Eon. [Figure 17] It is a timing chart showing the control of the control unit according to Embodiment 6. [Figure 18] It is a timing chart showing the control of the control unit according to Embodiment 7. [Figure 19] It is a timing chart showing the control of the control unit according to Embodiment 7. [Figure 20] [[ID=ES]]It is a timing chart showing the control of the control unit according to Embodiment 8.
Embodiments for Carrying Out the Invention
[0011] The embodiments will be described below with reference to the attached drawings. The features described in each of the embodiments below are illustrative, and not all features are necessarily required. In addition, in the descriptions below, the same or similar reference numerals are used for similar components in multiple embodiments, and the descriptions mainly focus on different components. Also, in the descriptions below, specific positions and directions such as "top," "bottom," "left," "right," "front," or "back" do not necessarily coincide with the positions and directions in actual implementation. Furthermore, a higher concentration in one part than in another part means, for example, that the average concentration of one part is higher than the average concentration of the other part. Conversely, a lower concentration in one part than in another part means, for example, that the average concentration of one part is lower than the average concentration of the other part.
[0012] <Embodiment 1> Figure 1 is a diagram showing the configuration of a semiconductor device according to this embodiment 1. The semiconductor device in Figure 1 comprises a first transistor 1, a second transistor 2, and a control unit 3.
[0013] The first transistor 1 and the second transistor 2 are provided adjacent to each other on the chip 51. The following description mainly focuses on a configuration where each of the first transistor 1 and the second transistor 2 is a trench-type IGBT (Insulated Gate Bipolar Transistor), but this is not the only configuration; for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) may also be used.
[0014] The control unit 3 controls the on / off state of the first transistor 1 and the second transistor 2 by controlling the voltage of the first gate 1a of the first transistor 1 and the voltage of the second gate 2a of the second transistor 2. The control unit 3 includes, for example, a CPU (Central Processing Unit).
[0015] Figure 2 shows the configuration of an IGBT module, which is a semiconductor module that includes the configuration shown in Figure 1. The upper and lower parts of Figure 2 have the same configuration, so only one of these parts will be described here.
[0016] The collector of the first transistor 1 is connected to the collector of the second transistor 2, and the emitter of the first transistor 1 is connected to the emitter of the second transistor 2, thereby connecting the first transistor 1 and the second transistor 2 in parallel. A diode 6 is connected in parallel to the first transistor 1 and the second transistor 2. Diode 6 may be a diode using a PN junction or a Schottky barrier diode. In Figure 2, diode 6 is provided outside the chip 51, but it may also be provided on the same chip 51 as the first transistor 1 and the second transistor 2, as in an RC-IGBT (Reverse Conducting IGBT).
[0017] Figure 3 is a plan view showing the configuration of the chip 51. The chip 51 includes a cell portion 52 on which the first transistor 1 and the second transistor 2 are provided, and a peripheral portion of the cell portion 52. The cell portion 52 is provided with the first gate 1a of the first transistor 1 and the second gate 2a of the second transistor 2.
[0018] In the example shown in Figure 3, pads 53 and 54 are provided on the outer periphery of the chip 51, electrically connected to the first gate 1a and the second gate 2a, respectively, in order to input signals from the control unit 3 outside the chip 51 to the first gate 1a and the second gate 2a. Alternatively, the control unit 3 may be provided instead of the pads 53 and 54, so that the chip 51 and the control unit 3 are configured monolithically (integrally).
[0019] Figure 4 is an enlarged plan view showing the configuration of the semiconductor device according to this embodiment 1, and specifically, it is an enlarged plan view of the portion of Figure 3 shown by the dashed line. In the example of Figure 4, the first transistor 1 and the second transistor 2 are arranged alternately one by one, but they may also be arranged alternately in units other than one, such as two by two. Figure 5 is a cross-sectional view showing the configuration along line AA and line BB of Figure 4. Note that for the sake of illustration, some of the components of Figure 5 are omitted from the illustration in Figure 4.
[0020] The configurations of the first transistor 1 and the second transistor 2 will be described below. Note that the n-type and p-type may be reversed in the following description.
[0021] As shown in Figures 4 and 5, the first transistor 1 has a first gate 1a and n + Type or n ++ The first emitter region 1b of type n - A drift layer 11 of type n, a CS (charge storage) layer 12 of type n, a base layer 13 of type p, and p + A type contact layer 14, a gate insulating film 17, an interlayer insulating film 21, an emitter 22, an n-type buffer layer 23, and p + It includes a collector area 24 of type 24 and a collector 25.
[0022] A CS layer 12 is provided on the drift layer 11, a base layer 13 is provided on the CS layer 12, and a first emitter region 1b and a contact layer 14 are selectively provided on the base layer 13.
[0023] The trench 16 extends across the first emitter region 1b, the base layer 13 and the CS layer 12, and the upper part of the drift layer 11. The first gate 1a is an electrode provided on the inner wall of the trench 16 via a gate insulating film 17. The gate insulating film 17 is, for example, an oxide film, and the first gate 1a is made of, for example, doped polysilicon.
[0024] The interlayer insulating film 21 insulates the first gate 1a from the emitter 22. The interlayer insulating film 21 is, for example, an oxide film. The emitter 22 is an electrode electrically connected to the first emitter region 1b and the contact layer 14 through contact holes in the interlayer insulating film 21. The buffer layer 23, collector region 24, and collector 25 are stacked in this order on the underside of the drift layer 11.
[0025] As shown in Figures 4 and 5, the second transistor 2 has a second gate 2a and n + Type or n ++ The second transistor 2 includes a type 2 emitter region 2b. The second transistor 2 also includes, like the first transistor 1, a drift layer 11, a CS layer 12, a base layer 13, a contact layer 14, a gate insulating film 17, an interlayer insulating film 21, an emitter 22, a buffer layer 23, a collector region 24, and a collector 25.
[0026] The configuration of the second transistor 2 is generally the same as that of the first transistor 1, except for the first emitter region 1b and the second emitter region 2b. The first emitter region 1b in Figure 4 is provided intermittently (for example, periodically) along the first gate 1a, so the cross-sectional configuration along line AA in Figure 5 is provided with the first emitter region 1b, but the cross-sectional configuration along line BB is not provided with the first emitter region 1b. On the other hand, the second emitter region 2b in Figure 4 is provided continuously along the second gate 2a, so the second emitter region 2b is provided in both the cross-sectional configuration along line AA and the cross-sectional configuration along line BB in Figure 5. In other words, in the plan view of Figure 4, the length of the portion of the second emitter region 2b facing the second gate 2a is greater than the length of the portion of the first emitter region 1b facing the first gate 1a.
[0027] The first emitter region 1b, the second emitter region 2b, the drift layer 11, the CS layer 12, the base layer 13, the contact layer 14, the gate insulating film 17, the buffer layer 23, and the collector region 24 are included in a semiconductor layer that is at least one of the semiconductor substrate and the epitaxial growth layer. In this specification, for example, at least one of A, B, C, ..., and Z means any one of all combinations selected from the groups A, B, C, ..., and Z. The semiconductor layer may be composed of ordinary silicon (Si), or it may be composed of a wide-bandgap semiconductor such as silicon carbide (SiC), gallium nitride (GaN), or diamond. When the semiconductor layer is composed of a wide-bandgap semiconductor, stable operation at high temperatures and high voltages, and faster switching speeds are possible.
[0028] In the examples of Figures 4 and 5, the entire mesa region (i.e., the upper part of the semiconductor layer sandwiched between the first gate 1a and the second gate 2a in Figure 5) is in contact with the emitter 22, but this is not the only option. For example, as shown in Figures 6 and 7, by making the interlayer insulating film 21 larger than the interlayer insulating film 21 in Figure 4, only a portion of the mesa region may be in contact with the emitter 22.
[0029] Furthermore, in Figure 7, the mesa portion covered by the interlayer insulating film 21 and the mesa portion not covered by the interlayer insulating film 21 have the same height in the vertical direction of the paper. However, this is not the only option, and as shown in Figure 8, the height of the mesa portion covered by the interlayer insulating film 21 and the height of the mesa portion not covered by the interlayer insulating film 21 may be different.
[0030] In the above configuration, the control unit 3 in Figure 1 or Figure 2 controls the voltage of the first gate 1a of the first transistor 1 and the voltage of the second gate 2a of the second transistor 2. When a voltage greater than the threshold voltage VGE(th) is applied to the first gate 1a of the first transistor 1, the portion of the semiconductor layer near the gate insulating film 17 of the first gate 1a functions substantially as an n-type semiconductor layer and forms a channel. On the other hand, when a negative bias, which is a negative voltage, is applied to the first gate 1a, the portion of the semiconductor layer near the gate insulating film 17 of the first gate 1a functions substantially as a p-type semiconductor layer. Similarly, when a voltage greater than the threshold voltage VGE(th) is applied to the second gate 2a of the second transistor 2, the portion of the semiconductor layer near the gate insulating film 17 of the second gate 2a functions substantially as an n-type semiconductor layer and forms a channel. On the other hand, when a negative bias is applied to the second gate 2a, the portion of the semiconductor layer near the gate insulating film 17 of the second gate 2a functions substantially as a p-type semiconductor layer.
[0031] Figure 9 is a timing chart showing the control of the control unit 3 according to this embodiment 1. Figure 9 shows the voltages of pads 53 and 54 of the chip 51 in Figure 3, that is, the voltages of the first gate 1a and the second gate 2a. The threshold voltages VGE(th) of the first transistor 1 and the second transistor 2 are greater than 0V.
[0032] The transient off state of the first transistor 1 is, strictly speaking, the state from when the first transistor 1 is on until when it is off, and Figure 9 shows the transient off period, including the transient off state. Similarly, the transient on state of the first transistor 1 is, strictly speaking, the state from when the first transistor 1 is off until when it is on, and Figure 9 shows the transient on period, including the transient on state.
[0033] The control unit 3 applies a second off voltage V2, which is lower than the first off voltage V1, to the second gate 2a before the first transistor 1 enters a transient off state. The control unit 3 turns on the second transistor 2 before the first transistor 1 enters a transient on state. Then, after the first transistor 1 has gone through the transient on state and turned on, the control unit 3 applies the first off voltage V1 to the second gate 2a to turn off the second transistor 2.
[0034] In the example shown in Figure 9, the first off-voltage V1 is 0V and the second off-voltage V2 is negatively biased. However, this is not limited to the example shown, as long as both the first and second off-voltages V1 and V2 are lower than the threshold voltage VGE(th), and the second off-voltage V2 is lower than the first off-voltage V1.
[0035] In the example shown in Figure 9, during the steady-state off period from the transient off period to the transient on period of the first transistor 1, the control unit 3 maintains the application of the second off voltage V2 (i.e., negative bias) to the second gate 2a. Also, during the steady-state on period from the transient on period to the transient off period of the first transistor 1, the control unit 3 maintains the application of the first off voltage V1 (i.e., 0V) to the second gate 2a. However, the voltage of the second gate 2a during the steady-state off period and the steady-state on period is not limited to these. For example, as shown in Figure 10, during the steady-state off period, the control unit 3 may apply a third off voltage V3 to the second gate 2a that is greater than or equal to 0 and less than the threshold voltage VGE(th). The first to third effects can be obtained by the control of the control unit 3 as described above.
[0036] <First effect> The control unit 3 applies a second off voltage V2 (i.e., a negative bias) to the second gate 2a before the first transistor 1 enters a transient off state. As a result, the portion of the semiconductor layer near the gate insulating film 17 of the second gate 2a functions as a p-type semiconductor layer. This has the effect of making it easier for holes accumulated in the drift layer 11 to be discharged from the front surface via the p-type semiconductor layer. This reduces the total amount of holes contributing to the conductivity modulation of the entire first transistor 1 and second transistor 2. Consequently, fewer holes are discharged when the first transistor 1 is turned off after this operation, resulting in a smaller tail current and reducing the energy loss (Eoff) during the transient off period of the first transistor 1.
[0037] <Second effect> The control unit 3 turns on the second transistor 2 before the first transistor 1 enters a transient on state. As a result, energy loss during the transient on period mainly occurs in the second transistor 2, which is turned on first. In this embodiment 1, in a plan view, the length of the portion of the second emitter region 2b facing the second gate 2a is greater than the length of the portion of the first emitter region 1b facing the first gate 1a. Therefore, when the first transistor 1 and the second transistor are turned on individually, the amount of electrons injected at the moment the second transistor 2 is turned on is greater than the amount of electrons injected in the first transistor 1, so the switching is completed faster than that of the first transistor.
[0038] As a result, the energy loss during the transient on-period when the second transistor 2 is turned on individually is smaller than the energy loss during the transient on-period when the first transistor 1 is turned on individually. Consequently, the total energy loss Eon during the transient on-period of both the first and second transistors can be reduced. Furthermore, by turning on the first transistor after turning on the second transistor, both the first and second transistors can be turned on with a smaller gate charge than when they are turned on simultaneously.
[0039] <Third effect> After the first transistor 1 is turned on, the control unit 3 applies a first off voltage V1 to the second gate 2a to turn off the second transistor 2, thereby improving the behavior during the short-circuit operation mode. The short-circuit operation mode is a mode in which the main power supply is directly short-circuited to the collector 25 due to a failure in the peripheral circuit, etc. In the short-circuit operation mode, it is preferable that the duration of the steady-state on period after the transient on period is completed is long. This duration corresponds to the time until the time-integrated power, determined from the voltage applied to the IGBT (i.e., the voltage of the main power supply) and the current (i.e., the saturation current of the IGBT), exceeds the energy tolerance value of the IGBT. The current (saturation current of the IGBT) here depends on the size of the emitter region of the on transistor.
[0040] In this embodiment 1, in a plan view, the length of the portion of the second emitter region 2b facing the second gate 2a is greater than the length of the portion of the first emitter region 1b facing the first gate 1a. Since the length of the emitter region and the size of the emitter region are in a corresponding relationship, the saturation current of the ON first transistor 1 is smaller than the saturation current of the ON second transistor 2. In this embodiment 1, since the first transistor 1, which has a small saturation current, turns on, and then the second transistor 2, which has a large saturation current, turns off, the duration of the short-circuit operation mode can be extended.
[0041] <Embodiment 2> Figure 11 is an enlarged plan view showing the configuration of the semiconductor device according to this second embodiment. In the first embodiment, the second emitter region 2b was continuously provided along the second gate 2a in the plan view of Figure 4. In this second embodiment, the second emitter region 2b is provided intermittently (for example, periodically) along the second gate 2a in the plan view of Figure 11, which is different from the first embodiment.
[0042] As shown in the example in Figure 11, the first emitter region 1b and the second emitter region 2b may be arranged alternately such that, in a plan view, the lower and upper parts of the first emitter region 1b correspond to the upper and lower parts of the second emitter region 2b. Alternatively, the first emitter region 1b and the second emitter region 2b may be arranged according to a certain rule such that, in a plan view, the upper part of the first emitter region 1b corresponds to the upper part of the second emitter region 2b.
[0043] With this configuration, the potential directly below the second emitter region 2b can be lowered by thinning out the second emitter region 2b, thereby increasing the latch-up tolerance of the semiconductor device.
[0044] <Embodiment 3> Figure 12 is an enlarged plan view showing the configuration of the semiconductor device according to this third embodiment. This third embodiment differs from the first embodiment in that, in plan view, the first emitter region 1b and the second emitter region 2b are connected to each other.
[0045] Here, the first emitter region 1b and the second emitter region 2b need to be electrically connected to the emitter 22 via contact holes in the interlayer insulating film 21. For this reason, in embodiments 1 and 2, the width of the contact holes in the interlayer insulating film 21 is limited by the arrangement of the first emitter region 1b and the second emitter region 2b. In contrast, in embodiment 3, as shown in Figure 12, the first emitter region 1b and the second emitter region 2b are connected to each other, and there is no such limitation on the width of the contact holes 21a in the interlayer insulating film 21, thus increasing the design freedom of the contact holes.
[0046] <Embodiment 4> Figure 13 is an enlarged plan view showing the configuration of the semiconductor device according to this fourth embodiment, and Figure 14 is a diagram showing the impurity profiles of the first emitter region 1b and the second emitter region 2b. The horizontal axis of Figure 14 represents the depth from the surface of the semiconductor layer (i.e., the respective surfaces of the first emitter region 1b and the second emitter region 2b), and the vertical axis of Figure 14 represents the impurity concentration.
[0047] As shown in FIG. 14, the peak of the n-type impurity concentration in the first emitter region 1b and the peak of the n-type impurity concentration in the second emitter region 2b are located on the upper surface side of the semiconductor layer. In the fourth embodiment, the peak of the n-type impurity concentration in the second emitter region 2b is larger than the peak of the n-type impurity concentration in the first emitter region 1b, which is different from the first embodiment.
[0048] According to such a configuration, since the amount of electron injection at the moment when the second transistor 2 is turned on is large, switching is completed earlier than the first transistor. As a result, the amount of electron injection at the moment when the second transistor 2 is turned on becomes larger than the amount of electron injection of the first transistor 1, so that the energy loss Eon during the transient on period of the entire first transistor 1 and second transistor 2 can be reduced. Note that the fourth embodiment as described above is also applicable to the second and third embodiments.
[0049] <Embodiment 5> FIG. 15 is a timing chart showing the control of the control unit 3 according to the fifth embodiment, and specifically shows the control during the transient on period of the first transistor 1. In the fifth embodiment, when the time from when the second transistor 2 is turned on until the first transistor 1 is turned on is Δt1 and the mirror section of the second transistor 2 is tm, the point where 0 < Δt1 < tm holds is different from the first embodiment. Note that the mirror section is a period during which the gate voltage becomes constant when the transistor is turned on due to the effective capacitance between the gate and the collector of the transistor.
[0050] FIG. 16 is a diagram showing the relationship between the ratio of tm to Δt1, that is, Δt1 / tm (horizontal axis), and the energy loss Eon (vertical axis) during the transient on period of the entire first transistor 1 and second transistor 2. Note that the energy loss Eon shown on the vertical axis is normalized by the energy loss Eon when Δt1 / tm = -0.2 (that is, when the first transistor 1 rises before the mirror section of the second transistor).
[0051] In the portion where 0 < Δt1 < tm holds, that is, in the portion on the horizontal axis of FIG. 16 that is greater than 0 and less than 1, the energy loss Eon can be reduced compared to the case where Δt1 / tm = -0.2. In particular, among the results of FIG. 16, the energy loss Eon can be reduced the most when Δt1 / tm = 0.3. Note that the fifth embodiment as described above is also applicable to the second to fourth embodiments.
[0052] <Embodiment 6> FIG. 17 is a timing chart showing the control of the control unit 3 according to the sixth embodiment, specifically, regarding the control during the transient on-period and the main voltage VCE and main current IC of the semiconductor device. In the sixth embodiment, the point where the voltage of the first gate 1a exceeds the mirror voltage before the voltage of the second gate 2a falls below the mirror voltage while the first transistor 1 is in the transient on state is different from the first embodiment.
[0053] The dashed-dotted line in FIG. 17 shows the waveform when the voltage of the first gate 1a exceeds the mirror voltage after the voltage of the second gate 2a has fallen below the mirror voltage. In this case, since the voltage VCE that once became 0 becomes greater than 0 between when the voltage of the first gate 1a rises and when the voltage of the second gate 2a falls below the mirror voltage, the energy loss Eon increases by that amount.
[0054] The solid line in FIG. 17 shows the waveform according to the control of the sixth embodiment of the present situation, that is, the waveform when the voltage of the first gate 1a exceeds the mirror voltage before the voltage of the second gate 2a falls below the mirror voltage. In this case, since the voltage VCE that once became 0 maintains 0, the energy loss Eon can be reduced compared to the above case. Note that the sixth embodiment as described above is also applicable to the second to fifth embodiments.
[0055] <Embodiment 7> Figure 18 is a timing chart showing the control of the control unit 3 according to this embodiment 7, specifically showing the control during the transient on-period and transient off-period of the first transistor 1. This embodiment 7 is similar to the control shown in Figure 10 described in embodiment 1, but with the control modified so that the first transistor 1 transitions from the transient on-period state to the transient off-period state without going through the steady-state on-period state. In other words, this embodiment 7 differs from embodiment 1 in that when the first transistor 1 enters the transient off-period state immediately after the transient on-period state, the control unit 3 does not maintain the voltage of the second gate 2a from the on-level on-voltage to the first off-voltage V1, but instead sets it to the second off-voltage V2.
[0056] Figure 19 is an enlarged view of a portion of Figure 18. The dashed line in Figure 19 shows the waveform when the control unit 3 controls the voltage of the second gate 2a from the ON voltage to the third OFF voltage V3, and the solid line in Figure 19 shows the waveform controlled by the control unit 3 according to this embodiment 7.
[0057] In order to turn off the second transistor 2 earlier than the first transistor 1, the voltage of the second gate 2a needs to reach the threshold voltage VGE(th) earlier than the voltage of the first gate 1a. In contrast, according to this embodiment 7, the control unit 3 can turn off the second transistor 2 earlier than the first transistor 1 by the time Δt(Vth) shown in Figure 19, compared to when the control unit 3 controls the voltage of the second gate 2a from the on voltage to the third off voltage V3. As a result, the period during which the first transistor 1 is on can be shortened. This embodiment 7 is also applicable to Figure 9 described in Embodiment 1, in which case the voltage of the second gate 2a is maintained at the second off voltage V2 during the steady-state off period after the transient off period. This embodiment 7 is also applicable to Embodiments 2 to 6.
[0058] <Embodiment 8> Figure 20 is a timing chart showing the control of the control unit 3 according to this embodiment 8. This embodiment 8 differs from embodiment 1 in that the second off voltage V2 is 0V or higher, the first off voltage V1 is greater than the second off voltage V2, and the third off voltage V3 is greater than the second off voltage V2.
[0059] With this configuration, the control unit 3 does not need to provide a power supply to negatively bias the second gate 2a, thus simplifying the configuration of the semiconductor device. This embodiment 8 described above is also applicable to Figure 9 and to embodiments 2 to 7.
[0060] Furthermore, it is possible to freely combine each embodiment and each variation, and to modify or omit each embodiment and each variation as appropriate.
[0061] The various aspects of this disclosure are summarized below as an appendix.
[0062] (Note 1) A first transistor including a first gate and a first emitter region provided along the first gate, The first transistor and the second transistor adjacent to it include a second gate and a second emitter region provided along the second gate, A control unit that controls the on and off states of the first transistor and the second transistor, and Equipped with, In a plan view, the length of the portion of the second emitter region facing the second gate is greater than the length of the portion of the first emitter region facing the first gate. The control unit, Before the first transistor enters a transient off state, a second off voltage lower than the first off voltage is applied to the second gate. Before the first transistor enters a transient on state, the second transistor is turned on. A semiconductor device that, after the first transistor is turned on, applies the first off voltage to the second gate to turn off the second transistor.
[0063] (Appendix 2) The semiconductor device according to Appendix 1, In a plan view, the first emitter region is intermittently provided along the first gate, and the second emitter region is continuously provided along the second gate. A semiconductor device.
[0064] (Appendix 3) The semiconductor device according to Appendix 1, In a plan view, the first emitter region is intermittently provided along the first gate, and the second emitter region is intermittently provided along the second gate. A semiconductor device.
[0065] (Appendix 4) The semiconductor device according to any one of Appendices 1 to 3, In a plan view, the first emitter region and the second emitter region are connected to each other. A semiconductor device.
[0066] (Appendix 5) The semiconductor device according to any one of Appendices 1 to 4, The peak of the impurity concentration of the second emitter region is larger than the peak of the impurity concentration of the first emitter region. A semiconductor device.
[0067] (Appendix 6) The semiconductor device according to any one of Appendices 1 to 5, [[ID=3 ninety-nine]]When the time from when the second transistor is turned on until the first transistor is turned on is Δt1 and the mirror section of the second transistor is tm, 0 < Δt1 < tm holds. A semiconductor device.
[0068] (Appendix 7) The semiconductor device according to any one of Appendices 1 to 6, A semiconductor device wherein, while the first transistor is in the transient ON state, the voltage of the first gate exceeds the Miller voltage before the voltage of the second gate falls below the Miller voltage.
[0069] (Note 8) A semiconductor device described in any one of the items from Appendix 1 to Appendix 7, The control unit, A semiconductor device that controls the voltage of the second gate to the second off voltage without maintaining it at the on voltage, when the first transistor enters the transient off state immediately after the transient on state.
[0070] (Note 9) A semiconductor device described in any one of the items from Appendix 1 to Appendix 8, A semiconductor device in which the second off-voltage is 0V or higher. [Explanation of Symbols]
[0071] 1 First transistor, 1a First gate, 1b First emitter region, 2 Second transistor, 2a Second gate, 2b Second emitter region, 3 Control unit.
Claims
1. A first transistor including a first gate and a first emitter region provided along the first gate, The first transistor and the second transistor adjacent to it include a second gate and a second emitter region provided along the second gate, A control unit that controls the on and off states of the first transistor and the second transistor, and Equipped with, In a plan view, the length of the portion of the second emitter region facing the second gate is greater than the length of the portion of the first emitter region facing the first gate. The control unit, Before the first transistor enters a transient off state, a second off voltage lower than the first off voltage is applied to the second gate. Before the first transistor enters a transient ON state, the second transistor is turned ON. A semiconductor device that, after the first transistor is turned on, applies the first off voltage to the second gate to turn off the second transistor.
2. A semiconductor device according to claim 1, A semiconductor device in which, in a plan view, the first emitter region is provided intermittently along the first gate, and the second emitter region is provided continuously along the second gate.
3. A semiconductor device according to claim 1, A semiconductor device in which, in a plan view, the first emitter region is intermittently provided along the first gate, and the second emitter region is intermittently provided along the second gate.
4. A semiconductor device according to any one of claims 1 to 3, A semiconductor device in which, in a plan view, the first emitter region and the second emitter region are connected to each other.
5. A semiconductor device according to any one of claims 1 to 3, A semiconductor device wherein the peak of the impurity concentration in the second emitter region is greater than the peak of the impurity concentration in the first emitter region.
6. A semiconductor device according to any one of claims 1 to 3, A semiconductor device in which, when Δt1 is the time from when the second transistor turns on until the first transistor turns on, and tm is the mirror interval of the second transistor, the condition 0 < Δt1 < tm holds.
7. A semiconductor device according to any one of claims 1 to 3, A semiconductor device wherein, while the first transistor is in the transient ON state, the voltage of the first gate exceeds the Miller voltage before the voltage of the second gate falls below the Miller voltage.
8. A semiconductor device according to any one of claims 1 to 3, The control unit, A semiconductor device that controls the voltage of the second gate to the second off voltage without maintaining it at the on voltage, when the first transistor enters the transient off state immediately after the transient on state.
9. A semiconductor device according to any one of claims 1 to 3, The aforementioned second off-voltage is 0V or higher, and the semiconductor device.