High-clock-efficient random number generation system and method

Abstract

A system and method for quickly and efficiently generating a sequence of random numbers from a source of random numbers in a computing system. The steps include loading a data loop (a looped array of stored values ​​with an index) with random data from a source of random data, then reading values ​​from the data loop relative to the index, operating on the multi-bit values ​​thereby outputting derived random numbers, and moving the index relative to the looped array. The data loop may be a simple feedback loop, which may be a shift register loaded by direct memory access (DMA). Operations may be fed by one or more data feeds and performed by one or more arithmetic logic units (ALUs) that may perform XOR, mask generator, data MUX, and / or MOD.

Description

Technical Field

[0001] Background Art Cross - Reference to Related Applications This invention claims priority under the Patent Cooperation Treaty and the Paris Convention to U.S. Provisional Patent Application No. 63 / 149,751 to Patrick D. Ross, filed Feb. 16, 2021, and through that application, to U.S. Non - Provisional Patent Application No. 17 / 672,656 to Patrick D. Ross, filed Feb. 15, 2022, both of which are incorporated herein by reference.

[0002] Technical Field The present invention relates to methods and systems for generating random numbers, specifically, computer generated random numbers.

[0003] Industrial Applicability The present invention is applicable to various industries in various ways. The present invention can be used within computer hardware as a source of random numbers that can be consumed by the same hardware or third - party devices. The present invention can be manufactured using computer circuit manufacturing techniques including silicon deposition technology.

Background Art

[0004] Description of Related Technologies Computing systems and operations sometimes require the generation and / or utilization of random or pseudorandom numbers (deterministic numbers that appear random but are not actually random) for a variety of purposes, including but not limited to games, simulations, modeling, security, seeding, and combinations thereof. Streams of random and pseudorandom numbers have varying qualities of randomness, and some applications of their use require a minimum standard of quality. NIST Special Publication 800-22 is an example of the main part of standards for random and pseudorandom number generators, and includes methods for testing streams of numbers for randomness, unpredictability, etc., including 16 different tests for various types of non-randomness. Various sources of random / pseudorandom number streams produce streams of a particular quality, and high-quality streams are often particularly difficult / expensive to generate and / or produce with reliable / consistent quality.

[0005] Examples of physical sources for random number streams include noise in electronic circuits, spontaneous decay of radioactive nuclei, date / time vectors, mouse movements, delays between keyboard presses, and combinations thereof. Examples of sources for pseudorandom number streams include seed PRNG functions (e.g., middle squares method, Römer generator, linear congruential generator (LCG), linear feedback shift register (LFSR), nonlinear feedback shift register, inverse congruential generator (ICG)), cryptographic algorithms, cryptographic hashes, and combinations thereof (including some very complex combinations).

[0006] Conventionally, it is known to use computing systems to generate on-demand streams of random / pseudorandom numbers. Various hardware, software, and hybrid systems have been developed to meet the need for random value streams. Several improvements have been made in this field. Examples of references relevant to this invention are listed below in their own words, and the teachings supporting each reference are incorporated herein by reference.

[0007] Chinese Patent Application No. CN101515228, titled TRUE RANDOM NUMBER GENERATOR, teaches a true random number generator comprising a probabilistic source module and a post-processing module. The probabilistic source module is used to generate a digital signal with random characteristics and provide the digital signal to the post-processing module. The post-processing module removes the bias from the data signal by post-processing the digital signal using a loop code error correction method, thereby obtaining a random number sequence. The probabilistic source module can consist of multiple inverter oscillator rings, and the post-processing module is implemented by a linear feedback shift register (LFSR). Because the TRNG (True Random Number Generator) has a simple structure and uses only common digital logic devices, the true random number generator has good technically weak correlation and can be quickly ported to the integrated circuit design flow after prototype verification, thereby improving the efficiency of module design and reducing development risk.

[0008] U.S. Patent No. 6,954,770, issued to Carlson et al., discloses a random number generator comprising: an oscillator having an output signal dependent on a random source; a sampling device that samples the output signal from the oscillator to obtain a sampled oscillator output; and a fixed-frequency clock-driven linear feedback shift register (LFSR) that receives the sampled oscillator output and is communicatively coupled to the sampling device via a digital gate to provide random numbers at the output of the LFSR. Furthermore, the random number generator may include an optional mixed function communicatively coupled to the LFSR to read out random numbers and to insert the random numbers into an algorithm to obtain robust random numbers.

[0009] Wan et al., U.S. Patent Application Publication No. 20050036607, discloses a method for generating pseudorandom numbers by sampling the output sequence of a linear feedback shift register having a specific periodicity. In one embodiment, the generation of pseudorandom numbers using a linear feedback shift register is achieved by periodically switching the iterative outputs generated by a plurality of linear feedback shift registers. In one embodiment, a method for encrypting pseudorandom numbers generated by a linear feedback shift register includes the use of a nonlinear operator. In one embodiment, a method for further encrypting pseudorandom numbers is achieved by using a hash function whose initial value changes over time by a function operating on one or more variables. In one embodiment, an apparatus for generating pseudorandom numbers using a linear feedback shift register comprises digital hardware.

[0010] The present invention as known to date has many drawbacks, including being slow, inefficient, degrading or failing to maintain a quality standard of randomness, having an exponentially increasing cost for additional random values ​​beyond the initial generation cycle, requiring many clock cycles to generate random values, generating deterministic values, and being unable to generate actual random streams.

[0011] What is needed is a method and / or system for solving one or more problems described herein and / or one or more problems that a person skilled in the art, upon becoming familiar with this specification, may notice. [Overview of the project] [Problems that the invention aims to solve]

[0012] Disclosure of the invention This invention was developed in accordance with the current state of the art, and in particular in response to problems and needs in the art that have not yet been fully solved by currently available methods and systems for generating random numbers. Accordingly, this invention was developed to provide a system and / or method for generating random numbers. [Means for solving the problem]

[0013] According to one non-limiting embodiment, there is a method for rapidly and efficiently generating a series of random numbers from a source of random numbers in a computing system. The method includes the steps of loading a data loop with random data which may be from a source of random data, the data loop comprising one or more of a loop array of stored values ​​and indices; reading a value which may be multibit from the data loop in relation to the position of the index in the loop array; performing a first data operation on the value to thereby derive a derived random number from the multibit value; moving the index to a different position in the loop array in relation to the loop array; and / or repeating one or more of these steps to thereby generate a series of derived random numbers.

[0014] The data loop may be a shift register. The shift register may be a universal shift register. Different positions may be adjacent positions. The data operation may be a separable operation that can be selected from the group consisting of XOR, mask generator, data MUX, URNG, and MOD. The source of random data may be the output of one or more methods / steps described herein. The step of loading the data loop may be performed by direct memory access. The data operation may be a MOD operation performed with a multibit value as the numerator and a denominator with fewer bits than the multibit value. The denominator may be a value obtained directly from, derived from, or acquired from the source of random data. The denominator may be greater than the desired range of derived random numbers. The controller may include one or more of programmable logic circuits, scripts, and drivers.

[0015] There may be a step of automatically selecting a separation operation from a plurality of separation operations depending on the controller. Simultaneously with the step of performing the first data operation, there may be a step of performing a second data operation on a multibit value to derive a second derived random number from the multibit value. Furthermore, a second / secondary computing system may independently perform one or more of the steps described herein using substantially the same random data source as the primary computing system, so that the data loop of the second computing system is loaded identically to the data loop of the primary system, and perform substantially the same data operations so that the resulting derived random numbers are the same as those derived by the primary system / method, thereby generating a second set of derived random numbers that are identical to the set of derived random numbers of the primary system.

[0016] The second computing system may be structurally different from the primary computing system in at least one of the following: data loops, read operators, shifters, controller types, and data loop loader types.

[0017] In another, less restrictive embodiment, there may be a computerized system for efficiently generating a stream of random numbers. The system may include a data loop having one or more of the following: a data loop having one or more of a simple feedback loop-like array of random data, an index, and / or output ports that read values ​​from the simple feedback loop-like array based on the relative position of the index to the simple feedback loop-like array; a data operator having one or more of an input and an output that can provide access to an output value from the data operator, and which may be functionally coupled to the output port so that a value from the output port is supplied to the data operator as an input value; and / or an incrementer that can be functionally coupled to the data loop and shifts an index relative to the simple feedback loop-like array.

[0018] The data loop may further include input ports. Values ​​from output ports may be multi-bit values. The data loop may be a universal shift register. The data loop may be a shift register. The data operator may be a separable operation selected from the group consisting of XOR, mask generator, data MUX, and MOD.

[0019] A second data loop may also exist that has input ports that can be functionally coupled to the output of a data operator, such that the output value from the data operator is input to the second data loop.

[0020] Just as a loop-like array of random data is supplied with data from a random data source, there may also be a source of random data that can be functionally coupled to the input ports of the data loop.

[0021] Throughout this specification, references to features, advantages, or similar language do not imply that all such features and advantages must be present in any one embodiment of the invention. Rather, the language referring to the features and advantages is understood to mean that a particular feature, advantage, or characteristic described in connection with an embodiment is included in at least one embodiment of the invention. Thus, throughout this specification, the description of features and advantages and similar language may, but do not necessarily, refer to the same embodiment.

[0022] Furthermore, the described features, advantages, and characteristics of the invention may be combined in any suitable manner in one or more embodiments. One skilled in the art will recognize that the invention can be practiced without one or more of the specific features or advantages of a particular embodiment. In other instances, additional features and advantages may be recognized in particular embodiments that may not be present in all embodiments of the invention.

[0023] These features and advantages of the invention will become more fully apparent from the following description and appended claims, or may be learned by the practice of the invention as set forth hereinafter.

[0024] Brief Description of the Drawings To facilitate an understanding of the advantages of the invention, a more specific description of the invention briefly described above is provided by reference to specific embodiments shown in the appended drawings. It should be noted that the drawings of the invention are not to scale. The drawings are merely schematic and are not intended to depict specific parameters of the invention. Understanding that these drawings show only typical embodiments of the invention and should not be considered as limiting its scope, the invention will be described and explained in further detail with reference to the appended drawings.

Brief Description of the Drawings

[0025] [Figure 1]Shows a computerized system for efficiently generating a stream of random numbers according to an embodiment of the present invention. [Figure 2] Shows a computerized system mainly in hardware for efficiently generating a stream of random numbers according to an embodiment of the present invention. [Figure 3] Shows a computerized system in hybrid hardware for efficiently generating a random number stream according to an embodiment of the present invention. [Figure 4] Shows a computerized system mainly in software for efficiently generating a random number stream according to an embodiment of the present invention. [Figure 5] Is a flowchart showing a method for efficiently generating random numbers in a computerized system according to an embodiment of the present invention. [Figure 6] Is a sequence diagram showing a method for efficiently generating random numbers in a computerized system in pair / parallel according to an embodiment of the present invention. [Figure 7] Shows the implementation of an XOR separation operation in a computerized system for efficiently generating random numbers according to an embodiment of the present invention. [Figure 8] Shows the implementation of a mask generator or data Mux separation operation in a computerized system for efficiently generating random numbers according to an embodiment of the present invention. [Figure 9] Shows the implementation of a MOD separation operation in a computerized system for efficiently generating random numbers according to an embodiment of the present invention. [Figure 10] Is a clock diagram showing the synchronous operation of the components of a computerized system for efficiently generating a stream of random numbers according to an embodiment of the present invention.

Mode for Carrying Out the Invention

[0026] Mode for Carrying Out the Invention For the purpose of facilitating an understanding of the principles of the present invention, exemplary embodiments shown in the drawings will be described herein with reference and using specific terminology. However, it will be understood that this is not intended to limit the scope of the invention. Any changes and further modifications to the features of the invention shown herein, and any additional applications of the principles of the invention shown herein, would be conceivable by a person skilled in the art and owner of this disclosure, and should be considered within the scope of the invention.

[0027] Throughout this specification, any reference to “embodiments,” “examples,” or similar terms means that certain features, structures, characteristics, or combinations thereof described in relation to an embodiment are included in at least one embodiment of the present invention. Therefore, throughout this specification, any appearance of the words “embodiments,” “examples,” and similar terms could, but not necessarily, all refer to the same embodiment, a different embodiment, or one or more figures. Furthermore, any reference to “embodiments,” “examples,” or similar expressions concerning two or more features, elements, etc., does not necessarily mean that those features are related, dissimilar, or identical.

[0028] Each description of an embodiment or example should be considered independent of any other description of an embodiment, despite the use of similar or identical language characterizing each embodiment. Therefore, if an embodiment is identified as “another embodiment,” the identified embodiment is independent of any other embodiment characterized by the “another embodiment” language. The features, functions, etc., described herein can be considered to be combined with one another, in whole or in part, because the claims and / or technology may directly or indirectly, implicitly or explicitly, indicate them.

[0029] As used herein, “comprising,” “including,” “containing,” “is,” “are,” “characterized by,” and their grammatical equivalents are inclusive or non-exclusive terms that do not exclude additional unenumerated elements or methodological steps. “Comprising” should be interpreted as including the more restrictive terms “consisting of” and “consisting essentially of.”

[0030] Figure 1 shows a computerized system 100 for efficiently generating a stream of random numbers according to one embodiment of the present invention. A controller 110 is shown operably coupled to a data loop 120, a data operator 130, and a derived random number utilization system (DRNUS) 140. There is also a random number source 150 functionally coupled to the data loop 120 and multiple data feeds 160 coupled to the data operator 130. The illustrated data loop 120 also supplies the data operator 130, which supplies the derived random number utilization system 140. The DRNUS 140 may or may not be part of the illustrated system depending on the particular embodiment.

[0031] The illustrated controller 110 provides operational control for various parts of the illustrated system. The controller may include one or more scripts, programs, control circuits, processors, buses, memory, network adapters, power systems, etc., and may interface with data loops, data operators, and derived random number utilization systems, and may provide them with instructions and / or control signals, along with any analysis, processing, or configuration of them. The controller may be a microcontroller, a plug-in board, a state machine, a flash controller, etc., and / or a combination thereof. The controller is coupled to the data loop via at least an incrementer 125, which may be embodied within the controller, within the data loop, and / or between them. The controller sends an increment / decrement signal to the data loop, which moves to an index in the data loop relative to the loop-like array of the data loop via the incrementer / decrementer 125 (wherein used herein, incrementer and decrementer are synonymous). The incrementer 125 may be as simple as a clock signal coupled to a shift register in a way that shifts a value related to the loop into the shift register, thereby moving that value to other structures (e.g., indices, input / output ports). The incrementer 125 may also include logic circuits that change which lines are actively coupled to the loop, thereby the structures being coupled to the loop at different positions. This may include gate connections that are either open or closed according to gate signals. Because there are many implementations that are very expensive, slow, difficult, and / or require large power requirements compared to others, the precise implementation of an incrementer will generally be subject to operating requirements and manufacturing constraints, and therefore it is generally expected that simple incrementer structures are generally preferred.

[0032] Therefore, the controller can manage the relative position of an index and any changes made to it. The controller sends control signals to data operators to manage the selection, modification, alteration, activation, deactivation, and driving of active operators from the operator library of data operators. The controller receives requests from the derived random number utilization system for additional derived random numbers and, in response to such requests, drives activity in the data loop, causing the data operators to generate derived random numbers to satisfy the requested request.

[0033] The following is a non-restrictive example of a controller and its internal structure. Such a controller may include a bus that communicates with a system that requires derived random numbers. The controller receives such a request and uses an internal driver to interpret the request, e.g., how many numbers are desired, when, what addresses / instances are specified for the resulting values, and what format / size / range is sufficient to satisfy the request. The controller may then check an index age counter within the controller, which counts how many times it needs to check whether it is necessary to move the index before generating additional random numbers. If the age counter is 0, a control signal is sent to the incrementer to increment the index, thereby moving its position in a loop array, and then the age counter is reset to a number (which may be predefined according to the schema, or may be a random number that can be derived from a random number source and / or the output of the computerized system itself). If it is not 0, the age counter is decremented. The controller can also check the operator age counter, which can be decremented if it is not zero, or reset if it is zero, and a signal is sent to the data operator to select a new operator from the operator library, which can be selected according to a predefined schema or a random schema.

[0034] The controller can then signal the data loop and data operators to together generate a specific number of random values, which can then be output to a derived random number utilization system at a specific network address, or otherwise made available to the DRNUS. If additional random values ​​are required in the operation of the illustrated system, the controller may order the random values ​​in addition to those requested by the DRNUS, and a specific delivery address / location may be used. Alternatively, the computerized system can "double-dip" by internally utilizing the random values ​​generated during the operation of one or more DRNUSs and delivering or otherwise making those values ​​available to the requesting DRNUS. As a non-limiting example, the illustrated data feed 160 may be a network address location and / or memory location to which the data operator's output transmits derived random values ​​and which are then used by the data operator when creating subsequent random values. Furthermore, since the illustrated system utilizes a random number source 150, that random number source may be the output of the illustrated data operator and / or the output of a separate computerized system for efficiently generating random numbers, as described herein.

[0035] The illustrated data loop 120 includes a simple feedback loop array of random data 122, each having an index 124 associated with a specific position in the loop array. There are also input ports 126 and output ports 128 through which data can be imported into and exported from the loop array, each associated with an index position. Such a thing may also be a shift register, which can be manufactured using D-type flip-flops, generally one flip-flop for each data bit. The data loop may also be a shift register. Such a shift register may be a universal shift register such as a TTL 74LS194, 74LS195, or CMOS 4035, but is not limited to these. Furthermore, many integrated circuits include shift registers as components of a chip (e.g., CPU, GPU, serial port, system-on-a-chip "SoC").

[0036] The simple feedback loop-like array of random data 122 shown in the illustration is a hardware memory element that structures the array into a loop (i.e., the beginning and end of the array are adjacent to each other). Furthermore, if the hardware includes the ability to shift data along the loop's position, there is a simple feedback relationship between the beginning and end of the loop, and as a result, data passing from end to beginning or vice versa does so without changing its data value. This is different from linear or nonlinear feedback shift registers, where the data values ​​passing between the beginning and end of the loop in such registers change according to a linear or nonlinear process. As a non-limiting example, a simple feedback loop-like array of random data may be implemented as a circular shift register, a circular memory buffer, a series of sequential (actually sequential or logically sequential) memory address locations on a hard drive, a solid-state drive, a flash drive, RAM, SRAM, DRAM, Z-RAM, A-RAM, FERAM, CBRAM, PRAM, STT-RAM, SONOS, RRAM, Racetrack Memory, NRAM, 3D XPOINT, millipede memory, virtual memory coupled to one or more different hardware memory sources, ROM, PROM, EPROM, EEPROM, etc., and combinations thereof.

[0037] The size of the data loop (i.e., the number of serial bits) is generally large enough to produce the desired output in a satisfactory manner for the intended use. This generally means that the data loop is large compared to the expected usage rate (e.g., the larger the data loop, the less frequently it will be necessary to reload more data from the random number source). Therefore, the size of the data loop is chosen to be large enough so that reload operations do not significantly impair the desired operating speed / efficiency.

[0038] The illustrated index 124 points to a specific position within a loop-like array of random data. This may point to the boundary between the beginning and end of the loop-like array, or it may point to a different position. The index itself may be movable while the loop-like array remains fixed, the index may remain stationary while the loop-like array shifts data along the array, or both may move relative to each other. Regardless of the actual movement / shift of the index and the loop-like array, it is possible to change their relative positional relationship and thereby change the valid "value" held by the loop-like array. Changing the relative positional relationship between the index and the loop-like array can also change the relative positional relationship between the input / output ports and the loop-like array and / or the index. The hardware representation of the index will vary depending on the specific hardware environment of the loop-like array. The index may be as simple as a recording metatag, gate, line-in, uniquely identified memory cell, or a combination thereof, or it may be a more complex implementation, but not limited to, a separate record, a pointer implementation in a computerized program / script, a counter, or a combination thereof.

[0039] As an example of non-restrictive prediction, the following may be a string of binary values ​​held within a 16-bit loop array, as defined by the index relationship to the loop array. While a 16-bit example is provided to help illustrate the concept of a simple feedback loop array, many practical implementations of the simple feedback loop arrays described herein are likely to be loop arrays of thousands to millions of bits or more.

[0040] 1001011110010010 This value is represented as 38802 in decimal. When this value is shifted one bit to the right in a simple feedback loop array, the value changes as follows:

[0041] 0100101111001001 This new value is represented as 19401 in decimal. The subsequent 1-bit shift values, represented in decimal, are 42468, 21234, 10617, 38076, and 19038. The 16-bit loop array may be shifted 15 times before repeating the sequence. Thus, a single 16-bit value loaded into a simple feedback loop array can be used as if it were actually 16 different values.

[0042] The illustrated input port 126 and output port 128 enable write / read operations to and from the loop array, allowing values ​​stored there to be changed to new values ​​and values ​​stored there to be read from there. The ports may be single-bit write / read ports, allowing a single bit to be changed / read. In such a case, after changing / reading one bit, the loop array may be shifted to shift the new value to the port, then that bit may be written / read, and then the entire loop array may be rewritten / read by repeating until the entire loop array is rewritten / read. The input ports may be multi-bit write ports, allowing writing to multiple bits at once, and may include the ability to write to all bits of the loop array. The structure of the input ports will vary depending on the hardware of the loop array. If the loop array is a shift register, the input ports may simply include a line-in with a gate to determine whether the input port is writing. Shift register ports (and other ports) may be serial-in-serial-out (SISO) ports, serial-in-parallel-out (SIPO) ports, or parallel-in-serial-out (PISO) ports.

[0043] The illustrated random number source 150 provides true random values ​​and / or pseudo-random values ​​to the data loop. Such values ​​can be derived from physical sources such as atmospheric noise, thermal noise, radio noise, clock drift, Zener diode avalanche noise, optical disturbances, amplified spontaneous emission noise, external electromagnetic and / or quantum phenomena (e.g., radioactive decay, cosmic microwave background radiation), pseudorandom number generators (PRNGs), for example, but not limited to linear congruence generators, middle squares, Weyl sequences, Römer generators, lag-assisted Fibonacci generators, linear feedback shift registers, Witchman-Hill generators, Rule 30, inverse congruence generators, Park Miller generators, ACORN generators, MIXMAX generators, Add-with-carry, Subtract-with-borrow, Multiply-with-carry, Maximum Periodic Round Trip, KISS, Xorshift, WELL, JSF, ARS, Threefry, Philox, SplitMix, PCG, Xoroshiro128+, 64-bit MELG, Squares RNG, and those based on the Mersenne Twister algorithm. There is also the TRNG9803 hardware random number generator, which combines multiple methods. Furthermore, there are cryptographic algorithms for generating very high-quality streams of random values ​​(at high cost), including but not limited to stream ciphers, block ciphers, and cryptographic hash functions. There are also methods that link computationally difficult problems rather than relying on algorithms, which can generate high-quality values ​​but are computationally intensive, and include but are not limited to the Bram-Mikari algorithm, Blum-Bloom-Schub, and Naor-Reingold pseudorandom functions.

[0044] The illustrated random number source 150 may include a memory storage device for holding random values ​​supplied to the system. It may also include hardware and / or software for implementing one or more algorithms and / or computational operations for generating random values ​​as required by the illustrated system. As a non-limiting example, the illustrated system may be used to generate random values ​​for itself and / or for other computerized systems described herein. Thus, the systems described herein may be daisy-chained to various implementations of itself to generate multiple streams of random values.

[0045] The illustrated data operator 130 manipulates the output of the data loop 120 and is functionally coupled to its output port 128. The data operator 130 takes the value from output port 128 and the values ​​from multiple data feeds 160 as input 134. The input is functionally coupled to an active operator 136, which is activated from the illustrated operator library 137. The active operator 136 operates on the received value and is functionally coupled to output 138, which provides the resulting value.

[0046] The available data operators are ambiguous and can include one or more arithmetic and / or bitwise operations. Non-restrictive examples include addition by 1, division by 2 (truncation or rounding up), and bitwise NOT. These examples illustrate data operators that change an input value from an input value to some other value, and such are sufficient to generate a new value. The new value may or may not retain the randomness quality of the original value, and this may or may not be important depending on the specific implementation required.

[0047] However, in many cases, it is important and / or valuable for data operators to possess certain qualities. One such quality is that a data operator decouples its output from its input, meaning that the input value cannot be determined by knowing the operator and the output. For example, if an operator is addition by 1 or division by 2, and the operator (including one of its operands) is known and the value of the result is known, then the input is also known. For example, if the operator is x+1=y and y is known, then x is also known. In contrast, if an operator is addition or division, but the other operand comes from an unknown data feed, then the input cannot be determined by knowing the output and the operator (for example, x+z=y, and y is known, but this does not determine the value of the input x). This isolation provides important value for many implementation forms. The following are non-restrictive examples of isolation operators where the input operands are not specified with the operator: Two or more operands; arithmetic addition, subtraction, division, Mod; bitwise OR, XOR, addition; mask / MUX operations, etc. and combinations thereof.

[0048] Another quality of data operators is the preservation of randomness quality from input to output. Different operators can preserve / maintain or degrade the randomness quality of the input. In general, it is impossible to reliably improve the randomness quality of an input to an output using data operators. As a non-restrictive example, an operator that has a significant bias over time to produce one of 1 or 0 will degrade randomness quality, even if the input has no bias towards its value in the output (e.g., arithmetic addition of 1). This is because one test of randomness is to check for a substantially equal number of 1s and 0s in the output. For many purposes, degrading randomness quality is not appropriate.

[0049] XOR, Mod, and Mask / MUX are examples of data operators that preserve the randomness of the input stream. In particular, such operators are not recursive functions and therefore do not have "memory" between sequential operations, thus they do not have a bias towards a particular value and do not tend to generate patterns in the output stream.

[0050] Another quality of data operators is whether they consume more "randomness" than they generate. XOR and Mask / MUX each require multiple streams of random values ​​to operate, and then generate a single stream of random values. Thus, they consume more values ​​than they produce. In contrast, the Mod operator can continue to generate random values ​​with a single static divisor and therefore consumes only one stream of random values ​​to generate a single stream of random values. It is also possible that Mod generates more bits of random values ​​than it consumes. Thus, Mod operators and others have the quality of maintaining or multiplying the amount of random values ​​in the system, which can be beneficial in some applications.

[0051] The illustrated data feed 160 provides values ​​to the data operator 130 for use in manipulating values ​​from the data loop 120. Multiple data feeds 160 are shown, and the exact number of different data feeds will vary from implementation to implementation. In particular, various operators within the operator library may require multiple inputs of values ​​to perform the value operations they respect, and data feeds enable the supply of such values. Such may include the output of a PRNG function, a pool of uncertain values, a real-time feed of random values ​​(e.g., atmospheric noise), the output of a system similar to those described herein, and combinations thereof. The exact configuration of a data feed depends on the purpose and operational constraints provided by the particular implementation. As a non-limiting example where duplication or pair generation of output values ​​from a data operator is desired, data feeds are generally required to be supplied in a precisely reproducible / replicable manner (e.g., PRNG) and not in a precisely reproducible manner (e.g., atmospheric noise).

[0052] The illustrated derived random number utilization system (DRNUS) 140 is functionally coupled to the data operator 130 so that the DRNUS can receive values ​​from there. The DRNUS 140 is also functionally coupled to the controller 110 so that it can request values ​​from there and / or provide the controller 110 with requested characteristics (e.g., value bit length, value quality, seed value, and / or other metadata necessary to replicate a set of random values, such as situations where the DRNUS needs to receive a replicated set of random values ​​as a paired system). Non-limiting examples of the DRNUS 140 include programs / systems that utilize random values ​​(e.g., gaming engines, gaming devices, simulation systems, gaming systems, cryptographic systems, authenticators, key generators, compression engines, expansion circuits, hash circuits, noise generators, statistical sampling systems, etc., and combinations thereof). Thus, a computerized system for efficiently generating a stream of random numbers, similar to the embodiments described herein, may be a DRNUS of another such system.

[0053] During operation, the data loop 120 is loaded with values ​​from the random source 150 via its input port 126. The derived random number utilization system DRNUS 140 requests a value from the controller 110, which may include details about the requested value. The controller 110 can provide operational instructions to an incrementer 125 coupled to a set of data operators 130 and / or index 124 of the data loop. Such instructions may include one or more of the following instruction sets (or similar instructions), which may be executed directly by the receiver and / or indirectly by issuing further instructions to appropriate resources.

[0054] - Increment / decrement index 124 with respect to loop 122. - Start / end / modify the output of values ​​from data loop 120 through output port 128 to the input of data operator 130. - Start / end / modify the output of values ​​from one or more data feeds 160 - Start / end / modify active operator 136 - Modify the restrictions imposed on operator library 137 (for example, which operators or groups of operators are valid choices). - Switch the output of values ​​from output 138 and / or output port 128. - Change the mode of the output from output 138 and / or output port 128 (e.g., word size, value type, e.g., binary, ternary, decimal).

[0055] - Load values ​​from random number source 150 into data loop 120. - Terminate / start / change connections between system resources (e.g., join a new data feed to the input of a data operator, swap out a data loop joined to the input of a data operator, add a parallel operating data operator to a system supplied by the same data loop, switch to a new DRNUS, and terminate existing DRNUS connections).

[0056] The system, under the command of the controller 110, supplies values ​​from the data loop 120 to the data operator 130, where those values ​​are manipulated and then output to DRNUS as requested. Generally, the operations provided by the data operator separate the output of the data operator from the output of the data loop, but this is not always the case.

[0057] As a non-restrictive example, if the active operator performs a simple NOT operation, the output retains, but does not isolate, the quality characteristics of the random values ​​in the data loop. In particular, the NOT operation flips bit values ​​from 1 to 0 and 0 to 1. This essentially creates its mirror image, so the ratio of 1 and 0 values ​​in the stream is preserved (as its reciprocal), and when evaluating a stream of random values, quality is judged by its "distance" from the single ratio, so the inverse ratio is of the same quality as the non-inverse ratio. However, the mirror image of the values ​​from the data loop provides a map of what those values ​​are. Specifically, by knowing the output of the data operator and that the NOT operator was used, we can know what the data loop values ​​are. That said, when isolation is not required, the NOT operator provides a very fast and efficient output value that is different from what was loaded into the data loop.

[0058] For purposes requiring isolation, the non-restrictive operator types XOR, Mask generator, data MUX, and MOD are useful. These operator types require the use of a data feed and can produce output values ​​isolated from the values ​​stored in the data loop. In particular, if the operator is known and the output is known, the values ​​in the data loop are not revealed. Furthermore, the values ​​from the data feed are not revealed. Thus, the security of values ​​in the data loop is maintained even if the system architecture is known. This is very valuable because it allows values ​​stored in the data loop to behave as if they were one-time pads that are generally understood to be obviously indestructible, although PRNGs, no matter how complex, are obviously indestructible.

[0059] According to one embodiment, there may be a computerized system for efficiently generating a stream of random numbers. The system may include a data loop having one or more of the following: a data loop having one or more of a simple feedback loop-like array of random data, an index, and / or an output port which reads a value from the simple feedback loop-like array based on the relative position of the index to the simple feedback loop-like array; a data operator having one or more of an input and an output which can provide access to an output value from the data operator, and which may be functionally coupled to the output port so that a value from the output port is supplied to the data operator as an input value; and / or an incrementer which can be functionally coupled to the data loop and shifts an index relative to the simple feedback loop-like array.

[0060] The data loop may further include input ports. Values ​​from output ports may be multi-bit values. The data loop may be a universal shift register. The data loop may be a shift register. The data operator may be a separable operation selected from the group consisting of XOR, mask generator, data MUX, and MOD.

[0061] A second data loop may also exist that has input ports that can be functionally coupled to the output of a data operator, so that the output values ​​from the data operator are input to the second data loop. A source of random data may also exist that can be functionally coupled to the input ports of the data loop, so that a loop-like array of random data is supplied with data from a source of random data.

[0062] Figure 2 shows a primarily hardware-computerized system 200 for efficiently generating a random number stream according to one embodiment of the present invention. A controller 210 operably coupled to a shift register 220, a data operator 230, and a derived random number utilization system (DRNUS) 240 is shown. Multiple data feeds 260 coupled to the data operator 230 are also shown. The illustrated shift register 220 also supplies the data operator 230, which supplies the derived random number utilization system 240. The DRNUS 240 may or may not be part of the illustrated system depending on the particular embodiment.

[0063] In contrast to Figure 1, there is no random number source functionally coupled to the shift register 220. The illustrated shift register is loaded at manufacturing and does not change. Therefore, the shift register is of sufficient size to produce the desired output in a satisfactory manner for its intended use. This generally means that the shift register is very large compared to the expected lifecycle. As a non-limiting example, if the device is expected to produce an output of approximately 500,000 random values ​​during its lifespan, a shift register of 10,000 bits or more is far more than sufficient for the expected use and therefore does not need to supply any further random values.

[0064] The illustrated shift register 220 is generally a cascade of flip-flops sharing the same clock. The output of each flip-flop is connected to the input of the next flip-flop in the chain / loop. Thus, the circuit shifts the bit array stored therein by one bit at a time (i.e., shifts right / left) on each transition of the clock input. This occurs when, on the clock signal, each flip-flop shifts its value to the input of the next flip-flop. Here, the shift register is a simple feedback shift register (a so-called circular shift register) where the last bit in the array is shifted to the input of the first bit in the array without modification or manipulation.

[0065] A shift register can have both parallel input and serial output (e.g., SIPO and / or PISO configurations). The illustrated output port 228 may contain multiple pins / wires, allowing for the simultaneous output of multiple bits from each shift of the register, up to the total number of bits in the shift register. Additionally, the illustrated input port 226 of the shift register can be disabled or removed after manufacturing to prevent further modification of the values ​​in the array. Typical shift registers used in various computing applications (e.g., delay circuits, hardware stack implementations, hardware solutions for the problem of too few pins / wires, changing output / input to / from parallel and serial as pulse extenders, and circular memory) are of about 10, 100, 1000, or 10k bit array size, but shift registers used in various embodiments of the present invention may be much larger, such as 100k, 1M, 10M, 100M, and / or 1 billion or more.

[0066] The illustrated controller and data operators are also hardware devices, and Figure 2 can represent a fully hardware system for efficiently generating a stream of random numbers. In such an example, the operator library 237 may include an array of gate-controlled operator circuits (e.g., XOR, MUX, MOD, mask generators) that are activated only one at a time (or in other ways limited quantities), each having similarly restricted access to gate control / output. The data feed 260 may include a hardware random number generator that includes, but is not limited to, a hardware PRNG generator and / or memory components (e.g., delay circuits, circular memory) having random values ​​stored internally.

[0067] Figure 3 shows a hybrid hardware computerized system 300 for efficiently generating a random number stream according to one embodiment of the present invention. The illustrated system includes a shift register, a data operator, and a controller operably coupled to a derived random number utilization system (DRNUS). There is also a memory component 302 functionally coupled to the input port 326 of the shift register via direct memory access (DMA) 304. There are multiple data feeds coupled to the data operator. The illustrated shift register also supplies a data operator 130, which supplies the derived random number utilization system. The DRNUS may or may not be part of the illustrated system depending on the particular embodiment.

[0068] The illustrated memory components are devices used to store information for use in a computer or associated hardware device. These are typically semiconductor memory devices, often metal-oxide-semiconductor (MOS) memory where data is stored in memory cells on a silicon integrated circuit chip. These may be implemented as RAM, DRAM, SRAM, cache memory, ROM, PROM, EPROM, EEPROM, tape drive memory storage, hard drive memory storage, floppy disk memory storage, CD / DVD / optical disk storage, volatile / non-volatile / semi-volatile memory, FERAM, CBRAM, PRAM, STT-RAM, SONOS, RRAM®, racetrack memory, NRAM, 3D XPoint, virtual memory, and / or millipede memory, and / or combinations thereof. The illustrated memory 302 contains random values ​​and is functionally coupled to a shift register via DMA 304.

[0069] The illustrated DMA304 enables memory access independent of the CPU. Therefore, the illustrated system can operate to load new values ​​into the illustrated shift register on demand without having to wait for or occupy CPU cycles. This is particularly important when DRNUS utilizes available CPU cycles, and the illustrated system's intrusion into CPU resources would cause slowdowns or delays within DRNUS. In DMA, the CPU typically initiates the transfer, performs other operations while the transfer is in progress, and finally receives an interrupt from the DMA controller (DMAC) when the operations are complete. Standard DMA, also called third-party DMA, uses a DMA controller. The DMA controller can generate memory addresses and initiate memory read or write cycles. This includes several hardware registers that can be written to and read by the CPU. These include a memory address register, a byte count register, and one or more control registers.

[0070] Depending on the functionality provided by the DMA controller, these control registers can specify several combinations of source, destination, transfer direction (reading from or writing to an I / O device), transfer unit size, and / or the number of words / bytes to transfer in a single burst. To perform input, output, or memory-to-memory operations, the host processor initializes the DMA controller with a count of the number of words / bytes / block size to transfer and the memory address to be used. The CPU then instructs the peripheral device to begin transferring data. The DMA controller then provides the address and read / write control lines to system memory. Each time a byte of data is ready to be transferred between the peripheral device and memory, the DMA controller increments its internal address register until the entire block of data has been transferred.

[0071] Figure 4 shows a primarily software-computerized system 400 for efficiently generating a random number stream according to one embodiment of the present invention. A data loop in memory 420, a data operator, and a controller operably coupled to a derived random number utilization system (DRNUS) are shown. Multiple data feeds coupled to the data operator are also present. The illustrated data loop in memory 420 also supplies the data operator, which supplies the derived random number utilization system. DRNUS 140 may or may not be part of the illustrated system depending on the particular embodiment.

[0072] The illustrated data loop within memory 420 includes, but is not limited to, one or more memory devices / structures, such as those described herein, which can be managed via a memory controller and may include the body of virtual memory and / or even one or more swap files, caches, databases and / or even one or more federated databases. The data loop within memory 420 includes a logical arrangement of related physical and / or virtual memory cells to form a loop-like array of memory associated with an index, such that the contents of the memory "cells" may be shifted in one direction or the other, and / or the order of the contents of the memory "cells" may remain immutable but the index may be shifted relative to the array of memory "cells". The logical arrangement may be managed / controlled by scripts, systems of pointers, data arrays / matrices, and combinations thereof.

[0073] Figure 5 is a flowchart illustrating a method for efficiently generating random numbers in a computerized system according to one embodiment of the present invention. The illustrated method for efficiently generating random numbers in a computerized system 500 comprises the steps of loading a data loop 510, then reading a value from the data loop 520, where the current decoupling operation is "stale", selecting a decoupling operation 530, then performing a decoupling operation on the read value, thereby generating an output value 540, then moving the index of the data loop 550, and the process loopback to step 520 of reading a value from the data loop. Advantageously, a single n-digit random value stored in the data loop can be used to efficiently generate a large number (≧n) of separated random values ​​from it.

[0074] Step 510 in the illustration, which loads the data loop, sets bit values ​​as stored values ​​in a loop-like array of data storage units (e.g., memory cells, bit registers, data latches, and flip-flops). Loading can be achieved sequentially and / or in parallel, or a combination thereof. Loading may occur during the manufacturing of the data loop. This may occur in real time while the associated device / system for generating random values ​​is in operation. There may be one or more input lines that can be gated to allow write operations to be performed on the data storage units. The quality of randomness resulting from the isolation step generally depends largely on the quality of randomness of the values ​​in the data loop, and it is appropriate to be selective with respect to where / how the load values ​​for the loading step are sourced, i.e., with respect to the source of the random data into which the data loop is loaded having a quality of randomness greater than or equal to the desired quality of randomness intended for the output values.

[0075] Step 520 in the illustration, which reads a value from a data loop, generally involves reading a multibit value from the data storage units of the data loop as a contiguous sequence of bits (relative to the position of the index relative to the data storage units). The read may be performed as a bitwise read and / or as a parallel read in which multiple bits can be read simultaneously (e.g., via multiple parallel gated lines functionally communicating with a particular data storage unit). Furthermore, multiple multibit values ​​can be read simultaneously from the same data loop, and the read structure allows for simultaneous reads from different parts of the same data loop (e.g., two different arrays of gated red lines functionally coupled to two non-identical sets of data storage units in the data loop). The size of the read value may be equal to the size of the data loop (e.g., the data loop contains 1 million sequentially arranged data storage units and the read value is 1 million bits long), or it may be smaller than the size of the data loop (e.g., the data loop contains 1 million sequentially arranged data storage units and the read value is 50,000 bits long). Once a value is read, it is retained / stored by the system / device to make the actions performed on it accessible.

[0076] Step 530 in the diagram for selecting a isolation operation includes conditionally determining one or more isolation operations and / or parameters (as well as the associated physical structures / programming that implement such isolation operations and / or parameters) to be used in order to “activate” so that they can operate on read values ​​held / stored by the system / device (e.g., by the operation of a script, random selection, instructions from a third-party device, settings during installation / manufacturing of the associated device / system, or instructions from a controller). “Activating” the associated structures / programming may include activating one or more gate input lines to a set of transistors, flip-flops, chips, chipsets, etc., that function to perform the selected isolation operation, thereby allowing the read values ​​to be input into the structures for processing. If the isolation operation includes software components, activation may include calling a function or software module that performs the selected isolation operation.

[0077] The step 530 of selecting this isolation operator may be performed at each cycle of the illustrated method, but generally, it is expected that new isolation operators and / or parameters will not be needed very often. As a non-limiting example, if a load value of length n has a reasonable quality of randomness, the device / system operating the illustrated method may continue to use the same isolation operator without changing the isolation operator or the parameters used with it n times before there is a risk of repeating patterns appearing in the output. Therefore, generally, it is expected that this selection step 530 will not occur in most cycles of the illustrated step, especially if the data loop is large. In fact, in some implementations (e.g., when the data loop is large compared to its size and the actual use / lifecycle of the system is small), the step of selecting the isolation operator may be performed only once during the manufacture of the device / system and will not be changed thereafter.

[0078] Step 540 in the diagram, which separates the read value, involves performing a selected separation operation on the read value, thereby generating an output in the form of a new value separated from the read value. Such separation is performed by the hardware and / or software structure of the selected separation operation. As a non-limiting example, if the separation operation is an XOR operation, it may include a CMOS XOR gate, a MOSFET XOR (e.g., using pass transistor logic), a NOT gate followed by an XNOR gate, and / or a combination thereof.

[0079] If multiple operations are selected, the isolation step may be performed multiple times, and this may be done in parallel. Thus, a single read value can yield multiple or even more output values ​​separated from the read value. When the supply of isolated random values ​​is desired at a rate as large as the clock rate of the associated system, this feature of multiple parallel isolation operations can be used to compensate for significant mismatches between the clock rate of the device / system generating the output values ​​and the device / system desiring the output values.

[0080] Step 550 of moving the index of a data loop includes changing the position of the index relative to the loop-like array of data storage units of the data loop. This may include shifting all stored values ​​within the data storage unit by one or more positions in one direction. This may include deactivating an active index structure at one position around the data loop and activating index structures associated with different positions around the data loop. This may include shifting the index value around the data loop (for example, in the case of a set of pairs of data loops, the first is for the loop-like array of stored values, and the second is circumscribing the first or otherwise structurally parallel to the first and acts to hold an index marker, which is shifted around the second loop, and may be a single bit value (e.g., 1 and all the rest 0) that identifies the current position of the index around the first loop). When the read step 520 is performed in relation to the index, moving the index changes the next read value to a new value that is significantly different from the previous read value (the stored values ​​are sufficiently random).

[0081] According to one non-limiting embodiment, there is a method for rapidly and efficiently generating a series of random numbers from a source of random numbers in a computing system. The method includes the steps of loading a data loop with random data which may be from a source of random data, the data loop comprising one or more of a loop array of stored values ​​and indices; reading a value which may be multibit from the data loop in relation to the position of the index in the loop array; performing a first data operation on the value to thereby derive a derived random number from the multibit value; moving the index to a different position in the loop array in relation to the loop array; and / or repeating one or more of these steps to thereby generate a series of derived random numbers.

[0082] The data loop is a shift register, which may be a simple feedback shift register, where "simple feedback" means that the data is not manipulated as the shift register increments, but instead remains constant as the value shifts through the register, particularly for values ​​returning from the "tail" to the "head" of the register. Such a register can be manufactured using D-type flip-flops, generally one flip-flop for each data bit. The shift register may be a universal shift register such as a TTL 74LS194, 74LS195, or CMOS 4035, and / or may be included as part of a larger integrated circuit (e.g., CPU, GPU, serial port, SoC). Different positions may be adjacent positions. The data operation may be a segregated operation, which may be selected from the group consisting of XOR, mask generator, data MUX, and MOD. The source of random data may be the output of one or more methods / steps described herein. The step of loading the data loop may be performed by direct memory access. The data operation may be a MOD operation, which is performed with a multi-bit value as the numerator and a denominator with fewer bits than the multi-bit value. The denominator may be a value obtained directly from, or derived from, a source of random data. The denominator may be greater than the desired range of derived random numbers. The controller may include one or more of the following: programmable logic circuits, scripts, and drivers.

[0083] There may be a step of automatically selecting a separation operation from a plurality of separation operations depending on the controller. Simultaneously with the step of performing the first data operation, there may be a step of performing a second data operation on a multibit value to derive a second derived random number from the multibit value. Furthermore, a second / secondary computing system may independently perform one or more of the steps described herein using substantially the same random data source as the primary computing system, so that the data loop of the second computing system is loaded identically to the data loop of the primary system, and perform substantially the same data operations so that the resulting derived random numbers are the same as those derived by the primary system / method, thereby generating a second set of derived random numbers that are identical to the set of derived random numbers of the primary system.

[0084] The second computing system may be structurally different from the primary computing system in at least one of the data loop, read operator, shifter, controller type, and data loop loader type. As an unrestricted example, the second computing system may use a shifter that shifts stored values ​​in a loop array while the first computing system activates and deactivates an index structure, thereby shifting index values. As yet another unrestricted example, the second computing system may utilize a universal shift register as its data loop, and the first computing system may utilize a virtual data loop formed using data stored on a hard drive. As yet another unrestricted example, the second computing system may utilize DMA, while the first computing system does not. As yet another unrestricted example, the second computing system may have a controller with a script stored in RAM, while the first computing system has a pure hardware controller that stores its script in ROM. Each of these examples illustrates first and second computing systems that can generate the same set of random values, while having different specific structural embodiments.

[0085] Figure 6 is a sequence diagram illustrating a method for efficiently generating random numbers in a paired / parallel computerized system according to one embodiment of the present invention. Each illustrated computerized system includes controllers (controller 1 and controller 2) functionally coupled to their respective data loops (data loop 1 and data loop 2, respectively) and their respective decoupling operators (decoupling operator 1 and decoupling operator 2, respectively). In the illustrated example, the two computerized systems can be called paired systems (i.e., their structures are sufficiently identical to produce identical output streams given identical input values ​​from the illustrated random number source). The two computerized systems can also be said to be parallel systems (i.e., their structures include sufficient differences to produce different output streams given identical input values ​​from the illustrated random number source). In particular, when multiple decoupling operators are used simultaneously within the same system, the two systems can be both paired and parallel, producing identical streams between the two systems and one or more other streams that are not identical between the two systems. Thus, a single random number source can be efficiently utilized across multiple systems as desired to generate outputs in a paired / parallel manner.

[0086] In the illustrated example, values ​​from a random number source are loaded into the data loop of each system.610 Next, the data loop is read out.630 Loop operations620 are performed within each system, and the controller determines whether the decoupling operator and / or its parameters should be changed.640 If such a change occurs, the decoupling operator then operates on the read values.650 The result of such operation is provided as output, the index of the data loop is shifted (e.g., incremented),660 and the loop is repeated, thereby generating a stream of decoupled values.

[0087] Figure 7 shows the implementation of an XOR separation operation in a computerized system for efficiently generating random numbers according to one embodiment of the present invention. The illustrated XOR separation operation 700 is shown as an active operator selected from the operator library of the data operator (see Figure 1) and is therefore functionally coupled to the input of the data operator. The XOR separation operation 700 receives a read value 710 as one of its inputs and a second input 720 from the data feed. There is an XOR operator 730, which may be a set of logic gates, a software XOR function, or a combination thereof. Such may include CMOS XOR gates, MOSFET XOR (e.g., using pass transistor logic), a NOT gate followed by an XNOR gate, and / or a combination thereof. The XOR operator 730 may include a set of logic gates that can simultaneously perform XOR operations on many or all of the bits of the read value 710, although each can perform an XOR operation on a single bit. The output of the XOR operator 740 is functionally coupled to the output of the data operator and can therefore be provided as desired to one or more DRNUSs (see Figure 1).

[0088] Figure 8 shows an implementation of a mask generator or data mux (multiplexer) isolation operator (mask / mux selector / operator) in a computerized system for efficiently generating random numbers, according to one embodiment of the present invention. For clarity, the mask operator / generator is a software implementation of data mux. The illustrated mask / mux selector 800 is shown as the active operator selected from the operator library of the data operator (see Figure 1) and is therefore functionally coupled to the input of the data operator. The mask / mux selector 800 receives a read value 810 as one of its inputs, and second inputs 820 and third inputs 830 from the data feed. There is a mask / mux operator 850, which may be a set of logic gates, a software mask / mux function, or a combination thereof. It may contain one or more multiplexers / data selectors.

[0089] The Mask / MUX operator in the diagram is called a selector because it acts as a "selector" that determines whether the bit value of the read value from the loop array is selected from a first input (data 0) or a second input (data 1) from the data feed. If the bit value of the read value is 0, any value in the corresponding data 0 becomes the output value, and the bit value in data 1 is ignored and not used. If the bit value of the read value is 1, any value in the corresponding data 1 becomes the output value, and the bit value in data 0 is ignored and not used. Such a thing may be implemented in hardware as a switching gate (or an array of many switching gates) that switches the input lines of data 0 and data 1 based on the 0 / 1 bit value of the read value.

[0090] The mask / MUX operator 850 can include a set of logic gates, each capable of performing a mask / MUX operation on a single bit, but together they can simultaneously perform mask / MUX operations on many or all of the bits of the read value 810. The output 840 of the mask / MUX operator 850 is functionally coupled to the output of a data operator and can as desired be provided to one or more DRNUSs (see Figure 1).

[0091] Figure 9 shows the implementation of a MOD isolation operation in a computerized system for efficiently generating random numbers, according to one embodiment of the present invention. The illustrated MOD isolation operation 900 is shown as an active operator selected from the operator library of the data operator (see Figure 1) and is therefore functionally coupled to the input of the data operator. The MOD isolation operation 900 receives a read value 910 as one of its inputs and a second input 920 from the data feed. There is a MOD operator 930, which may be a CPU, SoC, GPU, or other computing integrated circuit, a set of logic gates, a software MOD function, or a combination thereof. If the MOD operator cannot perform the MOD operation in a single system clock cycle, the CPU may put one or more other components of the system into a pending state until the MOD operator completes its operation and produces an output.

[0092] The MOD operator 930 generally involves programming / circuitry that performs the following operations to output the modulo:

[0093] - Determine the molecule - Determine the denominator - Divide the numerator by the denominator, truncate, and determine the quotient. - Multiply the denominator by the quotient and find the product. - Subtract the product from the numerator to determine the modulo. There are special techniques for generating modulo using other operations, which can be used, and their associated constraints are met within the context of the system (e.g., numerator or denominator of a particular type / size / relationship). As an unrestricted example, the system can transform the numerator into the difference between a first number, which is the rounded product of the numerators, and a second number, which must be subtracted from that number to equal the original numerator. The second number can then be reduced in the same way by addition or subtraction, and this can continue until further reduction is impossible. A concrete example of such operation is as follows:

[0094] 9322=9500-178=9500-190+12≡12(mod95) In contrast to XOR and Mask / MUX operators, MOD operations are not performed as a single bitwise parallel operation across bit widths; instead, there is a sequence of operations that generally run in a specific order. This means that in order to produce an output value at system clock speed, the MOD operator must operate in clock cycles faster than the system clock, or the CPU must hold the system clock and wait for the MOD operator to finish.

[0095] In the MOD operation, the entire value of the read value 910 is used as the numerator in a mathematical division operation with the second value 920 as the denominator. The output is the remainder of such a division, but the quotient is generally not used at all and is often not even determined. Since the remainder is not divisible by the denominator, it must have a bit length equal to or less than the denominator (D bits), and therefore the choice of the denominator size controls the output bit length and the range of possible values ​​of the output. Also, for the output to have the same random quality as the read value, the size of the numerator (Y bits) must be significantly larger than the size of the denominator (D bits), i.e., Y >> D. Thus, the values ​​drawn from the data feed are selected by the system to be values ​​that generate the output word size as required by the relevant DRNUS, and the read values ​​are read to generate values ​​with a bit length sufficient to produce a high-quality output. The output 940 of the MOD operator 930 is functionally coupled to the output of the data operator and can as desired be provided to one or more DRNUSs (see Figure 1).

[0096] Figure 10 is a clock diagram showing the synchronous operation of components of a computerized system for efficiently generating a stream of random numbers according to one embodiment of the present invention. These components include a shift register and one or more arithmetic logic units (ALU0-ALU). n ), 1 preference data feed (data feed 0 - data feed nThe diagram shows a system clock that pulses a system clock signal to synchronize the operation of the DRNUS receiving the random number stream. The illustrated operation can generate random values ​​in a random value stream of substantially equal quality to the quality of the values ​​used to populate a shift register (which can be of very high quality) at clock speed, which is very efficient and can be very fast compared to a computerized system that generates random values ​​of similar quality.

[0097] The illustrated system clock generates a computerized system concept regarding the passage of time and provides a timing structure that allows various components to operate synchronously. The system clock generates a clock signal, and the various components can functionally communicate with the clock signal and perform operations in conjunction with a portion of the clock signal. The illustrated signal is a series of clock cycles (ticks) alternating between a first state (e.g., 0) and a second state (e.g., 1) in a square wave. The system clock generally includes a clock generator, which is an electronic oscillator that generates the clock signal. The clock generator is often a quartz piezoelectric oscillator, but alternative generators (e.g., tank circuits and RC circuits) may be used. The system may have two or more clocks, and the various components may operate according to different clocks (e.g., an internal clock versus a system clock) or multiple versions of the same clock (e.g., using frequency dividers and / or clock multipliers), but the illustrated embodiment focuses on a single clock to which the illustrated components are connected.

[0098] The illustrated shift register may be any type of shift register described herein and / or may include any of the features, functions, structures, etc., described herein. The shift register may be loaded with random values ​​and may include a structure that provides further value loading as needed. The illustrated shift register is configured to shift values ​​around the register in relation to the index in the change of the clock signal from a first state to a second state, and then output the value in the change of the clock signal from the second state to the first state. Thus, in each cycle, a random value from the shift register or a new set of random values ​​is presented to the system.

[0099] The illustrated ALU is functionally coupled to a shift register and any associated data feeds necessary for their operation. They are generally combinational digital circuits that perform arithmetic or bitwise operations on binary integers, but may operate on other numbers and / or perform other operations required by the system context. Inputs to the illustrated ALU are loaded from the outputs of the shift register and the data feeds. The ALU then outputs the result of an operation configured to be performed (e.g., mask, XOR, AND, Mod) in opposition to the shift register's output timing, i.e., when the clock signal changes from a first state to a second state. Thus, when the shift register is outputting, the ALU is loading, and when the shift register is shifting, the ALU is outputting. The ALU may be as simple as a mask operation, where the shift register's output determines which of two values ​​to output from two separate data feeds, which can be achieved in a single internal clock cycle. The ALU can be more complex (e.g., Mod) and therefore may require its own internal clock, which operates faster than the illustrated system clock, in order to output values ​​as shown in the diagram.

[0100] The illustrated data feed provides the ALU with the required output values, and therefore provides those values ​​when the relevant ALU is ready to load. The data feed may be a shift register, DMA, memory output / access, etc., or a combination thereof. The illustrated data feed is shown to output a value once per clock cycle, but such rapid value delivery is not always necessary. For example, if the ALU is performing sequential mod arithmetic, the same denominator can be used many times (e.g., 100,000 or more times) before a change is needed. However, if the ALU is performing mask operations, new data feed values ​​from two different data feeds are needed each cycle. Therefore, the output of the illustrated data feed may be available each clock cycle, but is not necessarily loaded every time. The illustrated data feed includes a change operation in which the output value is changed to a new value. If a new value is needed each time (e.g., mask), the change operation is performed on the other side of the output. If it is not needed every cycle, the change operation is performed on demand, which may be controlled by the controller.

[0101] The illustrated DRNUS loads the output of the ALU, thereby loading it in sync with the output timing of the associated ALU. The illustrated DRNUS receives a new value every clock cycle of all connected ALUs. This is useful because, as illustrated, a single system can generate multiple random values ​​per clock cycle, with multiple ALUs utilizing the same shift register. Therefore, random value generation can occur at a speed exceeding the system clock. Furthermore, when the shift register and DMA are utilized, the burden on the illustrated system's CPU resources of the computerized system is minimal to zero, and thus random values ​​can be provided to an application or hardware device (i.e., the DRNUS) without causing a significant slowdown of the computer system. This means that a system that greatly needs random values ​​can receive random values ​​of known quality essentially at "no cost".

[0102] In the operation of the illustrated process, the system clock drives the timing of the operation of the illustrated components. When the illustrated clock signal rises, the shift register shifts, and the ALU outputs the output value to the DRNUS, which receives the output value. When the illustrated clock signal falls, the shift register (and data feed, if necessary) outputs the new value to the ALU, and the ALU loads the required value in preparation for subsequent operation.

[0103] Advantageously, the illustrated system can generate a large number of random values ​​of known quality for use by one or more DRNUS at system clock speed and without placing a significant burden on the CPU. This is quite different from known methods of generating random values ​​within a computerized system, such known systems generate random values ​​of low quality / limited quality / quantity, cannot do so at clock speed, and / or place a significant burden on the associated CPU or require a separate computing system with a separate CPU to operate.

[0104] It is understood that the embodiments described above are merely illustrative examples of the application of the principles of the present invention. The present invention may be embodied in other specific forms without departing from its spirit or essential features. The embodiments described should be considered in all respects as illustrative only and not limiting. Accordingly, the scope of the present invention is indicated not by the above description but by the appended claims. All modifications that fall within the meaning and scope of the equivalents of the claims should be encompassed within their scope.

[0105] The following is a non-limiting illustrative description of an embodiment. 1. A method for rapidly and efficiently generating a series of random numbers from a random number source in a computing system, a. A step of loading a data loop using random data from a random data source, wherein the data loop is: i. Loop-like array of stored values, and ii. Index The steps include loading the data loop, b. A step of reading a multibit value from a data loop in relation to the index position in a loop-like array, c. A step of performing a first data operation on a multibit value to derive a derived random number from the multibit value, d. A step of moving the index to a different position within the loop-like array in relation to the loop-like array, e. Repeat steps b to d to generate a series of derived random numbers, Methods that include...

[0106] 2. The data loop is a shift register, as described in Description 1. 3. The shift register is a universal shift register, as described in Description 2.

[0107] 4. Different positions are adjacent positions, as described in any of descriptions 1 to 15. 5. The data operator is a separable operation selected from the group consisting of XOR, mask generator, data MUX, and MOD, as described in any of descriptions 1 to 15.

[0108] 6. The source of the random data is the output of the method according to Description 1, or a method according to any of Descriptions 1 to 15.

[0109] 7. The step of loading the data loop is performed by direct memory access, as described in any of the methods in Descriptions 1-15.

[0110] 8. The method according to any one of descriptions 1 to 15, further comprising the step of performing a second data operation on a multibit value, simultaneously with the step of performing a first data operation, thereby deriving a second derived random number from the multibit value.

[0111] 9. The method according to any one of Descriptions 1 to 15, wherein the second computing system independently performs the steps described in Description 1 using substantially identical sources of random data so that the data loop of the second computing system is loaded identically to the data loop described in Description 1, and performs substantially identical data operations so that the resulting derived random numbers are the same as those described in Description 1, thereby generating a second set of derived random numbers that are identical to the set of derived random numbers described in Description 1.

[0112] 10. The method according to Description 9, wherein the second computing system is structurally different from the computing system described in Description 1 in at least one of the data loop, read operator, shifter, controller type, and data loop loader type.

[0113] 11. The data operation is a MOD operation performed with a multi-bit value as the numerator and a denominator with fewer bits than the multi-bit value, as described in any of the methods in 1 to 15.

[0114] 12. The method described in Description 11, wherein the denominator is a value obtained directly from or derived from a source of random data.

[0115] 13. The denominator is greater than the desired range of derived random numbers, as described in 11. 14. The method according to any one of descriptions 1 to 15, further comprising the step of automatically selecting a separation operation from a set of separation operations depending on the controller.

[0116] 15. The controller is the method described in Description 14, comprising one or more of a programmable logic circuit, a script, and a driver.

[0117] 16. A computerized system for efficiently generating streams of random numbers, a. A data loop, i. A simple feedback loop-like array of random data, ii. Index, and iii. A data loop including an output port that reads a value from a simple feedback loop array based on the relative position of the index to the simple feedback loop array, b. Data operators, i. Input, and ii. A data operator having an output that provides access to the output value from the data operator, and functionally coupled to the output port such that the value from the output port is supplied to the data operator as an input value, c. An incrementer functionally coupled to the data loop that shifts the index for a simple feedback loop-like array, A system equipped with these features.

[0118] 17. The data loop further includes input ports, as described in any of descriptions 16-23 of the system.

[0119] 18. The value from the output port is a multi-bit value, as described in any of the systems in descriptions 16-23.

[0120] 19. The data loop is a universal shift register, as described in any of the systems in descriptions 16-23.

[0121] 20. The data loop is a shift register, as described in any of descriptions 16-23 of the system.

[0122] 21. The data operation is a separation operator selected from the group consisting of XOR, mask generator, data MUX, and MOD, as described in any of the systems in descriptions 16-23.

[0123] 22. The system according to any one of descriptions 16 to 23, further comprising a second data loop having an input port functionally coupled to the output of a data operator such that the output value from the data operator is input to the second data loop.

[0124] 23. The system according to any one of descriptions 16 to 23, further comprising a source of random data functionally coupled to the input port of a data loop, such that a loop-like array of random data is supplied with data from the source of random data.

[0125] Accordingly, although the present invention has been adequately described above in specific and detail in relation to what is currently considered to be the most practical and preferred embodiment of the invention, it will be apparent to those skilled in the art that many modifications can be made, including but not limited to changes in size, materials, shape, form, function and mode of operation, assembly and use, without departing from the principles and concepts of the invention as set forth in the claims. Furthermore, embodiments may be limited to consisting of or essentially being one or more of the features, functions, structures and methods described herein.

Claims

1. A method for rapidly and efficiently generating a series of random numbers from a source of random numbers in a computing system, a. A step of loading a data loop using random data from a random data source, wherein the data loop is: i. A loop-like array of stored values, and ii. Index, The steps include loading the data loop, b. A step of reading a multi-bit value from the data loop in relation to the position of the index in the loop-like array, c. A step of performing a first data operation on the multi-bit value and thereby deriving a derived random number from the multi-bit value, d. The step of moving the index to a different position within the loop-shaped array in relation to the loop-shaped array, e. A step of repeating steps b to d to generate a series of derived random numbers, Includes, A method further comprising the step of performing a second data operation on the multibit value, simultaneously with the step of performing the first data operation, thereby deriving a second derived random number from the multibit value.

2. The method according to claim 1, wherein the data loop is a shift register.

3. The method according to claim 1, wherein the different positions are adjacent positions.

4. The method according to claim 1, wherein the source of the random data is the output of the method according to claim 1.

5. The method according to claim 1, wherein the step of loading the data loop is performed by direct memory access.

6. The method according to claim 1, wherein a second computing system independently performs the steps described in claim 1 using substantially the same source of random data, thereby loading the data loop of the second computing system in the same way as the data loop described in claim 1, and performing substantially the same data operations such that the resulting derived random numbers are the same as those described in claim 1, thereby generating a second set of derived random numbers that are the same as the set of derived random numbers described in claim 1.

7. The method according to claim 6, wherein the second computing system is structurally different from the computing system according to claim 1 in at least one of the data loop, read operator, shifter, controller type, and data loop loader type.

8. The method according to claim 1, wherein the first data operation is a MOD operation performed with the multi-bit value as the numerator and the number of bits less than the multi-bit value as the denominator.

9. The method according to claim 8, wherein the denominator is a value obtained directly from or derived from the source of the random data.

10. A computerized system for efficiently generating a stream of random numbers as described in Claim 1, a. A data loop, i. A simple feedback loop-like arrangement of random data, ii. Index, and, iii. An output port that reads a value from the simple feedback loop array based on the relative position of the index with respect to the simple feedback loop array, A data loop including, b. A data operator, i. Input, and, ii. A data operator having an output that provides access to the output value from the data operator, and functionally coupled to the output port such that the value from the output port is supplied to the data operator as an input value, c. An incrementer functionally coupled to the data loop that shifts the index relative to the simple feedback loop array, A system equipped with these features.

11. The system according to claim 10, further comprising an input port in the data loop.

12. The system according to claim 10, wherein the value from the output port is a multi-bit value.

13. The system according to claim 10, wherein the data loop is a universal shift register.

14. The system according to claim 10, further comprising a second data loop having an input port functionally coupled to the output of the data operator such that the output value from the data operator is input to the second data loop.

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