Nitride semiconductor device and method for manufacturing a nitride semiconductor device

Abstract

To provide a nitride semiconductor device that can improve mobility of a MOSFET and also reduce fixed electric charges in a gate insulation film, and a method of manufacturing the nitride semiconductor device.SOLUTION: A nitride semiconductor device has an AlxGa(1-x)N layer (0<x≤1) provided on a gallium nitride layer, an intermediate layer provided on the AlxGa(1-x)N layer (0<x≤1), and a gate insulation film provided on the intermediate layer. The intermediate layer is an oxide or oxynitride of at least one of Al and Ga. The gate insulation film is an oxide or oxynitride consisting principally of Si and O.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a nitride semiconductor device and a method for manufacturing a nitride semiconductor device.

Background Art

[0002] Conventionally, a vertical MOSFET using gallium nitride has been known (for example, see Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a vertical MOSFET using gallium nitride, improvement in mobility and reduction of fixed charges in the gate insulating film are desired.

[0005] The present invention has been made in view of such circumstances, and an object thereof is to provide a nitride semiconductor device and a method for manufacturing a nitride semiconductor device capable of improving the mobility of a MOSFET and reducing fixed charges in the gate insulating film.

Means for Solving the Problems

[0006] In order to solve the above problems, a nitride semiconductor device according to an aspect of the present invention includes an AlxGa(1-x)N layer (0 < x ≤ 1) provided on a gallium nitride layer, an intermediate layer provided on the AlxGa(1-x)N layer (0 < x ≤ 1), and a gate insulating film provided on the intermediate layer. The intermediate layer is an oxide or oxynitride of at least one of Al and Ga. The gate insulating film is an oxide or oxynitride containing Si and O as main components.

[0007] A method for manufacturing a nitride semiconductor device according to an aspect of the present invention includes a step of forming an AlxGa(1−x)N layer (0 < x ≦ 1) on a gallium nitride layer, a step of forming an intermediate layer on the AlxGa(1−x)N layer (0 < x ≦ 1), a step of forming a gate insulating film on the intermediate layer, and a step of performing heat treatment after forming the gate insulating film. In the step of forming the intermediate layer, at least one of oxides or oxynitrides of Al and Ga is formed as the intermediate layer. In the step of forming the gate insulating film, an oxide or oxynitride containing Si and O as main components is formed as the gate insulating film.

Effects of the Invention

[0008] According to the present invention, it is possible to provide a nitride semiconductor device and a method for manufacturing a nitride semiconductor device capable of improving the mobility of a MOSFET and reducing fixed charges in a gate insulating film.

Brief Description of the Drawings

[0009] [Figure 1] FIG. 1 is a plan view showing a configuration example of a GaN semiconductor device according to an embodiment of the present invention. [Figure 2] FIG. 2 is a cross-sectional view showing a configuration example of a GaN semiconductor device according to an embodiment of the present invention. [Figure 3] FIG. 3 is an enlarged cross-sectional view showing a p-type well region, an AlxGa(1−x)N layer, an intermediate layer, and a gate insulating film of a vertical MOSFET1 according to an embodiment of the present invention. [Figure 4] FIG. 4 is a process diagram showing Manufacturing Method Example 1 of a GaN semiconductor device according to an embodiment of the present invention. [Figure 5] FIG. 5 is a process diagram showing Manufacturing Method Example 2 of a GaN semiconductor device according to an embodiment of the present invention. [Figure 6] FIG. 6 is a cross-sectional view showing a configuration example of a stacked film of a vertical MOSFET showing Comparative Example 1 of the present invention. [Figure 7] FIG. 7 is a cross-sectional view showing a configuration example of a stacked film of a vertical MOSFET showing Comparative Example 2 of the present invention. [Figure 8] FIG. 8 is a diagram showing the relationship between the formation energy of Ga in a Si-rich SiO2 film and the Fermi level. [Figure 9] FIG. 9 is a diagram showing the relationship between the formation energy of Ga in an O-rich SiO2 film and the Fermi level. [Figure 10] FIG. 10 is a diagram schematically showing the band gap of the stacked film according to an embodiment of the present invention. [Figure 11] FIG. 11 is a diagram schematically showing the band gap of the stacked film according to an embodiment of the present invention. [Figure 12] FIG. 12 is a graph showing the relationship between the film thickness (nm) of the AlxGa(1-x)N layer and the flat band voltage Vfb (V). [Figure 13] FIG. 13 is a cross-sectional view showing the configuration of a vertical MOSFET according to a modified example of an embodiment of the present invention.

MODE FOR CARRYING OUT THE INVENTION

[0010] Embodiments of the present invention will be described below. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thicknesses of each device and each member, etc. are different from the actual ones. Therefore, the specific thickness and dimensions should be determined in consideration of the following description. Also, it is a matter of course that there are portions where the dimensional relationships and ratios are different between the drawings.

[0011] In the following description, the directions may be described using the terms in the X-axis direction, the Y-axis direction, and the Z-axis direction. For example, the X-axis direction and the Y-axis direction are directions parallel to the surface 10a of the GaN substrate 10. The X-axis direction and the Y-axis direction are also referred to as the horizontal direction. The Z-axis direction is the normal direction of the surface 10a of the GaN substrate 10. The X-axis direction, the Y-axis direction, and the Z-axis direction are perpendicular to each other.

[0012] In the following explanation, the direction of the Z-axis arrow may be referred to as "up," and the opposite direction of the Z-axis arrow may be referred to as "down." "Up" and "down" do not necessarily mean the vertical direction relative to the ground. In other words, the directions of "up" and "down" are not limited to the direction of gravity. "Up" and "down" are merely convenient expressions to specify the relative positional relationship in regions, layers, films, substrates, etc., and do not limit the technical concept of the present invention. For example, it goes without saying that if the paper is rotated 180 degrees, "up" becomes "down" and "down" becomes "up."

[0013] In the following explanation, the + and - prefixes attached to p and n, which indicate the conductivity type of a semiconductor region, mean that the semiconductor region has a relatively higher or lower impurity concentration compared to semiconductor regions without + and - prefixes. However, even if two semiconductor regions are labeled with the same p, this does not mean that their impurity concentrations are exactly the same.

[0014] <Embodiment> (Example configuration) Figure 1 is a plan view showing an example configuration of a gallium nitride (GaN) semiconductor device 100 (an example of a "nitride semiconductor device" of the present invention) according to an embodiment of the present invention. Figure 2 is a cross-sectional view showing an example configuration of the GaN semiconductor device 100 according to an embodiment of the present invention. Figure 2 shows a cross-section obtained by cutting the plan view of Figure 1 along line AA'.

[0015] The GaN semiconductor device 100 shown in Figures 1 and 2 is a power device. As shown in Figures 1 and 2, the GaN semiconductor device is provided with a plurality of vertical MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) 1. For example, the plurality of vertical MOSFETs 1 are repeatedly arranged in one direction (for example, in the X-axis direction). One vertical MOSFET 1 is a repeating unit structure, and these unit structures are arranged in a line in one direction (for example, in the X-axis direction).

[0016] As shown in Figure 2, the GaN semiconductor device 100 includes a gallium nitride substrate (hereinafter referred to as GaN substrate) 10. The GaN substrate 10 has an n+ type GaN substrate 11 and an n- type GaN layer 12 provided on the GaN substrate 11.

[0017] The GaN substrate 11 is, for example, a c-plane GaN single crystal substrate. The n-type impurities contained in the GaN substrate 11 are one or more elements from among Si (silicon), O (oxygen), and Ge (germanium). For example, the n-type impurities contained in the GaN substrate 11 are Si or O.

[0018] The GaN layer 12 is a single-crystal GaN layer epitaxially grown on the surface of the GaN substrate 11. The GaN layer 12 is formed by doping with n-type impurities during the epitaxial growth process. The n-type impurities are, for example, silicon.

[0019] On the surface 10a of the GaN substrate 10 (i.e., the surface of the n-type GaN layer 12), there is a p-type well region 21 (an example of the "gallium nitride layer" of the present invention), an n+-type source region 22, and a p+-type contact region 23. Hereinafter, the p-type well region 21 will also be referred to as the p-type GaN layer.

[0020] The well region 21 is formed when acceptor elements such as Mg are ion-implanted on the surface 10a side of the GaN substrate 10 and activated by heat treatment. The well region 21 faces the surface 10a of the GaN substrate 10.

[0021] The source region 22 is formed by ion implantation of a donor element such as Si or O into the surface 10a side of the GaN substrate 10, and activation by heat treatment. The source region 22 faces the surface 10a of the GaN substrate 10. The source region 22 is located inside the well region 21 and is in contact with the well region 21.

[0022] The contact region 23 is formed by ion-implanting an acceptor element such as Mg into the surface 10a side of the GaN substrate 10 and activating it by heat treatment. The contact region 23 faces the surface 10a of the GaN substrate 10. The contact region 23 is located inside the well region 21 and is in contact with the well region 21. Also, source regions 22 are located on both sides of the contact region 23. The contact region 23 is also in contact with the source regions 22.

[0023] FIG. 3 is a cross-sectional view showing an enlarged view of the p-type well region 21, the AlxGa(1 - x)N layer 31, the intermediate layer 32, and the gate insulating film 33 of the vertical MOSFET 1 according to an embodiment of the present invention. As shown in FIGS. 2 and 3, in the vertical MOSFET 1, a stacked film 30 including an AlxGa(1 - x)N layer 31, an intermediate layer 32, and a gate insulating film 33 is provided on the p-type well region (i.e., p-type GaN layer) 21.

[0024] More specifically, an AlxGa(1 - x)N layer 31 is provided on the p-type well region 21. The p-type well region 21 and the AlxGa(1 - x)N layer 31 are in contact with each other. An intermediate layer 32 is provided on the AlxGa(1 - x)N layer 31. The AlxGa(1 - x)N layer 31 and the intermediate layer 32 are in contact with each other. A gate insulating film 33 is provided on the intermediate layer 32. The intermediate layer 32 and the gate insulating film 33 are in contact with each other.

[0025] In the AlxGa(1 - x)N layer 31, the range of x is greater than 0 and less than or equal to 1 (0 < x ≤ 1). The AlxGa(1 - x)N layer 31 may be an Al 0.1 Ga 0.9 N layer or an AlGaN layer. Also, the Al content per unit area in the AlxGa(1 - x)N layer 31 is 5×10 14 cm -2 or more and 5×10 15 cm -2 or less.

[0026] Let the Al concentration in the AlxGa(1 - x)N layer 31 be A cm -3and the thickness of the AlxGa(1-x)N layer 31 is T nm (= cm × 10 -7 ), then A and T satisfy the relationship of the following formula (1), formula (1´) or formula (1´´).

[0027] 5 × 10 14 cm -2 ≤ A cm -3 × T nm ≤ 5 × 10 15 cm -2 …(1) When converting the unit of T in formula (1) from nm to cm, it becomes formula (1´). 5 × 10 14 cm -2 ≤ A cm -3 × T cm × 10 -7 ≤ 5 × 10 15 cm -2 …(1´) When removing the units from formula (1´) and organizing the powers of 10, it becomes formula (1´´). 5 × 10 21 ≤ A × T ≤ 5 × 10 22 …(1´´)

[0028] The intermediate layer 32 is an oxide or oxynitride of at least one of aluminum (Al) and gallium (Ga). For example, the intermediate layer 32 is a GaOx layer, a GaON layer, an AlGaO layer, an Al2O3 layer or an AlON layer. The thickness of the intermediate layer 32 is, for example, 0.2 nm or more and 2 nm or less, preferably 0.5 nm or more and 2 nm or less.

[0029] The gate insulating film 33 is an oxide or oxynitride mainly composed of silicon (Si) and oxygen (O). For example, the gate insulating film 33 is a SiO2 film, a SiON film or an AlSiO film.

[0030] In the vertical MOSFET 1, mainly, a channel is formed at the contact interface between the AlxGa(1-x)N layer (0 < x ≤ 1) 31 and the well region 21 and in the vicinity thereof.

[0031] As shown in Figure 2, a gate electrode 41 is provided on the gate insulating film 33. Source electrodes 42 are provided on the source region 22 and the contact region 23. A drain electrode 43 is provided on the back surface 10b side of the GaN substrate 10. (Manufacturing method)

[0032] Next, as a method for manufacturing the GaN semiconductor device 100 according to an embodiment of the present invention, a method for forming a laminated film including an AlxGa(1-x)N layer 31, an intermediate layer 32, and a gate insulating film 33 on the p-type well region 21 shown in Figure 3 will be described. The GaN semiconductor device 100 is manufactured using various equipment such as film deposition equipment (e.g., plasma CVD (Chemical Vapor Deposition) equipment, thermal CVD equipment, thermal oxidation equipment), heat treatment equipment, ion implantation equipment, exposure equipment, etching equipment, and CMP (Chemical Mechanical Polishing) equipment. Hereinafter, these equipment will be collectively referred to as manufacturing equipment.

[0033] (1) Manufacturing method example 1 Figure 4 is a process diagram showing Example 1 of a manufacturing method for a GaN semiconductor device 100 according to an embodiment of the present invention. In step ST1 of Figure 4, the manufacturing apparatus ion-implants magnesium (Mg) into the surface 10a side of the GaN substrate 10, activates the Mg by heat treatment, and forms p-type well regions 21.

[0034] Next, as shown in step ST2 of Figure 4, the manufacturing apparatus forms an AlxGa(1-x)N layer 31 on the surface 10a of the GaN substrate 10 including the well region 21. The AlxGa(1-x)N layer 31 is formed, for example, by the MOCVD (Metal Organic Chemical Vapor Deposition) method. In the AlxGa(1-x)N layer 31 formation process, the Al content per unit area is 5 × 10 atoms. 14 cm -2 The above 5 x 10 15 cm -2It is preferable to set the Al concentration in the AlxGa(1-x)N layer 31 and the thickness of the AlxGa(1-x)N layer 31 in advance, as follows. The Al concentration in the AlxGa(1-x)N layer 31 can be adjusted by the Al composition ratio x.

[0035] The AlxGa(1-x)N layer 31 may also be formed by epitaxially growing a p-type GaN layer that forms the well region 21, and then continuously epitaxially growing the AlxGa(1-x)N layer on the p-type GaN layer.

[0036] Next, as shown in step ST3 of Figure 4, the manufacturing apparatus forms an intermediate layer 32 on the AlxGa(1-x)N layer 31. The intermediate layer 32 is, for example, GaOx, and is formed by plasma oxidation or thermal oxidation of the surface of the underlying AlxGa(1-x)N layer 31. Alternatively, the intermediate layer 32 may be deposited on the AlxGa(1-x)N layer 31 by CVD. The thickness of the deposited intermediate layer 32 is, for example, 0.2 nm or more and 2 nm or less, preferably 0.5 nm or more and 2 nm or less.

[0037] Next, as shown in step ST4 of Figure 4, the manufacturing apparatus forms a gate insulating film 33 on the intermediate layer 32. The gate insulating film 33 is, for example, SiO2 and is deposited by plasma CVD or sputtering.

[0038] Subsequently, the manufacturing apparatus heat-treats the entire substrate on which the gate insulating film 33 is formed in order to improve the film quality of the gate insulating film 33. The maximum temperature for this heat treatment is, for example, 600°C to 1000°C, and one example is 800°C. This heat treatment may be carried out in an inert gas atmosphere (for example, an argon atmosphere or a nitrogen atmosphere) or in an oxidizing atmosphere (for example, an oxygen atmosphere). After the above steps, a laminated film 30 including an AlxGa(1-x)N layer 31, an intermediate layer 32, and a gate insulating film 33 is completed on the p-type well region 21.

[0039] (2) Manufacturing method example 2 In the above manufacturing method example 1, it was explained that an AlxGa(1-x)N layer 31, an intermediate layer 32, and a gate insulating film 33 are formed in this order on a p-type well region 21. However, the formation order of the AlxGa(1-x)N layer 31, intermediate layer 32, and gate insulating film 33 is not limited to this. In embodiments of the present invention, the intermediate layer 32 may be formed by heat treatment under an oxidizing atmosphere after the gate insulating film 33 has been formed on the AlxGa(1-x)N layer 31.

[0040] Figure 5 is a process diagram showing Example 2 of a manufacturing method for a GaN semiconductor device 100 according to an embodiment of the present invention. Steps ST11 and ST12 in Figure 5 are the same as steps ST1 and ST2 in Figure 4, so their explanation is omitted.

[0041] After the AlxGa(1-x)N layer 31 is formed as shown in step ST12 of Figure 5, the manufacturing apparatus forms a gate insulating film 33 on the AlxGa(1-x)N layer 31 as shown in ST13 of Figure 5. The gate insulating film 33 is, for example, SiO2 and is deposited by plasma CVD or sputtering.

[0042] Next, the manufacturing apparatus heat-treats the entire substrate on which the gate insulating film 33 is formed in an oxidizing atmosphere (for example, an oxygen atmosphere). This heat treatment causes thermal oxidation of the AlxGa(1-x)N layer 31 at and near the contact interface between the gate insulating film 33 and the AlxGa(1-x)N layer 31. As a result, as shown in step ST14 of Figure 5, an intermediate layer 32 such as GaOx is formed between the gate insulating film 33 and the AlxGa(1-x)N layer 31. After these steps, a laminated film 30 including the AlxGa(1-x)N layer 31, the intermediate layer 32, and the gate insulating film 33 is completed on the p-type well region 21.

[0043] (Comparative example) (1) Comparative Example 1 Figure 6 is a cross-sectional view showing an example of the configuration of a multilayer film 130 of a vertical MOSFET representing Comparative Example 1 of the present invention. The vertical MOSFET according to Comparative Example 1 is an n-type MOSFET in which a channel is formed in a p-type GaN layer 21. As shown in Figure 6, the multilayer film 130 of the vertical MOSFET according to Comparative Example 1 has an AlGaN layer 131 provided on the p-type GaN layer 21 and an SiO2 film 133 provided on the AlGaN layer 131. A gate electrode (not shown) is provided on the multilayer film 130.

[0044] In Comparative Example 1 shown in Figure 6, an electric traveling layer is provided at the interface between the p-type GaN layer 21 and the AlGaN layer 131, thereby improving the mobility of the vertical MOSFET. On the other hand, in Comparative Example 1, Ga diffuses from the p-type GaN layer 21 into the SiO2 film 133 due to the heat treatment after the formation of the SiO2 film 133. Since Ga becomes a positive fixed charge in the SiO2 film 133, the threshold voltage of the vertical MOSFET may decrease.

[0045] (2) Comparative Example 2 Figure 7 is a cross-sectional view showing an example of the configuration of a multilayer film 140 of a vertical MOSFET representing Comparative Example 2 of the present invention. The vertical MOSFET according to Comparative Example 2 is an n-type MOSFET in which a channel is formed in a p-type GaN layer 21. As shown in Figure 7, the multilayer film 140 of the vertical MOSFET according to Comparative Example 2 has a GaOx layer 132 provided on the p-type GaN layer 21 and an SiO2 film 133 provided on the GaOx layer 132. Unlike the multilayer film 130 of Comparative Example 1, the multilayer film 140 of Comparative Example 2 does not have an AlGaN layer 131 (see Figure 6). The SiO2 film 133 is in contact with the GaOx layer 132, not the AlGaN layer 131 (see Figure 6).

[0046] In the structure of Comparative Example 2, the GaOx layer acts as an electron trap, resulting in low mobility at the interface between the p-type GaN layer 21 and the GaOx layer 132. In the structure of Comparative Example 2, from the viewpoint of improving mobility, it is preferable that the film thickness of the GaOx layer 132 be as thin as possible.

[0047] (Examples) The inventors found that in the structure of Comparative Example 2, controlling the thickness of the GaOx layer 132 (i.e., intentionally forming the GaOx layer 132) suppresses the increase in positive fixed charge even when heat treatment is performed after the formation of the SiO2 film 133. From this discovery, the inventors invented a structure (i.e., the structure shown in Figure 3) that suppresses the increase in positive fixed charge in the SiO2 film while ensuring mobility by forming the electron transport layer at a different interface.

[0048] As described above, in Figure 3, the AlxGa(1-x)N layer 31 is, for example, an AlGaN layer, the intermediate layer 32 is, for example, a GaOx layer, and the gate insulating film 33 is, for example, an SiO2 film. This is one embodiment of the present invention.

[0049] In this embodiment, the presence of an intermediate layer 32 between the gate insulating film 33 and the AlxGa(1-x)N layer 31 during the heat treatment after the formation of the gate insulating film 33 makes it possible to suppress the increase of positive fixed charge in the gate insulating film 33. This makes it possible to suppress the decrease in the threshold voltage of the n-type vertical MOSFET.

[0050] Furthermore, the interface between the p-type well region 21 (i.e., the p-type GaN layer 21) and the AlxGa(1-x)N layer 31 becomes the electron transport layer. This prevents a decrease in mobility caused by the intermediate layer 32, making it possible to improve the mobility of the vertical MOSFET.

[0051] (1) Mechanism of reduction of positive fixed charge Figure 8 shows the relationship between the formation energy of gallium (Ga) in a silicon (Si)-rich SiO2 film and the Fermi level. Figure 9 shows the relationship between the formation energy of gallium (Ga) in an oxygen (O)-rich SiO2 film and the Fermi level. In Figures 8 and 9, the vertical axis represents the formation energy of Ga in the SiO2 film, and the horizontal axis represents the Fermi level of the SiO2 film. Also, in Figures 8 and 9, GaSi refers to Ga located at the Si sites of SiO2, and Gai refers to Ga located between the lattice of SiO2.

[0052] When a heat treatment is performed after the formation of an SiO2 film, if there is no GaOx layer in the substrate (or if the underlying GaOx layer is present but extremely thin), almost no oxygen is supplied from the substrate to the SiO2 film, resulting in a Si-rich state as shown in Figure 8. Conversely, if a thick layer of GaOx is present in the substrate during heat treatment, a large amount of oxygen is supplied from the underlying GaOx layer to the SiO2 film, resulting in an O-rich state as shown in Figure 9.

[0053] When a heat treatment is performed after the formation of an SiO2 film, Ga diffuses from the p-GaN layer into the SiO2 film. However, as shown in Figure 8, in a Si-rich SiO2 film, Gai has a lower formation energy than GaSi, so the Ga that diffuses into the SiO2 film is mainly Gai. Similarly, as shown in Figure 9, in an O-rich SiO2 film, GaO has a lower formation energy than Gai, so the Ga that diffuses into the SiO2 film is mainly Gai.

[0054] Here, if a p-type GaN layer exists below the SiO2 film, the Fermi level of the SiO2 film is located on the lower energy side of the band gap midpoint (i.e., closer to 0 than the midpoint on the horizontal axis in Figures 8 and 9). Also, in Figures 8 and 9, if the Ga in the SiO2 film is positively charged, the formation energy of Ga increases as the Fermi level increases (i.e., it slopes upwards). If the Ga in the SiO2 film is negatively charged, the formation energy of the SiO2 film decreases as the Fermi level increases (i.e., it slopes downwards). If the Ga in the SiO2 film is neutral, the formation energy of Ga remains constant and is not affected by the Fermi level.

[0055] In the embodiments of the present invention, heat treatment is performed with a GaOx layer present beneath the SiO2 film, corresponding to the case shown in Figure 9. As shown in Figure 9, in an O-rich SiO2 film, heat treatment after film formation tends to convert GaSi, which is neutral, into Gai, which is positively fixed charge. This is thought to be the reason why the increase in positively fixed charge in the SiO2 film is suppressed. By suppressing the increase in positively fixed charge, the threshold voltage of the n-type vertical MOSFET can be kept high.

[0056] (2) Improvement of mobility Figures 10 and 11 schematically show the band gap of a laminated film 30 according to an embodiment of the present invention. The difference between Figure 10 and Figure 11 is the thickness of the GaOx layer constituting the laminated film 30. Figure 11 shows the case where the thickness of the GaOx layer is thicker than that of Figure 10.

[0057] As shown by the solid arrow in Figure 10, in the embodiment of the present invention, an electron transport layer is formed at the interface between the p-type GaN layer and the AlGaN layer. This electron transport layer ensures high mobility.

[0058] As shown in Figure 11, if the thickness of the GaOx layer becomes too thick, the energy level at the interface between the GaOx layer and the SiO2 film decreases. As a result, an electron transport layer is formed at the interface between the GaOx layer and the SiO2 film, as indicated by the dashed arrow in Figure 11. However, the GaOx layer acts as an electron trap, causing a decrease in effective mobility, so the formation of an electron transport layer at the interface between the GaOx layer and the SiO2 film is not very desirable.

[0059] If the GaOx layer is too thin, the positive fixed charge in the SiO2 film increases, and if it is too thick, the MOSFET mobility decreases. From the viewpoint of suppressing the increase in positive fixed charge in the SiO2 film and suppressing the decrease in MOSFET mobility, the thickness of the GaOx layer is, for example, 0.2 nm to 2 nm, preferably 0.5 nm to 2 nm.

[0060] (3) Preferred conditions for the AlGaN layer When an AlGaN layer is formed on a p-GaN layer, polarization occurs at the interface between the p-GaN and AlGaN layers, generating an electric charge. This charge is also called polarization charge. Since polarization charge is a factor that causes fluctuations in the characteristics of an n-type vertical MOSFET (e.g., threshold voltage), it is preferable to keep it within a certain range. The magnitude of the polarization charge is indicated, for example, by the flat-band voltage Vfb(V).

[0061] Figure 12 is a graph showing the relationship between the film thickness (nm) of the AlxGa(1-x)N layer and the flat-band voltage Vfb (V). The horizontal axis of Figure 12 represents the film thickness (nm) of the AlxGa(1-x)N layer, and the vertical axis represents the flat-band voltage Vfb (V). The "%" in the graph indicates the Al composition. Specifically, "100%" indicates X=1 in the AlxGa(1-x)N layer, "20%" indicates X=0.2 in the AlxGa(1-x)N layer, "10%" indicates X=0.1 in the AlxGa(1-x)N layer, and "10%" indicates X=0 in the AlxGa(1-x)N layer. The dashed line (Vfb=0) in the graph indicates Vfb when X=0, i.e., when the AlxGa(1-x)N layer is a GaN layer. The shaded area in the graph indicates a preferred range of Vfb in the embodiments and examples of the present invention.

[0062] In the embodiments and examples of the present invention, it is preferable to set the flat band voltage Vfb to 0(V) or the same level as 0(V), as shown in the shaded area of ​​Figure 12. As shown in Figure 12, the higher the Al composition ratio in the AlxGa(1-x)N layer and the thicker its film thickness, the more easily the flat band voltage Vfb tends to fluctuate to the negative side.

[0063] According to the inventor's calculations, the Al content per unit area in the AlxGa(1-x)N layer 31 is 5 × 10¹¹ atoms. 14 cm -2 The above 5 x 10 15 cm -2If the following conditions are met, the flat-band voltage Vfb can be confined within the masked region. For example, in the case of an AlxGa(1 - x)N layer where x = 1, i.e., AlN, by setting the film thickness to be 0.1 nm or more and 1 nm or less, the Al content per unit area can be confined within the approximate above range. Also, in the case of an AlxGa(1 - x)N layer where x = 0.2, i.e., Al 0.2 Ga 0.8 N, by setting the film thickness to be 0.5 nm or more and 5 nm or less, the Al content per unit area can be confined within the approximate above range. Also, in the case of an AlxGa(1 - x)N layer where x = 0.1, i.e., Al 0.1 Ga 0.9 N, by setting the film thickness to be 1 nm or more and 10 nm or less, the Al content per unit area can be confined within the approximate above range.

[0064] (Effect of the Embodiment) As described above, the GaN semiconductor device 100 according to the embodiment of the present invention includes an AlxGa(1 - x)N layer 31 provided on a p - type well region (p - type GaN layer) 21, an intermediate layer 32 provided on the AlxGa(1 - x)N layer (0 < x ≤ 1) 31, and a gate insulating film 33 provided on the intermediate layer 32. The intermediate layer 32 is an oxide or oxynitride of at least one of Al and Ga. The gate insulating film 33 is an oxide or oxynitride mainly composed of Si and O.

[0065] According to this, an electron traveling layer is formed at the interface between the p - type well region (p - type GaN layer) 21 and the AlxGa(1 - x)N layer 31. By this electron traveling layer, the mobility of the n - type vertical MOSFET 1 can be improved.

[0066] Furthermore, in the manufacturing process of the GaN semiconductor device 100, a heat treatment can be performed on the gate insulating film 33 for the purpose of improving its film quality, etc., while an intermediate layer 32, for example, composed of a GaOx layer, is present beneath the gate insulating film 33, which is composed of an SiO2 film, etc. During this heat treatment, oxygen (O) is supplied from the intermediate layer 32 into the gate insulating film 33, and the gate insulating film 33 changes from a Si-rich condition to an O-rich condition. As a result, even if Ga diffuses into the gate insulating film 33 from the p-type well region (p-type GaN layer) 21 side, the Ga is more likely to become neutral GaSi rather than Gai, which becomes a positive fixed charge, thus suppressing the increase of positive fixed charge in the gate insulating film 33. This makes it possible to maintain a high threshold voltage for the n-type vertical MOSFET 1.

[0067] (modified version) The above embodiments described the application of this technology to a vertical MOSFET with a planar structure. However, the MOSFETs to which this technology is applied are not limited to vertical MOSFETs with a planar structure. In embodiments of the present invention, this technology may also be applied to vertical MOSFETs with a trench gate structure.

[0068] Figure 13 is a cross-sectional view showing the configuration of a vertical MOSFET 1A according to a modified embodiment of the present invention. As shown in Figure 13, in the vertical MOSFET 1A, a trench h opening into the surface 10a is provided on the surface 10a side of the GaN substrate 10. The trench h is formed deeper than the p-type well region (p-type GaN layer) 21. The bottom of the trench h reaches the n-type GaN layer 12. A laminated film 30 and a gate electrode 27 are arranged inside the trench h. The laminated film 30 covers the inner side and bottom surfaces of the trench h.

[0069] The configuration of the laminated film 30 is the same as in the above embodiment, and includes an AlxGa(1-x)N layer 31 provided on a p-type well region 21, an intermediate layer 32 provided on the AlxGa(1-x)N layer 31, and a gate insulating film 33 provided on the intermediate layer 32.

[0070] In the vertical MOSFET 1A, the channel region is the p-type well region 21 located between the GaN layer 12 and the source region 22, and facing the gate electrode 41 via the multilayer film 30. In other words, the side surface of the trench h becomes the channel region.

[0071] Furthermore, a p+ type region 24 is provided below the p- type well region 21. The p+ type region 24 can alleviate charge concentration at the bottom of the trench h, thereby increasing the breakdown voltage of the vertical MOSFET 1A.

[0072] In the modified example shown in Figure 13, similar to the embodiment described above, it is possible to improve the mobility of the n-type vertical MOSFET 1A and reduce the fixed charge in the gate insulating film 33.

[0073] <Other Embodiments> As described above, the present invention has been described by embodiments and modifications, but the descriptions and drawings that constitute part of this disclosure should not be understood as limiting the present invention. Various alternative embodiments and modifications will be apparent to those skilled in the art from this disclosure. For example, the technology may be applied to a horizontal MOSFET instead of a vertical MOSFET. Of course, the present invention includes various embodiments and the like that are not described herein. At least one of various omissions, substitutions, and modifications of components can be made without departing from the spirit of the embodiments and modifications described above. Furthermore, the effects described herein are merely illustrative and not limiting, and other effects may also occur. The technical scope of the present invention is defined solely by the inventive features relating to the claims that are reasonable from the above description. [Explanation of Symbols]

[0074] 1. 1A Vertical MOSFET 10, 11 GaN substrate 10a surface 10b back side 12 GaN layers 21 p-type well region (p-type GaN layer) 22 Source Area 23 Contact Area 24 p+ type region 27 Shuttle gate 30 Multilayer film 31 AlxGa(1-x)N layer 32 Middle Class 33 Gate insulating film 41 Guard gate 42 Source electrodes 43 Drain electrode 100 GaN semiconductor device 130 Multilayer film 131 AlGaN layer 132 GaOx layer 133 SiO2 film 140 Multilayer film h trench

Claims

1. An AlxGa(1-x)N layer (0 < x ≤ 1) provided on a gallium nitride layer, An intermediate layer provided on the AlxGa(1-x)N layer (0 < x ≤ 1), The intermediate layer comprises a gate insulating film provided on the intermediate layer, The aforementioned intermediate layer is an oxide or oxynitride of at least one of Al and Ga. The gate insulating film is an oxide or oxynitride mainly composed of Si and O. The Al content per unit area in the AlxGa(1-x)N layer (0 < x ≤ 1) is 5 × 10¹¹ atoms. １４ cm －２ The above 5 x 10 １５ cm －２ The following is a nitride semiconductor device.

2. An AlxGa(1-x)N layer (0 < x ≤ 1) provided on a gallium nitride layer, An intermediate layer provided on the AlxGa(1-x)N layer (0 < x ≤ 1), The intermediate layer comprises a gate insulating film provided on the intermediate layer, The aforementioned intermediate layer is an oxide or oxynitride of at least one of Al and Ga. The gate insulating film is an oxide or oxynitride mainly composed of Si and O. The Al concentration in the AlxGa(1-x)N layer (0 < x ≤ 1) is A cm －３ year, If the thickness of the AlxGa(1-x)N layer (0 < x ≤ 1) is T nm, 5 x 10 ２１ ≤ A × T ≤ 5 × 10 ２２ A nitride semiconductor device that satisfies the following conditions.

3. The intermediate layer is a GaOx layer, a GaON layer, an AlGaO layer, an Al ２ O ３ layer or an AlON layer. The nitride semiconductor device according to claim 1 or 2.

4. The nitride semiconductor device according to any one of claims 1 to 3, wherein the thickness of the intermediate layer is 0.5 nm or more and 2 nm or less.

5. The gate insulating film is SiO ２ A nitride semiconductor device according to any one of claims 1 to 4, wherein the film is a film, a SiO film, or an AlSiO film.

6. The nitride semiconductor device according to any one of claims 1 to 5, wherein the conductivity type of the gallium nitride layer is p-type.

7. A step of forming an AlxGa(1-x)N layer (0 < x ≤ 1) on a gallium nitride layer, The process of forming an intermediate layer on the AlxGa(1-x)N layer (0 < x ≤ 1), The step of forming a gate insulating film on the intermediate layer, The process includes a step of performing a heat treatment after forming the gate insulating film, In the step of forming the intermediate layer, at least one oxide or oxynitride of Al and Ga is formed as the intermediate layer. In the step of forming the gate insulating film, an oxide or oxynitride mainly composed of Si and O is formed as the gate insulating film. In the process of forming the intermediate layer, A method for manufacturing a nitride semiconductor device, comprising forming the intermediate layer by plasma oxidation or thermal oxidation of the AlxGa(1-x)N layer (0 < x ≤ 1) or by a CVD method.

8. The step of forming the intermediate layer is, A method for manufacturing a nitride semiconductor device according to claim 7, wherein after forming the gate insulating film on the AlxGa(1-x)N layer (0 < x ≤ 1), heat treatment is performed in an oxidizing atmosphere to oxidize the interface in the AlxGa(1-x)N layer (0 < x ≤ 1) that is in contact with the gate insulating film, thereby forming the intermediate layer.

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