Silicon carbide semiconductor device and method for manufacturing a silicon carbide semiconductor device

Abstract

To provide a silicon carbide semiconductor device arranged so that the decrease in voltage resistance of a silicon carbide semiconductor device can be suppressed on the whole when the charge balance is shifted toward an n-rich side, and a manufacturing method thereof.SOLUTION: A silicon carbide semiconductor device comprises: a first parallel pn layer 51 arranged by repeatedly disposing a first first-conductivity-type region 52 and a first second-conductivity-type region 53 to alternate in an active region; a second parallel pn layer 54 arranged by repeatedly disposing a second first-conductivity-type region 55 and a second second-conductivity-type region 56 to alternate in a termination region; a second-conductivity-type first semiconductor region 32 forming a voltage resistance structure in the termination region; and a second-conductivity-type second semiconductor region 13 provided in the active region. The lower the impurity density of the second-conductivity-type regions 13 and 32 provided on the first parallel pn layer 51 and the second parallel pn layer 54, the lower the impurity density of the first first-conductivity-type region 52 and the second first-conductivity-type region 55.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] This invention relates to a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device. [Background technology]

[0002] Conventionally, semiconductor devices with a superjunction (SJ) structure are known, in which the drift layer is a parallel pn layer in which n-type and p-type regions are alternately and repeatedly arranged adjacent to each other in a direction parallel to the main surface of the substrate. The n-type and p-type regions constituting the parallel pn layer extend in a stripe-like manner parallel to the main surface of the semiconductor substrate (semiconductor chip). The n-type and p-type regions constituting the parallel pn layer are provided almost uniformly over almost the entire semiconductor substrate, from the active region in the center of the semiconductor substrate (center of the chip) to the edge of the semiconductor substrate (edge ​​of the chip).

[0003] The structure of a conventional silicon carbide semiconductor device with an SJ structure will be explained using a MOSFET (Metal Oxide Semiconductor Field Effect Transistor: a MOS-type field-effect transistor with an insulated gate consisting of a three-layer structure of metal-oxide-semiconductor) as an example. Figure 12 is a plan view showing the layout of a conventional silicon carbide semiconductor device as seen from the front side of the semiconductor substrate. Figures 13 and 14 are cross-sectional views showing the cross-sectional structure at the cutting lines AA-AA' and BB-BB' in Figure 12, respectively.

[0004] The conventional silicon carbide semiconductor device 150 shown in Figures 12 to 14 is a vertical MOSFET with an SJ structure, where the active region 110 of a silicon carbide semiconductor substrate (semiconductor chip) 140 has a general trench gate structure, and the drift layer 102 is a parallel pn layer 151. The semiconductor substrate 140 has a rectangular planar shape. The active region 110 has a substantially rectangular planar shape and is located in the center of the semiconductor substrate 140 (center of the chip). The periphery of the active region 110 is surrounded by an edge termination region 130 via an intermediate region 120.

[0005] In the intermediate region 120, gate wiring layers (not shown), such as gate runners, are arranged. The edge termination region 130 is the region between the intermediate region 120 and the edge (chip edge) of the semiconductor substrate 140. In the edge termination region 130, a junction termination extension (JTE) structure 132 and n are provided as a voltage-bearing structure. + A channel stopper region 134 and a JTE structure 132 are located. The JTE structure 132 surrounds the active region 110 via an intermediate region 120.

[0006] n + The channel stopper region 134 is located outside (towards the chip edge) of the JTE structure 132, away from the JTE structure 132, and reaches the edge of the semiconductor substrate 140. + The channel stopper region 134 extends along the edge of the semiconductor substrate 140 and surrounds the JTE structure 132. Figure 12 shows n + The inner circumference of the channel stopper region 134 is shown by the dashed line 134a. + The channel stopper region 134 is provided in the entire area outside of the dashed line 134a, n + The outer periphery of the channel stopper region 134 is the edge of the semiconductor substrate 140.

[0007] The parallel pn layer 151 is uniformly provided across almost the entire semiconductor substrate 140, from the active region 110 to the edge termination region 130. The parallel pn layer 151 has an SJ structure in which n-type regions 152 and p-type regions 153 are alternately and repeatedly arranged adjacently in a first direction X parallel to the front surface of the semiconductor substrate 140. The n-type region 152 and p-type region 153 of the parallel pn layer 151 extend in a stripe-like manner in a second direction Y parallel to the front surface of the semiconductor substrate 140 and perpendicular to the first direction X. In Figure 12, the p-type region 153 is shown with hatching.

[0008] The n-type region 152 and p-type region 153 of the parallel pn layer 151 are JTE structure 132 and n + Directly below the type channel stopper region 134 (n +On the side of the trench drain region 101 (see FIGS. 13 and 14), it is disposed over substantially the entire edge termination region 130. The parallel pn layer 151 is formed by the JTE structure 132 and n + type channel stopper region 134 over the entire circumference in the depth direction Z, the JTE structure 132 and n + type channel stopper region 134 adjacent thereto, and reaches the front surface of the semiconductor substrate 140 between the JTE structure 132 and the n + type channel stopper region 134.

[0009] The cross-sectional structure of a conventional silicon carbide semiconductor device 150 will be described. The semiconductor substrate 140 is formed by sequentially laminating an epitaxial layer 142 and an epitaxial layer 143 serving as a drift layer 102 and a p-type base region 104 on an n + type starting substrate 141 made of silicon carbide. The main surface on the p-type epitaxial layer 143 side of the semiconductor substrate 140 is defined as the front surface, and the main surface on the n + type drain region 101, which is the n + type starting substrate 141 side, is defined as the back surface. The epitaxial layer 142 is a portion that becomes the drift layer (drift region) 102 and includes the parallel pn layer 151.

[0010] The portion of the p-type epitaxial layer 143 in the edge termination region 130 is removed by etching, and a step 131 is formed on the front surface of the semiconductor substrate 140. The front surface of the semiconductor substrate 140 is recessed on the n + type drain region 101 side in the portion on the edge termination region 130 side (hereinafter referred to as the second surface) 140b rather than the portion on the active region 110 side (hereinafter referred to as the first surface) 140a with the step 131 as a boundary. Reference numeral 140c is a portion (hereinafter referred to as the third surface) that connects the first surface 140a and the second surface 140b of the front surface of the semiconductor substrate 140.

[0011] In the edge termination region 130, an n - type epitaxial layer 142 is exposed on the second surface 140b of the front surface of the semiconductor substrate 140. Inside the surface region of the second surface 140b of the front surface of the semiconductor substrate 140, inside the n - type epitaxial layer 142, a plurality of p-type regions constituting the JTE structure 132 and n+ A p-type channel stopper region 134 and a p-type region are selectively provided. Figures 12 and 13 show multiple p-type regions arranged concentrically adjacent to each other surrounding the active region 110 to constitute the JTE structure 132 as a single p-type region. - This is shown in type region 133.

[0012] JTE structure 132 p - The type region 133 extends from the active region 110 to the area outside the step 131. + The potential of the source electrode (not shown) is fixed via the outer peripheral region 113 of the mold. + The portion of the outer peripheral region 113 outside the step 131 and the p of the JTE structure 132 - Type region 133 and n + The channel stopper region 134 is exposed on the second surface 140b of the front surface of the semiconductor substrate 140. Exposure to the second surface 140b of the front surface of the semiconductor substrate 140 means that it is in contact with the field insulating film 135 on the second surface 140b.

[0013] The n-type region 152 and p-type region 153 of the parallel pn layer 151 are arranged at equal intervals across substantially the entire semiconductor substrate 140, from the active region 110 to the edge termination region 130. The n-type region 152 and p-type region 153 of the parallel pn layer 151 are arranged in the intermediate region 120. + It is positioned directly below the outer periphery region 113, and in the edge termination region 130, p - Type region 133 and n + It is positioned directly below the type channel stopper region 134, and in the depth direction Z, p + Mold outer area 113, p - Type region 133 and n + It is in contact with the channel stopper region 134.

[0014] The n-type region 152 and p-type region 153 of the parallel pn layer 151 are the p of the JTE structure 132 - Type domain 133 and n +It is exposed on the second surface 140b of the front surface of the semiconductor substrate 140, between the channel stopper region 134. The carrier concentration (impurity concentration) and width (width in the first direction X) Wn,Wp of the n-type region 152 and p-type region 153 of the parallel pn layer 151 are set so that the charge balance is achieved between the adjacent n-type region 152 and p-type region 153 of the parallel pn layer 151.

[0015] Charge balance means that the charge amount, expressed as the product of the carrier concentration and width Wn in the n-type region 152, and the charge amount, expressed as the product of the carrier concentration and width Wp in the p-type region 153, are approximately the same within a range that includes tolerances due to process variations. Reference numeral 102a indicates parallel pn layer 151 and n + This is a normal n-type drift region that does not have an SJ structure between it and the type drain region 101. Reference numerals 114, 116, and 136 indicate the interlayer insulating film, drain electrode, and passivation film, respectively.

[0016] As a conventional silicon carbide semiconductor device with an SJ structure, a silicon carbide semiconductor device is known in which the width of the n-type column region and the p-type column region in the active region are made wider than the width of the n-type column region and the p-type column region in the edge-terminal region, and the impurity concentration of the second parallel pn structure in the edge-terminal region is made lower than the impurity concentration of the first parallel pn region in the active region, thereby making the breakdown voltage of the edge-terminal region higher than that of the active region (see, for example, Patent Document 1 below).

[0017] Furthermore, as a conventional silicon carbide semiconductor device with an SJ structure, there is a known silicon carbide semiconductor device in which the widths of the p-type column region and the n-type column region constituting the parallel pn region in the active region are wider than those of the terminal region (see, for example, Patent Documents 2 and 3 below). [Prior art documents] [Patent Documents]

[0018] [Patent Document 1] Japanese Patent Publication No. 2020-174170 [Patent Document 2] Japanese Patent Publication No. 2019-102761 [Patent Document 3] Japanese Patent Publication No. 2019-021788 [Overview of the project] [Problems that the invention aims to solve]

[0019] In the conventional parallel pn layer 151, the n-type region 152 of the drift layer 102 has the same high impurity concentration throughout the entire chip (active region 110, intermediate region 120, and edge termination region 130). Therefore, when the charge balance (CB) shifts to a state where the charge amount, expressed as the product of the carrier concentration and width Wn of the n-type region 152, becomes greater than the charge amount, expressed as the product of the carrier concentration and width Wp of the p-type region 153 (hereinafter referred to as n-rich), the parallel pn layer 151 (SJ region) becomes depleted, and then charge remains due to excess carriers.

[0020] The impurity concentration of the JTE structure 132 in the edge termination region 130 is designed to be lower towards the outside. Under n-rich conditions, the amount of residual charge after the SJ region is depleted is high, and depletion of the JTE structure 132 progresses faster than expected towards the outside. As a result, there is a problem in that the JTE structure 132 is depleted before the desired breakdown voltage is achieved, leading to a decrease in breakdown voltage.

[0021] The purpose of this invention is to provide a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device that can suppress the overall breakdown voltage reduction of the silicon carbide semiconductor device when the charge balance shifts to the n-rich side, in order to solve the problems of the prior art described above. [Means for solving the problem]

[0022] To solve the above-mentioned problems and achieve the objectives of the present invention, the silicon carbide semiconductor device according to this invention has the following features: In the active region, a first parallel pn layer is provided inside a semiconductor substrate made of silicon carbide, in which a first first conductivity type region and a first second conductivity type region are alternately and repeatedly arranged in a first direction parallel to the first main surface of the semiconductor substrate. In the terminal region surrounding the active region, a second parallel pn layer is provided inside the semiconductor substrate, in which a second first conductivity type region and a second second conductivity type region are alternately and repeatedly arranged in the first direction. In the active region, a predetermined element structure is provided between the first main surface of the semiconductor substrate and the first parallel pn layer. A first electrode electrically connected to the element structure is provided on the first main surface of the semiconductor substrate. A second electrode is provided on the second main surface of the semiconductor substrate. In the terminal region, a first semiconductor region of a second conductivity type is selectively provided between the first main surface of the semiconductor substrate and the second parallel pn layer, surrounding the active region and electrically connected to the first electrode to constitute a breakdown structure. In the active region, a second semiconductor region of a second conductivity type is provided on the first parallel pn layer, having a higher impurity concentration than the first semiconductor region. The impurity concentration of the first first conductivity type region and the second first conductivity type region decreases as the impurity concentration of the second conductivity type region provided on the first parallel pn layer and the second parallel pn layer decreases.

[0023] Furthermore, the silicon carbide semiconductor device according to this invention is characterized in that, in the invention described above, the first second conductivity type region and the second second conductivity type region have the same impurity concentration, and the charge balance is achieved by narrowing the width of the first second conductivity type region and the second second conductivity type region as the impurity concentration of the first first conductivity type region and the second first conductivity type region decreases.

[0024] Furthermore, the silicon carbide semiconductor device according to this invention is characterized in that, in the invention described above, the first semiconductor region is composed of a first semiconductor region on the active region side and a second semiconductor region having a lower impurity concentration than the first semiconductor region, and the impurity concentration decreases in the order of the first conductivity region, the second conductivity region located opposite the first semiconductor region, and the second conductivity region located opposite the second semiconductor region.

[0025] Furthermore, the silicon carbide semiconductor device according to this invention is characterized in that, in the invention described above, charge balance is achieved in a region composed of the first second conductivity type region and two halves of the first first conductivity type region adjacent to the first second conductivity type region, and in a region composed of the second second conductivity type region and two halves of the second first conductivity type region adjacent to the second second conductivity type region.

[0026] Furthermore, the silicon carbide semiconductor device according to this invention is characterized in that, in the invention described above, it has a spatial modulation region within the first semiconductor region that decreases the impurity concentration distribution of the first semiconductor region toward the outside.

[0027] To solve the above-mentioned problems and achieve the objectives of the present invention, the method for manufacturing a silicon carbide semiconductor device according to this invention has the following features. First, a first step is performed to form a first parallel pn layer in which a first first conductivity type region and a first second conductivity type region are alternately and repeatedly arranged in a first direction parallel to the first main surface of the semiconductor substrate inside a semiconductor substrate made of silicon carbide in an active region, and a second parallel pn layer in which a second first conductivity type region and a second second conductivity type region are alternately and repeatedly arranged in the first direction inside the semiconductor substrate in a terminal region surrounding the periphery of the active region. Next, a second step is performed to form a predetermined device structure between the first main surface of the semiconductor substrate and the first parallel pn layer in the active region. Next, a third step is performed to form a first electrode electrically connected to the device structure on the first main surface of the semiconductor substrate. Next, a fourth step is performed to form a second electrode on the second main surface of the semiconductor substrate. Next, in the terminal region, a fifth step is performed to selectively form a first semiconductor region of a second conductivity type between the first main surface of the semiconductor substrate and the second parallel pn layer, surrounding the active region and electrically connected to the first electrode to constitute a breakdown structure. Next, in the active region, a sixth step is performed to form a second semiconductor region of a second conductivity type with a higher impurity concentration than the first semiconductor region on the first parallel pn layer. In the first step, after forming the first first conductivity type region and the second first conductivity type region, impurities that become the first conductivity type are selectively ion-implanted into the first first conductivity type region and the second first conductivity type region, so that the impurity concentration of the first first conductivity type region and the second first conductivity type region is lower as the impurity concentration of the second conductivity type region provided on the first parallel pn layer and the second parallel pn layer is lower.

[0028] According to the invention described above, the carrier concentration in the n-type region (first conductivity type region and second conductivity type region) decreases as you move outward from the active region. As a result, the carrier concentration in the n-type region decreases in areas where the concentration of the surface p-type region (first semiconductor region of the second conductivity type and second semiconductor region of the second conductivity type) is low. Consequently, when the charge balance becomes n-rich, the amount of residual charge in the drift layer decreases in areas where the concentration of the surface p-type region is low, and depletion of the JTE region (first semiconductor region of the second conductivity type) progresses so that the desired breakdown voltage can be obtained. Therefore, the decrease in breakdown voltage when the charge balance shifts to n-rich can be suppressed. [Effects of the Invention]

[0029] The silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to the present invention have the effect of suppressing the overall breakdown voltage reduction of the silicon carbide semiconductor device when the charge balance shifts to the n-rich side. [Brief explanation of the drawing]

[0030] [Figure 1] This is a plan view showing the layout of the silicon carbide semiconductor device according to Embodiment 1 as seen from the front side of the semiconductor substrate. [Figure 2] This is a cross-sectional view showing the cross-sectional structure of the active region in Figure 1. [Figure 3] This is a cross-sectional view showing the cross-sectional structure along the cutting line A1-A2 in Figure 1. [Figure 4] This is a cross-sectional view showing the cross-sectional structure along the cutting line A2-A3 in Figure 1. [Figure 5] This is a plan view showing the carrier concentration distribution in the n-type region of the silicon carbide semiconductor device according to Embodiment 1. [Figure 6] This is a cross-sectional view showing the relationship between the carrier concentration in the n-type region and the JTE structure of the silicon carbide semiconductor device according to Embodiment 1. [Figure 7] This is a plan view showing the relationship between the carrier concentration in the n-type region, the width of the p-type region, and the carrier concentration of the JTE structure in a silicon carbide semiconductor device according to Embodiment 1. [Figure 8] This is a cross-sectional view (part 1) showing the JTE structure of the silicon carbide semiconductor device according to Embodiment 1 during the manufacturing process. [Figure 9] This is a cross-sectional view (part 2) showing the JTE structure of the silicon carbide semiconductor device according to Embodiment 1 during the manufacturing process. [Figure 10] This is a cross-sectional view (part 3) showing the JTE structure of the silicon carbide semiconductor device according to Embodiment 1 during the manufacturing process. [Figure 11] This is a cross-sectional view showing the details of the JTE structure of the silicon carbide semiconductor device according to Embodiment 2. [Figure 12] This is a plan view showing the layout of a conventional silicon carbide semiconductor device as seen from the front side of the semiconductor substrate. [Figure 13] Figure 12 is a cross-sectional view showing the cross-sectional structure along the cutting line AA-AA'. [Figure 14] Figure 12 is a cross-sectional view showing the cross-sectional structure along the cutting line BB-BB'. [Modes for carrying out the invention]

[0031] Preferred embodiments of the silicon carbide semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers or regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. Furthermore, the + and - signs attached to n and p indicate higher and lower impurity concentrations, respectively, compared to layers or regions without these signs. In the following description of embodiments and in the accompanying drawings, similar components are denoted by the same reference numerals, and redundant explanations are omitted.

[0032] (Embodiment 1) The structure of the silicon carbide semiconductor device according to Embodiment 1 will be described using a MOSFET as an example. Figure 1 is a plan view showing the layout of the silicon carbide semiconductor device according to Embodiment 1 as seen from the front side of the semiconductor substrate. Figure 1 shows, for example, 3 mm 2The layout of the corner semiconductor substrate 40 is shown. In Figure 1, the number of n-type regions (first and second first conductivity type regions) 52, 55 and p-type regions (first and second second conductivity type regions) 53, 56 of the first and second parallel pn layers 51, 54 is simplified and differs from Figures 2 to 4.

[0033] Figure 2 is a cross-sectional view showing the cross-sectional structure of the active region in Figure 1. Figure 2 shows one of several unit cells (constituent units of the element) of the same structure arranged in the active region 10. Figures 3 and 4 are cross-sectional views showing the cross-sectional structure at cutting lines A1-A2 and A2-A3, respectively, in Figure 1. Figure 3 shows the area from near the boundary with the intermediate region 20 to near the boundary between the intermediate region 20 and the edge termination region 30. Figure 4 shows the area from near the boundary between the intermediate region 20 and the edge termination region 30 to the edge (chip edge) of the semiconductor substrate 40.

[0034] The silicon carbide semiconductor device 50 according to Embodiment 1 shown in Figures 1 to 4 is a vertical MOSFET with a trench gate structure (device structure) of an SJ structure, comprising an active region 10, an intermediate region 20, and an edge termination region 30 on a semiconductor substrate (semiconductor chip) 40 made of silicon carbide (SiC), and a drift layer (drift region) 2 in parallel pn layers (first and second parallel pn layers 51 and 54) extending from the active region 10 to the edge termination region 30. The active region 10 is the region through which the main current flows when the MOSFET is ON, and is located in the center of the semiconductor substrate 40 (center of the chip).

[0035] The intermediate region 20 is adjacent to the active region 10 and surrounds the active region 10. The edge termination region 30 is the region between the intermediate region 20 and the edge of the semiconductor substrate 40, and surrounds the active region 10 via the intermediate region 20. The active region 10 and the intermediate region 20 have an SJ structure in which the drift layer 2 is a first parallel pn layer 51. The edge termination region 30 has an SJ structure in which the drift layer 2 is a second parallel pn layer 54.

[0036] The boundary between the active region 10 and the intermediate region 20 is p for minority carrier (hole) extraction, which will be described later. ++This is the inner end (inner circumference) of the outer peripheral contact region 21 (see Figure 3). The boundary between the intermediate region 20 and the edge termination region 30 is the inner end (inner circumference) of the JTE structure 32, which will be described later. The inner end of the JTE structure 32 refers to the multiple p-type regions that make up the JTE structure 32 (in Figure 4, p - Type region 32a and the outside of p -- The innermost p-type region of type region 32b) (in Figure 4, p - The inner end of the type region 32a), and the intermediate region 20, as described later, p + This is the junction (interface) with the outer periphery region 13 of the mold (see Figure 4, the second semiconductor region of the second conductivity type).

[0037] The edge termination region 30 has the function of mitigating the electric field on the front side (first main surface) of the semiconductor substrate 40 of the drift layer 2 in the active region 10 and intermediate region 20, thereby maintaining the breakdown voltage. Breakdown voltage is the limit voltage at which leakage current does not increase excessively and the element does not malfunction or break down. The edge termination region 30 has a breakdown voltage structure, p - Type region (first semiconductor region) 32a and the p outside of it -- A junction termination extension (JTE) structure 32 (first semiconductor region of second conductivity type) composed of a type region (second first semiconductor region) 32b, and n + A channel stopper region 34 is located there. The JTE structure 32 surrounds the active region 10 via an intermediate region 20.

[0038] The JTE structure 32 is a structure in which multiple p-type regions are arranged concentrically adjacent to the active region 10 via an intermediate region 20, such that the p-type regions with lower impurity concentrations are located further away from the active region 10. The JTE structure 32 mitigates electric field concentration outside the intermediate region 20, preventing device breakdown due to the application of a voltage below a predetermined voltage (the breakdown voltage of the edge termination region 30).

[0039] n + The channel stopper region 34 is located outside the JTE structure 32 and at a distance from the JTE structure 32, and reaches the edge of the semiconductor substrate 40, for example, along the four sides (straight sections) of the edge of the semiconductor substrate 40. +The channel stopper region 34 extends along the edge of the semiconductor substrate 40 and surrounds the JTE structure 32. Figure 1 shows n + The inner circumference of the channel stopper region 34 is shown by the dashed line 34a. + The channel stopper region 34 is provided in the entire area outside the dashed line 34a, n + The outer periphery of the channel stopper region 34 is the edge of the semiconductor substrate 40, which has a roughly rectangular planar shape.

[0040] The first parallel pn layer 51 is an SJ structure in which n-type regions 52 and p-type regions 53 are alternately and repeatedly arranged adjacent to each other in a first direction X parallel to the front surface of the semiconductor substrate 40. The n-type regions 52 and p-type regions 53 of the first parallel pn layer 51 extend in a stripe-like manner in a second direction Y parallel to the front surface of the semiconductor substrate 40 and perpendicular to the first direction X, up to near the edge of the intermediate region 20.

[0041] Furthermore, the first parallel pn layer 51 is positioned in the first direction X in the active region 10 and the intermediate region 20. Therefore, the boundary between the first parallel pn layer 51 and the second parallel pn layer 54 is located at the end of the intermediate region 20. The first parallel pn layer 51 has an n-type region 52 and a p-type region 53 that pass through the active region 10 and the intermediate region 20.

[0042] The n-type region 52 and p-type region 53 of the first parallel pn layer 51 are in the depth direction Z, and the intermediate region 20 is p + It is in contact with the outer peripheral region 13. The p-type region 53 of the first parallel pn layer 51 is p + The potential of the source electrode 15 (see Figures 2 and 3) is fixed via the outer peripheral region 13 of the mold.

[0043] The second parallel pn layer 54 has an SJ structure in which n-type regions 55 and p-type regions 56 are arranged alternately and repeatedly adjacent to each other in a first direction X parallel to the front surface of the semiconductor substrate 40. The n-type regions 55 and p-type regions 56 of the second parallel pn layer 54 extend in a stripe shape in a second direction Y parallel to the n-type regions 52 and p-type regions 53 of the first parallel pn layer 51. The second parallel pn layer 54 is connected to both sides of the first parallel pn layer 51 in the second direction Y, respectively, and is located only in the edge termination region 30. The second parallel pn layer 54 is located adjacent to both sides of the first parallel pn layer 51 in the first direction X, respectively, and is located only in the edge termination region 30. The second parallel pn layer 54 is arranged such that the outermost p-type region 53 in the first direction X is adjacent to the n-type region 55 on the outside in the first direction X. Furthermore, the second parallel pn layer 54 is positioned beyond the outer edge (periphery) of the JTE structure 32 in the first direction X, such that at least one p-type region 56 is located beyond the outer edge (periphery) of the JTE structure 32 in the first direction X.

[0044] By positioning the p-type region 56 of the second parallel pn layer 54 beyond the outer edge of the JTE structure 32 in the first direction X, electric field concentration at the outer edge of the JTE structure 32 can be suppressed when the MOSFET is off. The outer edge of the JTE structure 32 refers to the outer edge of the innermost p-type region among the multiple p-type regions that constitute the JTE structure 32. Alternatively, the second parallel pn layer 54 may be positioned within a range of, for example, 10 μm or less from the outer edge of the JTE structure 32 in the first direction X.

[0045] The range in which the second parallel pn layer 54 is placed is defined as the range from the outer edge of the JTE structure 32 in the first direction X, thereby reducing the number of floating p-type regions 56 placed in the edge termination region 30. This reduces the amount of accumulated charge of minority carriers (holes) that accumulate in the edge termination region 30 due to MOSFET switching, etc., and remain without being discharged to the outside. For this reason, it is preferable to have a small number of p-type regions 56 placed outside the outer edge of the JTE structure 32 in the first direction X.

[0046] The second parallel pn layer 54 is within the above range from the outer end of the JTE structure 32 in the first direction X, and in the first direction X, n + Directly below the type channel stopper region 34 (n + It may also be placed up to the drain region 1 side. In the first direction X, between the second parallel pn layer 54 and the edge of the semiconductor substrate 40, a normal n layer described later will be placed. - A type drift region 2b (see Figure 4) may be provided. - Either do not provide a drift region 2b, or use this normal n - The narrower the width of the type drift region 2b, the smaller the semiconductor substrate 40 can be made.

[0047] The n-type region 55 and p-type region 56 of the second parallel pn layer 54 are in contact with the JTE structure 32 in the depth direction Z. The p-type region 56 of the second parallel pn layer 54 is in contact with the JTE structure 32 + The potential of the source electrode 15 (see Figures 2 and 3) is fixed via the outer peripheral region 13 of the mold.

[0048] Figure 5 is a plan view showing the carrier concentration distribution in the n-type region of the silicon carbide semiconductor device according to Embodiment 1. In Embodiment 1, the active region 10, the intermediate region 20, and the region of the JTE structure 32 (p - Type region 32a and p -- The carrier concentrations in n-type regions 52 and 55 are set individually for each type region 32b), and the carrier concentrations in n-type regions 52 and 55 decrease as you move outward from the active region 10.

[0049] Specifically, the carrier concentration of the n-type region 52 of the active region 10 and intermediate region 20 is taken as n1, and the p of the JTE structure 32 - Lower part of type region 32a (p - Let n2 be the carrier concentration of the n-type region 55 (the region on the drain electrode 16 side from the n-type region 32a), and the p of the JTE structure 32. -- If n3 is the carrier concentration in the n-type region 55 at the bottom of type region 32b, then n1 ≥ n2 ≥ n3 holds true.

[0050] Figure 6 is a cross-sectional view showing the relationship between the carrier concentration in the n-type region and the JTE structure of the silicon carbide semiconductor device according to Embodiment 1. Figure 7 is a plan view showing the relationship between the carrier concentration in the n-type region, the width of the p-type region, and the carrier concentration of the JTE structure of the silicon carbide semiconductor device according to Embodiment 1. Figure 6 is a cross-sectional view showing the cross-sectional structure along the cutting line A2-A3 in Figure 1. As shown in Figures 6 and 7, the n-type regions 52 and 55 are provided on the first parallel pn layer 51 and the second parallel pn layer 54, respectively, and the p-type region (p + Mold outer area 13, p - Type area 32a,p -- The lower the carrier concentration in type region 32b), the lower the carrier concentration. Also, the transition in carrier concentration in n-type regions 52 and 55 coincides with the change in carrier concentration in the p-type region on the surface.

[0051] On the other hand, the carrier concentrations in the p-type regions 53 and 56 are the same throughout the entire active region 10 and the JTE structure 32. The charge balance (CB) is maintained throughout the entire region by narrowing and expanding the width of the p-type regions 53 and 56 as they move outwards. A charge balance means that the charge amount, expressed as the product of the carrier concentration (impurity concentration) and width of the n-type region in the parallel pn layer, and the charge amount, expressed as the product of the carrier concentration and width of the p-type region, are approximately the same within a range that includes tolerances due to process variations.

[0052] Specifically, the width of the p-type region 53 of the active region 10 and the intermediate region 20 is W p1 As such, p of JTE structure 32 - The width of the p-type region 56 at the bottom of the type region 32a is W. p2 As such, p of JTE structure 32 -- The width of the p-type region 56 at the bottom of type region 32b is W p3 Therefore, W p1 ≥W p2 ≥W p3 This holds true.

[0053] Also, the cell pitch W in each region c They are the same, W n1 +W p1 =W n2+W p2 =W n3 +W p3 =W c holds. Here, W n1 is the width of the n-type regions 52 of the active region 10 and the intermediate region 20, and W n2 is the width of the n-type region 55 at the bottom of the p - -type region 32a of the JTE structure 32, and W n3 is the width of the p-type region 55 at the bottom of the p -- -type region 32b of the JTE structure 32. The cell pitch W c is the width of the region composed of one p-type region 53, 56 and half of the two n-type regions 52, 55 adjacent to the p-type regions 53, 56. For each cell pitch W c , the charge balance calculated from the carrier concentration p of the p-type regions 53, 56, the carrier concentration of the n-type regions 52, 55, and the width of the p-type regions 53, 56 in any region is designed so that the width of the p-type regions 53, 56 corresponds to just balance (0).

Number

[0054] That is, the above formula holds.

[0055] Here, the boundaries (a), (b) where the carrier concentration of the surface p-type regions (p + -type outer peripheral region 13, p - -type region 32a, p -- -type region 32b) changes, and the distances from the boundaries (a), (b) to the p-type regions 53, 56 closest to the boundaries (a), (b) are the widths of the n-type regions 52, 55 in each region (active region 10 and intermediate region 20, p - -type region 32a of the JTE structure 32, p -- -type region 32b of the JTE structure 32) are each half of the width. By doing so, for each cell pitch W c , the charge balance can be made equivalent to just balance (0). This prevents the charge balance from being locally shifted and allows the depletion layer to be uniformly expanded.

[0056] As described above, in Embodiment 1, the carrier concentration of the n-type regions 52 and 55 is lower in the regions where the concentration of the p-type region on the surface is lower. As a result, when the charge balance becomes n-rich, the amount of residual charge in the drift layer 2 becomes smaller in the regions where the concentration of the p-type region on the surface is lower, and the depletion of the JTE region 32 progresses so that the desired breakdown voltage can be obtained. Therefore, it is possible to suppress a decrease in the breakdown voltage when the charge balance shifts to n-rich.

[0057] The cross-sectional structure of the silicon carbide semiconductor device 50 according to Embodiment 1 will be described. As shown in FIG. 2, a general trench gate structure is provided on the front surface side of the semiconductor substrate 40 in the active region 10. The trench gate structure is composed of a p-type base region 4, an n + -type source region 5, a p ++ -type contact region 6, a gate trench 7, a gate insulating film 8, and a gate electrode 9. The semiconductor substrate 40 is formed by sequentially depositing an epitaxial layer 42 serving as a drift layer 2 and an epitaxial layer 43 serving as a p-type base region 4 on the front surface of an n + -type starting substrate 41 made of silicon carbide.

[0058] With the main surface on the p-type epitaxial layer 43 side of the semiconductor substrate 40 as the front surface, the main surface on the n + -type starting substrate 41 side is the back surface (second main surface). The n + -type starting substrate 41 is an n + -type drain region 1. The portion of the p-type epitaxial layer 43 in the edge termination region 30 is removed by etching, and a step 31 is formed on the front surface of the semiconductor substrate 40. The front surface of the semiconductor substrate 40 is recessed toward the n + -type drain region 1 on the portion (second surface) 40b on the edge termination region 30 side rather than the portion (first surface) 40a on the active region 10 side with the step 31 as a boundary.

[0059] The second surface 40b of the front surface of the semiconductor substrate 40 is the n -This is the exposed surface of the p-type epitaxial layer 42. The portion 40c (third surface: mesa edge of step 31) connecting the first surface 40a and the second surface 40b of the front surface of the semiconductor substrate 40 is separated from the active region 10, the intermediate region 20, and the edge termination region 30. The gate trench 7 penetrates the p-type epitaxial layer 43 from the first surface 40a of the front surface of the semiconductor substrate 40 in the depth direction Z to n - It reaches the epitaxial layer 42.

[0060] The gate trench 7 extends in a stripe-like manner in a direction parallel to the front surface of the semiconductor substrate 40 (here, in the second direction Y). A gate electrode 9 is provided inside the gate trench 7 via a gate insulating film 8. p-type base region 4, n + Type source region 5 and p ++ The type contact regions 6 are selectively provided between adjacent gate trenches 7. The p-type base region 4 is the n of the p-type epitaxial layer 43. + Type source region 5 and p ++ This is the portion excluding the contact area 6.

[0061] The p-type base region 4 extends outward from the active region 10 (towards the chip edge) and reaches the third surface 40c of the front surface of the semiconductor substrate 40. + Type source region 5 and p ++ The p-type contact region 6 is selectively provided between the first surface 40a of the front surface of the semiconductor substrate 40 and the p-type base region 4, in contact with the p-type base region 4, and is exposed to the first surface 40a of the front surface of the semiconductor substrate 40. Exposure to the first surface 40a of the front surface of the semiconductor substrate 40 means contact with the source electrode 15 at the contact hole of the interlayer insulating film 14.

[0062] p ++ The contact area 6 is n + It is located further away from the gate trench 7 than the type source region 5. - The n-type current diffusion region 3 of the type epitaxial layer 42, p + Type region 11,12, p + Mold outer area 13, p -Type area 32a,p -- Type regions 32b and n + The portion excluding the channel stopper region 34 is the drift layer 2, which functions as the drift region of the MOSFET, and includes the first and second parallel pn layers 51 and 54. + The portion between the starting substrate 41 and the drift region 2a may be a normal n-type drift region 2a that does not have an SJ structure.

[0063] The first and second parallel pn layers 51 and 54 are n - It is provided at the predetermined position described above inside the type epitaxial layer 42. The first and second parallel pn layers 51 and 54 are, for example, n that become the drift layer 2. - Each time the type epitaxial layer 42 is epitaxially grown in multiple stages in multiple steps, the n - The type epitaxial layer 42 is formed using a multi-stage epitaxial method in which regions that become n-type regions 52, 55 and p-type regions 53, 56 are selectively formed by ion implantation so that regions of the same conductivity type are adjacent to each other in the depth direction Z.

[0064] Furthermore, the first and second parallel pn layers 51 and 54 may be formed using a trench-filled epitaxial method, for example, in which trenches (hereinafter referred to as SJ trenches) are formed in the n-type epitaxial layer, leaving portions that become n-type regions 52 and 55, and the SJ trenches are filled with p-type epitaxial layers that become p-type regions 53 and 56.

[0065] In the active region 10, between the p-type base region 4 and the first parallel pn layer 51 (drift layer 2), there is an n-type current diffusion region 3 and p + n-type current diffusion region 3 and p + Type regions 11 and 12 are, for example, n - This is a diffusion region formed by ion implantation inside the n-type epitaxial layer 42. n-type current diffusion region 3 and p + The mold regions 11 and 12 are n greater than the bottom surface of the gate trench 7. +It is positioned deep within the drain region 1 and extends linearly in the second direction Y, parallel to the gate trench 7.

[0066] The n-type current spreading region 3 is a so-called current spreading layer (CSL) that reduces the carrier spreading resistance. In the n-type current spreading region 3, between adjacent gate trenches 7, p + The n-type region 52 of the first parallel pn layer 51 is adjacent to the p-type regions 11 and 12, the p-type base region 4, and the n-type region 52 of the first parallel pn layer 51, and is further from the bottom surface of the gate trench 7 than n + It reaches a deep position on the drain region 1 side. Instead of the n-type current diffusion region 3, n - A portion of the type epitaxial layer 42 that is not ion-implanted may be provided.

[0067] p + The type regions 11 and 12 have the function of mitigating the electric field applied to the bottom surface of the gate trench 7. + The p-type regions 11 and 12 are adjacent to different p-type regions 53 of the first parallel pn layer 51 in the depth direction Z, respectively. + The type region 11 is positioned separately from the p-type base region 4 and faces the bottom surface of the gate trench 7 in the depth direction Z. + The type region 12 is adjacent to the p-type base region 4 between the gate trenches 7, and p + It is located away from the mold region 11 and the gate trench 7.

[0068] The interlayer insulating film 14 covers the entire surface of the semiconductor substrate 40, except for the contact portion of the active region 10 and the outer peripheral contact portion of the intermediate region 20, which will be described later. The contact portion of the active region 10 is between the source electrode 15 and n + Type source region 5 and p ++ This is the ohmic contact area with the type contact region 6. The outer peripheral contact area of ​​the intermediate region 20 is the source electrode 15 and the p (described later). ++ Type outer peripheral contact area 21(p ++ If the outer peripheral contact region 21 is not provided, it is an ohmic contact region with the p-type base region 4).

[0069] In the intermediate region 20, on the front side of the semiconductor substrate 40, from the active region 10, there is a p-type base region 4 and a p-type base region facing the bottom surface of the outermost gate trench 7 in the first direction X. + Type area 11 (hereinafter p + A p-type base region (referred to as the outer peripheral region 13) extends therein. The p-type base region 4 of the intermediate region 20 surrounds the active region 10. In the intermediate region 20, between the first surface 40a of the front surface of the semiconductor substrate 40 and the p-type base region 4, ++ Type contact area (hereinafter referred to as p ++ A mold outer peripheral contact region (21) is selectively provided.

[0070] p ++ The outer peripheral contact region 21 receives minority carriers (holes) accumulated in the edge termination region 30 due to MOSFET switching, etc., when the MOSFET is turned off. + This is the outer peripheral contact portion with the source electrode 15 for drawing the source electrode 15 through the outer peripheral region 13 and the p-type base region 4. ++ The outer peripheral contact region 21 surrounds the active region 10. ++ The outer peripheral contact region 21 of the mold is in ohmic contact with the portion that extends into the intermediate region of the source electrode 15.

[0071] p + The outer peripheral region 13 extends along the boundary between the active region 10 and the intermediate region 20, surrounding the active region 10. + The outer peripheral region 13 contains all of the p of the active region 10. + The ends of type regions 11 and 12 are connected. Also, p + The outer periphery region 13 of the mold extends outward beyond the step 31 on the front surface of the semiconductor substrate 40 and is exposed to the second surface 40b of the front surface of the semiconductor substrate. Exposure to the second surface 40b of the front surface of the semiconductor substrate 40 means that it is in contact with the field oxide film 35, which will be described later, on the second surface 40b.

[0072] In the intermediate region 20 and the edge termination region 30, on the front surface of the semiconductor substrate 40, p ++An insulating layer is provided over the entire surface outside the outer peripheral contact region 21 of the mold, by sequentially laminating a field oxide film 35 and an interlayer insulating film 14. In the intermediate region 20, on the field oxide film 35, p ++ Outside the outer peripheral contact region 21 of the mold, a polysilicon (poly-Si) layer 22 and a metal wiring layer 23 are sequentially stacked, serving as gate runners that electrically connect the gate electrode 9 and the gate pad (not shown).

[0073] In the surface region of the second surface 40b of the front surface of the semiconductor substrate 40, n - Multiple p-type regions constituting the JTE structure 32 are selectively provided inside the type epitaxial layer 42, and outside of them, away from the JTE structure 32, n + A p-type channel stopper region 34 is selectively provided. The innermost p-type region of the multiple p-type regions constituting the JTE structure 32 is oriented in a direction parallel to the front surface of the semiconductor substrate 40. + It is in contact with the outer peripheral region 13 of the mold. The multiple p-type regions that constitute the JTE structure 32 are p + The potential of the source electrode 15 is fixed via the outer peripheral region 13 of the mold.

[0074] JTE structure 32 and n + The relationship between the channel stopper region 34 and the channel stopper region is not an SJ structure, but a normal n - This is the type drift region 2b. Multiple p-type regions (p - Type area 32a,p -- Type region 32b) and n + The channel stopper region 34 is n - This is a diffusion region formed by ion implantation into the type epitaxial layer 42, and is exposed on the second surface 40b of the front surface of the semiconductor substrate 40. - The drift region 2b is n - This is the portion that remains unimplanted on the surface region of the type epitaxial layer 42 and is exposed on the second surface 40b of the front surface of the semiconductor substrate 40.

[0075] The n-type region 52 and p-type region 53 of the first parallel pn layer 51 are p in the depth direction Z in the intermediate region 20.+ It is adjacent to the outer peripheral region 13 of the type. The n-type region 55 and p-type region 56 of the second parallel pn layer 54 are p in the depth direction Z of the JTE structure 32 - Type area 32a,p -- Opposite to type region 32b. The n-type region 55 and p-type region 56 of the second parallel pn layer 54 are p in the depth direction Z at the edge termination region 30. + It is adjacent to the outer periphery region 13 of the mold.

[0076] The second parallel pn layer 54 and the p of the JTE structure 32 - Type area 32a,p -- The relationship between type region 32b and the normal n is not an SJ structure. - This is the drift region 2b. Between the second parallel pn layer 54 and the edge of the semiconductor substrate 40 is a normal n layer that does not have an SJ structure. - A type drift region 2c may be placed. - The drift region 2c is n - This is the portion of the type epitaxial layer 42 that remains un-ion-implanted between the second parallel pn layer 54 and the edge of the semiconductor substrate 40.

[0077] The second and third surfaces 40b and 40c of the front surface of the semiconductor substrate 40 are covered with an insulating layer formed by sequentially laminating a field oxide film 35 and an interlayer insulating film 14, as described above. The passivation film 36 covers the entire front surface of the semiconductor substrate 40, protecting the front surface of the semiconductor substrate 40. The portion of the source electrode 15 exposed through the opening in the passivation film 36 functions as a source pad. The back surface (n + A drain electrode (second electrode) 16 is provided across the entire surface of the back surface of the mold starting substrate 41.

[0078] Next, a method for manufacturing the silicon carbide semiconductor device 50 according to Embodiment 1 will be described. First, n + n becomes type drain region 1 + A drift layer 2 including first and second parallel pn layers 51 and 54 is formed on the front surface of the starting substrate (semiconductor wafer) 41. For example, when a multi-stage epitaxial method is used, the n layers that become the drift layer 2 are formed. -Each time the type epitaxial layer 42 is epitaxially grown in multiple stages (for example, 9 stages) in several steps, the n - In the type epitaxial layer 42, n-type regions 52 and 55 and p-type regions 53 and 56 are selectively formed by ion implantation such that regions of the same conductivity type are adjacent to each other in the depth direction Z. Alternatively, the n-type regions 52 and 55 and the p-type regions 53 and 56 may be formed by a trench-embedded epitaxial method.

[0079] Here, Figures 8 to 10 are cross-sectional views showing the JTE structure of the silicon carbide semiconductor device according to Embodiment 1 during the manufacturing process. As shown in Figure 8, in both the multi-stage epitaxial method and the trench-embedded epitaxial method, initially, the carrier concentration of the n-type regions 52 and 55 is formed with the lowest carrier concentration, n3, and the carrier concentration of the p-type regions 53 and 56 is formed with p.

[0080] Next, as shown in Figure 9, the n-type region 52 of the active region 10 and the intermediate region 20, and the p of the JTE structure 32 - N-type ions are implanted into the n-type region 55 at the bottom of the type region 32a to increase the carrier concentration and create n2. Next, as shown in Figure 10, n-type ions are implanted into the n-type region 52 of the active region 10 and the intermediate region 20 to increase the carrier concentration and create n1. In this way, the carrier concentrations in the n-type regions 52 and 55 can be made lower as you move outward from the active region 10.

[0081] Next, by ion implantation, an n-type current diffusion region 3, p + Type regions 11, 12 and p + Forms the outer peripheral region 13 of the mold. n in the active region 10 and the intermediate region - Without forming the first parallel pn layer 51 on the uppermost stage of the type epitaxial layer 42, the n-type current diffusion region 3, p + Type regions 11, 12 and p + A type outer peripheral region 13 may be formed. n-type current diffusion region 3, p + Type region 12 and p + The outer periphery region 13 of the mold is divided into two stages, lower and upper, n -A type epitaxial layer 42 is formed each time it is epitaxially grown, p + Type region 11 is p + Type region 12 and p + It may be formed simultaneously with the lower part of the outer periphery region 13 of the mold.

[0082] Next, n - A p-type epitaxial layer 43, which will become the p-type base region 4, is epitaxially grown on the p-type epitaxial layer 42. + Epitaxial layers 42 and 43 are sequentially stacked on a starting substrate 41 to create a semiconductor substrate (semiconductor wafer) 40, in which the n-type epitaxial layer 42 includes first and second parallel pn layers 51 and 54. Next, the portion of the p-type epitaxial layer 43 on the edge termination region 30 side is removed by etching to form a step 31 on the front surface of the semiconductor substrate 40, which is lower on the edge termination region 30 side (second surface 40b) than on the active region 10 side (first surface 40a) (see Figures 3 and 4).

[0083] In the edge termination region 30, the n-type current diffusion region (third semiconductor region of the first conductivity type) 3 is exposed on the second surface 40b, which has newly become the front surface of the semiconductor substrate 40. The portion of the front surface of the semiconductor substrate 40 between the first surface 40a and the second surface 40b (third surface 40c) may, for example, form an obtuse angle (inclined surface) with respect to the first and second surfaces 40a and 40b, or it may form a nearly right angle (vertical surface). The second and third surfaces 40b and 40c of the front surface of the semiconductor substrate 40 have a p-type base region 4 and p + The outer periphery region 13 of the mold is exposed. By etching to form this step 31, the n is formed together with the p-type epitaxial layer 43. - The type epitaxial layer 42 may be partially removed.

[0084] Next, by ion implantation, n + Type source area 5, p ++ Type contact area 6, p ++ Multiple p-type regions (p) of the outer peripheral contact region 21 and JTE structure 32. - Type area 32a,p -- Type region 32b), and n +Each type channel stopper region 34 is selectively formed. + Type source area 5, p ++ Type contact area 6 and p ++ The outer peripheral contact region 21 is formed on the surface region of the p-type epitaxial layer 43. + Type source area 5, p ++ Type contact area 6 and p ++ The portion excluding the outer peripheral contact region 21 of the type becomes the p-type base region 4.

[0085] JTE structure 32 p - Type area 32a,p -- Type regions 32b and n + The channel stopper region 34 is exposed on the second surface 40b of the front surface of the semiconductor substrate 40 in the edge termination region 30. - They are selectively formed on the surface regions of the type epitaxial layer 42. + Type source area 5, p ++ Type contact area 6, p ++ Multiple p-type regions (p) of the outer peripheral contact region 21 and JTE structure 32. - Type area 32a,p -- Type region 32b), and n + The formation order of the channel stopper region 34 is interchangeable. Before the formation of the step 31, n + Type source area 5, p ++ Type contact area 6 and p ++ A mold outer peripheral contact region 21 may be formed.

[0086] Next, a heat treatment (hereinafter referred to as activation annealing) is performed to activate the impurities ion-implanted in the epitaxial layers 42 and 43. Then, from the front surface of the semiconductor substrate 40, n + The p-type source region 5 and the p-type base region 4 penetrate through the inside of the n-type current diffusion region 3. +A gate trench 7 is formed opposite the mold region 11. Next, a gate insulating film 8 is formed along the front surface of the semiconductor substrate 40 and the inner wall of the gate trench 7. Then, the polysilicon layer deposited on the front surface of the semiconductor substrate 40 is etched back so as to be embedded inside the gate trench 7, leaving the portion that will become the gate electrode 9 inside the gate trench 7.

[0087] A field oxide film 35 is formed on the front surface of the semiconductor substrate 40 in the intermediate region 20 and the edge termination region 30. In the intermediate region 20, a polysilicon layer 22, which will serve as a gate runner, is formed on the field oxide film 35. This polysilicon layer 22 may be formed from a portion of the polysilicon layer deposited on the front surface of the semiconductor substrate 40 when the gate electrode 9 was formed. Next, an interlayer insulating film 14 is formed over the entire front surface of the semiconductor substrate 40. Then, surface electrodes (source electrode 15, gate pad, metal wiring layer 23, and drain electrode 16) are formed on both sides of the semiconductor substrate 40 using a general method.

[0088] Next, the front surface of the semiconductor substrate 40 is covered and protected with a passivation film 36, excluding a portion of the source electrode 15 (the portion that will become the source pad), the gate pad, and the metal wiring layer 23. After that, the semiconductor wafer (semiconductor substrate 40) is diced (cut) to separate it into individual chips, thereby completing the silicon carbide semiconductor device 50 shown in Figures 1-4.

[0089] As explained above, according to Embodiment 1, the carrier concentration in the n-type region decreases as you move outward from the active region. Therefore, the carrier concentration in the n-type region is lower in areas where the concentration in the p-type region on the surface is lower. As a result, when the charge balance becomes n-rich, the amount of residual charge in the drift layer decreases in areas where the concentration in the p-type region on the surface is lower, and the depletion of the JTE region progresses so that the desired breakdown voltage can be obtained. Therefore, it is possible to suppress the decrease in breakdown voltage when the charge balance shifts to n-rich.

[0090] (Embodiment 2) Next, the structure of the silicon carbide semiconductor device according to Embodiment 2 will be described. Figure 11 is a cross-sectional view showing the details of the JTE structure of the silicon carbide semiconductor device according to Embodiment 2. The layout and cross-sectional structure of the active region of the silicon carbide semiconductor device according to Embodiment 2, as viewed from the front side of the semiconductor substrate, are the same as those of Embodiment 1, so the description is omitted (see Figures 1 and 2). Figure 11 is a cross-sectional view showing the cross-sectional structure along the cutting line A2-A3 in Figure 1.

[0091] In the silicon carbide semiconductor device according to Embodiment 2, the JTE structure 32 is a spatially modulated JTE structure 39. The spatially modulated JTE structure 39 is made up of adjacent p-type regions (p) that constitute the JTE structure 32. - Type area 32a,p -- In the type region 32b), a spatial modulation region 39a having an impurity concentration distribution spatially equivalent to the intermediate impurity concentration of these two regions is placed, resulting in a structure in which the impurity concentration distribution of the entire JTE structure 32 gradually decreases toward the outside (towards the tip edge). In Figure 11, the spatial modulation region 39a is set to p - An example of placement in type region 32a is shown. The spatial modulation region 39a is p -- It may also be located in type region 32b, p - Type region 32a and p -- It may be placed in both the type region 32b and p - Type region 32a and p -- It may be placed between the type region 32b and the other region.

[0092] The spatial modulation region 39a constituting the spatial modulation JTE structure 39 is formed by alternately arranging two small regions with approximately the same impurity concentration as the adjacent region on each side of itself in a predetermined pattern. In the example in Figure 11, p - within type region 32a, p + Multiple regions with approximately the same impurity concentration as the outer peripheral region 13 are arranged with increasing spacing towards the outside. The spatial impurity concentration distribution of the entire spatial modulation region 39a is determined by the width and impurity concentration ratio of the two sub-regions. The spatial modulation JTE structure 39 can ensure a predetermined withstand voltage more stably than a general JTE structure 32 that does not have a spatial modulation region 39a.

[0093] The method for manufacturing a silicon carbide semiconductor device according to Embodiment 2 is the same as the method for manufacturing a silicon carbide semiconductor device according to Embodiment 1, p - Type area 32a,p -- After forming a JTE structure 32 consisting of type region 32b, a spatial modulation region 39a can be formed within the JTE structure 32 by ion implantation, thereby forming a spatial modulation JTE structure 39.

[0094] As described above, Embodiment 2 provides the same effects as Embodiment 1. Furthermore, Embodiment 2 has a spatial modulation region within the JTE structure. Therefore, compared to a general JTE structure that does not have a spatial modulation region, it is possible to ensure a predetermined withstand voltage more stably.

[0095] In summary, the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit of the invention. For example, in the embodiments described above, the parallel pn layer and n + The impurity concentration in the normal n-type drift region, which does not have an SJ structure between the starting substrate and the core substrate, may be higher than the impurity concentration in the n-type region of the parallel pn layer. Furthermore, the present invention also holds true when the conductivity type (n-type, p-type) is reversed. [Industrial applicability]

[0096] As described above, the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to the present invention are useful for SJ structure power semiconductor devices used in power converters, power supply devices for various industrial machines, and the like. [Explanation of Symbols]

[0097] 1 n + Type drain region 2 Drift Layers 2a The first and second parallel pn layers and n + A normal n-type drift region that is not an SJ structure between the starting substrate and the type of substrate. 3 n-type current diffusion region 4 p-type base region 5 n +Type source area 6 p ++ Type Contact Area 7 Gate Trench 8 gate insulating film 9. Postal Service 10 Active area pp. 11, 12 + type area 13 p + Mold outer area 14 Interlayer insulating film 15 Source electrodes 16 Drain electrode 20 Intermediate area 21 p ++ Outer peripheral contact area 22 Polysilicon layer (gate runner) 23. Metal wiring layer (gate runner) 30 Edge Termination Region 31 Steps on the front surface of the semiconductor substrate 32 JTE structure 32a p of JTE structure - type area 32b p of JTE structure -- type area 34 n + Type channel stopper region 35 Field Oxide Film 36 Passivation membrane 39. Spatial Modulation JTE Structure 39a Spatial modulation region 40 Semiconductor substrates 40a The active region side of the front surface of the semiconductor substrate (first surface) 40b The edge termination region on the front surface of the semiconductor substrate (second surface) 40c The portion connecting the first and second surfaces (third surface) on the front surface of the semiconductor substrate. 41 n + Mold starting substrate 42 n - Type epitaxial layer 43 p-type epitaxial layer 50 Silicon Carbide Semiconductor Devices 51 1st parallel pn layer 52 n-type region of the first parallel pn layer 53 p-type region of the first parallel pn layer 54 2nd parallel pn layer 55 n-type region of the second parallel pn layer 56 p-type region of the second parallel pn layer W n1 Width of the n-type region in the first parallel pn layer W p1 Width of the p-type region in the first parallel pn layer W n2 , W n3 Width of the n-type region in the second parallel pn layer W p2 , W p3 Width of the p-type region in the second parallel pn layer W c Cell pitch X Direction parallel to the front surface of the semiconductor substrate (first direction) Y: A direction parallel to the front surface of the semiconductor substrate and perpendicular to the first direction (second direction). Z-direction (depth)

Claims

1. A semiconductor substrate made of silicon carbide, In the active region, a first parallel pn layer is provided inside the semiconductor substrate, in which a first first conductivity type region and a first second conductivity type region are alternately and repeatedly arranged in a first direction parallel to the first main surface of the semiconductor substrate, In the terminal region surrounding the active region, a second parallel pn layer is provided inside the semiconductor substrate, in which a second first conductivity type region and a second second conductivity type region are alternately and repeatedly arranged in the first direction, A predetermined element structure is provided in the active region between the first main surface of the semiconductor substrate and the first parallel pn layer, A first electrode is provided on the first main surface of the semiconductor substrate and is electrically connected to the element structure, A second electrode provided on the second main surface of the semiconductor substrate, In the terminal region, a first semiconductor region of a second conductivity type is selectively provided between the first main surface of the semiconductor substrate and the second parallel pn layer, surrounding the active region and electrically connected to the first electrode to constitute a breakdown structure. In the active region, a second semiconductor region of a second conductivity type having a higher impurity concentration than the first semiconductor region is provided on the first parallel pn layer, Equipped with, The first first conductivity type region and the second first conductivity type region have lower impurity concentrations as the impurity concentration of the second conductivity type region provided on the first parallel pn layer and the second parallel pn layer decreases. The first second conductivity type region and the second second conductivity type region have the same impurity concentration. A silicon carbide semiconductor device characterized in that the charge balance is achieved by narrowing the width of the first second conductivity region and the second second conductivity region as the impurity concentration of the first first conductivity region and the second first conductivity region decreases.

2. A semiconductor substrate made of silicon carbide, In the active region, a first parallel pn layer is provided inside the semiconductor substrate, in which a first first conductivity type region and a first second conductivity type region are alternately and repeatedly arranged in a first direction parallel to the first main surface of the semiconductor substrate, In the terminal region surrounding the active region, a second parallel pn layer is provided inside the semiconductor substrate, in which a second first conductivity type region and a second second conductivity type region are alternately and repeatedly arranged in the first direction, A predetermined element structure is provided in the active region between the first main surface of the semiconductor substrate and the first parallel pn layer, A first electrode is provided on the first main surface of the semiconductor substrate and is electrically connected to the element structure, A second electrode provided on the second main surface of the semiconductor substrate, In the terminal region, a first semiconductor region of a second conductivity type is selectively provided between the first main surface of the semiconductor substrate and the second parallel pn layer, surrounding the active region and electrically connected to the first electrode to constitute a breakdown structure. In the active region, a second semiconductor region of a second conductivity type having a higher impurity concentration than the first semiconductor region is provided on the first parallel pn layer, Equipped with, The first first conductivity type region and the second first conductivity type region have lower impurity concentrations as the impurity concentration of the second conductivity type region provided on the first parallel pn layer and the second parallel pn layer decreases. The first semiconductor region is composed of a first semiconductor region on the active region side and a second semiconductor region having a lower impurity concentration than the first semiconductor region. A silicon carbide semiconductor device characterized in that the impurity concentration decreases in the following order: the first conductivity type region, the second conductivity type region located opposite the first semiconductor region, and the second conductivity type region located opposite the second semiconductor region.

3. A semiconductor substrate made of silicon carbide, In the active region, a first parallel pn layer is provided inside the semiconductor substrate, in which a first first conductivity type region and a first second conductivity type region are alternately and repeatedly arranged in a first direction parallel to the first main surface of the semiconductor substrate, In the terminal region surrounding the active region, a second parallel pn layer is provided inside the semiconductor substrate, in which a second first conductivity type region and a second second conductivity type region are alternately and repeatedly arranged in the first direction, A predetermined element structure is provided in the active region between the first main surface of the semiconductor substrate and the first parallel pn layer, A first electrode is provided on the first main surface of the semiconductor substrate and is electrically connected to the element structure, A second electrode provided on the second main surface of the semiconductor substrate, In the terminal region, a first semiconductor region of a second conductivity type is selectively provided between the first main surface of the semiconductor substrate and the second parallel pn layer, surrounding the active region and electrically connected to the first electrode to constitute a breakdown structure. In the active region, a second semiconductor region of a second conductivity type having a higher impurity concentration than the first semiconductor region is provided on the first parallel pn layer, Equipped with, The first first conductivity type region and the second first conductivity type region have lower impurity concentrations as the impurity concentration of the second conductivity type region provided on the first parallel pn layer and the second parallel pn layer decreases. A region comprising the first second conductivity type region and two halves of the first first conductivity type region adjacent to the first second conductivity type region, and A silicon carbide semiconductor device characterized in that charge balance is achieved in a region composed of the second second conductivity type region and the halves of two second first conductivity type regions adjacent to the second second conductivity type region.

4. The first semiconductor region is composed of a first first semiconductor region on the active region side and a second first semiconductor region having a lower impurity concentration than the first first semiconductor region. The silicon carbide semiconductor device according to claim 1, characterized in that the impurity concentration decreases in the order of the first conductivity type region, the second conductivity type region located opposite the first semiconductor region, and the second conductivity type region located opposite the second semiconductor region.

5. A region comprising the first second conductivity type region and two halves of the first first conductivity type region adjacent to the first second conductivity type region, A silicon carbide semiconductor device according to any one of claims 1, 2, or 4, characterized in that charge balance is achieved in a region composed of the second second conductivity type region and half of the two second first conductivity type regions adjacent to the second second conductivity type region.

6. The silicon carbide semiconductor device according to any one of claims 1 to 5, characterized in that the first semiconductor region has a spatial modulation region that decreases the impurity concentration distribution of the first semiconductor region toward the outside.

7. A first step of forming a first parallel pn layer in which a first first conductivity type region and a first second conductivity type region are alternately and repeatedly arranged in a first direction parallel to the first main surface of the semiconductor substrate in an active region, and a second parallel pn layer in which a second first conductivity type region and a second second conductivity type region are alternately and repeatedly arranged in the first direction in a terminal region surrounding the active region, A second step of forming a predetermined element structure between the first main surface of the semiconductor substrate and the first parallel pn layer in the active region, A third step involves forming a first electrode electrically connected to the element structure on the first main surface of the semiconductor substrate, A fourth step involves forming a second electrode on the second main surface of the semiconductor substrate, A fifth step in which, in the terminal region, a first semiconductor region of a second conductivity type is selectively formed between the first main surface of the semiconductor substrate and the second parallel pn layer, surrounding the periphery of the active region and electrically connected to the first electrode to constitute a breakdown structure, A sixth step in which a second semiconductor region of a second conductivity type having a higher impurity concentration than the first semiconductor region is formed on the first parallel pn layer in the active region, Includes, In the first step, after forming the first first conductivity type region and the second first conductivity type region, impurities that become the first conductivity type are selectively ion-implanted into the first first conductivity type region and the second first conductivity type region, thereby forming the first first conductivity type region and the second first conductivity type region with a lower impurity concentration as the impurity concentration of the second conductivity type region provided on the first parallel pn layer and the second parallel pn layer decreases. A method for manufacturing a silicon carbide semiconductor device, characterized in that, in the first step, the first second conductivity type region and the second second conductivity type region are formed with the same impurity concentration, and the charge balance is achieved by narrowing the width of the first second conductivity type region and the second second conductivity type region as the impurity concentration of the first first conductivity type region and the second first conductivity type region decreases.

8. A first step of forming a first parallel pn layer in which a first first conductivity type region and a first second conductivity type region are alternately and repeatedly arranged in a first direction parallel to the first main surface of the semiconductor substrate in an active region, and a second parallel pn layer in which a second first conductivity type region and a second second conductivity type region are alternately and repeatedly arranged in the first direction in a terminal region surrounding the active region, A second step of forming a predetermined element structure between the first main surface of the semiconductor substrate and the first parallel pn layer in the active region, A third step involves forming a first electrode electrically connected to the element structure on the first main surface of the semiconductor substrate, A fourth step involves forming a second electrode on the second main surface of the semiconductor substrate, A fifth step in which, in the terminal region, a first semiconductor region of a second conductivity type is selectively formed between the first main surface of the semiconductor substrate and the second parallel pn layer, surrounding the periphery of the active region and electrically connected to the first electrode to constitute a breakdown structure, A sixth step in which a second semiconductor region of a second conductivity type having a higher impurity concentration than the first semiconductor region is formed on the first parallel pn layer in the active region, Includes, In the first step, after forming the first first conductivity type region and the second first conductivity type region, impurities that become the first conductivity type are selectively ion-implanted into the first first conductivity type region and the second first conductivity type region, thereby forming the first first conductivity type region and the second first conductivity type region with a lower impurity concentration as the impurity concentration of the second conductivity type region provided on the first parallel pn layer and the second parallel pn layer decreases. In the fifth step, the first semiconductor region is formed into a first first semiconductor region on the active region side and a second first semiconductor region having a lower impurity concentration than the first first semiconductor region. A method for manufacturing a silicon carbide semiconductor device, characterized in that the impurity concentration decreases in the following order: the first first conductivity type region, the second first conductivity type region located opposite the first first semiconductor region, and the second first conductivity type region located opposite the second first semiconductor region.

9. A first step of forming a first parallel pn layer in which a first first conductivity type region and a first second conductivity type region are alternately and repeatedly arranged in a first direction parallel to the first main surface of the semiconductor substrate in an active region, and a second parallel pn layer in which a second first conductivity type region and a second second conductivity type region are alternately and repeatedly arranged in the first direction in a terminal region surrounding the active region, A second step of forming a predetermined element structure between the first main surface of the semiconductor substrate and the first parallel pn layer in the active region, A third step involves forming a first electrode electrically connected to the element structure on the first main surface of the semiconductor substrate, A fourth step involves forming a second electrode on the second main surface of the semiconductor substrate, A fifth step in which, in the terminal region, a first semiconductor region of a second conductivity type is selectively formed between the first main surface of the semiconductor substrate and the second parallel pn layer, surrounding the periphery of the active region and electrically connected to the first electrode to constitute a breakdown structure, A sixth step in which a second semiconductor region of a second conductivity type having a higher impurity concentration than the first semiconductor region is formed on the first parallel pn layer in the active region, Includes, In the first step, after forming the first first conductivity type region and the second first conductivity type region, impurities that become the first conductivity type are selectively ion-implanted into the first first conductivity type region and the second first conductivity type region, thereby forming the first first conductivity type region and the second first conductivity type region with a lower impurity concentration as the impurity concentration of the second conductivity type region provided on the first parallel pn layer and the second parallel pn layer decreases. A region comprising the first second conductivity type region and two halves of the first first conductivity type region adjacent to the first second conductivity type region, and A method for manufacturing a silicon carbide semiconductor device, characterized in that charge balance is achieved in a region composed of the second second conductivity type region and half of the two second first conductivity type regions adjacent to the second second conductivity type region.

Images