Capacitor
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- KK TOSHIBA
- Filing Date
- 2023-03-22
- Publication Date
- 2026-05-26
Smart Images
Figure 0007865911000001 
Figure 0007865911000002 
Figure 0007865911000003
Abstract
Description
Technical Field
[0001] The embodiment relates to a capacitor.
Background Art
[0002] Capacitors disposed in an electronic circuit are required to be miniaturized and have high-frequency responsiveness.
Prior Art Documents
Patent Documents
[0003]
Patent Document 1
Non-Patent Documents
[0004]
Non-Patent Document 1
Summary of the Invention
Problems to be Solved by the Invention
[0005] The embodiment provides a capacitor that can be miniaturized and has improved high-frequency responsiveness.
Means for Solving the Problems
[0006] The capacitor according to the embodiment includes a semiconductor substrate, an electrode layer, a dielectric film, a first terminal, and a second terminal. The electrode layer extends from the surface of the semiconductor substrate into the semiconductor substrate and includes a metal silicide in the semiconductor substrate. The dielectric film is provided between the electrode layer and the semiconductor substrate and electrically insulates the electrode layer from the semiconductor substrate. The first terminal is connected to the electrode layer, and the second terminal is connected to the semiconductor substrate.
Brief Description of the Drawings
[0007] [Figure 1] This is a schematic cross-sectional view showing a capacitor according to the embodiment. [Figure 2] This is a schematic plan view representing a capacitor according to the embodiment. [Figure 3] This is a schematic diagram illustrating the characteristics of a capacitor according to this embodiment. [Figure 4] This is a schematic cross-sectional view illustrating the manufacturing process of a capacitor according to this embodiment. [Figure 5] This is a schematic cross-sectional view showing the manufacturing process, following Figure 4. [Figure 6] This is a schematic cross-sectional view showing a capacitor according to a first modified example of the embodiment. [Figure 7] This is a schematic cross-sectional view showing a capacitor according to a second modified example of the embodiment. [Figure 8] This is a schematic plan view showing a capacitor according to a third modified example of the embodiment. [Figure 9] This is a schematic cross-sectional view showing the dielectric film of a capacitor according to the embodiment. [Modes for carrying out the invention]
[0008] The embodiments will be described below with reference to the drawings. Identical parts in the drawings will be numbered the same, and detailed explanations of those parts will be omitted as appropriate, while different parts will be described. Note that the drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of sizes between parts, etc., are not necessarily the same as in reality. Furthermore, even when representing the same part, the dimensions and ratios may be depicted differently in different drawings.
[0009] Furthermore, the arrangement and configuration of each part will be explained using the X, Y, and Z axes shown in each figure. The X, Y, and Z axes are mutually orthogonal and represent the X, Y, and Z directions, respectively. In some cases, the Z direction is described as upward and the opposite direction as downward.
[0010] Figure 1 is a schematic cross-sectional view showing a capacitor 1 according to an embodiment. The capacitor 1 is provided on a semiconductor substrate 10, for example, a silicon substrate. The capacitor 1 may be a standalone device or may be provided together with an integrated circuit on the semiconductor substrate 10.
[0011] As shown in Figure 1, the capacitor 1 includes a semiconductor substrate 10, a dielectric film 20, an electrode layer 30, an insulating film 40, a first terminal 53, and a second terminal 55. The semiconductor substrate 10 is, for example, a low-resistance n-type silicon substrate. The n-type impurity concentration of the semiconductor substrate 10 is, for example, 1 × 10⁻¹⁶. 18 ~1 × 10 20 cm -3 It is within the range.
[0012] The semiconductor substrate 10 includes a plurality of trenches TR provided on its surface 10F side. Hereinafter, the trenches TR will have a depth TD and a width TW. The trenches TR will be provided in a size that will yield a predetermined capacitance. The aspect ratio TD / TW of the trenches TR will be, for example, 50 or more, and preferably, for example, 100.
[0013] The dielectric film 20 is provided on the surface 10F side of the semiconductor substrate 10 and covers the inner surface of the trench TR. The dielectric film 20 includes, for example, at least one of a silicon oxide film or a silicon nitride film. Alternatively, the dielectric film 20 may be a high-dielectric constant film such as aluminum oxide or hafnium oxide, a so-called high-k film.
[0014] The electrode layer 30 is provided on the dielectric film 20 and covers the inner surface of the trench TR. The electrode layer 30 is provided such that a void AG remains inside the trench TR. The electrode layer 30 has an opening, for example, on the surface 10F side of the semiconductor substrate 10. The void AG extends from the opening of the electrode layer 30 to near the lower end on the bottom surface side of the trench TR. The dielectric film 20 and the electrode layer 30 are stacked on the bottom surface of the trench TR, and the electrode layer 30 is exposed at the lower end of the void AG.
[0015] The electrode layer 30 includes, for example, a first conductive layer 33 and a second conductive layer 35. The first conductive layer 33 is, for example, conductive polysilicon. The second conductive layer 35 is a metal silicide. The second conductive layer 35 is, for example, nickel silicide (NiSi). The second conductive layer 35 is exposed on the inner surface of the void AG.
[0016] The electrode layer 30 faces the semiconductor substrate 10 through the dielectric film 20 within the trench TR. The first conductive layer 33 is provided between the dielectric film 20 and the second conductive layer 35. The first conductive layer 33 faces the semiconductor substrate 10 through the dielectric film 20.
[0017] The insulating film 40 is provided on the electrode layer 30 on the surface 10F side of the semiconductor substrate 10. The insulating film 40 is, for example, a silicon nitride film. The insulating film 40 closes the opening of the electrode layer 30, and a void AG is provided inside the trench TR.
[0018] The first terminal 53 is provided on the insulating film 40. The first terminal 53 is provided on the electrode layer 30 through the insulating film 40 and is connected to the electrode layer 30 through a contact hole CH1 provided in the insulating film 40. The first terminal 53 contains, for example, aluminum and is electrically connected to the second conductive layer 35 of the electrode layer 30.
[0019] The second terminal 55 contains, for example, aluminum and is provided on the insulating film 40. The insulating film 40 also covers a portion on the surface 10F side of the semiconductor substrate 10 where the electrode layer 30 is not provided. The dielectric film 20 extends, for example, between the semiconductor substrate 10 and the insulating film 40. The second terminal 55 is connected to the semiconductor substrate 10 through contact holes CH2 provided in the dielectric film 20 and the insulating film 40.
[0020] FIG. 2 is a schematic plan view showing the capacitor 1 according to the embodiment. In FIG. 2, the first terminal 53 and the second terminal 55 provided on the insulating film 40 are shown. The first terminal 53 is located on the electrode layer 30.
[0021] As shown in Figure 2, the multiple trenches TR each extend in the Y direction and are aligned in the X direction. The first terminal 53 and the second terminal 55 each extend in the Y direction. In a plan view, the multiple trenches TR are provided between the first terminal 53 and the second terminal 55.
[0022] Figures 3(a) and 3(b) are schematic diagrams showing the characteristics of capacitor 1 according to the embodiment. Figure 3(a) is the equivalent circuit of capacitor 1. Figure 3(b) is a graph showing the high-frequency characteristics of capacitor 1.
[0023] As shown in Figure 3(a), the capacitor 1 includes a substrate resistance Rs, capacitances C provided inside each of the multiple trenches TR, and a resistance Re of the electrode layer 30. In the capacitor 1, by providing capacitances C inside each of the multiple trenches TR, the capacitance can be increased without increasing the occupied area on the surface 10F side of the semiconductor substrate 10. In other words, the capacitor 1 can be miniaturized by providing trenches TR.
[0024] Figure 3(b) is a graph showing the relationship between the cutoff frequency between the first terminal 53 and the second terminal 55 and the resistivity of the electrode layer 30. The horizontal axis represents resistivity, and the vertical axis represents the cutoff frequency. Figure 3(b) shows the characteristics of two samples DT and ST with different trench sizes TR.
[0025] In Figure 3(b), the substrate resistance Rs is assumed to be constant. In sample ST, the trench depth TD is 50 micrometers (μm), and the trench width TW is 2 μm. In sample DT, the trench depth TD is 100 micrometers (μm), and the trench width TW is 1 μm.
[0026] The cutoff frequency decreases as the resistivity of the electrode layer 30 increases. Furthermore, the cutoff frequency decreases as the trench TR deepens. When the electrode layer 30 is a single layer of polysilicon, the resistivity is 10 mΩcm, and the cutoff frequency is 1 GHz or less.
[0027] To improve the cutoff frequency of capacitor 1, it is preferable to reduce the resistivity of the electrode layer 30. Furthermore, to increase the capacitance by increasing the depth TD of the trench TR, it is desirable to further reduce the resistivity of the electrode layer 30. The electrode layer 30 is made less resistive by including a second conductive layer 35 of metal silicide. This makes it possible to raise the cutoff frequency of capacitor 1.
[0028] Next, the manufacturing method of the capacitor 1 will be explained with reference to Figures 4(a) to 5(c). Figures 4(a) to 5(c) are schematic cross-sectional views showing the manufacturing process of the capacitor 1 according to this embodiment.
[0029] As shown in Figure 4(a), a plurality of trenches TR are formed on the surface 10F side of the semiconductor substrate 10. The trenches TR are provided, for example, by selectively removing the semiconductor substrate 10 using anisotropic RIE (Reactive Ion Etching).
[0030] Furthermore, a dielectric film 20 is formed on the surface 10F side of the semiconductor substrate 10. The dielectric film 20 covers the inner surface of the trench TR. The dielectric film 20 is provided, for example, by thermal oxidation or thermal nitriding of the semiconductor substrate 10. Alternatively, the dielectric film 20 may be formed using CVD (Chemical Vapor Deposition). The dielectric film 20 is formed so as to leave a space SP inside the trench TR.
[0031] As shown in Figure 4(b), a first conductive layer 33 is formed on the dielectric film 20. The first conductive layer 33 is a semiconductor layer containing silicon, for example, polysilicon. The first conductive layer 33 contains, for example, n-type or p-type impurities. The first conductive layer 33 is formed, for example, by CVD. The first conductive layer 33 covers the surface 10F of the semiconductor substrate 10 via the dielectric film 20. The first conductive layer 33 also covers the inner surface of the trench TR via the dielectric film 20. The first conductive layer 33 is formed so as to leave a space SP inside the trench TR.
[0032] As shown in Figure 4(c), a metal layer 37 is formed on the first conductive layer 33. The metal layer 37 covers the first conductive layer 33 on the surface 10F side of the semiconductor substrate 10 and inside the trench TR. The metal layer 37 is also formed so as to leave a space SP inside the trench TR.
[0033] The metal layer 37 is formed using a non-electroplating method after treating the surface of the first conductive layer 33 by a wet process using a precious metal catalyst, so-called MacEtch (see Non-Patent Document 1). The metal atoms adhering to the surface of the first conductive layer 33 during the MacEtch process make it possible to form a uniform plating layer. As a result, the metal layer 37, for example, a nickel layer, can be uniformly formed on the inner surface of a trench TR with a large aspect ratio TD / TW (see Figure 1).
[0034] As shown in Figure 5(a), a second conductive layer 35 is formed on the first conductive layer 33. The second conductive layer 35 is formed, for example, after partially removing the first conductive layer 33 and the metal layer 37. That is, on the surface 10F of the semiconductor substrate 10, portions formed around the trenches TR of the first conductive layer 33 and the metal layer 37 (see Figure 2) are removed. The second conductive layer 35 is formed by reacting the first conductive layer 33 and the metal layer 37 by heat treatment. That is, the second conductive layer 35 contains a metal silicide formed by the reaction of the first conductive layer 33 and the metal layer 37.
[0035] As shown in Figure 5(b), an insulating film 40 is formed on the surface 10F side of the semiconductor substrate 10. The insulating film 40 is provided to cover the second conductive layer 35 and to close the opening of the space SP in the trench TR. As a result, a void AG is left inside the trench TR.
[0036] The insulating film 40 is formed, for example, using PCVD (Plasma-enhanced chemical vapor deposition). The insulating film 40 is, for example, a silicon nitride film. The insulating film 40 is also provided on the surface 10F side of the semiconductor substrate 10, on the region around the trench TR (see Figure 2) where the first conductive layer 33 and the metal layer 37 have been removed.
[0037] As shown in Figure 5(c), the first terminal 53 and the second terminal 55 are formed on the insulating film 40. The first terminal 53 is formed on the surface 10F of the semiconductor substrate 10 after a contact hole CH1 communicating with the second conductive layer 35 is formed in the insulating film 40. The second terminal 55 is formed on the surface 10F of the semiconductor substrate 10 after a contact hole CH2 communicating with the semiconductor substrate 10 is formed in the dielectric film 20 and the insulating film 40.
[0038] The first terminal 53 and the second terminal 55 are formed by patterning a metal layer, such as an aluminum layer, formed on the insulating film 40. The first terminal 53 extends into the contact hole CH1 and is provided to contact the second conductive layer 35, and is electrically connected to the second conductive layer 35. The second terminal 55 extends into the contact hole CH2 and is provided to contact the semiconductor substrate 10, and is electrically connected to the semiconductor substrate 10.
[0039] In the manufacturing method of the capacitor 1 according to this embodiment, by leaving a space SP inside the trench TR, stress during the process of forming the dielectric film 20, the first conductive film 33, and the second conductive film 35 can be relieved, and warping of the semiconductor substrate 10 can be prevented. This makes it possible to improve the manufacturing yield.
[0040] Figure 6 is a schematic cross-sectional view showing a capacitor 2 according to a first modified example of the embodiment. The capacitor 2 includes a semiconductor substrate 10, a dielectric film 20, a second conductive layer 35, an insulating film 40, a first terminal 53, and a second terminal 55.
[0041] In capacitor 2, the electrode layer 30 (see Figure 1) is replaced by a single-layer second conductive layer 35. That is, when the first conductive layer 33 is thin, the entire layer reacts with the metal layer 37, and the electrode layer 30 becomes the second conductive layer 35 containing metal silicide. The second conductive layer 35 containing metal silicide faces the semiconductor substrate 10 via the dielectric film 20. This makes it possible to reduce the resistance Re of the electrode layer (see Figure 3) and increase the cutoff frequency.
[0042] Capacitor 2 is formed, for example, by increasing the thickness of the metal layer 37. The metal layer 37 can be formed to a desired thickness, for example, by combining a non-electroplating method and an electroplating method. In this example as well, the void AG extends from the opening on the surface 10F side of the semiconductor substrate 10 in the second conductive layer 35 to the vicinity of the lower end on the bottom side of the trench TR.
[0043] Figure 7 is a schematic cross-sectional view showing a capacitor 3 according to a second modified example of the embodiment. The capacitor 3 includes a semiconductor substrate 10, a dielectric film 20, an electrode layer 30, an insulating film 40, a first terminal 53, and a second terminal 55.
[0044] As shown in Figure 7, the electrode layer 30 includes a first conductive layer 33 and a second conductive layer 35. The first conductive layer 33 is, for example, conductive polysilicon and is provided on the bottom surface and side walls at the bottom of the trench TR. The second conductive layer 35 is provided at the top of the trench TR and is provided so as to connect to the first conductive layer 33. The second conductive layer 35 contains a metal silicide.
[0045] For example, in the manufacturing process shown in Figure 4(c), if the metal layer 37 is not formed all the way to the bottom of the trench TR but is provided to cover the top of the trench TR, the second conductive layer 35 will not be formed at the bottom of the trench TR, and the first conductive layer 33 will remain at the bottom of the trench TR. Note that if the first conductive layer 33 is thick, it may remain between the dielectric film 20 and the second conductive layer 35 (see Figure 1).
[0046] Even with this structure, the resistance Re of the electrode layer 30 (see Figure 3) is reduced by the second conductive layer 35. This allows the cutoff frequency of the capacitor 3 to be increased. The air gap AG extends from the opening of the second conductive layer 35 to the vicinity of the lower end of the first conductive layer 33. This reduces the stress in the semiconductor substrate 10.
[0047] Figure 8 is a schematic plan view showing a capacitor 4 according to a third modified embodiment. Figure 2 shows a first terminal 53 and a second terminal 55 provided on the insulating film 40. The first terminal 53 is located on the electrode layer 30.
[0048] As shown in Figure 8, the multiple trenches TR each extend in the Y direction and are aligned in the X direction. The first terminal 53 and the second terminal 55 are aligned in the Y direction. The first terminal 53 and the second terminal 55 and the multiple trenches TR are aligned in the X direction. This allows the leads connected to the first terminal 53 and the second terminal 55 to be drawn out in the same direction.
[0049] Figures 9(a) and (b) are schematic cross-sectional views showing the dielectric film 20 of capacitors 1 to 3 according to the embodiment. The dielectric film 20 is not limited to a single layer film, but may have a laminated structure including multiple films.
[0050] As shown in Figure 9(a), the dielectric film 20 includes a first film 20a, a second film 20b, and a third film 20c. Between the semiconductor substrate 10 and the first conductive film 33, the third film 20c is provided between the first film 20a and the second film 20b. The first film 20a is provided between the semiconductor substrate 10 and the third film 20c. The second film 20b is provided between the first conductive film 33 and the third film 20c.
[0051] The first film 20a and the second film 20b are, for example, silicon oxide films. The third film 20c is, for example, a silicon nitride film. Alternatively, the third film 20c may be a high dielectric constant film such as aluminum oxide or hafnium oxide.
[0052] As shown in Figure 9(b), the dielectric film 20 includes a first film 20a and a second film 20b. The first film 20a is provided between the semiconductor substrate 10 and the second film 20b. The second film 20b is provided between the first conductive film 33 and the first film 20a.
[0053] The first film 20a is, for example, a silicon oxide film. The second film 20b is, for example, a silicon nitride film. Alternatively, the second film 20b may be a high dielectric constant film such as aluminum oxide or hafnium oxide.
[0054] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents.
[0055] (Note 1) Semiconductor substrate and An electrode layer extending from the surface of the semiconductor substrate into the semiconductor substrate, and containing a metal silicide within the semiconductor substrate, A dielectric film is provided between the electrode layer and the semiconductor substrate, which electrically insulates the electrode layer from the semiconductor substrate. A first terminal connected to the electrode layer, A second terminal connected to the semiconductor substrate, A capacitor equipped with [a specific feature / feature]. (Note 2) The semiconductor substrate further comprises an insulating film covering the electrode layer on the surface side, The electrode layer includes an opening located on the surface side of the semiconductor substrate and a void extending from the opening to the edge in the semiconductor substrate. The capacitor according to Appendix 1, wherein the insulating film is provided so as to block the opening in the electrode layer. (Note 3) The first terminal is provided on the insulating film and extends into a first contact hole provided in the insulating film so as to be connected to the electrode layer. The capacitor described in Appendix 2, wherein the second terminal is provided on the insulating film and extends into a second contact hole provided in the insulating film so as to be connected to the semiconductor substrate. (Note 4) The insulating film covers the surface side of the semiconductor substrate. The dielectric film extends between the semiconductor substrate and the insulating film, A second contact hole is provided that penetrates the insulating film and the dielectric film and communicates with the semiconductor substrate. The second terminal is a capacitor as described in Appendix 3, extending into the second contact hole so as to be connected to the semiconductor substrate. (Note 5) The capacitor according to any one of appendices 1 to 4, wherein the electrode layer further comprises a polysilicon layer provided between the dielectric film and the metal silicide. (Note 6) The capacitor according to any one of Appendix 1 to 5, wherein the dielectric film comprises at least one of a silicon oxide film, a silicon nitride film, and a high dielectric constant film. (Note 7) The semiconductor substrate has a trench provided on the surface side, The dielectric film covers the bottom surface and side walls of the trench. The capacitor according to any one of claims 1 to 6, wherein the electrode layer covers the dielectric film on the inner surface of the trench. (Note 8) The electrode layer further contains conductive polysilicon, The polysilicon is provided on the dielectric film on the bottom surface of the trench and on the bottom side of the side wall, The aforementioned metal silicide is provided on the dielectric film on the opening side of the trench, as described in Appendix 7 of the capacitor. [Explanation of Symbols]
[0056] 1, 2, 3, 4…Capacitor, 10…Semiconductor substrate, 10F…Surface, 20…Dielectric film, 30…Electrode layer, 33…First conductive layer, 35…Second conductive layer, 37…Metal layer, 40…Insulating film, AG…Void, CH1…First contact hole, CH2…Second contact hole, Re…Electrode resistance, Rs…Substrate resistance, SP…Space, TR…Trench
Claims
1. Semiconductor substrate and An electrode layer extending from the surface of the semiconductor substrate into the semiconductor substrate, and containing a metal silicide within the semiconductor substrate, A dielectric film is provided between the electrode layer and the semiconductor substrate, which electrically insulates the electrode layer from the semiconductor substrate. A first terminal connected to the electrode layer, A second terminal connected to the semiconductor substrate, On the surface side of the semiconductor substrate, an insulating film covering the electrode layer, Equipped with, The electrode layer includes an opening located on the surface side of the semiconductor substrate and a void extending from the opening to the edge in the semiconductor substrate. The insulating film is a capacitor provided so as to block the opening in the electrode layer.
2. The first terminal is provided on the insulating film and extends into a first contact hole provided in the insulating film so as to be connected to the electrode layer. The capacitor according to claim 1, wherein the second terminal is provided on the insulating film and extends into a second contact hole provided in the insulating film so as to be connected to the semiconductor substrate.
3. The insulating film covers the surface side of the semiconductor substrate. The dielectric film extends between the semiconductor substrate and the insulating film, A second contact hole is provided that penetrates the insulating film and the dielectric film and communicates with the semiconductor substrate. The capacitor according to claim 2, wherein the second terminal extends into the second contact hole so as to be connected to the semiconductor substrate.
4. A semiconductor substrate and An electrode layer extending from the surface of the semiconductor substrate into the semiconductor substrate, and containing a metal silicide within the semiconductor substrate, A dielectric film is provided between the electrode layer and the semiconductor substrate, which electrically insulates the electrode layer from the semiconductor substrate. A first terminal connected to the electrode layer, A second terminal connected to the semiconductor substrate, Equipped with, The electrode layer further includes a polysilicon layer provided between the dielectric film and the metal silicide in the capacitor.
5. A semiconductor substrate and An electrode layer extending from the surface of the semiconductor substrate into the semiconductor substrate, and containing a metal silicide within the semiconductor substrate, A dielectric film is provided between the electrode layer and the semiconductor substrate, which electrically insulates the electrode layer from the semiconductor substrate. A first terminal connected to the electrode layer, A second terminal connected to the semiconductor substrate, Equipped with, The semiconductor substrate has a trench provided on the surface side, The dielectric film covers the bottom surface and side walls of the trench. The electrode layer covers the dielectric film on the inner surface of the trench. The electrode layer further contains conductive polysilicon, The polysilicon is provided on the dielectric film on the bottom surface of the trench and on the bottom side of the side wall, The metal silicide is a capacitor provided on the dielectric film on the opening side of the trench.
6. The capacitor according to any one of claims 1 to 5, wherein the dielectric film comprises at least one of a silicon oxide film, a silicon nitride film, and a high dielectric constant film.
7. The semiconductor substrate has a trench provided on the surface side, The dielectric film covers the bottom surface and side walls of the trench. The capacitor according to any one of claims 1 to 4, wherein the electrode layer covers the dielectric film on the inner surface of the trench.